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GET /api/patches/45265/?format=api
{ "id": 45265, "url": "https://patches.dpdk.org/api/patches/45265/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20180925023442.134705-4-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180925023442.134705-4-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180925023442.134705-4-qi.z.zhang@intel.com", "date": "2018-09-25T02:34:25", "name": "[03/20] net/i40e/base: introduce PHY type bitmask", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "183e43b743ff6ff8f71a848326eef4e2d6066e55", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20180925023442.134705-4-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 1477, "url": "https://patches.dpdk.org/api/series/1477/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1477", "date": "2018-09-25T02:34:22", "name": "base code update", "version": 1, "mbox": "https://patches.dpdk.org/series/1477/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/45265/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/45265/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5F0B81B194;\n\tTue, 25 Sep 2018 04:34:20 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 775D11B144\n\tfor <dev@dpdk.org>; Tue, 25 Sep 2018 04:34:10 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t24 Sep 2018 19:34:08 -0700", "from dpdk51.sh.intel.com ([10.67.110.190])\n\tby orsmga005.jf.intel.com with ESMTP; 24 Sep 2018 19:33:46 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,300,1534834800\"; d=\"scan'208\";a=\"259958455\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "beilei.xing@intel.com", "Cc": "dev@dpdk.org, ferruh.yigit@intel.com, helin.zhang@intel.com,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Tue, 25 Sep 2018 10:34:25 +0800", "Message-Id": "<20180925023442.134705-4-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20180925023442.134705-1-qi.z.zhang@intel.com>", "References": "<20180925023442.134705-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 03/20] net/i40e/base: introduce PHY type bitmask", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch introduces a helper macro define.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/i40e/base/i40e_adminq_cmd.h | 37 +++++++++++++++++++++++++++++++++\n 1 file changed, 37 insertions(+)", "diff": "diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h\nindex beb1274ad..af9c90b78 100644\n--- a/drivers/net/i40e/base/i40e_adminq_cmd.h\n+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h\n@@ -1855,6 +1855,43 @@ enum i40e_aq_phy_type {\n \tI40E_PHY_TYPE_DEFAULT\t\t\t= 0xFF,\n };\n \n+#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XAUI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XFI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_SFI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XLAUI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XLPPI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))\n+\n #define I40E_LINK_SPEED_100MB_SHIFT\t0x1\n #define I40E_LINK_SPEED_1000MB_SHIFT\t0x2\n #define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n", "prefixes": [ "03/20" ] }