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GET /api/patches/45150/?format=api
{ "id": 45150, "url": "https://patches.dpdk.org/api/patches/45150/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1537550255-252066-4-git-send-email-yipeng1.wang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1537550255-252066-4-git-send-email-yipeng1.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1537550255-252066-4-git-send-email-yipeng1.wang@intel.com", "date": "2018-09-21T17:17:31", "name": "[v2,3/7] test/hash: fix rw test with non-consecutive cores", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "02c127103998e8b595bd1c73b3af6a8ffa2be5f2", "submitter": { "id": 754, "url": "https://patches.dpdk.org/api/people/754/?format=api", "name": "Wang, Yipeng1", "email": "yipeng1.wang@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1537550255-252066-4-git-send-email-yipeng1.wang@intel.com/mbox/", "series": [ { "id": 1449, "url": "https://patches.dpdk.org/api/series/1449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1449", "date": "2018-09-21T17:17:28", "name": "hash: add extendable bucket and partial key hashing", "version": 2, "mbox": "https://patches.dpdk.org/series/1449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/45150/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/45150/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7C20B4D3A;\n\tSat, 22 Sep 2018 02:22:24 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id B590EA49\n\tfor <dev@dpdk.org>; Sat, 22 Sep 2018 02:22:12 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t21 Sep 2018 17:22:10 -0700", "from skx-yipeng.jf.intel.com ([10.54.81.175])\n\tby orsmga006.jf.intel.com with ESMTP; 21 Sep 2018 17:22:10 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,287,1534834800\"; d=\"scan'208\";a=\"76346601\"", "From": "Yipeng Wang <yipeng1.wang@intel.com>", "To": "bruce.richardson@intel.com", "Cc": "dev@dpdk.org, yipeng1.wang@intel.com, michel@digirati.com.br,\n\thonnappa.nagarahalli@arm.com", "Date": "Fri, 21 Sep 2018 10:17:31 -0700", "Message-Id": "<1537550255-252066-4-git-send-email-yipeng1.wang@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1537550255-252066-1-git-send-email-yipeng1.wang@intel.com>", "References": "<1536253745-133104-1-git-send-email-yipeng1.wang@intel.com>\n\t<1537550255-252066-1-git-send-email-yipeng1.wang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 3/7] test/hash: fix rw test with\n\tnon-consecutive cores", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "the multi-reader and multi-writer rte_hash unit test does not\nwork correctly with non-consicutive core ids. This commit\nfixes the issue.\n\nFixes: 0eb3726ebcf1 (\"test/hash: add test for read/write concurrency\")\nCc: stable@dpdk.org\n\nSigned-off-by: Yipeng Wang <yipeng1.wang@intel.com>\n---\n test/test/test_hash_readwrite.c | 78 ++++++++++++++++++++++++++---------------\n 1 file changed, 49 insertions(+), 29 deletions(-)", "diff": "diff --git a/test/test/test_hash_readwrite.c b/test/test/test_hash_readwrite.c\nindex 55ae33d..2a4f7b9 100644\n--- a/test/test/test_hash_readwrite.c\n+++ b/test/test/test_hash_readwrite.c\n@@ -24,6 +24,7 @@\n #define NUM_TEST 3\n unsigned int core_cnt[NUM_TEST] = {2, 4, 8};\n \n+unsigned int slave_core_ids[RTE_MAX_LCORE];\n struct perf {\n \tuint32_t single_read;\n \tuint32_t single_write;\n@@ -60,12 +61,15 @@ test_hash_readwrite_worker(__attribute__((unused)) void *arg)\n \tuint64_t begin, cycles;\n \tint ret;\n \n-\toffset = (lcore_id - rte_get_master_lcore())\n-\t\t\t* tbl_rw_test_param.num_insert;\n+\tfor (i = 0; i < rte_lcore_count(); i++) {\n+\t\tif (slave_core_ids[i] == lcore_id)\n+\t\t\tbreak;\n+\t}\n+\toffset = tbl_rw_test_param.num_insert * i;\n \n \tprintf(\"Core #%d inserting and reading %d: %'\"PRId64\" - %'\"PRId64\"\\n\",\n \t lcore_id, tbl_rw_test_param.num_insert,\n-\t offset, offset + tbl_rw_test_param.num_insert);\n+\t offset, offset + tbl_rw_test_param.num_insert - 1);\n \n \tbegin = rte_rdtsc_precise();\n \n@@ -171,6 +175,7 @@ test_hash_readwrite_functional(int use_htm)\n \tuint32_t duplicated_keys = 0;\n \tuint32_t lost_keys = 0;\n \tint use_jhash = 1;\n+\tint slave_cnt = rte_lcore_count() - 1;\n \n \trte_atomic64_init(&gcycles);\n \trte_atomic64_clear(&gcycles);\n@@ -182,17 +187,17 @@ test_hash_readwrite_functional(int use_htm)\n \t\tgoto err;\n \n \ttbl_rw_test_param.num_insert =\n-\t\tTOTAL_INSERT / rte_lcore_count();\n+\t\tTOTAL_INSERT / slave_cnt;\n \n \ttbl_rw_test_param.rounded_tot_insert =\n \t\ttbl_rw_test_param.num_insert\n-\t\t* rte_lcore_count();\n+\t\t* slave_cnt;\n \n \tprintf(\"++++++++Start function tests:+++++++++\\n\");\n \n \t/* Fire all threads. */\n \trte_eal_mp_remote_launch(test_hash_readwrite_worker,\n-\t\t\t\t NULL, CALL_MASTER);\n+\t\t\t\t NULL, SKIP_MASTER);\n \trte_eal_mp_wait_lcore();\n \n \twhile (rte_hash_iterate(tbl_rw_test_param.h, &next_key,\n@@ -249,7 +254,7 @@ test_hash_readwrite_functional(int use_htm)\n }\n \n static int\n-test_rw_reader(__attribute__((unused)) void *arg)\n+test_rw_reader(void *arg)\n {\n \tuint64_t i;\n \tuint64_t begin, cycles;\n@@ -276,7 +281,7 @@ test_rw_reader(__attribute__((unused)) void *arg)\n }\n \n static int\n-test_rw_writer(__attribute__((unused)) void *arg)\n+test_rw_writer(void *arg)\n {\n \tuint64_t i;\n \tuint32_t lcore_id = rte_lcore_id();\n@@ -285,8 +290,13 @@ test_rw_writer(__attribute__((unused)) void *arg)\n \tuint64_t start_coreid = (uint64_t)(uintptr_t)arg;\n \tuint64_t offset;\n \n-\toffset = TOTAL_INSERT / 2 + (lcore_id - start_coreid)\n-\t\t\t\t\t* tbl_rw_test_param.num_insert;\n+\tfor (i = 0; i < rte_lcore_count(); i++) {\n+\t\tif (slave_core_ids[i] == lcore_id)\n+\t\t\tbreak;\n+\t}\n+\n+\toffset = TOTAL_INSERT / 2 + (i - (start_coreid)) *\n+\t\t\t\ttbl_rw_test_param.num_insert;\n \tbegin = rte_rdtsc_precise();\n \tfor (i = offset; i < offset + tbl_rw_test_param.num_insert; i++) {\n \t\tret = rte_hash_add_key_data(tbl_rw_test_param.h,\n@@ -384,8 +394,8 @@ test_hash_readwrite_perf(struct perf *perf_results, int use_htm,\n \tperf_results->single_read = end / i;\n \n \tfor (n = 0; n < NUM_TEST; n++) {\n-\t\tunsigned int tot_lcore = rte_lcore_count();\n-\t\tif (tot_lcore < core_cnt[n] * 2 + 1)\n+\t\tunsigned int tot_slave_lcore = rte_lcore_count() - 1;\n+\t\tif (tot_slave_lcore < core_cnt[n] * 2)\n \t\t\tgoto finish;\n \n \t\trte_atomic64_clear(&greads);\n@@ -415,17 +425,19 @@ test_hash_readwrite_perf(struct perf *perf_results, int use_htm,\n \t\t */\n \n \t\t/* Test only reader cases */\n-\t\tfor (i = 1; i <= core_cnt[n]; i++)\n+\t\tfor (i = 0; i < core_cnt[n]; i++)\n \t\t\trte_eal_remote_launch(test_rw_reader,\n-\t\t\t\t\t(void *)(uintptr_t)read_cnt, i);\n+\t\t\t\t\t(void *)(uintptr_t)read_cnt,\n+\t\t\t\t\tslave_core_ids[i]);\n \n \t\trte_eal_mp_wait_lcore();\n \n \t\tstart_coreid = i;\n \t\t/* Test only writer cases */\n-\t\tfor (; i <= core_cnt[n] * 2; i++)\n+\t\tfor (; i < core_cnt[n] * 2; i++)\n \t\t\trte_eal_remote_launch(test_rw_writer,\n-\t\t\t\t\t(void *)((uintptr_t)start_coreid), i);\n+\t\t\t\t\t(void *)((uintptr_t)start_coreid),\n+\t\t\t\t\tslave_core_ids[i]);\n \n \t\trte_eal_mp_wait_lcore();\n \n@@ -464,22 +476,26 @@ test_hash_readwrite_perf(struct perf *perf_results, int use_htm,\n \t\t\t}\n \t\t}\n \n-\t\tstart_coreid = core_cnt[n] + 1;\n+\t\tstart_coreid = core_cnt[n];\n \n \t\tif (reader_faster) {\n-\t\t\tfor (i = core_cnt[n] + 1; i <= core_cnt[n] * 2; i++)\n+\t\t\tfor (i = core_cnt[n]; i < core_cnt[n] * 2; i++)\n \t\t\t\trte_eal_remote_launch(test_rw_writer,\n-\t\t\t\t\t(void *)((uintptr_t)start_coreid), i);\n-\t\t\tfor (i = 1; i <= core_cnt[n]; i++)\n+\t\t\t\t\t(void *)((uintptr_t)start_coreid),\n+\t\t\t\t\tslave_core_ids[i]);\n+\t\t\tfor (i = 0; i < core_cnt[n]; i++)\n \t\t\t\trte_eal_remote_launch(test_rw_reader,\n-\t\t\t\t\t(void *)(uintptr_t)read_cnt, i);\n+\t\t\t\t\t(void *)(uintptr_t)read_cnt,\n+\t\t\t\t\tslave_core_ids[i]);\n \t\t} else {\n-\t\t\tfor (i = 1; i <= core_cnt[n]; i++)\n+\t\t\tfor (i = 0; i < core_cnt[n]; i++)\n \t\t\t\trte_eal_remote_launch(test_rw_reader,\n-\t\t\t\t\t(void *)(uintptr_t)read_cnt, i);\n-\t\t\tfor (; i <= core_cnt[n] * 2; i++)\n+\t\t\t\t\t(void *)(uintptr_t)read_cnt,\n+\t\t\t\t\tslave_core_ids[i]);\n+\t\t\tfor (; i < core_cnt[n] * 2; i++)\n \t\t\t\trte_eal_remote_launch(test_rw_writer,\n-\t\t\t\t\t(void *)((uintptr_t)start_coreid), i);\n+\t\t\t\t\t(void *)((uintptr_t)start_coreid),\n+\t\t\t\t\tslave_core_ids[i]);\n \t\t}\n \n \t\trte_eal_mp_wait_lcore();\n@@ -562,13 +578,19 @@ test_hash_readwrite_main(void)\n \t * writer threads for performance numbers.\n \t */\n \tint use_htm, reader_faster;\n+\tunsigned int i = 0, core_id = 0;\n \n-\tif (rte_lcore_count() == 1) {\n-\t\tprintf(\"More than one lcore is required \"\n+\tif (rte_lcore_count() <= 2) {\n+\t\tprintf(\"More than two lcores are required \"\n \t\t\t\"to do read write test\\n\");\n \t\treturn 0;\n \t}\n \n+\tRTE_LCORE_FOREACH_SLAVE(core_id) {\n+\t\tslave_core_ids[i] = core_id;\n+\t\ti++;\n+\t}\n+\n \tsetlocale(LC_NUMERIC, \"\");\n \n \tif (rte_tm_supported()) {\n@@ -610,8 +632,6 @@ test_hash_readwrite_main(void)\n \n \tprintf(\"Results summary:\\n\");\n \n-\tint i;\n-\n \tprintf(\"single read: %u\\n\", htm_results.single_read);\n \tprintf(\"single write: %u\\n\", htm_results.single_write);\n \tfor (i = 0; i < NUM_TEST; i++) {\n", "prefixes": [ "v2", "3/7" ] }