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GET /api/patches/44992/?format=api
{ "id": 44992, "url": "https://patches.dpdk.org/api/patches/44992/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1537394318-17682-2-git-send-email-rasesh.mody@cavium.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1537394318-17682-2-git-send-email-rasesh.mody@cavium.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1537394318-17682-2-git-send-email-rasesh.mody@cavium.com", "date": "2018-09-19T21:59:39", "name": "[2/5] net/bnx2x: update link/PHY management", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "26c864fee7e11485d93ecdae009d8733e5b19046", "submitter": { "id": 569, "url": "https://patches.dpdk.org/api/people/569/?format=api", "name": "Mody, Rasesh", "email": "rasesh.mody@cavium.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1537394318-17682-2-git-send-email-rasesh.mody@cavium.com/mbox/", "series": [ { "id": 1402, "url": "https://patches.dpdk.org/api/series/1402/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1402", "date": "2018-09-19T21:59:05", "name": "[1/5] net/bnx2x: fix logging to include dev name", "version": 1, "mbox": "https://patches.dpdk.org/series/1402/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/44992/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/44992/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 128385F16;\n\tThu, 20 Sep 2018 10:12:48 +0200 (CEST)", "from NAM02-BL2-obe.outbound.protection.outlook.com\n\t(mail-bl2nam02on0085.outbound.protection.outlook.com [104.47.38.85])\n\tby dpdk.org (Postfix) with ESMTP id 159C91B142\n\tfor <dev@dpdk.org>; Wed, 19 Sep 2018 23:59:49 +0200 (CEST)", "from BYAPR07MB5365.namprd07.prod.outlook.com (20.177.125.18) by\n\tBYAPR07MB5703.namprd07.prod.outlook.com (20.178.0.29) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1143.17; Wed, 19 Sep 2018 21:59:40 +0000", "from BYAPR07MB5365.namprd07.prod.outlook.com\n\t([fe80::2047:9647:f196:bde0]) by\n\tBYAPR07MB5365.namprd07.prod.outlook.com\n\t([fe80::2047:9647:f196:bde0%6]) with mapi id 15.20.1143.017;\n\tWed, 19 Sep 2018 21:59:40 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=H/LXGJHwIczcYwXRleY1qOticSUX3pz/jA29xBQmfyI=;\n\tb=WdvxTVd3DGxKOW2Qc5BTF2lJQtlA5jUIaile07KVSZYBYKTRUvq/Qco/tifqPgyWqOCfHzFOGIPo5K44CwOE6GqUjWsx7wFjeF2PD1v9Jpy2PlzGT7RfQg43x0Jxt+fdu9S+PSNjU4hUjV+PLU/avpDWT04Y6zIclls6slm9ey4=", "From": "\"Mody, Rasesh\" <Rasesh.Mody@cavium.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "CC": "\"Mody, Rasesh\" <Rasesh.Mody@cavium.com>, \"ferruh.yigit@intel.com\"\n\t<ferruh.yigit@intel.com>, Dept-Eng DPDK Dev <Dept-EngDPDKDev@cavium.com>", "Thread-Topic": "[PATCH 2/5] net/bnx2x: update link/PHY management", "Thread-Index": "AQHUUGQOdkERfZV+nUCXyy2mNyttWw==", "Date": "Wed, 19 Sep 2018 21:59:39 +0000", "Message-ID": "<1537394318-17682-2-git-send-email-rasesh.mody@cavium.com>", "References": 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cavium.com does not designate\n\tpermitted sender hosts)", "x-microsoft-antispam-message-info": "UGYBNr/5TeChGEr8Fbl8I7oxjkHCQJZxITo3TzndLDxmu+PKXp81cJYNAHchUBi4nkLMO6r/FxlctVby6RB09MzrgSne2exOH/BxJIVE6QgqQNfcibZ+EoFSiPUoAuyzCc8XnNQmuNE7Y/Ii5ftID3s569m77CCJiGEuhhH6JRgummCQfCehYMa6Sd2qraL2qjQXMZDpC7p31c4CtvQYGFleOelDCg+QegS3FGNupbk3lVl+VRt8SqoEkj5ZwrAdx2cJWbyTPtGhqmwfDhz1V3yuHtiy48gdfJDkcJxd9t2THYS4W7rAUBDvGsL9kZkua9netuBFm/lq3nR1aUDg6lURsRJlt5axEK0lU12QcAw=", "spamdiagnosticoutput": "1:99", "spamdiagnosticmetadata": "NSPM", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "cavium.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "4eb00401-2152-4529-e1a4-08d61e7b3129", "X-MS-Exchange-CrossTenant-originalarrivaltime": "19 Sep 2018 21:59:40.3164\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB5703", "X-Mailman-Approved-At": "Thu, 20 Sep 2018 10:12:46 +0200", "Subject": "[dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch has changes to update the link/PHY management (elink) code\nto the latest.\n\nSigned-off-by: Rasesh Mody <rasesh.mody@cavium.com>\n---\n drivers/net/bnx2x/bnx2x.h | 3 +\n drivers/net/bnx2x/ecore_hsi.h | 20 +-\n drivers/net/bnx2x/elink.c | 7951 ++++++++++++++++++++++++++---------------\n drivers/net/bnx2x/elink.h | 234 +-\n 4 files changed, 5231 insertions(+), 2977 deletions(-)", "diff": "diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 2d545f5..1cc5a6b 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -824,6 +824,7 @@ struct bnx2x_devinfo {\n #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)\n #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)\n /* device ids */\n+#define CHIP_NUM_57710 0x164e\n #define CHIP_NUM_57711 0x164f\n #define CHIP_NUM_57711E 0x1650\n #define CHIP_NUM_57712 0x1662\n@@ -865,6 +866,8 @@ struct bnx2x_devinfo {\n #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)\n #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)\n \n+#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)\n+#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)\n #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)\n #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)\n #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \\\ndiff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h\nindex 57085eb..1192e5d 100644\n--- a/drivers/net/bnx2x/ecore_hsi.h\n+++ b/drivers/net/bnx2x/ecore_hsi.h\n@@ -500,6 +500,18 @@ struct port_hw_cfg {\t\t /* port 0: 0x12c port 1: 0x2bc */\n \t#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000\n \t#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16\n \n+\t/* Set non-default values for TXFIR in SFP mode. */\n+\t#define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000\n+\t#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20\n+\n+\t/* Set non-default values for IPREDRIVER in SFP mode. */\n+\t#define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000\n+\t#define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24\n+\n+\t/* Set non-default values for POST2 in SFP mode. */\n+\t#define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000\n+\t#define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28\n+\n \tuint32_t reserved0[5];\t\t\t\t /* 0x17c */\n \n \tuint32_t aeu_int_mask;\t\t\t\t /* 0x190 */\n@@ -783,6 +795,7 @@ struct port_hw_cfg {\t\t /* port 0: 0x12c port 1: 0x2bc */\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100\n+\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00\n@@ -2532,7 +2545,12 @@ struct shmem2_region {\n \tuint32_t drv_func_info_addr;\t\t\t/* Offset 0x14C */\n \tuint32_t drv_func_info_size;\t\t\t/* Offset 0x150 */\n \tuint32_t link_attr_sync[PORT_MAX];\t\t/* Offset 0x154 */\n-\t#define LINK_ATTR_SYNC_KR2_ENABLE\t(1<<0)\n+\t#define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001\n+\t#define LINK_ATTR_84858 0x00000002\n+\t#define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00\n+\t#define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8\n+\n+\tuint32_t link_change_count[PORT_MAX];\t\t/* Offset 0x160-0x164 */\n };\n \n \ndiff --git a/drivers/net/bnx2x/elink.c b/drivers/net/bnx2x/elink.c\nindex 1f94476..930b425 100644\n--- a/drivers/net/bnx2x/elink.c\n+++ b/drivers/net/bnx2x/elink.c\n@@ -18,166 +18,159 @@\n #include \"ecore_hsi.h\"\n #include \"ecore_reg.h\"\n \n-static elink_status_t elink_link_reset(struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t uint8_t reset_ext_phy);\n-static elink_status_t elink_check_half_open_conn(struct elink_params *params,\n-\t\t\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t\t\t uint8_t notify);\n-static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n-\t\t\t\t\t\t struct elink_params *params);\n \n #define MDIO_REG_BANK_CL73_IEEEB0\t\t\t0x0\n-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL\t\t0x0\n-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN\t0x0200\n-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN\t\t0x1000\n-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST\t0x8000\n+\t#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL\t\t0x0\n+\t\t#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN\t0x0200\n+\t\t#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN\t\t0x1000\n+\t\t#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST\t0x8000\n \n #define MDIO_REG_BANK_CL73_IEEEB1\t\t\t0x10\n-#define MDIO_CL73_IEEEB1_AN_ADV1\t\t\t0x00\n-#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE\t\t\t0x0400\n-#define\tMDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC \t\t0x0800\n-#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH\t\t0x0C00\n-#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK\t\t0x0C00\n-#define MDIO_CL73_IEEEB1_AN_ADV2\t\t\t\t0x01\n-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M\t\t0x0000\n-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX\t\t0x0020\n-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4\t\t0x0040\n-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR\t\t0x0080\n-#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1\t\t\t0x03\n-#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE\t\t0x0400\n-#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC \t\t0x0800\n-#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH\t\t0x0C00\n-#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK\t\t0x0C00\n-#define\tMDIO_CL73_IEEEB1_AN_LP_ADV2\t\t\t0x04\n+\t#define MDIO_CL73_IEEEB1_AN_ADV1\t\t\t0x00\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE\t\t\t0x0400\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC\t\t0x0800\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH\t\t0x0C00\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK\t\t0x0C00\n+\t#define MDIO_CL73_IEEEB1_AN_ADV2\t\t\t\t0x01\n+\t\t#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M\t\t0x0000\n+\t\t#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX\t\t0x0020\n+\t\t#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4\t\t0x0040\n+\t\t#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR\t\t0x0080\n+\t#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1\t\t\t0x03\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE\t\t0x0400\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC\t\t0x0800\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH\t\t0x0C00\n+\t\t#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK\t\t0x0C00\n+\t#define\tMDIO_CL73_IEEEB1_AN_LP_ADV2\t\t\t0x04\n \n #define\tMDIO_REG_BANK_RX0\t\t\t\t0x80b0\n-#define\tMDIO_RX0_RX_STATUS\t\t\t\t0x10\n-#define\tMDIO_RX0_RX_STATUS_SIGDET\t\t\t0x8000\n-#define\tMDIO_RX0_RX_STATUS_RX_SEQ_DONE\t\t\t0x1000\n-#define\tMDIO_RX0_RX_EQ_BOOST\t\t\t\t0x1c\n-#define\tMDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n-#define\tMDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n+\t#define\tMDIO_RX0_RX_STATUS\t\t\t\t0x10\n+\t\t#define\tMDIO_RX0_RX_STATUS_SIGDET\t\t\t0x8000\n+\t\t#define\tMDIO_RX0_RX_STATUS_RX_SEQ_DONE\t\t\t0x1000\n+\t#define\tMDIO_RX0_RX_EQ_BOOST\t\t\t\t0x1c\n+\t\t#define\tMDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n+\t\t#define\tMDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n \n #define\tMDIO_REG_BANK_RX1\t\t\t\t0x80c0\n-#define\tMDIO_RX1_RX_EQ_BOOST\t\t\t\t0x1c\n-#define\tMDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n-#define\tMDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n+\t#define\tMDIO_RX1_RX_EQ_BOOST\t\t\t\t0x1c\n+\t\t#define\tMDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n+\t\t#define\tMDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n \n #define\tMDIO_REG_BANK_RX2\t\t\t\t0x80d0\n-#define\tMDIO_RX2_RX_EQ_BOOST\t\t\t\t0x1c\n-#define\tMDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n-#define\tMDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n+\t#define\tMDIO_RX2_RX_EQ_BOOST\t\t\t\t0x1c\n+\t\t#define\tMDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n+\t\t#define\tMDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n \n #define\tMDIO_REG_BANK_RX3\t\t\t\t0x80e0\n-#define\tMDIO_RX3_RX_EQ_BOOST\t\t\t\t0x1c\n-#define\tMDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n-#define\tMDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n+\t#define\tMDIO_RX3_RX_EQ_BOOST\t\t\t\t0x1c\n+\t\t#define\tMDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n+\t\t#define\tMDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n \n #define\tMDIO_REG_BANK_RX_ALL\t\t\t\t0x80f0\n-#define\tMDIO_RX_ALL_RX_EQ_BOOST\t\t\t\t0x1c\n-#define\tMDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n-#define\tMDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL\t0x10\n+\t#define\tMDIO_RX_ALL_RX_EQ_BOOST\t\t\t\t0x1c\n+\t\t#define\tMDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n+\t\t#define\tMDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL\t0x10\n \n #define\tMDIO_REG_BANK_TX0\t\t\t\t0x8060\n-#define\tMDIO_TX0_TX_DRIVER\t\t\t\t0x17\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n-#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n+\t#define\tMDIO_TX0_TX_DRIVER\t\t\t\t0x17\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n+\t\t#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n \n #define\tMDIO_REG_BANK_TX1\t\t\t\t0x8070\n-#define\tMDIO_TX1_TX_DRIVER\t\t\t\t0x17\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n-#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n+\t#define\tMDIO_TX1_TX_DRIVER\t\t\t\t0x17\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n+\t\t#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n \n #define\tMDIO_REG_BANK_TX2\t\t\t\t0x8080\n-#define\tMDIO_TX2_TX_DRIVER\t\t\t\t0x17\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n-#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n+\t#define\tMDIO_TX2_TX_DRIVER\t\t\t\t0x17\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n+\t\t#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n \n #define\tMDIO_REG_BANK_TX3\t\t\t\t0x8090\n-#define\tMDIO_TX3_TX_DRIVER\t\t\t\t0x17\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n-#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n-#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n-#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n-#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n-#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n+\t#define\tMDIO_TX3_TX_DRIVER\t\t\t\t0x17\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n+\t\t#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n+\t\t#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n+\t\t#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n \n #define\tMDIO_REG_BANK_XGXS_BLOCK0\t\t\t0x8000\n-#define\tMDIO_BLOCK0_XGXS_CONTROL\t\t\t0x10\n+\t#define\tMDIO_BLOCK0_XGXS_CONTROL\t\t\t0x10\n \n #define\tMDIO_REG_BANK_XGXS_BLOCK1\t\t\t0x8010\n-#define\tMDIO_BLOCK1_LANE_CTRL0\t\t\t\t0x15\n-#define\tMDIO_BLOCK1_LANE_CTRL1\t\t\t\t0x16\n-#define\tMDIO_BLOCK1_LANE_CTRL2\t\t\t\t0x17\n-#define\tMDIO_BLOCK1_LANE_PRBS\t\t\t\t0x19\n+\t#define\tMDIO_BLOCK1_LANE_CTRL0\t\t\t\t0x15\n+\t#define\tMDIO_BLOCK1_LANE_CTRL1\t\t\t\t0x16\n+\t#define\tMDIO_BLOCK1_LANE_CTRL2\t\t\t\t0x17\n+\t#define\tMDIO_BLOCK1_LANE_PRBS\t\t\t\t0x19\n \n #define\tMDIO_REG_BANK_XGXS_BLOCK2\t\t\t0x8100\n-#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP\t\t\t0x10\n-#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE\t\t0x8000\n-#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE\t0x4000\n-#define\tMDIO_XGXS_BLOCK2_TX_LN_SWAP\t\t0x11\n-#define\tMDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE\t\t0x8000\n-#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G\t0x14\n-#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS\t0x0001\n-#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS\t0x0010\n-#define\tMDIO_XGXS_BLOCK2_TEST_MODE_LANE\t\t0x15\n+\t#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP\t\t\t0x10\n+\t\t#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE\t\t0x8000\n+\t\t#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE\t0x4000\n+\t\t#define\tMDIO_XGXS_BLOCK2_TX_LN_SWAP\t\t0x11\n+\t\t#define\tMDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE\t\t0x8000\n+\t\t#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G\t0x14\n+\t\t#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS\t0x0001\n+\t\t#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS\t0x0010\n+\t\t#define\tMDIO_XGXS_BLOCK2_TEST_MODE_LANE\t\t0x15\n \n #define\tMDIO_REG_BANK_GP_STATUS\t\t\t\t0x8120\n #define\tMDIO_GP_STATUS_TOP_AN_STATUS1\t\t\t\t0x1B\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE\t0x0001\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE\t0x0002\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS\t\t0x0004\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS\t\t0x0008\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE\t0x0010\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE\t0x0020\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE\t0x0040\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE\t0x0080\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK\t\t0x3f00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M\t\t0x0000\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M\t\t0x0100\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G\t\t0x0200\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G\t\t0x0300\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G\t\t0x0400\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G\t\t0x0500\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG\t0x0600\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4\t0x0700\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG\t0x0800\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G\t0x0900\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G\t\t0x0A00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G\t\t0x0B00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G\t\t0x0C00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX\t0x0D00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4\t0x0E00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR\t0x0F00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI\t0x1B00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS\t0x1E00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI\t0x1F00\n-#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2\t0x3900\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE\t0x0001\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE\t0x0002\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS\t\t0x0004\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS\t\t0x0008\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE\t0x0010\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE\t0x0020\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE\t0x0040\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE\t0x0080\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK\t\t0x3f00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M\t\t0x0000\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M\t\t0x0100\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G\t\t0x0200\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G\t\t0x0300\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G\t\t0x0400\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G\t\t0x0500\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG\t0x0600\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4\t0x0700\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG\t0x0800\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G\t0x0900\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G\t\t0x0A00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G\t\t0x0B00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G\t\t0x0C00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX\t0x0D00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4\t0x0E00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR\t0x0F00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI\t0x1B00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS\t0x1E00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI\t0x1F00\n+\t#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2\t0x3900\n+\n \n #define\tMDIO_REG_BANK_10G_PARALLEL_DETECT\t\t0x8130\n #define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS\t\t0x10\n@@ -320,6 +313,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n Theotherbitsarereservedandshouldbezero*/\n #define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE\t0x0001\n \n+\n #define\tMDIO_PMA_DEVAD\t\t\t0x1\n /*ieee*/\n #define\tMDIO_PMA_REG_CTRL\t\t0x0\n@@ -328,7 +322,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_PMA_REG_TX_DISABLE\t\t0x0009\n #define\tMDIO_PMA_REG_RX_SD\t\t0xa\n /*bnx2x*/\n-#define\tMDIO_PMA_REG_BNX2X_CTRL\t\t0x0096\n+#define\tMDIO_PMA_REG_BCM_CTRL\t\t0x0096\n #define MDIO_PMA_REG_FEC_CTRL\t\t0x00ab\n #define\tMDIO_PMA_LASI_RXCTRL\t\t0x9000\n #define\tMDIO_PMA_LASI_TXCTRL\t\t0x9001\n@@ -343,8 +337,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define\tMDIO_PMA_REG_CMU_PLL_BYPASS\t0xca09\n #define\tMDIO_PMA_REG_MISC_CTRL\t\t0xca0a\n #define\tMDIO_PMA_REG_GEN_CTRL\t\t0xca10\n-#define\tMDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP\t0x0188\n-#define\tMDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET\t\t0x018a\n+\t#define\tMDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP\t0x0188\n+\t#define\tMDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET\t\t0x018a\n #define\tMDIO_PMA_REG_M8051_MSGIN_REG\t0xca12\n #define\tMDIO_PMA_REG_M8051_MSGOUT_REG\t0xca13\n #define\tMDIO_PMA_REG_ROM_VER1\t\t0xca19\n@@ -358,21 +352,21 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define\tMDIO_PMA_REG_MISC_CTRL1\t\t0xca85\n \n #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL\t\t0x8000\n-#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK \t0x000c\n-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE \t\t0x0000\n-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE \t0x0004\n-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS \t0x0008\n-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED \t0x000c\n+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK\t0x000c\n+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE\t\t0x0000\n+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE\t0x0004\n+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS\t0x0008\n+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED\t\t0x000c\n #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT \t0x8002\n #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR \t0x8003\n #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF\t0xc820\n-#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff\n+\t#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff\n #define MDIO_PMA_REG_8726_TX_CTRL1\t\t0xca01\n #define MDIO_PMA_REG_8726_TX_CTRL2\t\t0xca05\n \n #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR\t0x8005\n #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF\t0x8007\n-#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff\n+\t#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff\n #define MDIO_PMA_REG_8727_MISC_CTRL\t\t0x8309\n #define MDIO_PMA_REG_8727_TX_CTRL1\t\t0xca02\n #define MDIO_PMA_REG_8727_TX_CTRL2\t\t0xca05\n@@ -404,6 +398,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK\t0x800\n #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT\t11\n \n+\n+\n #define\tMDIO_WIS_DEVAD\t\t\t0x2\n /*bnx2x*/\n #define\tMDIO_WIS_REG_LASI_CNTL\t\t0x9002\n@@ -415,13 +411,15 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_PCS_REG_7101_DSP_ACCESS\t0xD000\n #define MDIO_PCS_REG_7101_SPI_MUX \t0xD008\n #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A\n-#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)\n+\t#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)\n #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A\n-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)\n-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)\n-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)\n+\t#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)\n+\t#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)\n+\t#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)\n #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028\n \n+\n+\n #define\tMDIO_XS_DEVAD\t\t\t0x4\n #define\tMDIO_XS_REG_STATUS\t\t0x0001\n #define MDIO_XS_PLL_SEQUENCER \t\t0x8000\n@@ -439,12 +437,12 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n /*ieee*/\n #define\tMDIO_AN_REG_CTRL\t\t0x0000\n #define\tMDIO_AN_REG_STATUS\t\t0x0001\n-#define\tMDIO_AN_REG_STATUS_AN_COMPLETE\t\t0x0020\n+\t#define\tMDIO_AN_REG_STATUS_AN_COMPLETE\t\t0x0020\n #define\tMDIO_AN_REG_ADV_PAUSE\t\t0x0010\n-#define\tMDIO_AN_REG_ADV_PAUSE_PAUSE\t\t0x0400\n-#define\tMDIO_AN_REG_ADV_PAUSE_ASYMMETRIC\t0x0800\n-#define\tMDIO_AN_REG_ADV_PAUSE_BOTH\t\t0x0C00\n-#define\tMDIO_AN_REG_ADV_PAUSE_MASK\t\t0x0C00\n+\t#define\tMDIO_AN_REG_ADV_PAUSE_PAUSE\t\t0x0400\n+\t#define\tMDIO_AN_REG_ADV_PAUSE_ASYMMETRIC\t0x0800\n+\t#define\tMDIO_AN_REG_ADV_PAUSE_BOTH\t\t0x0C00\n+\t#define\tMDIO_AN_REG_ADV_PAUSE_MASK\t\t0x0C00\n #define\tMDIO_AN_REG_ADV\t\t\t0x0011\n #define MDIO_AN_REG_ADV2\t\t0x0012\n #define\tMDIO_AN_REG_LP_AUTO_NEG\t\t0x0013\n@@ -465,13 +463,16 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n \n #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL\t0x0020\n #define MDIO_AN_REG_8481_LEGACY_MII_CTRL\t0xffe0\n-#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G\t0x40\n+\t#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G\t0x40\n #define MDIO_AN_REG_8481_LEGACY_MII_STATUS\t0xffe1\n+#define MDIO_AN_REG_848xx_ID_MSB\t\t0xffe2\n+\t#define BNX2X84858_PHY_ID\t\t\t\t\t0x600d\n+#define MDIO_AN_REG_848xx_ID_LSB\t\t0xffe3\n #define MDIO_AN_REG_8481_LEGACY_AN_ADV\t\t0xffe4\n #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION\t0xffe6\n #define MDIO_AN_REG_8481_1000T_CTRL\t\t0xffe9\n #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL\t0xfff0\n-#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF\t0x0008\n+\t#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF\t0x0008\n #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW\t0xfff5\n #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS\t0xfff7\n #define MDIO_AN_REG_8481_AUX_CTRL\t\t0xfff8\n@@ -480,62 +481,62 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n /* BNX2X84823 only */\n #define\tMDIO_CTL_DEVAD\t\t\t0x1e\n #define MDIO_CTL_REG_84823_MEDIA\t\t0x401a\n-#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK\t\t0x0018\n+\t#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK\t\t0x0018\n \t/* These pins configure the BNX2X84823 interface to MAC after reset. */\n-#define MDIO_CTL_REG_84823_CTRL_MAC_XFI\t\t\t0x0008\n-#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M\t\t0x0010\n+\t\t#define MDIO_CTL_REG_84823_CTRL_MAC_XFI\t\t\t0x0008\n+\t\t#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M\t\t0x0010\n \t/* These pins configure the BNX2X84823 interface to Line after reset. */\n-#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK\t\t0x0060\n-#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L\t\t0x0020\n-#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI\t\t0x0040\n+\t#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK\t\t0x0060\n+\t\t#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L\t\t0x0020\n+\t\t#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI\t\t0x0040\n \t/* When this pin is active high during reset, 10GBASE-T core is power\n \t * down, When it is active low the 10GBASE-T is power up\n \t */\n-#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN\t0x0080\n-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK\t\t0x0100\n-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER\t0x0000\n-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER\t\t0x0100\n-#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G\t\t\t0x1000\n+\t#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN\t0x0080\n+\t#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK\t\t0x0100\n+\t\t#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER\t0x0000\n+\t\t#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER\t\t0x0100\n+\t#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G\t\t\t0x1000\n #define MDIO_CTL_REG_84823_USER_CTRL_REG\t\t\t0x4005\n-#define MDIO_CTL_REG_84823_USER_CTRL_CMS\t\t\t0x0080\n+\t#define MDIO_CTL_REG_84823_USER_CTRL_CMS\t\t\t0x0080\n #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH\t\t0xa82b\n-#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ\t0x2f\n+\t#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ\t0x2f\n #define MDIO_PMA_REG_84823_CTL_LED_CTL_1\t\t\t0xa8e3\n #define MDIO_PMA_REG_84833_CTL_LED_CTL_1\t\t\t0xa8ec\n-#define MDIO_PMA_REG_84823_LED3_STRETCH_EN\t\t\t0x0080\n+\t#define MDIO_PMA_REG_84823_LED3_STRETCH_EN\t\t\t0x0080\n \n /* BNX2X84833 only */\n #define MDIO_84833_TOP_CFG_FW_REV\t\t\t0x400f\n-#define MDIO_84833_TOP_CFG_FW_EEE\t\t0x10b1\n-#define MDIO_84833_TOP_CFG_FW_NO_EEE\t\t0x1f81\n+#define MDIO_84833_TOP_CFG_FW_EEE\t\t\t0x10b1\n+#define MDIO_84833_TOP_CFG_FW_NO_EEE\t\t\t0x1f81\n #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 \t\t0x401a\n-#define MDIO_84833_SUPER_ISOLATE \t\t0x8000\n-/* These are mailbox register set used by 84833. */\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG0\t\t\t0x4005\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG1 \t\t0x4006\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG2\t\t\t0x4007\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG3\t\t\t0x4008\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG4\t\t\t0x4009\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG26\t\t0x4037\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG27\t\t0x4038\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG28\t\t0x4039\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG29\t\t0x403a\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG30\t\t0x403b\n-#define MDIO_84833_TOP_CFG_SCRATCH_REG31\t\t0x403c\n-#define MDIO_84833_CMD_HDLR_COMMAND\tMDIO_84833_TOP_CFG_SCRATCH_REG0\n-#define MDIO_84833_CMD_HDLR_STATUS\tMDIO_84833_TOP_CFG_SCRATCH_REG26\n-#define MDIO_84833_CMD_HDLR_DATA1\tMDIO_84833_TOP_CFG_SCRATCH_REG27\n-#define MDIO_84833_CMD_HDLR_DATA2\tMDIO_84833_TOP_CFG_SCRATCH_REG28\n-#define MDIO_84833_CMD_HDLR_DATA3\tMDIO_84833_TOP_CFG_SCRATCH_REG29\n-#define MDIO_84833_CMD_HDLR_DATA4\tMDIO_84833_TOP_CFG_SCRATCH_REG30\n-#define MDIO_84833_CMD_HDLR_DATA5\tMDIO_84833_TOP_CFG_SCRATCH_REG31\n-\n-/* Mailbox command set used by 84833. */\n-#define PHY84833_CMD_SET_PAIR_SWAP\t\t\t0x8001\n-#define PHY84833_CMD_GET_EEE_MODE\t\t\t0x8008\n-#define PHY84833_CMD_SET_EEE_MODE\t\t\t0x8009\n-#define PHY84833_CMD_GET_CURRENT_TEMP\t\t\t0x8031\n-/* Mailbox status set used by 84833. */\n+#define MDIO_84833_SUPER_ISOLATE\t\t\t0x8000\n+/* These are mailbox register set used by 84833/84858. */\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG0\t\t\t0x4005\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG1\t\t\t0x4006\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG2\t\t\t0x4007\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG3\t\t\t0x4008\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG4\t\t\t0x4009\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG26\t\t0x4037\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG27\t\t0x4038\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG28\t\t0x4039\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG29\t\t0x403a\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG30\t\t0x403b\n+#define MDIO_848xx_TOP_CFG_SCRATCH_REG31\t\t0x403c\n+#define MDIO_848xx_CMD_HDLR_COMMAND\t(MDIO_848xx_TOP_CFG_SCRATCH_REG0)\n+#define MDIO_848xx_CMD_HDLR_STATUS\t(MDIO_848xx_TOP_CFG_SCRATCH_REG26)\n+#define MDIO_848xx_CMD_HDLR_DATA1\t(MDIO_848xx_TOP_CFG_SCRATCH_REG27)\n+#define MDIO_848xx_CMD_HDLR_DATA2\t(MDIO_848xx_TOP_CFG_SCRATCH_REG28)\n+#define MDIO_848xx_CMD_HDLR_DATA3\t(MDIO_848xx_TOP_CFG_SCRATCH_REG29)\n+#define MDIO_848xx_CMD_HDLR_DATA4\t(MDIO_848xx_TOP_CFG_SCRATCH_REG30)\n+#define MDIO_848xx_CMD_HDLR_DATA5\t(MDIO_848xx_TOP_CFG_SCRATCH_REG31)\n+\n+/* Mailbox command set used by 84833/84858 */\n+#define PHY848xx_CMD_SET_PAIR_SWAP\t\t\t0x8001\n+#define PHY848xx_CMD_GET_EEE_MODE\t\t\t0x8008\n+#define PHY848xx_CMD_SET_EEE_MODE\t\t\t0x8009\n+#define PHY848xx_CMD_GET_CURRENT_TEMP\t\t\t0x8031\n+/* Mailbox status set used by 84833 only */\n #define PHY84833_STATUS_CMD_RECEIVED\t\t\t0x0001\n #define PHY84833_STATUS_CMD_IN_PROGRESS\t\t\t0x0002\n #define PHY84833_STATUS_CMD_COMPLETE_PASS\t\t0x0004\n@@ -545,6 +546,19 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS\t\t0x0040\n #define PHY84833_STATUS_CMD_CLEAR_COMPLETE\t\t0x0080\n #define PHY84833_STATUS_CMD_OPEN_OVERRIDE\t\t0xa5a5\n+/* Mailbox Process */\n+#define PHY84833_MB_PROCESS1\t\t\t\t1\n+#define PHY84833_MB_PROCESS2\t\t\t\t2\n+#define PHY84833_MB_PROCESS3\t\t\t\t3\n+\n+\n+/* Mailbox status set used by 84858 only */\n+#define PHY84858_STATUS_CMD_RECEIVED\t\t\t0x0001\n+#define PHY84858_STATUS_CMD_IN_PROGRESS\t\t\t0x0002\n+#define PHY84858_STATUS_CMD_COMPLETE_PASS\t\t0x0004\n+#define PHY84858_STATUS_CMD_COMPLETE_ERROR\t\t0x0008\n+#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb\n+\n \n /* Warpcore clause 45 addressing */\n #define MDIO_WC_DEVAD\t\t\t\t\t0x3\n@@ -553,8 +567,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10\n #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11\n #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12\n-#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY\t0x4000\n-#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ\t\t0x8000\n+\t#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY\t0x4000\n+\t#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ\t\t0x8000\n #define MDIO_WC_REG_PCS_STATUS2\t\t\t\t0x0021\n #define MDIO_WC_REG_PMD_KR_CONTROL\t\t\t0x0096\n #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000\n@@ -570,6 +584,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_WC_REG_TX2_ANA_CTRL0\t\t\t0x8081\n #define MDIO_WC_REG_TX3_ANA_CTRL0\t\t\t0x8091\n #define MDIO_WC_REG_TX0_TX_DRIVER\t\t\t0x8067\n+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET\t\t\t0x01\n+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK\t\t\t\t0x000e\n #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET\t\t0x04\n #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK\t\t\t0x00f0\n #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET\t\t0x08\n@@ -585,7 +601,9 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_WC_REG_RX1_PCI_CTRL\t\t\t0x80ca\n #define MDIO_WC_REG_RX2_PCI_CTRL\t\t\t0x80da\n #define MDIO_WC_REG_RX3_PCI_CTRL\t\t\t0x80ea\n+#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI\t\t0x80fa\n #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G \t\t0x8104\n+#define MDIO_WC_REG_XGXSBLK2_LANE_RESET\t\t\t0x810a\n #define MDIO_WC_REG_XGXS_STATUS3\t\t\t0x8129\n #define MDIO_WC_REG_PAR_DET_10G_STATUS\t\t\t0x8130\n #define MDIO_WC_REG_PAR_DET_10G_CTRL\t\t\t0x8131\n@@ -599,35 +617,35 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_WC_REG_GP2_STATUS_GP_2_2\t\t\t0x81d2\n #define MDIO_WC_REG_GP2_STATUS_GP_2_3\t\t\t0x81d3\n #define MDIO_WC_REG_GP2_STATUS_GP_2_4\t\t\t0x81d4\n-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000\n-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100\n-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010\n-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1\n+\t#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000\n+\t#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100\n+\t#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010\n+\t#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1\n #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE\n #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0\n #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE\t\t0x81F2\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET\t0x0\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET\t0x4\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET\t0x8\n-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET\t0xc\n+\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET\t0x0\n+\t\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0\n+\t\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1\n+\t\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2\n+\t\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3\n+\t\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4\n+\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET\t0x4\n+\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET\t0x8\n+\t#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET\t0xc\n #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE\n #define MDIO_WC_REG_DSC1B0_UC_CTRL\t\t\t\t0x820e\n #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD\t\t\t(1<<7)\n #define MDIO_WC_REG_DSC_SMC\t\t\t\t0x8213\n #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0\t\t0x821e\n #define MDIO_WC_REG_TX_FIR_TAP\t\t\t\t0x82e2\n-#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET\t\t0x00\n-#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK\t\t\t0x000f\n-#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET\t\t0x04\n-#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK\t\t0x03f0\n-#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET\t\t0x0a\n-#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK\t\t0x7c00\n-#define MDIO_WC_REG_TX_FIR_TAP_ENABLE\t\t0x8000\n+\t#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET\t\t0x00\n+\t#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK\t\t\t0x000f\n+\t#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET\t\t0x04\n+\t#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK\t\t0x03f0\n+\t#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET\t\t0x0a\n+\t#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK\t\t0x7c00\n+\t#define MDIO_WC_REG_TX_FIR_TAP_ENABLE\t\t0x8000\n #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP\t\t0x82e2\n #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3\n #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL\t0x82e6\n@@ -689,8 +707,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1\n \n #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A\n-#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT \t0\n-#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT \t4\n+#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT\t0\n+#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT\t4\n \n #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141\n \n@@ -700,33 +718,31 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n #define MDIO_REG_GPHY_MII_STATUS\t\t\t0x1\n #define MDIO_REG_GPHY_PHYID_LSB\t\t\t\t0x3\n #define MDIO_REG_GPHY_CL45_ADDR_REG\t\t\t0xd\n-#define MDIO_REG_GPHY_CL45_REG_WRITE\t\t0x4000\n-#define MDIO_REG_GPHY_CL45_REG_READ\t\t0xc000\n+\t#define MDIO_REG_GPHY_CL45_REG_WRITE\t\t0x4000\n+\t#define MDIO_REG_GPHY_CL45_REG_READ\t\t0xc000\n #define MDIO_REG_GPHY_CL45_DATA_REG\t\t\t0xe\n-#define MDIO_REG_GPHY_EEE_RESOLVED\t\t0x803e\n+\t#define MDIO_REG_GPHY_EEE_RESOLVED\t\t0x803e\n #define MDIO_REG_GPHY_EXP_ACCESS_GATE\t\t\t0x15\n #define MDIO_REG_GPHY_EXP_ACCESS\t\t\t0x17\n-#define MDIO_REG_GPHY_EXP_ACCESS_TOP\t\t0xd00\n-#define MDIO_REG_GPHY_EXP_TOP_2K_BUF\t\t0x40\n+\t#define MDIO_REG_GPHY_EXP_ACCESS_TOP\t\t0xd00\n+\t#define MDIO_REG_GPHY_EXP_TOP_2K_BUF\t\t0x40\n #define MDIO_REG_GPHY_AUX_STATUS\t\t\t0x19\n #define MDIO_REG_INTR_STATUS\t\t\t\t0x1a\n #define MDIO_REG_INTR_MASK\t\t\t\t0x1b\n-#define MDIO_REG_INTR_MASK_LINK_STATUS\t\t\t(0x1 << 1)\n+\t#define MDIO_REG_INTR_MASK_LINK_STATUS\t\t\t(0x1 << 1)\n #define MDIO_REG_GPHY_SHADOW\t\t\t\t0x1c\n-#define MDIO_REG_GPHY_SHADOW_LED_SEL1\t\t\t(0x0d << 10)\n-#define MDIO_REG_GPHY_SHADOW_LED_SEL2\t\t\t(0x0e << 10)\n-#define MDIO_REG_GPHY_SHADOW_WR_ENA\t\t\t(0x1 << 15)\n-#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED\t\t(0x1e << 10)\n-#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD\t\t(0x1 << 8)\n-\n-typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,\n-\t\t\t\t\t\t\tstruct elink_params *\n-\t\t\t\t\t\t\tparams,\n-\t\t\t\t\t\t\tuint8_t dev_addr,\n-\t\t\t\t\t\t\tuint16_t addr,\n-\t\t\t\t\t\t\tuint8_t byte_cnt,\n-\t\t\t\t\t\t\tuint8_t * o_buf,\n-\t\t\t\t\t\t\tuint8_t);\n+\t#define MDIO_REG_GPHY_SHADOW_LED_SEL1\t\t\t(0x0d << 10)\n+\t#define MDIO_REG_GPHY_SHADOW_LED_SEL2\t\t\t(0x0e << 10)\n+\t#define MDIO_REG_GPHY_SHADOW_WR_ENA\t\t\t(0x1 << 15)\n+\t#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED\t\t(0x1e << 10)\n+\t#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD\t\t(0x1 << 8)\n+\n+\n+typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,\n+\t\t\t\t\t struct elink_params *params,\n+\t\t\t\t\t uint8_t dev_addr, uint16_t addr,\n+\t\t\t\t\t uint8_t byte_cnt,\n+\t\t\t\t\t uint8_t *o_buf, uint8_t);\n /********************************************************/\n #define ELINK_ETH_HLEN\t\t\t14\n /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */\n@@ -850,21 +866,29 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,\n \t\t\t LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)\n \n #define ELINK_SFP_EEPROM_CON_TYPE_ADDR\t\t0x2\n-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC\t0x7\n-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER\t0x21\n-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45\t0x22\n+\t#define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN\t0x0\n+\t#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC\t0x7\n+\t#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER\t0x21\n+\t#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45\t0x22\n+\n+\n+#define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR\t\t0x3\n+\t#define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK\t(1 << 4)\n+\t#define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK\t(1 << 5)\n+\t#define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK\t(1 << 6)\n \n-#define ELINK_SFP_EEPROM_COMP_CODE_ADDR\t\t0x3\n-#define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK\t(1<<4)\n-#define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK\t(1<<5)\n-#define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK\t(1<<6)\n+#define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR\t\t0x6\n+\t#define ELINK_SFP_EEPROM_1G_COMP_CODE_SX\t(1 << 0)\n+\t#define ELINK_SFP_EEPROM_1G_COMP_CODE_LX\t(1 << 1)\n+\t#define ELINK_SFP_EEPROM_1G_COMP_CODE_CX\t(1 << 2)\n+\t#define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T\t(1 << 3)\n \n #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR\t\t0x8\n-#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4\n-#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8\n+\t#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4\n+\t#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8\n \n #define ELINK_SFP_EEPROM_OPTIONS_ADDR\t\t\t0x40\n-#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1\n+\t#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1\n #define ELINK_SFP_EEPROM_OPTIONS_SIZE\t\t\t2\n \n #define ELINK_EDC_MODE_LINEAR\t\t\t\t0x0022\n@@ -883,6 +907,10 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,\n \n #define ELINK_MAX_PACKET_SIZE\t\t\t\t\t(9700)\n #define MAX_KR_LINK_RETRY\t\t\t\t4\n+#define DEFAULT_TX_DRV_BRDCT\t\t2\n+#define DEFAULT_TX_DRV_IFIR\t\t0\n+#define DEFAULT_TX_DRV_POST2\t\t3\n+#define DEFAULT_TX_DRV_IPRE_DRIVER\t6\n \n /**********************************************************/\n /* INTERFACE */\n@@ -900,6 +928,11 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,\n \t\t(_bank + (_addr & 0xf)), \\\n \t\t_val)\n \n+static elink_status_t elink_check_half_open_conn(struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars, uint8_t notify);\n+static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params);\n+\n static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)\n {\n \tuint32_t val = REG_RD(sc, reg);\n@@ -935,16 +968,16 @@ static int elink_check_lfa(struct elink_params *params)\n \tstruct bnx2x_softc *sc = params->sc;\n \n \tadditional_config =\n-\t REG_RD(sc, params->lfa_base +\n-\t\t offsetof(struct shmem_lfa, additional_config));\n+\t\tREG_RD(sc, params->lfa_base +\n+\t\t\t offsetof(struct shmem_lfa, additional_config));\n \n \t/* NOTE: must be first condition checked -\n-\t * to verify DCC bit is cleared in any case!\n-\t */\n+\t* to verify DCC bit is cleared in any case!\n+\t*/\n \tif (additional_config & NO_LFA_DUE_TO_DCC_MASK) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"No LFA due to DCC flap after clp exit\");\n+\t\tELINK_DEBUG_P0(sc, \"No LFA due to DCC flap after clp exit\");\n \t\tREG_WR(sc, params->lfa_base +\n-\t\t offsetof(struct shmem_lfa, additional_config),\n+\t\t\t offsetof(struct shmem_lfa, additional_config),\n \t\t additional_config & ~NO_LFA_DUE_TO_DCC_MASK);\n \t\treturn LFA_DCC_LFA_DISABLED;\n \t}\n@@ -983,8 +1016,8 @@ static int elink_check_lfa(struct elink_params *params)\n \t\t\t offsetof(struct shmem_lfa, req_duplex));\n \treq_val = params->req_duplex[0] | (params->req_duplex[1] << 16);\n \tif ((saved_val & lfa_mask) != (req_val & lfa_mask)) {\n-\t\tPMD_DRV_LOG(INFO, sc, \"Duplex mismatch %x vs. %x\",\n-\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n+\t\tELINK_DEBUG_P2(sc, \"Duplex mismatch %x vs. %x\",\n+\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n \t\treturn LFA_DUPLEX_MISMATCH;\n \t}\n \t/* Compare Flow Control */\n@@ -992,8 +1025,8 @@ static int elink_check_lfa(struct elink_params *params)\n \t\t\t offsetof(struct shmem_lfa, req_flow_ctrl));\n \treq_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);\n \tif ((saved_val & lfa_mask) != (req_val & lfa_mask)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Flow control mismatch %x vs. %x\",\n-\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n+\t\tELINK_DEBUG_P2(sc, \"Flow control mismatch %x vs. %x\",\n+\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n \t\treturn LFA_FLOW_CTRL_MISMATCH;\n \t}\n \t/* Compare Link Speed */\n@@ -1001,8 +1034,8 @@ static int elink_check_lfa(struct elink_params *params)\n \t\t\t offsetof(struct shmem_lfa, req_line_speed));\n \treq_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);\n \tif ((saved_val & lfa_mask) != (req_val & lfa_mask)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Link speed mismatch %x vs. %x\",\n-\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n+\t\tELINK_DEBUG_P2(sc, \"Link speed mismatch %x vs. %x\",\n+\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n \t\treturn LFA_LINK_SPEED_MISMATCH;\n \t}\n \n@@ -1012,21 +1045,21 @@ static int elink_check_lfa(struct elink_params *params)\n \t\t\t\t\t\t speed_cap_mask[cfg_idx]));\n \n \t\tif (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Speed Cap mismatch %x vs. %x\",\n-\t\t\t\t cur_speed_cap_mask,\n-\t\t\t\t params->speed_cap_mask[cfg_idx]);\n+\t\t\tELINK_DEBUG_P2(sc, \"Speed Cap mismatch %x vs. %x\",\n+\t\t\t\t cur_speed_cap_mask,\n+\t\t\t\t params->speed_cap_mask[cfg_idx]);\n \t\t\treturn LFA_SPEED_CAP_MISMATCH;\n \t\t}\n \t}\n \n \tcur_req_fc_auto_adv =\n-\t REG_RD(sc, params->lfa_base +\n-\t\t offsetof(struct shmem_lfa, additional_config)) &\n-\t REQ_FC_AUTO_ADV_MASK;\n+\t\tREG_RD(sc, params->lfa_base +\n+\t\t offsetof(struct shmem_lfa, additional_config)) &\n+\t\tREQ_FC_AUTO_ADV_MASK;\n \n-\tif ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Flow Ctrl AN mismatch %x vs. %x\",\n-\t\t\t cur_req_fc_auto_adv, params->req_fc_auto_adv);\n+\tif ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {\n+\t\tELINK_DEBUG_P2(sc, \"Flow Ctrl AN mismatch %x vs. %x\",\n+\t\t\t cur_req_fc_auto_adv, params->req_fc_auto_adv);\n \t\treturn LFA_FLOW_CTRL_MISMATCH;\n \t}\n \n@@ -1038,27 +1071,25 @@ static int elink_check_lfa(struct elink_params *params)\n \t (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||\n \t ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^\n \t (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"EEE mismatch %x vs. %x\", params->eee_mode,\n-\t\t\t eee_status);\n+\t\tELINK_DEBUG_P2(sc, \"EEE mismatch %x vs. %x\", params->eee_mode,\n+\t\t\t eee_status);\n \t\treturn LFA_EEE_MISMATCH;\n \t}\n \n \t/* LFA conditions are met */\n \treturn 0;\n }\n-\n /******************************************************************/\n /*\t\t\tEPIO/GPIO section\t\t\t */\n /******************************************************************/\n static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,\n-\t\t\t uint32_t * en)\n+\t\t\t uint32_t *en)\n {\n \tuint32_t epio_mask, gp_oenable;\n \t*en = 0;\n \t/* Sanity check */\n \tif (epio_pin > 31) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid EPIO pin %d to get\", epio_pin);\n+\t\tELINK_DEBUG_P1(sc, \"Invalid EPIO pin %d to get\", epio_pin);\n \t\treturn;\n \t}\n \n@@ -1069,17 +1100,16 @@ static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,\n \n \t*en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;\n }\n-\n static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)\n {\n \tuint32_t epio_mask, gp_output, gp_oenable;\n \n \t/* Sanity check */\n \tif (epio_pin > 31) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid EPIO pin %d to set\", epio_pin);\n+\t\tELINK_DEBUG_P1(sc, \"Invalid EPIO pin %d to set\", epio_pin);\n \t\treturn;\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting EPIO pin %d to %d\", epio_pin, en);\n+\tELINK_DEBUG_P2(sc, \"Setting EPIO pin %d to %d\", epio_pin, en);\n \tepio_mask = 1 << epio_pin;\n \t/* Set this EPIO to output */\n \tgp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);\n@@ -1105,12 +1135,12 @@ static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,\n \t} else {\n \t\tuint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;\n \t\tuint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;\n-\t\telink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);\n+\t\telink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);\n \t}\n }\n \n static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,\n-\t\t\t\t uint32_t * val)\n+\t\t\t\t uint32_t *val)\n {\n \tif (pin_cfg == PIN_CFG_NA)\n \t\treturn ELINK_STATUS_ERROR;\n@@ -1122,14 +1152,939 @@ static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,\n \t\t*val = elink_cb_gpio_read(sc, gpio_num, gpio_port);\n \t}\n \treturn ELINK_STATUS_OK;\n+}\n+\n+/******************************************************************/\n+/*\t\t\t\tETS section\t\t\t */\n+/******************************************************************/\n+static void elink_ets_e2e3a0_disabled(struct elink_params *params)\n+{\n+\t/* ETS disabled configuration*/\n+\tstruct bnx2x_softc *sc = params->sc;\n+\n+\tELINK_DEBUG_P0(sc, \"ETS E2E3 disabled configuration\");\n+\n+\t/* mapping between entry priority to client number (0,1,2 -debug and\n+\t * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)\n+\t * 3bits client num.\n+\t * PRI4 | PRI3 | PRI2 | PRI1 | PRI0\n+\t * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000\n+\t */\n+\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);\n+\t/* Bitmap of 5bits length. Each bit specifies whether the entry behaves\n+\t * as strict. Bits 0,1,2 - debug and management entries, 3 -\n+\t * COS0 entry, 4 - COS1 entry.\n+\t * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT\n+\t * bit4 bit3\t bit2 bit1\t bit0\n+\t * MCP and debug are strict\n+\t */\n+\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);\n+\t/* defines which entries (clients) are subjected to WFQ arbitration */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);\n+\t/* For strict priority entries defines the number of consecutive\n+\t * slots for the highest priority.\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);\n+\t/* mapping between the CREDIT_WEIGHT registers and actual client\n+\t * numbers\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);\n+\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);\n+\tREG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);\n+\t/* ETS mode disable */\n+\tREG_WR(sc, PBF_REG_ETS_ENABLED, 0);\n+\t/* If ETS mode is enabled (there is no strict priority) defines a WFQ\n+\t * weight for COS0/COS1.\n+\t */\n+\tREG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);\n+\tREG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);\n+\t/* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */\n+\tREG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);\n+\tREG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);\n+\t/* Defines the number of consecutive slots for the strict priority */\n+\tREG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tGetting min_w_val will be set according to line speed .\n+ *.\n+ ******************************************************************************/\n+static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)\n+{\n+\tuint32_t min_w_val = 0;\n+\t/* Calculate min_w_val.*/\n+\tif (vars->link_up) {\n+\t\tif (vars->line_speed == ELINK_SPEED_20000)\n+\t\t\tmin_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;\n+\t\telse\n+\t\t\tmin_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;\n+\t} else {\n+\t\tmin_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;\n+\t}\n+\t/* If the link isn't up (static configuration for example ) The\n+\t * link will be according to 20GBPS.\n+\t */\n+\treturn min_w_val;\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tGetting credit upper bound form min_w_val.\n+ *.\n+ ******************************************************************************/\n+static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)\n+{\n+\tconst uint32_t credit_upper_bound = (uint32_t)\n+\t\t\t\t\t\tELINK_MAXVAL((150 * min_w_val),\n+\t\t\t\t\t\t\tELINK_MAX_PACKET_SIZE);\n+\treturn credit_upper_bound;\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tSet credit upper bound for NIG.\n+ *.\n+ ******************************************************************************/\n+static void elink_ets_e3b0_set_credit_upper_bound_nig(\n+\tconst struct elink_params *params,\n+\tconst uint32_t min_w_val)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint8_t port = params->port;\n+\tconst uint32_t credit_upper_bound =\n+\t elink_ets_get_credit_upper_bound(min_w_val);\n+\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :\n+\t\tNIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);\n+\n+\tif (!port) {\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,\n+\t\t\tcredit_upper_bound);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,\n+\t\t\tcredit_upper_bound);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,\n+\t\t\tcredit_upper_bound);\n+\t}\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tWill return the NIG ETS registers to init values.Except\n+ *\tcredit_upper_bound.\n+ *\tThat isn't used in this configuration (No WFQ is enabled) and will be\n+ *\tconfigured according to spec\n+ *.\n+ ******************************************************************************/\n+static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,\n+\t\t\t\t\tconst struct elink_vars *vars)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint8_t port = params->port;\n+\tconst uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);\n+\t/* Mapping between entry priority to client number (0,1,2 -debug and\n+\t * management clients, 3 - COS0 client, 4 - COS1, ... 8 -\n+\t * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by\n+\t * reset value or init tool\n+\t */\n+\tif (port) {\n+\t\tREG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);\n+\t\tREG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);\n+\t} else {\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);\n+\t}\n+\t/* For strict priority entries defines the number of consecutive\n+\t * slots for the highest priority.\n+\t */\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :\n+\t\t NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);\n+\t/* Mapping between the CREDIT_WEIGHT registers and actual client\n+\t * numbers\n+\t */\n+\tif (port) {\n+\t\t/*Port 1 has 6 COS*/\n+\t\tREG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);\n+\t\tREG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);\n+\t} else {\n+\t\t/*Port 0 has 9 COS*/\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,\n+\t\t 0x43210876);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);\n+\t}\n+\n+\t/* Bitmap of 5bits length. Each bit specifies whether the entry behaves\n+\t * as strict. Bits 0,1,2 - debug and management entries, 3 -\n+\t * COS0 entry, 4 - COS1 entry.\n+\t * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT\n+\t * bit4 bit3\t bit2 bit1\t bit0\n+\t * MCP and debug are strict\n+\t */\n+\tif (port)\n+\t\tREG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);\n+\telse\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);\n+\t/* defines which entries (clients) are subjected to WFQ arbitration */\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :\n+\t\t NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);\n+\n+\t/* Please notice the register address are note continuous and a\n+\t * for here is note appropriate.In 2 port mode port0 only COS0-5\n+\t * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4\n+\t * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT\n+\t * are never used for WFQ\n+\t */\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);\n+\tif (!port) {\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);\n+\t}\n+\n+\telink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tSet credit upper bound for PBF.\n+ *.\n+ ******************************************************************************/\n+static void elink_ets_e3b0_set_credit_upper_bound_pbf(\n+\tconst struct elink_params *params,\n+\tconst uint32_t min_w_val)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint32_t credit_upper_bound =\n+\t elink_ets_get_credit_upper_bound(min_w_val);\n+\tconst uint8_t port = params->port;\n+\tuint32_t base_upper_bound = 0;\n+\tuint8_t max_cos = 0;\n+\tuint8_t i = 0;\n+\t/* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4\n+\t * port mode port1 has COS0-2 that can be used for WFQ.\n+\t */\n+\tif (!port) {\n+\t\tbase_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;\n+\t\tmax_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;\n+\t} else {\n+\t\tbase_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;\n+\t\tmax_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;\n+\t}\n+\n+\tfor (i = 0; i < max_cos; i++)\n+\t\tREG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tWill return the PBF ETS registers to init values.Except\n+ *\tcredit_upper_bound.\n+ *\tThat isn't used in this configuration (No WFQ is enabled) and will be\n+ *\tconfigured according to spec\n+ *.\n+ ******************************************************************************/\n+static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint8_t port = params->port;\n+\tconst uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;\n+\tuint8_t i = 0;\n+\tuint32_t base_weight = 0;\n+\tuint8_t max_cos = 0;\n+\n+\t/* Mapping between entry priority to client number 0 - COS0\n+\t * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.\n+\t * TODO_ETS - Should be done by reset value or init tool\n+\t */\n+\tif (port)\n+\t\t/* 0x688 (|011|0 10|00 1|000) */\n+\t\tREG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, 0x688);\n+\telse\n+\t\t/* (10 1|100 |011|0 10|00 1|000) */\n+\t\tREG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, 0x2C688);\n+\n+\t/* TODO_ETS - Should be done by reset value or init tool */\n+\tif (port)\n+\t\t/* 0x688 (|011|0 10|00 1|000)*/\n+\t\tREG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);\n+\telse\n+\t/* 0x2C688 (10 1|100 |011|0 10|00 1|000) */\n+\tREG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);\n+\n+\tREG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :\n+\t\t PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0, 0x100);\n+\n+\n+\tREG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :\n+\t\t PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, 0);\n+\n+\tREG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :\n+\t\t PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 0);\n+\t/* In 2 port mode port0 has COS0-5 that can be used for WFQ.\n+\t * In 4 port mode port1 has COS0-2 that can be used for WFQ.\n+\t */\n+\tif (!port) {\n+\t\tbase_weight = PBF_REG_COS0_WEIGHT_P0;\n+\t\tmax_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;\n+\t} else {\n+\t\tbase_weight = PBF_REG_COS0_WEIGHT_P1;\n+\t\tmax_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;\n+\t}\n+\n+\tfor (i = 0; i < max_cos; i++)\n+\t\tREG_WR(sc, base_weight + (0x4 * i), 0);\n+\n+\telink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tE3B0 disable will return basicly the values to init values.\n+ *.\n+ ******************************************************************************/\n+static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,\n+\t\t\t\t const struct elink_vars *vars)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\n+\tif (!CHIP_IS_E3B0(sc)) {\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"elink_ets_e3b0_disabled the chip isn't E3B0\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\telink_ets_e3b0_nig_disabled(params, vars);\n+\n+\telink_ets_e3b0_pbf_disabled(params);\n+\n+\treturn ELINK_STATUS_OK;\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tDisable will return basicly the values to init values.\n+ *\n+ ******************************************************************************/\n+elink_status_t elink_ets_disabled(struct elink_params *params,\n+\t\t struct elink_vars *vars)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\telink_status_t elink_status = ELINK_STATUS_OK;\n+\n+\tif ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc))) {\n+\t\telink_ets_e2e3a0_disabled(params);\n+\t} else if (CHIP_IS_E3B0(sc)) {\n+\t\telink_status = elink_ets_e3b0_disabled(params, vars);\n+\t} else {\n+\t\tELINK_DEBUG_P0(sc, \"elink_ets_disabled - chip not supported\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\treturn elink_status;\n+}\n+\n+/******************************************************************************\n+ * Description\n+ *\tSet the COS mappimg to SP and BW until this point all the COS are not\n+ *\tset as SP or BW.\n+ ******************************************************************************/\n+static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,\n+\t\t __rte_unused const struct elink_ets_params *ets_params,\n+\t\t const uint8_t cos_sp_bitmap,\n+\t\t const uint8_t cos_bw_bitmap)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint8_t port = params->port;\n+\tconst uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);\n+\tconst uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;\n+\tconst uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;\n+\tconst uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;\n+\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :\n+\t NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);\n+\n+\tREG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :\n+\t PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, pbf_cli_sp_bitmap);\n+\n+\tREG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :\n+\t NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,\n+\t nig_cli_subject2wfq_bitmap);\n+\n+\tREG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :\n+\t PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,\n+\t pbf_cli_subject2wfq_bitmap);\n+\n+\treturn ELINK_STATUS_OK;\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tThis function is needed because NIG ARB_CREDIT_WEIGHT_X are\n+ *\tnot continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.\n+ ******************************************************************************/\n+static elink_status_t elink_ets_e3b0_set_cos_bw(struct bnx2x_softc *sc,\n+\t\t\t\t const uint8_t cos_entry,\n+\t\t\t\t const uint32_t min_w_val_nig,\n+\t\t\t\t const uint32_t min_w_val_pbf,\n+\t\t\t\t const uint16_t total_bw,\n+\t\t\t\t const uint8_t bw,\n+\t\t\t\t const uint8_t port)\n+{\n+\tuint32_t nig_reg_address_crd_weight = 0;\n+\tuint32_t pbf_reg_address_crd_weight = 0;\n+\t/* Calculate and set BW for this COS - use 1 instead of 0 for BW */\n+\tconst uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;\n+\tconst uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;\n+\n+\tswitch (cos_entry) {\n+\tcase 0:\n+\t nig_reg_address_crd_weight =\n+\t\t (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;\n+\t pbf_reg_address_crd_weight = (port) ?\n+\t\t PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;\n+\t\tbreak;\n+\tcase 1:\n+\t nig_reg_address_crd_weight = (port) ?\n+\t\t NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;\n+\t pbf_reg_address_crd_weight = (port) ?\n+\t\t PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;\n+\t\tbreak;\n+\tcase 2:\n+\t nig_reg_address_crd_weight = (port) ?\n+\t\t NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;\n+\n+\t\t pbf_reg_address_crd_weight = (port) ?\n+\t\t PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;\n+\t\tbreak;\n+\tcase 3:\n+\t\tif (port)\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\tnig_reg_address_crd_weight =\n+\t\t\tNIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;\n+\t\tpbf_reg_address_crd_weight =\n+\t\t\tPBF_REG_COS3_WEIGHT_P0;\n+\t\tbreak;\n+\tcase 4:\n+\t\tif (port)\n+\t\treturn ELINK_STATUS_ERROR;\n+\t nig_reg_address_crd_weight =\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;\n+\t pbf_reg_address_crd_weight = PBF_REG_COS4_WEIGHT_P0;\n+\t\tbreak;\n+\tcase 5:\n+\t\tif (port)\n+\t\treturn ELINK_STATUS_ERROR;\n+\t nig_reg_address_crd_weight =\n+\t\t NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;\n+\t pbf_reg_address_crd_weight = PBF_REG_COS5_WEIGHT_P0;\n+\t\tbreak;\n+\t}\n+\n+\tREG_WR(sc, nig_reg_address_crd_weight, cos_bw_nig);\n+\n+\tREG_WR(sc, pbf_reg_address_crd_weight, cos_bw_pbf);\n+\n+\treturn ELINK_STATUS_OK;\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tCalculate the total BW.A value of 0 isn't legal.\n+ *\n+ ******************************************************************************/\n+static elink_status_t elink_ets_e3b0_get_total_bw(\n+\tconst struct elink_params *params,\n+\tstruct elink_ets_params *ets_params,\n+\tuint16_t *total_bw)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tuint8_t cos_idx = 0;\n+\tuint8_t is_bw_cos_exist = 0;\n+\n+\t*total_bw = 0;\n+\t/* Calculate total BW requested */\n+\tfor (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {\n+\t\tif (ets_params->cos[cos_idx].state == elink_cos_state_bw) {\n+\t\t\tis_bw_cos_exist = 1;\n+\t\t\tif (!ets_params->cos[cos_idx].params.bw_params.bw) {\n+\t\t\t\tELINK_DEBUG_P0(sc, \"elink_ets_E3B0_config BW\"\n+\t\t\t\t\t\t \" was set to 0\");\n+\t\t\t\t/* This is to prevent a state when ramrods\n+\t\t\t\t * can't be sent\n+\t\t\t\t */\n+\t\t\t\tets_params->cos[cos_idx].params.bw_params.bw\n+\t\t\t\t\t = 1;\n+\t\t\t}\n+\t\t\t*total_bw +=\n+\t\t\t\tets_params->cos[cos_idx].params.bw_params.bw;\n+\t\t}\n+\t}\n+\n+\t/* Check total BW is valid */\n+\tif ((is_bw_cos_exist == 1) && (*total_bw != 100)) {\n+\t\tif (*total_bw == 0) {\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"elink_ets_E3B0_config total BW shouldn't be 0\");\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t}\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"elink_ets_E3B0_config total BW should be 100\");\n+\t\t/* We can handle a case whre the BW isn't 100 this can happen\n+\t\t * if the TC are joined.\n+\t\t */\n+\t}\n+\treturn ELINK_STATUS_OK;\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tInvalidate all the sp_pri_to_cos.\n+ *\n+ ******************************************************************************/\n+static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)\n+{\n+\tuint8_t pri = 0;\n+\tfor (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)\n+\t\tsp_pri_to_cos[pri] = DCBX_INVALID_COS;\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tCalculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers\n+ *\taccording to sp_pri_to_cos.\n+ *\n+ ******************************************************************************/\n+static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(\n+\t\t\t\t\t const struct elink_params *params,\n+\t\t\t\t\t uint8_t *sp_pri_to_cos,\n+\t\t\t\t\t const uint8_t pri,\n+\t\t\t\t\t const uint8_t cos_entry)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint8_t port = params->port;\n+\tconst uint8_t max_num_of_cos = (port) ?\n+\t\tELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :\n+\t\tELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;\n+\n+\tif (pri >= max_num_of_cos) {\n+\t\tELINK_DEBUG_P0(sc, \"elink_ets_e3b0_sp_pri_to_cos_set invalid \"\n+\t\t \"parameter Illegal strict priority\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\tif (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {\n+\t\tELINK_DEBUG_P0(sc, \"elink_ets_e3b0_sp_pri_to_cos_set invalid \"\n+\t\t\t\t \"parameter There can't be two COS's with \"\n+\t\t\t\t \"the same strict pri\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\tsp_pri_to_cos[pri] = cos_entry;\n+\treturn ELINK_STATUS_OK;\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tReturns the correct value according to COS and priority in\n+ *\tthe sp_pri_cli register.\n+ *\n+ ******************************************************************************/\n+static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos,\n+\t\t\t\t\t const uint8_t cos_offset,\n+\t\t\t\t\t const uint8_t pri_set,\n+\t\t\t\t\t const uint8_t pri_offset,\n+\t\t\t\t\t const uint8_t entry_size)\n+{\n+\tuint64_t pri_cli_nig = 0;\n+\tpri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *\n+\t\t\t\t\t\t (pri_set + pri_offset));\n+\n+\treturn pri_cli_nig;\n+}\n+/******************************************************************************\n+ * Description:\n+ *\tReturns the correct value according to COS and priority in the\n+ *\tsp_pri_cli register for NIG.\n+ *\n+ ******************************************************************************/\n+static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos,\n+\t\t\t\t\t\t const uint8_t pri_set)\n+{\n+\t/* MCP Dbg0 and dbg1 are always with higher strict pri*/\n+\tconst uint8_t nig_cos_offset = 3;\n+\tconst uint8_t nig_pri_offset = 3;\n+\n+\treturn elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,\n+\t\tnig_pri_offset, 4);\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tReturns the correct value according to COS and priority in the\n+ *\tsp_pri_cli register for PBF.\n+ *\n+ ******************************************************************************/\n+static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos,\n+\t\t\t\t\t\t const uint8_t pri_set)\n+{\n+\tconst uint8_t pbf_cos_offset = 0;\n+\tconst uint8_t pbf_pri_offset = 0;\n+\n+\treturn elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,\n+\t\tpbf_pri_offset, 3);\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tCalculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers\n+ *\taccording to sp_pri_to_cos.(which COS has higher priority)\n+ *\n+ ******************************************************************************/\n+static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(\n+\t\t\t\t\t const struct elink_params *params,\n+\t\t\t\t\t uint8_t *sp_pri_to_cos)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tuint8_t i = 0;\n+\tconst uint8_t port = params->port;\n+\t/* MCP Dbg0 and dbg1 are always with higher strict pri*/\n+\tuint64_t pri_cli_nig = 0x210;\n+\tuint32_t pri_cli_pbf = 0x0;\n+\tuint8_t pri_set = 0;\n+\tuint8_t pri_bitmask = 0;\n+\tconst uint8_t max_num_of_cos = (port) ?\n+\t\tELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :\n+\t\tELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;\n+\n+\tuint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;\n+\n+\t/* Set all the strict priority first */\n+\tfor (i = 0; i < max_num_of_cos; i++) {\n+\t\tif (sp_pri_to_cos[i] != DCBX_INVALID_COS) {\n+\t\t\tif (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {\n+\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t\t \"elink_ets_e3b0_sp_set_pri_cli_reg \"\n+\t\t\t\t\t \"invalid cos entry\");\n+\t\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t\t}\n+\n+\t\t\tpri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(\n+\t\t\t sp_pri_to_cos[i], pri_set);\n+\n+\t\t\tpri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(\n+\t\t\t sp_pri_to_cos[i], pri_set);\n+\t\t\tpri_bitmask = 1 << sp_pri_to_cos[i];\n+\t\t\t/* COS is used remove it from bitmap.*/\n+\t\t\tif (!(pri_bitmask & cos_bit_to_set)) {\n+\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t\t\"elink_ets_e3b0_sp_set_pri_cli_reg \"\n+\t\t\t\t\t\"invalid There can't be two COS's with\"\n+\t\t\t\t\t\" the same strict pri\");\n+\t\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t\t}\n+\t\t\tcos_bit_to_set &= ~pri_bitmask;\n+\t\t\tpri_set++;\n+\t\t}\n+\t}\n+\n+\t/* Set all the Non strict priority i= COS*/\n+\tfor (i = 0; i < max_num_of_cos; i++) {\n+\t\tpri_bitmask = 1 << i;\n+\t\t/* Check if COS was already used for SP */\n+\t\tif (pri_bitmask & cos_bit_to_set) {\n+\t\t\t/* COS wasn't used for SP */\n+\t\t\tpri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(\n+\t\t\t i, pri_set);\n+\n+\t\t\tpri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(\n+\t\t\t i, pri_set);\n+\t\t\t/* COS is used remove it from bitmap.*/\n+\t\t\tcos_bit_to_set &= ~pri_bitmask;\n+\t\t\tpri_set++;\n+\t\t}\n+\t}\n+\n+\tif (pri_set != max_num_of_cos) {\n+\t\tELINK_DEBUG_P0(sc, \"elink_ets_e3b0_sp_set_pri_cli_reg not all \"\n+\t\t\t\t \"entries were set\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\tif (port) {\n+\t\t/* Only 6 usable clients*/\n+\t\tREG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,\n+\t\t (uint32_t)pri_cli_nig);\n+\n+\t\tREG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, pri_cli_pbf);\n+\t} else {\n+\t\t/* Only 9 usable clients*/\n+\t\tconst uint32_t pri_cli_nig_lsb = (uint32_t)(pri_cli_nig);\n+\t\tconst uint32_t pri_cli_nig_msb = (uint32_t)\n+\t\t\t\t\t\t((pri_cli_nig >> 32) & 0xF);\n+\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,\n+\t\t pri_cli_nig_lsb);\n+\t\tREG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,\n+\t\t pri_cli_nig_msb);\n+\n+\t\tREG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, pri_cli_pbf);\n+\t}\n+\treturn ELINK_STATUS_OK;\n+}\n+\n+/******************************************************************************\n+ * Description:\n+ *\tConfigure the COS to ETS according to BW and SP settings.\n+ ******************************************************************************/\n+elink_status_t elink_ets_e3b0_config(const struct elink_params *params,\n+\t\t\t const struct elink_vars *vars,\n+\t\t\t struct elink_ets_params *ets_params)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\telink_status_t elink_status = ELINK_STATUS_OK;\n+\tconst uint8_t port = params->port;\n+\tuint16_t total_bw = 0;\n+\tconst uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);\n+\tconst uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;\n+\tuint8_t cos_bw_bitmap = 0;\n+\tuint8_t cos_sp_bitmap = 0;\n+\tuint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};\n+\tconst uint8_t max_num_of_cos = (port) ?\n+\t\tELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :\n+\t\tELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;\n+\tuint8_t cos_entry = 0;\n+\n+\tif (!CHIP_IS_E3B0(sc)) {\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"elink_ets_e3b0_disabled the chip isn't E3B0\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\tif (ets_params->num_of_cos > max_num_of_cos) {\n+\t\tELINK_DEBUG_P0(sc, \"elink_ets_E3B0_config the number of COS \"\n+\t\t\t\t \"isn't supported\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\t/* Prepare sp strict priority parameters*/\n+\telink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);\n+\n+\t/* Prepare BW parameters*/\n+\telink_status = elink_ets_e3b0_get_total_bw(params, ets_params,\n+\t\t\t\t\t\t &total_bw);\n+\tif (elink_status != ELINK_STATUS_OK) {\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"elink_ets_E3B0_config get_total_bw failed\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\t/* Upper bound is set according to current link speed (min_w_val\n+\t * should be the same for upper bound and COS credit val).\n+\t */\n+\telink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);\n+\telink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);\n+\n+\n+\tfor (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {\n+\t\tif (elink_cos_state_bw == ets_params->cos[cos_entry].state) {\n+\t\t\tcos_bw_bitmap |= (1 << cos_entry);\n+\t\t\t/* The function also sets the BW in HW(not the mappin\n+\t\t\t * yet)\n+\t\t\t */\n+\t\t\telink_status = elink_ets_e3b0_set_cos_bw(\n+\t\t\t\tsc, cos_entry, min_w_val_nig, min_w_val_pbf,\n+\t\t\t\ttotal_bw,\n+\t\t\t\tets_params->cos[cos_entry].params.bw_params.bw,\n+\t\t\t\t port);\n+\t\t} else if (elink_cos_state_strict ==\n+\t\t\tets_params->cos[cos_entry].state){\n+\t\t\tcos_sp_bitmap |= (1 << cos_entry);\n+\n+\t\t\telink_status = elink_ets_e3b0_sp_pri_to_cos_set(\n+\t\t\t\tparams,\n+\t\t\t\tsp_pri_to_cos,\n+\t\t\t\tets_params->cos[cos_entry].params.sp_params.pri,\n+\t\t\t\tcos_entry);\n+\n+\t\t} else {\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"elink_ets_e3b0_config cos state not valid\");\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t}\n+\t\tif (elink_status != ELINK_STATUS_OK) {\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"elink_ets_e3b0_config set cos bw failed\");\n+\t\t\treturn elink_status;\n+\t\t}\n+\t}\n+\n+\t/* Set SP register (which COS has higher priority) */\n+\telink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,\n+\t\t\t\t\t\t\t sp_pri_to_cos);\n+\n+\tif (elink_status != ELINK_STATUS_OK) {\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"elink_ets_E3B0_config set_pri_cli_reg failed\");\n+\t\treturn elink_status;\n+\t}\n+\n+\t/* Set client mapping of BW and strict */\n+\telink_status = elink_ets_e3b0_cli_map(params, ets_params,\n+\t\t\t\t\t cos_sp_bitmap,\n+\t\t\t\t\t cos_bw_bitmap);\n+\n+\tif (elink_status != ELINK_STATUS_OK) {\n+\t\tELINK_DEBUG_P0(sc, \"elink_ets_E3B0_config SP failed\");\n+\t\treturn elink_status;\n+\t}\n+\treturn ELINK_STATUS_OK;\n+}\n+static void elink_ets_bw_limit_common(const struct elink_params *params)\n+{\n+\t/* ETS disabled configuration */\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tELINK_DEBUG_P0(sc, \"ETS enabled BW limit configuration\");\n+\t/* Defines which entries (clients) are subjected to WFQ arbitration\n+\t * COS0 0x8\n+\t * COS1 0x10\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);\n+\t/* Mapping between the ARB_CREDIT_WEIGHT registers and actual\n+\t * client numbers (WEIGHT_0 does not actually have to represent\n+\t * client 0)\n+\t * PRI4 | PRI3 | PRI2 | PRI1 | PRI0\n+\t * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);\n+\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,\n+\t ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,\n+\t ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n+\n+\t/* ETS mode enabled*/\n+\tREG_WR(sc, PBF_REG_ETS_ENABLED, 1);\n+\n+\t/* Defines the number of consecutive slots for the strict priority */\n+\tREG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);\n+\t/* Bitmap of 5bits length. Each bit specifies whether the entry behaves\n+\t * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0\n+\t * entry, 4 - COS1 entry.\n+\t * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT\n+\t * bit4 bit3\t bit2 bit1\t bit0\n+\t * MCP and debug are strict\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);\n+\n+\t/* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/\n+\tREG_WR(sc, PBF_REG_COS0_UPPER_BOUND,\n+\t ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n+\tREG_WR(sc, PBF_REG_COS1_UPPER_BOUND,\n+\t ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n+}\n+\n+void elink_ets_bw_limit(const struct elink_params *params,\n+\t\t\tconst uint32_t cos0_bw,\n+\t\t\tconst uint32_t cos1_bw)\n+{\n+\t/* ETS disabled configuration*/\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tconst uint32_t total_bw = cos0_bw + cos1_bw;\n+\tuint32_t cos0_credit_weight = 0;\n+\tuint32_t cos1_credit_weight = 0;\n+\n+\tELINK_DEBUG_P0(sc, \"ETS enabled BW limit configuration\");\n \n+\tif ((!total_bw) ||\n+\t (!cos0_bw) ||\n+\t (!cos1_bw)) {\n+\t\tELINK_DEBUG_P0(sc, \"Total BW can't be zero\");\n+\t\treturn;\n+\t}\n+\n+\tcos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) /\n+\t\ttotal_bw;\n+\tcos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) /\n+\t\ttotal_bw;\n+\n+\telink_ets_bw_limit_common(params);\n+\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);\n+\n+\tREG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);\n+\tREG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);\n+}\n+\n+elink_status_t elink_ets_strict(const struct elink_params *params,\n+\t\t\t\tconst uint8_t strict_cos)\n+{\n+\t/* ETS disabled configuration*/\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tuint32_t val\t= 0;\n+\n+\tELINK_DEBUG_P0(sc, \"ETS enabled strict configuration\");\n+\t/* Bitmap of 5bits length. Each bit specifies whether the entry behaves\n+\t * as strict. Bits 0,1,2 - debug and management entries,\n+\t * 3 - COS0 entry, 4 - COS1 entry.\n+\t * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT\n+\t * bit4 bit3\t bit2 bit1 bit0\n+\t * MCP and debug are strict\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);\n+\t/* For strict priority entries defines the number of consecutive slots\n+\t * for the highest priority.\n+\t */\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);\n+\t/* ETS mode disable */\n+\tREG_WR(sc, PBF_REG_ETS_ENABLED, 0);\n+\t/* Defines the number of consecutive slots for the strict priority */\n+\tREG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);\n+\n+\t/* Defines the number of consecutive slots for the strict priority */\n+\tREG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);\n+\n+\t/* Mapping between entry priority to client number (0,1,2 -debug and\n+\t * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)\n+\t * 3bits client num.\n+\t * PRI4 | PRI3 | PRI2 | PRI1 | PRI0\n+\t * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000\n+\t * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000\n+\t */\n+\tval = (!strict_cos) ? 0x2318 : 0x22E0;\n+\tREG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);\n+\n+\treturn ELINK_STATUS_OK;\n }\n \n /******************************************************************/\n /*\t\t\tPFC section\t\t\t\t */\n /******************************************************************/\n static void elink_update_pfc_xmac(struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_vars *vars,\n+\t\t\t\t __rte_unused uint8_t is_lb)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t xmac_base;\n@@ -1144,7 +2099,8 @@ static void elink_update_pfc_xmac(struct elink_params *params,\n \tpfc1_val = 0x2;\n \n \t/* No PFC support */\n-\tif (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {\n+\tif (!(params->feature_config_flags &\n+\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) {\n \n \t\t/* RX flow control - Process pause frame in receive direction\n \t\t */\n@@ -1154,12 +2110,12 @@ static void elink_update_pfc_xmac(struct elink_params *params,\n \t\t/* TX flow control - Send pause packet when buffer is full */\n \t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n \t\t\tpause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;\n-\t} else {\t\t/* PFC support */\n+\t} else {/* PFC support */\n \t\tpfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |\n-\t\t XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |\n-\t\t XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |\n-\t\t XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |\n-\t\t XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;\n+\t\t\tXMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |\n+\t\t\tXMAC_PFC_CTRL_HI_REG_RX_PFC_EN |\n+\t\t\tXMAC_PFC_CTRL_HI_REG_TX_PFC_EN |\n+\t\t\tXMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;\n \t\t/* Write pause and PFC registers */\n \t\tREG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);\n \t\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);\n@@ -1173,21 +2129,76 @@ static void elink_update_pfc_xmac(struct elink_params *params,\n \tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);\n \tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);\n \n+\n \t/* Set MAC address for source TX Pause/PFC frames */\n \tREG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,\n \t ((params->mac_addr[2] << 24) |\n \t\t(params->mac_addr[3] << 16) |\n-\t\t(params->mac_addr[4] << 8) | (params->mac_addr[5])));\n+\t\t(params->mac_addr[4] << 8) |\n+\t\t(params->mac_addr[5])));\n \tREG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,\n-\t ((params->mac_addr[0] << 8) | (params->mac_addr[1])));\n+\t ((params->mac_addr[0] << 8) |\n+\t\t(params->mac_addr[1])));\n \n \tDELAY(30);\n }\n \n+static void elink_emac_get_pfc_stat(struct elink_params *params,\n+\t\t\t\t uint32_t pfc_frames_sent[2],\n+\t\t\t\t uint32_t pfc_frames_received[2])\n+{\n+\t/* Read pfc statistic */\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tuint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n+\tuint32_t val_xon = 0;\n+\tuint32_t val_xoff = 0;\n+\n+\tELINK_DEBUG_P0(sc, \"pfc statistic read from EMAC\");\n+\n+\t/* PFC received frames */\n+\tval_xoff = REG_RD(sc, emac_base +\n+\t\t\t\tEMAC_REG_RX_PFC_STATS_XOFF_RCVD);\n+\tval_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;\n+\tval_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);\n+\tval_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;\n+\n+\tpfc_frames_received[0] = val_xon + val_xoff;\n+\n+\t/* PFC received sent */\n+\tval_xoff = REG_RD(sc, emac_base +\n+\t\t\t\tEMAC_REG_RX_PFC_STATS_XOFF_SENT);\n+\tval_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;\n+\tval_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);\n+\tval_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;\n+\n+\tpfc_frames_sent[0] = val_xon + val_xoff;\n+}\n+\n+/* Read pfc statistic*/\n+void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,\n+\t\t\t uint32_t pfc_frames_sent[2],\n+\t\t\t uint32_t pfc_frames_received[2])\n+{\n+\t/* Read pfc statistic */\n+\tstruct bnx2x_softc *sc = params->sc;\n+\n+\tELINK_DEBUG_P0(sc, \"pfc statistic\");\n+\n+\tif (!vars->link_up)\n+\t\treturn;\n+\n+\tif (vars->mac_type == ELINK_MAC_TYPE_EMAC) {\n+\t\tELINK_DEBUG_P0(sc, \"About to read PFC stats from EMAC\");\n+\t\telink_emac_get_pfc_stat(params, pfc_frames_sent,\n+\t\t\t\t\tpfc_frames_received);\n+\t}\n+}\n /******************************************************************/\n /*\t\t\tMAC/PBF section\t\t\t\t */\n /******************************************************************/\n-static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)\n+static void elink_set_mdio_clk(struct bnx2x_softc *sc,\n+\t\t\t __rte_unused uint32_t chip_id,\n+\t\t\t uint32_t emac_base)\n {\n \tuint32_t new_mode, cur_mode;\n \tuint32_t clc_cnt;\n@@ -1206,26 +2217,16 @@ static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)\n \t\treturn;\n \n \tnew_mode = cur_mode &\n-\t ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);\n+\t\t~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);\n \tnew_mode |= clc_cnt;\n \tnew_mode |= (EMAC_MDIO_MODE_CLAUSE_45);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Changing emac_mode from 0x%x to 0x%x\",\n-\t\t cur_mode, new_mode);\n+\tELINK_DEBUG_P2(sc, \"Changing emac_mode from 0x%x to 0x%x\",\n+\t cur_mode, new_mode);\n \tREG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);\n \tDELAY(40);\n }\n \n-static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\tstruct elink_params *params)\n-{\n-\tuint8_t phy_index;\n-\t/* Set mdio clock per phy */\n-\tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n-\t phy_index++)\n-\t\telink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);\n-}\n-\n static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)\n {\n \tuint32_t port4mode_ovwr_val;\n@@ -1233,13 +2234,26 @@ static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)\n \tport4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);\n \tif (port4mode_ovwr_val & (1 << 0)) {\n \t\t/* Return 4-port mode override value */\n-\t\treturn (port4mode_ovwr_val & (1 << 1)) == (1 << 1);\n+\t\treturn ((port4mode_ovwr_val & (1 << 1)) == (1 << 1));\n \t}\n \t/* Return 4-port mode from input pin */\n-\treturn (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);\n+\treturn (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);\n }\n \n-static void elink_emac_init(struct elink_params *params)\n+static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,\n+\t\t\t\t\tstruct elink_params *params)\n+{\n+\tuint8_t phy_index;\n+\n+\t/* Set mdio clock per phy */\n+\tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n+\t phy_index++)\n+\t\telink_set_mdio_clk(sc, params->chip_id,\n+\t\t\t\t params->phy[phy_index].mdio_ctrl);\n+}\n+\n+static void elink_emac_init(struct elink_params *params,\n+\t\t\t __rte_unused struct elink_vars *vars)\n {\n \t/* reset and unreset the emac core */\n \tstruct bnx2x_softc *sc = params->sc;\n@@ -1263,9 +2277,9 @@ static void elink_emac_init(struct elink_params *params)\n \ttimeout = 200;\n \tdo {\n \t\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"EMAC reset reg is %u\", val);\n+\t\tELINK_DEBUG_P1(sc, \"EMAC reset reg is %u\", val);\n \t\tif (!timeout) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"EMAC timeout!\");\n+\t\t\tELINK_DEBUG_P0(sc, \"EMAC timeout!\");\n \t\t\treturn;\n \t\t}\n \t\ttimeout--;\n@@ -1273,17 +2287,20 @@ static void elink_emac_init(struct elink_params *params)\n \n \telink_set_mdio_emac_per_phy(sc, params);\n \t/* Set mac address */\n-\tval = ((params->mac_addr[0] << 8) | params->mac_addr[1]);\n+\tval = ((params->mac_addr[0] << 8) |\n+\t\tparams->mac_addr[1]);\n \telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);\n \n \tval = ((params->mac_addr[2] << 24) |\n \t (params->mac_addr[3] << 16) |\n-\t (params->mac_addr[4] << 8) | params->mac_addr[5]);\n+\t (params->mac_addr[4] << 8) |\n+\t\tparams->mac_addr[5]);\n \telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);\n }\n \n static void elink_set_xumac_nig(struct elink_params *params,\n-\t\t\t\tuint16_t tx_pause_en, uint8_t enable)\n+\t\t\t\tuint16_t tx_pause_en,\n+\t\t\t\tuint8_t enable)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \n@@ -1301,7 +2318,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)\n \tuint32_t val;\n \tstruct bnx2x_softc *sc = params->sc;\n \tif (!(REG_RD(sc, MISC_REG_RESET_REG_2) &\n-\t (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))\n+\t\t (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))\n \t\treturn;\n \tval = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);\n \tif (en)\n@@ -1315,7 +2332,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)\n }\n \n static void elink_umac_enable(struct elink_params *params,\n-\t\t\t struct elink_vars *vars, uint8_t lb)\n+\t\t\t struct elink_vars *vars, uint8_t lb)\n {\n \tuint32_t val;\n \tuint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;\n@@ -1328,15 +2345,15 @@ static void elink_umac_enable(struct elink_params *params,\n \tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n \t (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"enabling UMAC\");\n+\tELINK_DEBUG_P0(sc, \"enabling UMAC\");\n \n \t/* This register opens the gate for the UMAC despite its name */\n \tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);\n \n \tval = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |\n-\t UMAC_COMMAND_CONFIG_REG_PAD_EN |\n-\t UMAC_COMMAND_CONFIG_REG_SW_RESET |\n-\t UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;\n+\t\tUMAC_COMMAND_CONFIG_REG_PAD_EN |\n+\t\tUMAC_COMMAND_CONFIG_REG_SW_RESET |\n+\t\tUMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;\n \tswitch (vars->line_speed) {\n \tcase ELINK_SPEED_10:\n \t\tval |= (0 << 2);\n@@ -1351,8 +2368,8 @@ static void elink_umac_enable(struct elink_params *params,\n \t\tval |= (3 << 2);\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid speed for UMAC %d\",\n-\t\t\t vars->line_speed);\n+\t\tELINK_DEBUG_P1(sc, \"Invalid speed for UMAC %d\",\n+\t\t\t vars->line_speed);\n \t\tbreak;\n \t}\n \tif (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n@@ -1369,7 +2386,7 @@ static void elink_umac_enable(struct elink_params *params,\n \n \t/* Configure UMAC for EEE */\n \tif (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"configured UMAC for EEE\");\n+\t\tELINK_DEBUG_P0(sc, \"configured UMAC for EEE\");\n \t\tREG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,\n \t\t UMAC_UMAC_EEE_CTRL_REG_EEE_EN);\n \t\tREG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);\n@@ -1381,13 +2398,16 @@ static void elink_umac_enable(struct elink_params *params,\n \tREG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,\n \t ((params->mac_addr[2] << 24) |\n \t\t(params->mac_addr[3] << 16) |\n-\t\t(params->mac_addr[4] << 8) | (params->mac_addr[5])));\n+\t\t(params->mac_addr[4] << 8) |\n+\t\t(params->mac_addr[5])));\n \tREG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,\n-\t ((params->mac_addr[0] << 8) | (params->mac_addr[1])));\n+\t ((params->mac_addr[0] << 8) |\n+\t\t(params->mac_addr[1])));\n \n \t/* Enable RX and TX */\n \tval &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;\n-\tval |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;\n+\tval |= UMAC_COMMAND_CONFIG_REG_TX_ENA |\n+\t\tUMAC_COMMAND_CONFIG_REG_RX_ENA;\n \tREG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);\n \tDELAY(50);\n \n@@ -1427,7 +2447,8 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)\n \t is_port4mode &&\n \t (REG_RD(sc, MISC_REG_RESET_REG_2) &\n \t MISC_REGISTERS_RESET_REG_2_XMAC)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XMAC already out of reset in 4-port mode\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"XMAC already out of reset in 4-port mode\");\n \t\treturn;\n \t}\n \n@@ -1439,7 +2460,7 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)\n \tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n \t MISC_REGISTERS_RESET_REG_2_XMAC);\n \tif (is_port4mode) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Init XMAC to 2 ports x 10G per path\");\n+\t\tELINK_DEBUG_P0(sc, \"Init XMAC to 2 ports x 10G per path\");\n \n \t\t/* Set the number of ports on the system side to up to 2 */\n \t\tREG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);\n@@ -1450,13 +2471,13 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)\n \t\t/* Set the number of ports on the system side to 1 */\n \t\tREG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);\n \t\tif (max_speed == ELINK_SPEED_10000) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"Init XMAC to 10G x 1 port per path\");\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"Init XMAC to 10G x 1 port per path\");\n \t\t\t/* Set the number of ports on the Warp Core to 10G */\n \t\t\tREG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);\n \t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"Init XMAC to 20G x 2 ports per path\");\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"Init XMAC to 20G x 2 ports per path\");\n \t\t\t/* Set the number of ports on the Warp Core to 20G */\n \t\t\tREG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);\n \t\t}\n@@ -1478,7 +2499,8 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)\n \tuint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n \tuint32_t val;\n \n-\tif (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {\n+\tif (REG_RD(sc, MISC_REG_RESET_REG_2) &\n+\t MISC_REGISTERS_RESET_REG_2_XMAC) {\n \t\t/* Send an indication to change the state in the NIG back to XON\n \t\t * Clearing this bit enables the next set of this bit to get\n \t\t * rising edge\n@@ -1488,7 +2510,7 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)\n \t\t (pfc_ctrl & ~(1 << 1)));\n \t\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,\n \t\t (pfc_ctrl | (1 << 1)));\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Disable XMAC on port %x\", port);\n+\t\tELINK_DEBUG_P1(sc, \"Disable XMAC on port %x\", port);\n \t\tval = REG_RD(sc, xmac_base + XMAC_REG_CTRL);\n \t\tif (en)\n \t\t\tval |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);\n@@ -1499,11 +2521,11 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)\n }\n \n static elink_status_t elink_xmac_enable(struct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars, uint8_t lb)\n+\t\t\t struct elink_vars *vars, uint8_t lb)\n {\n \tuint32_t val, xmac_base;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"enabling XMAC\");\n+\tELINK_DEBUG_P0(sc, \"enabling XMAC\");\n \n \txmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n \n@@ -1537,10 +2559,10 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,\n \tREG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);\n \n \t/* update PFC */\n-\telink_update_pfc_xmac(params, vars);\n+\telink_update_pfc_xmac(params, vars, 0);\n \n \tif (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting XMAC for EEE\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting XMAC for EEE\");\n \t\tREG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);\n \t\tREG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);\n \t} else {\n@@ -1569,14 +2591,14 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,\n }\n \n static elink_status_t elink_emac_enable(struct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars, uint8_t lb)\n+\t\t\t struct elink_vars *vars, uint8_t lb)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n \tuint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n \tuint32_t val;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"enabling EMAC\");\n+\tELINK_DEBUG_P0(sc, \"enabling EMAC\");\n \n \t/* Disable BMAC */\n \tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n@@ -1585,19 +2607,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params,\n \t/* enable emac and not bmac */\n \tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);\n \n+#ifdef ELINK_INCLUDE_EMUL\n+\t/* for paladium */\n+\tif (CHIP_REV_IS_EMUL(sc)) {\n+\t\t/* Use lane 1 (of lanes 0-3) */\n+\t\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);\n+\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);\n+\t}\n+\t/* for fpga */\n+\telse\n+#endif\n+#ifdef ELINK_INCLUDE_FPGA\n+\tif (CHIP_REV_IS_FPGA(sc)) {\n+\t\t/* Use lane 1 (of lanes 0-3) */\n+\t\tELINK_DEBUG_P0(sc, \"elink_emac_enable: Setting FPGA\");\n+\n+\t\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);\n+\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);\n+\t} else\n+#endif\n+\t/* ASIC */\n \tif (vars->phy_flags & PHY_XGXS_FLAG) {\n \t\tuint32_t ser_lane = ((params->lane_config &\n-\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n-\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n+\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n+\t\t\t\tPORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XGXS\");\n+\t\tELINK_DEBUG_P0(sc, \"XGXS\");\n \t\t/* select the master lanes (out of 0-3) */\n \t\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);\n \t\t/* select XGXS */\n \t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);\n \n-\t} else {\t\t/* SerDes */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"SerDes\");\n+\t} else { /* SerDes */\n+\t\tELINK_DEBUG_P0(sc, \"SerDes\");\n \t\t/* select SerDes */\n \t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);\n \t}\n@@ -1607,28 +2649,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params,\n \telink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n \t\t EMAC_TX_MODE_RESET);\n \n-\t/* pause enable/disable */\n-\telink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,\n-\t\t EMAC_RX_MODE_FLOW_EN);\n-\n-\telink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n-\t\t (EMAC_TX_MODE_EXT_PAUSE_EN |\n-\t\t\tEMAC_TX_MODE_FLOW_EN));\n-\tif (!(params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) {\n-\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)\n-\t\t\telink_bits_en(sc, emac_base +\n-\t\t\t\t EMAC_REG_EMAC_RX_MODE,\n-\t\t\t\t EMAC_RX_MODE_FLOW_EN);\n+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n+\tif (CHIP_REV_IS_SLOW(sc)) {\n+\t\t/* config GMII mode */\n+\t\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);\n+\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,\n+\t\t\t\t (val | EMAC_MODE_PORT_GMII));\n+\t} else { /* ASIC */\n+#endif\n+\t\t/* pause enable/disable */\n+\t\telink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,\n+\t\t\t EMAC_RX_MODE_FLOW_EN);\n \n-\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n-\t\t\telink_bits_en(sc, emac_base +\n-\t\t\t\t EMAC_REG_EMAC_TX_MODE,\n-\t\t\t\t (EMAC_TX_MODE_EXT_PAUSE_EN |\n-\t\t\t\t EMAC_TX_MODE_FLOW_EN));\n-\t} else\n-\t\telink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n-\t\t\t EMAC_TX_MODE_FLOW_EN);\n+\t\telink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n+\t\t\t (EMAC_TX_MODE_EXT_PAUSE_EN |\n+\t\t\t\tEMAC_TX_MODE_FLOW_EN));\n+\t\tif (!(params->feature_config_flags &\n+\t\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) {\n+\t\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)\n+\t\t\t\telink_bits_en(sc, emac_base +\n+\t\t\t\t\t EMAC_REG_EMAC_RX_MODE,\n+\t\t\t\t\t EMAC_RX_MODE_FLOW_EN);\n+\n+\t\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n+\t\t\t\telink_bits_en(sc, emac_base +\n+\t\t\t\t\t EMAC_REG_EMAC_TX_MODE,\n+\t\t\t\t\t (EMAC_TX_MODE_EXT_PAUSE_EN |\n+\t\t\t\t\t EMAC_TX_MODE_FLOW_EN));\n+\t\t} else\n+\t\t\telink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n+\t\t\t\t EMAC_TX_MODE_FLOW_EN);\n+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n+\t}\n+#endif\n \n \t/* KEEP_VLAN_TAG, promiscuous */\n \tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);\n@@ -1643,18 +2696,18 @@ static elink_status_t elink_emac_enable(struct elink_params *params,\n \t */\n \telink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);\n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"PFC is enabled\");\n+\t\tELINK_DEBUG_P0(sc, \"PFC is enabled\");\n \t\t/* Enable PFC again */\n \t\telink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,\n-\t\t\t\t EMAC_REG_RX_PFC_MODE_RX_EN |\n-\t\t\t\t EMAC_REG_RX_PFC_MODE_TX_EN |\n-\t\t\t\t EMAC_REG_RX_PFC_MODE_PRIORITIES);\n+\t\t\tEMAC_REG_RX_PFC_MODE_RX_EN |\n+\t\t\tEMAC_REG_RX_PFC_MODE_TX_EN |\n+\t\t\tEMAC_REG_RX_PFC_MODE_PRIORITIES);\n \n \t\telink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,\n-\t\t\t\t ((0x0101 <<\n-\t\t\t\t EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |\n-\t\t\t\t (0x00ff <<\n-\t\t\t\t EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));\n+\t\t\t((0x0101 <<\n+\t\t\t EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |\n+\t\t\t (0x00ff <<\n+\t\t\t EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));\n \t\tval |= EMAC_RX_MODE_KEEP_MAC_CONTROL;\n \t}\n \telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);\n@@ -1672,9 +2725,8 @@ static elink_status_t elink_emac_enable(struct elink_params *params,\n \n \t/* Enable emac for jumbo packets */\n \telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,\n-\t\t\t (EMAC_RX_MTU_SIZE_JUMBO_ENA |\n-\t\t\t (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +\n-\t\t\t ELINK_ETH_OVREHEAD)));\n+\t\t(EMAC_RX_MTU_SIZE_JUMBO_ENA |\n+\t\t (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));\n \n \t/* Strip CRC */\n \tREG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);\n@@ -1688,13 +2740,23 @@ static elink_status_t elink_emac_enable(struct elink_params *params,\n \tREG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);\n \tval = 0;\n \tif ((params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n+\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n \t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n \t\tval = 1;\n \n \tREG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);\n \tREG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);\n \n+#ifdef ELINK_INCLUDE_EMUL\n+\tif (CHIP_REV_IS_EMUL(sc)) {\n+\t\t/* Take the BigMac out of reset */\n+\t\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n+\t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));\n+\n+\t\t/* Enable access for bmac registers */\n+\t\tREG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);\n+\t} else\n+#endif\n \tREG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);\n \n \tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n@@ -1706,13 +2768,13 @@ static void elink_update_pfc_bmac1(struct elink_params *params,\n {\n \tuint32_t wb_data[2];\n \tstruct bnx2x_softc *sc = params->sc;\n-\tuint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n-\t NIG_REG_INGRESS_BMAC0_MEM;\n+\tuint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n+\t\tNIG_REG_INGRESS_BMAC0_MEM;\n \n \tuint32_t val = 0x14;\n \tif ((!(params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&\n-\t (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n+\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&\n+\t\t(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n \t\t/* Enable BigMAC to react on received Pause packets */\n \t\tval |= (1 << 5);\n \twb_data[0] = val;\n@@ -1723,7 +2785,7 @@ static void elink_update_pfc_bmac1(struct elink_params *params,\n \tval = 0xc0;\n \tif (!(params->feature_config_flags &\n \t ELINK_FEATURE_CONFIG_PFC_ENABLED) &&\n-\t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n+\t\t(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n \t\tval |= 0x800000;\n \twb_data[0] = val;\n \twb_data[1] = 0;\n@@ -1731,7 +2793,8 @@ static void elink_update_pfc_bmac1(struct elink_params *params,\n }\n \n static void elink_update_pfc_bmac2(struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars, uint8_t is_lb)\n+\t\t\t\t struct elink_vars *vars,\n+\t\t\t\t uint8_t is_lb)\n {\n \t/* Set rx control: Strip CRC and enable BigMAC to relay\n \t * control packets to the system as well\n@@ -1739,12 +2802,12 @@ static void elink_update_pfc_bmac2(struct elink_params *params,\n \tuint32_t wb_data[2];\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n-\t NIG_REG_INGRESS_BMAC0_MEM;\n+\t\tNIG_REG_INGRESS_BMAC0_MEM;\n \tuint32_t val = 0x14;\n \n \tif ((!(params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&\n-\t (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n+\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&\n+\t\t(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n \t\t/* Enable BigMAC to react on received Pause packets */\n \t\tval |= (1 << 5);\n \twb_data[0] = val;\n@@ -1755,7 +2818,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,\n \t/* Tx control */\n \tval = 0xc0;\n \tif (!(params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED) &&\n+\t\t\t\tELINK_FEATURE_CONFIG_PFC_ENABLED) &&\n \t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n \t\tval |= 0x800000;\n \twb_data[0] = val;\n@@ -1763,21 +2826,21 @@ static void elink_update_pfc_bmac2(struct elink_params *params,\n \tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);\n \n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"PFC is enabled\");\n+\t\tELINK_DEBUG_P0(sc, \"PFC is enabled\");\n \t\t/* Enable PFC RX & TX & STATS and set 8 COS */\n \t\twb_data[0] = 0x0;\n-\t\twb_data[0] |= (1 << 0);\t/* RX */\n-\t\twb_data[0] |= (1 << 1);\t/* TX */\n-\t\twb_data[0] |= (1 << 2);\t/* Force initial Xon */\n-\t\twb_data[0] |= (1 << 3);\t/* 8 cos */\n-\t\twb_data[0] |= (1 << 5);\t/* STATS */\n+\t\twb_data[0] |= (1 << 0); /* RX */\n+\t\twb_data[0] |= (1 << 1); /* TX */\n+\t\twb_data[0] |= (1 << 2); /* Force initial Xon */\n+\t\twb_data[0] |= (1 << 3); /* 8 cos */\n+\t\twb_data[0] |= (1 << 5); /* STATS */\n \t\twb_data[1] = 0;\n \t\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,\n \t\t\t wb_data, 2);\n \t\t/* Clear the force Xon */\n \t\twb_data[0] &= ~(1 << 2);\n \t} else {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"PFC is disabled\");\n+\t\tELINK_DEBUG_P0(sc, \"PFC is disabled\");\n \t\t/* Disable PFC RX & TX & STATS and set 8 COS */\n \t\twb_data[0] = 0x8;\n \t\twb_data[1] = 0;\n@@ -1792,7 +2855,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,\n \t */\n \tval = 0x8000;\n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n-\t\tval |= (1 << 16);\t/* enable automatic re-send */\n+\t\tval |= (1 << 16); /* enable automatic re-send */\n \n \twb_data[0] = val;\n \twb_data[1] = 0;\n@@ -1800,10 +2863,10 @@ static void elink_update_pfc_bmac2(struct elink_params *params,\n \t\t wb_data, 2);\n \n \t/* mac control */\n-\tval = 0x3;\t\t/* Enable RX and TX */\n+\tval = 0x3; /* Enable RX and TX */\n \tif (is_lb) {\n-\t\tval |= 0x4;\t/* Local loopback */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"enable bmac loopback\");\n+\t\tval |= 0x4; /* Local loopback */\n+\t\tELINK_DEBUG_P0(sc, \"enable bmac loopback\");\n \t}\n \t/* When PFC enabled, Pass pause frames towards the NIG. */\n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n@@ -1815,47 +2878,46 @@ static void elink_update_pfc_bmac2(struct elink_params *params,\n }\n \n /******************************************************************************\n-* Description:\n-* This function is needed because NIG ARB_CREDIT_WEIGHT_X are\n-* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.\n-******************************************************************************/\n+ * Description:\n+ * This function is needed because NIG ARB_CREDIT_WEIGHT_X are\n+ * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.\n+ ******************************************************************************/\n static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t uint8_t cos_entry,\n-\t\t\t\t\t\t uint32_t priority_mask,\n-\t\t\t\t\t\t uint8_t port)\n+\t\t\t\t\t uint8_t cos_entry,\n+\t\t\t\t\t uint32_t priority_mask, uint8_t port)\n {\n \tuint32_t nig_reg_rx_priority_mask_add = 0;\n \n \tswitch (cos_entry) {\n \tcase 0:\n-\t\tnig_reg_rx_priority_mask_add = (port) ?\n-\t\t NIG_REG_P1_RX_COS0_PRIORITY_MASK :\n-\t\t NIG_REG_P0_RX_COS0_PRIORITY_MASK;\n+\t nig_reg_rx_priority_mask_add = (port) ?\n+\t\t NIG_REG_P1_RX_COS0_PRIORITY_MASK :\n+\t\t NIG_REG_P0_RX_COS0_PRIORITY_MASK;\n \t\tbreak;\n \tcase 1:\n-\t\tnig_reg_rx_priority_mask_add = (port) ?\n-\t\t NIG_REG_P1_RX_COS1_PRIORITY_MASK :\n-\t\t NIG_REG_P0_RX_COS1_PRIORITY_MASK;\n+\t nig_reg_rx_priority_mask_add = (port) ?\n+\t\tNIG_REG_P1_RX_COS1_PRIORITY_MASK :\n+\t\tNIG_REG_P0_RX_COS1_PRIORITY_MASK;\n \t\tbreak;\n \tcase 2:\n-\t\tnig_reg_rx_priority_mask_add = (port) ?\n-\t\t NIG_REG_P1_RX_COS2_PRIORITY_MASK :\n-\t\t NIG_REG_P0_RX_COS2_PRIORITY_MASK;\n+\t nig_reg_rx_priority_mask_add = (port) ?\n+\t\tNIG_REG_P1_RX_COS2_PRIORITY_MASK :\n+\t\tNIG_REG_P0_RX_COS2_PRIORITY_MASK;\n \t\tbreak;\n \tcase 3:\n \t\tif (port)\n-\t\t\treturn ELINK_STATUS_ERROR;\n-\t\tnig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;\n+\t\treturn ELINK_STATUS_ERROR;\n+\t nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;\n \t\tbreak;\n \tcase 4:\n \t\tif (port)\n-\t\t\treturn ELINK_STATUS_ERROR;\n-\t\tnig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;\n+\t\treturn ELINK_STATUS_ERROR;\n+\t nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;\n \t\tbreak;\n \tcase 5:\n \t\tif (port)\n-\t\t\treturn ELINK_STATUS_ERROR;\n-\t\tnig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;\n+\t\treturn ELINK_STATUS_ERROR;\n+\t nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;\n \t\tbreak;\n \t}\n \n@@ -1863,7 +2925,6 @@ static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,\n \n \treturn ELINK_STATUS_OK;\n }\n-\n static void elink_update_mng(struct elink_params *params, uint32_t link_status)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n@@ -1873,31 +2934,20 @@ static void elink_update_mng(struct elink_params *params, uint32_t link_status)\n \t\t\tport_mb[params->port].link_status), link_status);\n }\n \n-static void elink_update_link_attr(struct elink_params *params,\n-\t\t\t\t uint32_t link_attr)\n-{\n-\tstruct bnx2x_softc *sc = params->sc;\n-\n-\tif (SHMEM2_HAS(sc, link_attr_sync))\n-\t\tREG_WR(sc, params->shmem2_base +\n-\t\t offsetof(struct shmem2_region,\n-\t\t\t\tlink_attr_sync[params->port]), link_attr);\n-}\n-\n static void elink_update_pfc_nig(struct elink_params *params,\n-\t\t\t\t struct elink_nig_brb_pfc_port_params\n-\t\t\t\t *nig_params)\n+\t\t__rte_unused struct elink_vars *vars,\n+\t\tstruct elink_nig_brb_pfc_port_params *nig_params)\n {\n-\tuint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =\n-\t 0;\n+\tuint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0;\n+\tuint32_t llfc_out_en = 0;\n \tuint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;\n \tuint32_t pkt_priority_to_cos = 0;\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n \n \tint set_pfc = params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED;\n-\tPMD_DRV_LOG(DEBUG, sc, \"updating pfc nig parameters\");\n+\t\tELINK_FEATURE_CONFIG_PFC_ENABLED;\n+\tELINK_DEBUG_P0(sc, \"updating pfc nig parameters\");\n \n \t/* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set\n \t * MAC control frames (that are not pause packets)\n@@ -1917,19 +2967,19 @@ static void elink_update_pfc_nig(struct elink_params *params,\n \t\telse\n \t\t\tppp_enable = 1;\n \t\txcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :\n-\t\t\t NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);\n+\t\t\t\t NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);\n \t\txcm_out_en = 0;\n \t\thwpfc_enable = 1;\n-\t} else {\n+\t} else {\n \t\tif (nig_params) {\n \t\t\tllfc_out_en = nig_params->llfc_out_en;\n \t\t\tllfc_enable = nig_params->llfc_enable;\n \t\t\tpause_enable = nig_params->pause_enable;\n-\t\t} else\t\t/* Default non PFC mode - PAUSE */\n+\t\t} else /* Default non PFC mode - PAUSE */\n \t\t\tpause_enable = 1;\n \n \t\txcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :\n-\t\t\t NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);\n+\t\t\tNIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);\n \t\txcm_out_en = 1;\n \t}\n \n@@ -1966,9 +3016,7 @@ static void elink_update_pfc_nig(struct elink_params *params,\n \n \t\tfor (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)\n \t\t\telink_pfc_nig_rx_priority_mask(sc, i,\n-\t\t\t\t\t\t nig_params->\n-\t\t\t\t\t\t rx_cos_priority_mask[i],\n-\t\t\t\t\t\t port);\n+\t\tnig_params->rx_cos_priority_mask[i], port);\n \n \t\tREG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :\n \t\t NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,\n@@ -1979,13 +3027,13 @@ static void elink_update_pfc_nig(struct elink_params *params,\n \t\t nig_params->llfc_low_priority_classes);\n \t}\n \tREG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :\n-\t NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);\n+\t NIG_REG_P0_PKT_PRIORITY_TO_COS,\n+\t pkt_priority_to_cos);\n }\n \n elink_status_t elink_update_pfc(struct elink_params *params,\n-\t\t\t\tstruct elink_vars *vars,\n-\t\t\t\tstruct elink_nig_brb_pfc_port_params\n-\t\t\t\t*pfc_params)\n+\t\t struct elink_vars *vars,\n+\t\t struct elink_nig_brb_pfc_port_params *pfc_params)\n {\n \t/* The PFC and pause are orthogonal to one another, meaning when\n \t * PFC is enabled, the pause are disabled, and when PFC is\n@@ -1993,7 +3041,6 @@ elink_status_t elink_update_pfc(struct elink_params *params,\n \t */\n \tuint32_t val;\n \tstruct bnx2x_softc *sc = params->sc;\n-\telink_status_t elink_status = ELINK_STATUS_OK;\n \tuint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);\n \n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n@@ -2004,24 +3051,24 @@ elink_status_t elink_update_pfc(struct elink_params *params,\n \telink_update_mng(params, vars->link_status);\n \n \t/* Update NIG params */\n-\telink_update_pfc_nig(params, pfc_params);\n+\telink_update_pfc_nig(params, vars, pfc_params);\n \n \tif (!vars->link_up)\n-\t\treturn elink_status;\n+\t\treturn ELINK_STATUS_OK;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"About to update PFC in BMAC\");\n+\tELINK_DEBUG_P0(sc, \"About to update PFC in BMAC\");\n \n \tif (CHIP_IS_E3(sc)) {\n \t\tif (vars->mac_type == ELINK_MAC_TYPE_XMAC)\n-\t\t\telink_update_pfc_xmac(params, vars);\n+\t\t\telink_update_pfc_xmac(params, vars, 0);\n \t} else {\n \t\tval = REG_RD(sc, MISC_REG_RESET_REG_2);\n \t\tif ((val &\n \t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))\n \t\t == 0) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"About to update PFC in EMAC\");\n+\t\t\tELINK_DEBUG_P0(sc, \"About to update PFC in EMAC\");\n \t\t\telink_emac_enable(params, vars, 0);\n-\t\t\treturn elink_status;\n+\t\t\treturn ELINK_STATUS_OK;\n \t\t}\n \t\tif (CHIP_IS_E2(sc))\n \t\t\telink_update_pfc_bmac2(params, vars, bmac_loopback);\n@@ -2035,20 +3082,21 @@ elink_status_t elink_update_pfc(struct elink_params *params,\n \t\t\tval = 1;\n \t\tREG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);\n \t}\n-\treturn elink_status;\n+\treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_bmac1_enable(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars, uint8_t is_lb)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t uint8_t is_lb)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n \tuint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :\n-\t NIG_REG_INGRESS_BMAC0_MEM;\n+\t\t\t NIG_REG_INGRESS_BMAC0_MEM;\n \tuint32_t wb_data[2];\n \tuint32_t val;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Enabling BigMAC1\");\n+\tELINK_DEBUG_P0(sc, \"Enabling BigMAC1\");\n \n \t/* XGXS control */\n \twb_data[0] = 0x3c;\n@@ -2058,16 +3106,18 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,\n \n \t/* TX MAC SA */\n \twb_data[0] = ((params->mac_addr[2] << 24) |\n-\t\t (params->mac_addr[3] << 16) |\n-\t\t (params->mac_addr[4] << 8) | params->mac_addr[5]);\n-\twb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);\n+\t\t (params->mac_addr[3] << 16) |\n+\t\t (params->mac_addr[4] << 8) |\n+\t\t\tparams->mac_addr[5]);\n+\twb_data[1] = ((params->mac_addr[0] << 8) |\n+\t\t\tparams->mac_addr[1]);\n \tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);\n \n \t/* MAC control */\n \tval = 0x3;\n \tif (is_lb) {\n \t\tval |= 0x4;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"enable bmac loopback\");\n+\t\tELINK_DEBUG_P0(sc, \"enable bmac loopback\");\n \t}\n \twb_data[0] = val;\n \twb_data[1] = 0;\n@@ -2095,20 +3145,30 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,\n \twb_data[1] = 0;\n \tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,\n \t\t wb_data, 2);\n+#ifdef ELINK_INCLUDE_EMUL\n+\t/* Fix for emulation */\n+\tif (CHIP_REV_IS_EMUL(sc)) {\n+\t\twb_data[0] = 0xf000;\n+\t\twb_data[1] = 0;\n+\t\tREG_WR_DMAE(sc,\tbmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,\n+\t\t\t wb_data, 2);\n+\t}\n+#endif\n \n \treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_bmac2_enable(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars, uint8_t is_lb)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t uint8_t is_lb)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n \tuint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :\n-\t NIG_REG_INGRESS_BMAC0_MEM;\n+\t\t\t NIG_REG_INGRESS_BMAC0_MEM;\n \tuint32_t wb_data[2];\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Enabling BigMAC2\");\n+\tELINK_DEBUG_P0(sc, \"Enabling BigMAC2\");\n \n \twb_data[0] = 0;\n \twb_data[1] = 0;\n@@ -2125,9 +3185,11 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,\n \n \t/* TX MAC SA */\n \twb_data[0] = ((params->mac_addr[2] << 24) |\n-\t\t (params->mac_addr[3] << 16) |\n-\t\t (params->mac_addr[4] << 8) | params->mac_addr[5]);\n-\twb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);\n+\t\t (params->mac_addr[3] << 16) |\n+\t\t (params->mac_addr[4] << 8) |\n+\t\t\tparams->mac_addr[5]);\n+\twb_data[1] = ((params->mac_addr[0] << 8) |\n+\t\t\tparams->mac_addr[1]);\n \tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,\n \t\t wb_data, 2);\n \n@@ -2162,8 +3224,8 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,\n }\n \n static elink_status_t elink_bmac_enable(struct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars,\n-\t\t\t\t\tuint8_t is_lb, uint8_t reset_bmac)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t uint8_t is_lb, uint8_t reset_bmac)\n {\n \telink_status_t rc = ELINK_STATUS_OK;\n \tuint8_t port = params->port;\n@@ -2182,7 +3244,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,\n \t/* Enable access for bmac registers */\n \tREG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);\n \n-\t/* Enable BMAC according to BMAC type */\n+\t/* Enable BMAC according to BMAC type*/\n \tif (CHIP_IS_E2(sc))\n \t\trc = elink_bmac2_enable(params, vars, is_lb);\n \telse\n@@ -2192,7 +3254,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,\n \tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);\n \tval = 0;\n \tif ((params->feature_config_flags &\n-\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n+\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n \t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n \t\tval = 1;\n \tREG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);\n@@ -2206,13 +3268,15 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,\n \treturn rc;\n }\n \n-static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)\n+static void elink_set_bmac_rx(struct bnx2x_softc *sc,\n+\t\t\t __rte_unused uint32_t chip_id,\n+\t\t\t uint8_t port, uint8_t en)\n {\n \tuint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :\n-\t NIG_REG_INGRESS_BMAC0_MEM;\n+\t\t\tNIG_REG_INGRESS_BMAC0_MEM;\n \tuint32_t wb_data[2];\n-\tuint32_t nig_bmac_enable =\n-\t REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);\n+\tuint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN +\n+\t\t\t\t\t port * 4);\n \n \tif (CHIP_IS_E2(sc))\n \t\tbmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;\n@@ -2220,7 +3284,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)\n \t\tbmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;\n \t/* Only if the bmac is out of reset */\n \tif (REG_RD(sc, MISC_REG_RESET_REG_2) &\n-\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {\n+\t\t\t(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&\n+\t nig_bmac_enable) {\n \t\t/* Clear Rx Enable bit in BMAC_CONTROL register */\n \t\tREG_RD_DMAE(sc, bmac_addr, wb_data, 2);\n \t\tif (en)\n@@ -2233,7 +3298,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)\n }\n \n static elink_status_t elink_pbf_update(struct elink_params *params,\n-\t\t\t\t uint32_t flow_ctrl, uint32_t line_speed)\n+\t\t\t uint32_t flow_ctrl,\n+\t\t\t uint32_t line_speed)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n@@ -2246,7 +3312,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,\n \t/* Wait for init credit */\n \tinit_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);\n \tcrd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);\n-\tPMD_DRV_LOG(DEBUG, sc, \"init_crd 0x%x crd 0x%x\", init_crd, crd);\n+\tELINK_DEBUG_P2(sc, \"init_crd 0x%x crd 0x%x\", init_crd, crd);\n \n \twhile ((init_crd != crd) && count) {\n \t\tDELAY(1000 * 5);\n@@ -2255,24 +3321,25 @@ static elink_status_t elink_pbf_update(struct elink_params *params,\n \t}\n \tcrd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);\n \tif (init_crd != crd) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"BUG! init_crd 0x%x != crd 0x%x\",\n-\t\t\t init_crd, crd);\n+\t\tELINK_DEBUG_P2(sc, \"BUG! init_crd 0x%x != crd 0x%x\",\n+\t\t\t init_crd, crd);\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n \tif (flow_ctrl & ELINK_FLOW_CTRL_RX ||\n \t line_speed == ELINK_SPEED_10 ||\n \t line_speed == ELINK_SPEED_100 ||\n-\t line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {\n+\t line_speed == ELINK_SPEED_1000 ||\n+\t line_speed == ELINK_SPEED_2500) {\n \t\tREG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);\n \t\t/* Update threshold */\n \t\tREG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);\n \t\t/* Update init credit */\n-\t\tinit_crd = 778;\t/* (800-18-4) */\n+\t\tinit_crd = 778;\t\t/* (800-18-4) */\n \n \t} else {\n \t\tuint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +\n-\t\t\t\t ELINK_ETH_OVREHEAD) / 16;\n+\t\t\t ELINK_ETH_OVREHEAD) / 16;\n \t\tREG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);\n \t\t/* Update threshold */\n \t\tREG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);\n@@ -2282,14 +3349,14 @@ static elink_status_t elink_pbf_update(struct elink_params *params,\n \t\t\tinit_crd = thresh + 553 - 22;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid line_speed 0x%x\",\n-\t\t\t\t line_speed);\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid line_speed 0x%x\",\n+\t\t\t\t line_speed);\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \t}\n \tREG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);\n-\tPMD_DRV_LOG(DEBUG, sc, \"PBF updated to speed %d credit %d\",\n-\t\t line_speed, init_crd);\n+\tELINK_DEBUG_P2(sc, \"PBF updated to speed %d credit %d\",\n+\t\t line_speed, init_crd);\n \n \t/* Probe the credit changes */\n \tREG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);\n@@ -2317,7 +3384,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,\n * the emac_base for the CL45 read/writes operations\n */\n static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,\n-\t\t\t\t uint32_t mdc_mdio_access, uint8_t port)\n+\t\t\t uint32_t mdc_mdio_access, uint8_t port)\n {\n \tuint32_t emac_base = 0;\n \tswitch (mdc_mdio_access) {\n@@ -2365,7 +3432,8 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,\n \n \t/* Address */\n \ttmp = ((phy->addr << 21) | (reg << 16) | val |\n-\t EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);\n+\t EMAC_MDIO_COMM_COMMAND_WRITE_22 |\n+\t EMAC_MDIO_COMM_START_BUSY);\n \tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);\n \n \tfor (i = 0; i < 50; i++) {\n@@ -2378,7 +3446,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,\n \t\t}\n \t}\n \tif (tmp & EMAC_MDIO_COMM_START_BUSY) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"write phy register failed\");\n+\t\tELINK_DEBUG_P0(sc, \"write phy register failed\");\n \t\trc = ELINK_STATUS_TIMEOUT;\n \t}\n \tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);\n@@ -2387,7 +3455,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,\n \n static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,\n \t\t\t\t struct elink_phy *phy,\n-\t\t\t\t uint16_t reg, uint16_t * ret_val)\n+\t\t\t\t uint16_t reg, uint16_t *ret_val)\n {\n \tuint32_t val, mode;\n \tuint16_t i;\n@@ -2400,7 +3468,8 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,\n \n \t/* Address */\n \tval = ((phy->addr << 21) | (reg << 16) |\n-\t EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);\n+\t EMAC_MDIO_COMM_COMMAND_READ_22 |\n+\t EMAC_MDIO_COMM_START_BUSY);\n \tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);\n \n \tfor (i = 0; i < 50; i++) {\n@@ -2408,13 +3477,13 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,\n \n \t\tval = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);\n \t\tif (!(val & EMAC_MDIO_COMM_START_BUSY)) {\n-\t\t\t*ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);\n+\t\t\t*ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);\n \t\t\tDELAY(5);\n \t\t\tbreak;\n \t\t}\n \t}\n \tif (val & EMAC_MDIO_COMM_START_BUSY) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"read phy register failed\");\n+\t\tELINK_DEBUG_P0(sc, \"read phy register failed\");\n \n \t\t*ret_val = 0;\n \t\trc = ELINK_STATUS_TIMEOUT;\n@@ -2427,14 +3496,17 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,\n /*\t\t\tCL45 access functions\t\t\t */\n /******************************************************************/\n static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,\n-\t\t\t\t struct elink_phy *phy, uint8_t devad,\n-\t\t\t\t uint16_t reg, uint16_t * ret_val)\n+\t\t\t struct elink_phy *phy,\n+\t\t\t uint8_t devad, uint16_t reg, uint16_t *ret_val)\n {\n \tuint32_t val;\n \tuint16_t i;\n \telink_status_t rc = ELINK_STATUS_OK;\n+\tuint32_t chip_id;\n \tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {\n-\t\telink_set_mdio_clk(sc, phy->mdio_ctrl);\n+\t\tchip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |\n+\t\t\t ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);\n+\t\telink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);\n \t}\n \n \tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)\n@@ -2442,7 +3514,8 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,\n \t\t\t EMAC_MDIO_STATUS_10MB);\n \t/* Address */\n \tval = ((phy->addr << 21) | (devad << 16) | reg |\n-\t EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);\n+\t EMAC_MDIO_COMM_COMMAND_ADDRESS |\n+\t EMAC_MDIO_COMM_START_BUSY);\n \tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);\n \n \tfor (i = 0; i < 50; i++) {\n@@ -2455,8 +3528,9 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,\n \t\t}\n \t}\n \tif (val & EMAC_MDIO_COMM_START_BUSY) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"read phy register failed\");\n-\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n+\t\tELINK_DEBUG_P0(sc, \"read phy register failed\");\n+\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\n+\t\t/* \"MDC/MDIO access timeout\" */\n \n \t\t*ret_val = 0;\n \t\trc = ELINK_STATUS_TIMEOUT;\n@@ -2473,14 +3547,16 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,\n \t\t\tval = REG_RD(sc, phy->mdio_ctrl +\n \t\t\t\t EMAC_REG_EMAC_MDIO_COMM);\n \t\t\tif (!(val & EMAC_MDIO_COMM_START_BUSY)) {\n-\t\t\t\t*ret_val =\n-\t\t\t\t (uint16_t) (val & EMAC_MDIO_COMM_DATA);\n+\t\t\t\t*ret_val = (uint16_t)\n+\t\t\t\t\t\t(val & EMAC_MDIO_COMM_DATA);\n \t\t\t\tbreak;\n \t\t\t}\n \t\t}\n \t\tif (val & EMAC_MDIO_COMM_START_BUSY) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"read phy register failed\");\n-\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n+\t\t\tELINK_DEBUG_P0(sc, \"read phy register failed\");\n+\t\t\telink_cb_event_log(sc,\n+\t\t\t\t\t ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\n+\t\t\t/* \"MDC/MDIO access timeout\" */\n \n \t\t\t*ret_val = 0;\n \t\t\trc = ELINK_STATUS_TIMEOUT;\n@@ -2502,14 +3578,17 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,\n }\n \n static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,\n-\t\t\t\t struct elink_phy *phy, uint8_t devad,\n-\t\t\t\t uint16_t reg, uint16_t val)\n+\t\t\t struct elink_phy *phy,\n+\t\t\t uint8_t devad, uint16_t reg, uint16_t val)\n {\n \tuint32_t tmp;\n \tuint8_t i;\n \telink_status_t rc = ELINK_STATUS_OK;\n+\tuint32_t chip_id;\n \tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {\n-\t\telink_set_mdio_clk(sc, phy->mdio_ctrl);\n+\t\tchip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |\n+\t\t\t ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);\n+\t\telink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);\n \t}\n \n \tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)\n@@ -2518,7 +3597,8 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,\n \n \t/* Address */\n \ttmp = ((phy->addr << 21) | (devad << 16) | reg |\n-\t EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);\n+\t EMAC_MDIO_COMM_COMMAND_ADDRESS |\n+\t EMAC_MDIO_COMM_START_BUSY);\n \tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);\n \n \tfor (i = 0; i < 50; i++) {\n@@ -2531,8 +3611,9 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,\n \t\t}\n \t}\n \tif (tmp & EMAC_MDIO_COMM_START_BUSY) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"write phy register failed\");\n-\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n+\t\tELINK_DEBUG_P0(sc, \"write phy register failed\");\n+\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\n+\t\t/* \"MDC/MDIO access timeout\" */\n \n \t\trc = ELINK_STATUS_TIMEOUT;\n \t} else {\n@@ -2553,8 +3634,10 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,\n \t\t\t}\n \t\t}\n \t\tif (tmp & EMAC_MDIO_COMM_START_BUSY) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"write phy register failed\");\n-\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n+\t\t\tELINK_DEBUG_P0(sc, \"write phy register failed\");\n+\t\t\telink_cb_event_log(sc,\n+\t\t\t\t\t ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\n+\t\t\t/* \"MDC/MDIO access timeout\" */\n \n \t\t\trc = ELINK_STATUS_TIMEOUT;\n \t\t}\n@@ -2581,14 +3664,14 @@ static uint8_t elink_eee_has_cap(struct elink_params *params)\n \tstruct bnx2x_softc *sc = params->sc;\n \n \tif (REG_RD(sc, params->shmem2_base) <=\n-\t offsetof(struct shmem2_region, eee_status[params->port]))\n-\t\t return 0;\n+\t\t offsetof(struct shmem2_region, eee_status[params->port]))\n+\t\treturn 0;\n \n \treturn 1;\n }\n \n static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,\n-\t\t\t\t\t uint32_t * idle_timer)\n+\t\t\t\t\t uint32_t *idle_timer)\n {\n \tswitch (nvram_mode) {\n \tcase PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:\n@@ -2609,7 +3692,7 @@ static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,\n }\n \n static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,\n-\t\t\t\t\t uint32_t * nvram_mode)\n+\t\t\t\t\t uint32_t *nvram_mode)\n {\n \tswitch (idle_timer) {\n \tcase ELINK_EEE_MODE_NVRAM_BALANCED_TIME:\n@@ -2636,7 +3719,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)\n \n \tif (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {\n \t\tif (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {\n-\t\t\t/* time value in eee_mode --> used directly */\n+\t\t\t/* time value in eee_mode --> used directly*/\n \t\t\teee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;\n \t\t} else {\n \t\t\t/* hsi value in eee_mode --> time */\n@@ -2646,12 +3729,11 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)\n \t\t\t\treturn 0;\n \t\t}\n \t} else {\n-\t\t/* hsi values in nvram --> time */\n+\t\t/* hsi values in nvram --> time*/\n \t\teee_mode = ((REG_RD(sc, params->shmem_base +\n-\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_feature_config\n-\t\t\t\t\t [params->\n-\t\t\t\t\t port].eee_power_mode)) &\n+\t\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t port_feature_config[params->port].\n+\t\t\t\t eee_power_mode)) &\n \t\t\t PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>\n \t\t\t PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);\n \n@@ -2663,7 +3745,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)\n }\n \n static elink_status_t elink_eee_set_timers(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_vars *vars)\n {\n \tuint32_t eee_idle = 0, eee_mode;\n \tstruct bnx2x_softc *sc = params->sc;\n@@ -2676,7 +3758,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,\n \t} else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&\n \t\t (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&\n \t\t (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Error: Tx LPI is enabled with timer 0\");\n+\t\tELINK_DEBUG_P0(sc, \"Error: Tx LPI is enabled with timer 0\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n@@ -2685,7 +3767,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,\n \t\t/* eee_idle in 1u --> eee_status in 16u */\n \t\teee_idle >>= 4;\n \t\tvars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |\n-\t\t SHMEM_EEE_TIME_OUTPUT_BIT;\n+\t\t\t\t SHMEM_EEE_TIME_OUTPUT_BIT;\n \t} else {\n \t\tif (elink_eee_time_to_nvram(eee_idle, &eee_mode))\n \t\t\treturn ELINK_STATUS_ERROR;\n@@ -2696,8 +3778,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,\n }\n \n static elink_status_t elink_eee_initial_config(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t\t uint8_t mode)\n+\t\t\t\t struct elink_vars *vars, uint8_t mode)\n {\n \tvars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;\n \n@@ -2716,8 +3797,8 @@ static elink_status_t elink_eee_initial_config(struct elink_params *params,\n }\n \n static elink_status_t elink_eee_disable(struct elink_phy *phy,\n-\t\t\t\t\tstruct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars)\n+\t\t\t\tstruct elink_params *params,\n+\t\t\t\tstruct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \n@@ -2732,9 +3813,8 @@ static elink_status_t elink_eee_disable(struct elink_phy *phy,\n }\n \n static elink_status_t elink_eee_advertise(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t\t uint8_t modes)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars, uint8_t modes)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val = 0;\n@@ -2743,11 +3823,11 @@ static elink_status_t elink_eee_advertise(struct elink_phy *phy,\n \tREG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);\n \n \tif (modes & SHMEM_EEE_10G_ADV) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertise 10GBase-T EEE\");\n+\t\tELINK_DEBUG_P0(sc, \"Advertise 10GBase-T EEE\");\n \t\tval |= 0x8;\n \t}\n \tif (modes & SHMEM_EEE_1G_ADV) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertise 1GBase-T EEE\");\n+\t\tELINK_DEBUG_P0(sc, \"Advertise 1GBase-T EEE\");\n \t\tval |= 0x4;\n \t}\n \n@@ -2771,8 +3851,8 @@ static void elink_update_mng_eee(struct elink_params *params,\n }\n \n static void elink_eee_an_resolve(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t adv = 0, lp = 0;\n@@ -2787,7 +3867,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,\n \t\tif (adv & 0x2) {\n \t\t\tif (vars->line_speed == ELINK_SPEED_100)\n \t\t\t\tneg = 1;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"EEE negotiated - 100M\");\n+\t\t\tELINK_DEBUG_P0(sc, \"EEE negotiated - 100M\");\n \t\t}\n \t}\n \tif (lp & 0x14) {\n@@ -2795,7 +3875,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,\n \t\tif (adv & 0x14) {\n \t\t\tif (vars->line_speed == ELINK_SPEED_1000)\n \t\t\t\tneg = 1;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"EEE negotiated - 1G\");\n+\t\t\tELINK_DEBUG_P0(sc, \"EEE negotiated - 1G\");\n \t\t}\n \t}\n \tif (lp & 0x68) {\n@@ -2803,7 +3883,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,\n \t\tif (adv & 0x68) {\n \t\t\tif (vars->line_speed == ELINK_SPEED_10000)\n \t\t\t\tneg = 1;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"EEE negotiated - 10G\");\n+\t\t\tELINK_DEBUG_P0(sc, \"EEE negotiated - 10G\");\n \t\t}\n \t}\n \n@@ -2811,7 +3891,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,\n \tvars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);\n \n \tif (neg) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"EEE is active\");\n+\t\tELINK_DEBUG_P0(sc, \"EEE is active\");\n \t\tvars->eee_status |= SHMEM_EEE_ACTIVE_BIT;\n \t}\n }\n@@ -2832,37 +3912,34 @@ static void elink_bsc_module_sel(struct elink_params *params)\n \t\t\t\t dev_info.shared_hw_config.board));\n \ti2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;\n \ti2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>\n-\t SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;\n+\t\t\tSHARED_HW_CFG_E3_I2C_MUX1_SHIFT;\n \n \t/* Read I2C output value */\n \tsfp_ctrl = REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t e3_cmn_pin_cfg));\n+\t\t\t\t dev_info.port_hw_config[port].e3_cmn_pin_cfg));\n \ti2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;\n \ti2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting BSC switch\");\n+\tELINK_DEBUG_P0(sc, \"Setting BSC switch\");\n \tfor (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)\n \t\telink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);\n }\n \n-static elink_status_t elink_bsc_read(struct elink_params *params,\n-\t\t\t\t struct bnx2x_softc *sc,\n-\t\t\t\t uint8_t sl_devid,\n-\t\t\t\t uint16_t sl_addr,\n-\t\t\t\t uint8_t lc_addr,\n-\t\t\t\t uint8_t xfer_cnt, uint32_t * data_array)\n+static elink_status_t elink_bsc_read(struct bnx2x_softc *sc,\n+\t\t\t uint8_t sl_devid,\n+\t\t\t uint16_t sl_addr,\n+\t\t\t uint8_t lc_addr,\n+\t\t\t uint8_t xfer_cnt,\n+\t\t\t uint32_t *data_array)\n {\n \tuint32_t val, i;\n \telink_status_t rc = ELINK_STATUS_OK;\n \n \tif (xfer_cnt > 16) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"invalid xfer_cnt %d. Max is 16 bytes\",\n-\t\t\t xfer_cnt);\n+\t\tELINK_DEBUG_P1(sc, \"invalid xfer_cnt %d. Max is 16 bytes\",\n+\t\t\t\t\txfer_cnt);\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n-\tif (params)\n-\t\telink_bsc_module_sel(params);\n \n \txfer_cnt = 16 - lc_addr;\n \n@@ -2875,11 +3952,11 @@ static elink_status_t elink_bsc_read(struct elink_params *params,\n \tval = (sl_devid << 16) | sl_addr;\n \tREG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);\n \n-\t/* Start xfer with 0 byte to update the address pointer ??? */\n+\t/* Start xfer with 0 byte to update the address pointer ???*/\n \tval = (MCPR_IMC_COMMAND_ENABLE) |\n-\t (MCPR_IMC_COMMAND_WRITE_OP <<\n-\t MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |\n-\t (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);\n+\t (MCPR_IMC_COMMAND_WRITE_OP <<\n+\t\tMCPR_IMC_COMMAND_OPERATION_BITSHIFT) |\n+\t\t(lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);\n \tREG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);\n \n \t/* Poll for completion */\n@@ -2889,8 +3966,8 @@ static elink_status_t elink_bsc_read(struct elink_params *params,\n \t\tDELAY(10);\n \t\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n \t\tif (i++ > 1000) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"wr 0 byte timed out after %d try\",\n-\t\t\t\t i);\n+\t\t\tELINK_DEBUG_P1(sc, \"wr 0 byte timed out after %d try\",\n+\t\t\t\t\t\t\t\ti);\n \t\t\trc = ELINK_STATUS_TIMEOUT;\n \t\t\tbreak;\n \t\t}\n@@ -2900,10 +3977,10 @@ static elink_status_t elink_bsc_read(struct elink_params *params,\n \n \t/* Start xfer with read op */\n \tval = (MCPR_IMC_COMMAND_ENABLE) |\n-\t (MCPR_IMC_COMMAND_READ_OP <<\n-\t MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |\n-\t (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |\n-\t (xfer_cnt);\n+\t\t(MCPR_IMC_COMMAND_READ_OP <<\n+\t\tMCPR_IMC_COMMAND_OPERATION_BITSHIFT) |\n+\t\t(lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |\n+\t\t (xfer_cnt);\n \tREG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);\n \n \t/* Poll for completion */\n@@ -2913,8 +3990,7 @@ static elink_status_t elink_bsc_read(struct elink_params *params,\n \t\tDELAY(10);\n \t\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n \t\tif (i++ > 1000) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"rd op timed out after %d try\", i);\n+\t\t\tELINK_DEBUG_P1(sc, \"rd op timed out after %d try\", i);\n \t\t\trc = ELINK_STATUS_TIMEOUT;\n \t\t\tbreak;\n \t\t}\n@@ -2926,17 +4002,18 @@ static elink_status_t elink_bsc_read(struct elink_params *params,\n \t\tdata_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));\n #ifdef __BIG_ENDIAN\n \t\tdata_array[i] = ((data_array[i] & 0x000000ff) << 24) |\n-\t\t ((data_array[i] & 0x0000ff00) << 8) |\n-\t\t ((data_array[i] & 0x00ff0000) >> 8) |\n-\t\t ((data_array[i] & 0xff000000) >> 24);\n+\t\t\t\t((data_array[i] & 0x0000ff00) << 8) |\n+\t\t\t\t((data_array[i] & 0x00ff0000) >> 8) |\n+\t\t\t\t((data_array[i] & 0xff000000) >> 24);\n #endif\n \t}\n \treturn rc;\n }\n \n static void elink_cl45_read_or_write(struct bnx2x_softc *sc,\n-\t\t\t\t struct elink_phy *phy, uint8_t devad,\n-\t\t\t\t uint16_t reg, uint16_t or_val)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint8_t devad, uint16_t reg,\n+\t\t\t\t uint16_t or_val)\n {\n \tuint16_t val;\n \telink_cl45_read(sc, phy, devad, reg, &val);\n@@ -2953,7 +4030,42 @@ static void elink_cl45_read_and_write(struct bnx2x_softc *sc,\n \telink_cl45_write(sc, phy, devad, reg, val & and_val);\n }\n \n-static uint8_t elink_get_warpcore_lane(struct elink_params *params)\n+elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,\n+\t\t uint8_t devad, uint16_t reg, uint16_t *ret_val)\n+{\n+\tuint8_t phy_index;\n+\t/* Probe for the phy according to the given phy_addr, and execute\n+\t * the read request on it\n+\t */\n+\tfor (phy_index = 0; phy_index < params->num_phys; phy_index++) {\n+\t\tif (params->phy[phy_index].addr == phy_addr) {\n+\t\t\treturn elink_cl45_read(params->sc,\n+\t\t\t\t\t ¶ms->phy[phy_index], devad,\n+\t\t\t\t\t reg, ret_val);\n+\t\t}\n+\t}\n+\treturn ELINK_STATUS_ERROR;\n+}\n+\n+elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,\n+\t\t uint8_t devad, uint16_t reg, uint16_t val)\n+{\n+\tuint8_t phy_index;\n+\t/* Probe for the phy according to the given phy_addr, and execute\n+\t * the write request on it\n+\t */\n+\tfor (phy_index = 0; phy_index < params->num_phys; phy_index++) {\n+\t\tif (params->phy[phy_index].addr == phy_addr) {\n+\t\t\treturn elink_cl45_write(params->sc,\n+\t\t\t\t\t\t¶ms->phy[phy_index], devad,\n+\t\t\t\t\t\treg, val);\n+\t\t}\n+\t}\n+\treturn ELINK_STATUS_ERROR;\n+}\n+\n+static uint8_t elink_get_warpcore_lane(__rte_unused struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params)\n {\n \tuint8_t lane = 0;\n \tstruct bnx2x_softc *sc = params->sc;\n@@ -2987,14 +4099,16 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params)\n \t\t\tport = port ^ 1;\n \n \t\tlane = (port << 1) + path;\n-\t} else {\t\t/* Two port mode - no port swap */\n+\t} else { /* Two port mode - no port swap */\n \n \t\t/* Figure out path swap value */\n-\t\tpath_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);\n+\t\tpath_swap_ovr =\n+\t\t\tREG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);\n \t\tif (path_swap_ovr & 0x1) {\n \t\t\tpath_swap = (path_swap_ovr & 0x2);\n \t\t} else {\n-\t\t\tpath_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);\n+\t\t\tpath_swap =\n+\t\t\t\tREG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);\n \t\t}\n \t\tif (path_swap)\n \t\t\tpath = path ^ 1;\n@@ -3004,6 +4118,7 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params)\n \treturn lane;\n }\n \n+\n static void elink_set_aer_mmd(struct elink_params *params,\n \t\t\t struct elink_phy *phy)\n {\n@@ -3012,13 +4127,13 @@ static void elink_set_aer_mmd(struct elink_params *params,\n \tstruct bnx2x_softc *sc = params->sc;\n \tser_lane = ((params->lane_config &\n \t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n-\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n+\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n \n \toffset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?\n-\t (phy->addr + ser_lane) : 0;\n+\t\t(phy->addr + ser_lane) : 0;\n \n \tif (USES_WARPCORE(sc)) {\n-\t\taer_val = elink_get_warpcore_lane(params);\n+\t\taer_val = elink_get_warpcore_lane(phy, params);\n \t\t/* In Dual-lane mode, two lanes are joined together,\n \t\t * so in order to configure them, the AER broadcast method is\n \t\t * used here.\n@@ -3051,7 +4166,7 @@ static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)\n \tDELAY(500);\n \tREG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);\n \tDELAY(500);\n-\t/* Set Clause 45 */\n+\t /* Set Clause 45 */\n \tREG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);\n }\n \n@@ -3059,7 +4174,7 @@ static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)\n {\n \tuint32_t val;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"elink_serdes_deassert\");\n+\tELINK_DEBUG_P0(sc, \"elink_serdes_deassert\");\n \n \tval = ELINK_SERDES_RESET_BITS << (port * 16);\n \n@@ -3094,7 +4209,7 @@ static void elink_xgxs_deassert(struct elink_params *params)\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port;\n \tuint32_t val;\n-\tPMD_DRV_LOG(DEBUG, sc, \"elink_xgxs_deassert\");\n+\tELINK_DEBUG_P0(sc, \"elink_xgxs_deassert\");\n \tport = params->port;\n \n \tval = ELINK_XGXS_RESET_BITS << (port * 16);\n@@ -3109,8 +4224,9 @@ static void elink_xgxs_deassert(struct elink_params *params)\n \n static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params,\n-\t\t\t\t uint16_t * ieee_fc)\n+\t\t\t\t uint16_t *ieee_fc)\n {\n+\tstruct bnx2x_softc *sc = params->sc;\n \t*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;\n \t/* Resolve pause mode and advertisement Please refer to Table\n \t * 28B-3 of the 802.3ab-1999 spec\n@@ -3120,12 +4236,12 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,\n \tcase ELINK_FLOW_CTRL_AUTO:\n \t\tswitch (params->req_fc_auto_adv) {\n \t\tcase ELINK_FLOW_CTRL_BOTH:\n+\t\tcase ELINK_FLOW_CTRL_RX:\n \t\t\t*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;\n \t\t\tbreak;\n-\t\tcase ELINK_FLOW_CTRL_RX:\n \t\tcase ELINK_FLOW_CTRL_TX:\n \t\t\t*ieee_fc |=\n-\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n+\t\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n@@ -3145,16 +4261,18 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,\n \t\t*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;\n \t\tbreak;\n \t}\n-\tPMD_DRV_LOG(DEBUG, params->sc, \"ieee_fc = 0x%x\", *ieee_fc);\n+\tELINK_DEBUG_P1(sc, \"ieee_fc = 0x%x\", *ieee_fc);\n }\n \n-static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)\n+static void set_phy_vars(struct elink_params *params,\n+\t\t\t struct elink_vars *vars)\n {\n+\tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t actual_phy_idx, phy_index, link_cfg_idx;\n \tuint8_t phy_config_swapped = params->multi_phy_config &\n-\t PORT_HW_CFG_PHY_SWAPPED_ENABLED;\n+\t\t\tPORT_HW_CFG_PHY_SWAPPED_ENABLED;\n \tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n-\t phy_index++) {\n+\t phy_index++) {\n \t\tlink_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);\n \t\tactual_phy_idx = phy_index;\n \t\tif (phy_config_swapped) {\n@@ -3164,26 +4282,26 @@ static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)\n \t\t\t\tactual_phy_idx = ELINK_EXT_PHY1;\n \t\t}\n \t\tparams->phy[actual_phy_idx].req_flow_ctrl =\n-\t\t params->req_flow_ctrl[link_cfg_idx];\n+\t\t\tparams->req_flow_ctrl[link_cfg_idx];\n \n \t\tparams->phy[actual_phy_idx].req_line_speed =\n-\t\t params->req_line_speed[link_cfg_idx];\n+\t\t\tparams->req_line_speed[link_cfg_idx];\n \n \t\tparams->phy[actual_phy_idx].speed_cap_mask =\n-\t\t params->speed_cap_mask[link_cfg_idx];\n+\t\t\tparams->speed_cap_mask[link_cfg_idx];\n \n \t\tparams->phy[actual_phy_idx].req_duplex =\n-\t\t params->req_duplex[link_cfg_idx];\n+\t\t\tparams->req_duplex[link_cfg_idx];\n \n \t\tif (params->req_line_speed[link_cfg_idx] ==\n \t\t ELINK_SPEED_AUTO_NEG)\n \t\t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;\n \n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"req_flow_ctrl %x, req_line_speed %x,\"\n-\t\t\t \" speed_cap_mask %x\",\n-\t\t\t params->phy[actual_phy_idx].req_flow_ctrl,\n-\t\t\t params->phy[actual_phy_idx].req_line_speed,\n-\t\t\t params->phy[actual_phy_idx].speed_cap_mask);\n+\t\tELINK_DEBUG_P3(sc, \"req_flow_ctrl %x, req_line_speed %x,\"\n+\t\t\t \" speed_cap_mask %x\",\n+\t\t\t params->phy[actual_phy_idx].req_flow_ctrl,\n+\t\t\t params->phy[actual_phy_idx].req_line_speed,\n+\t\t\t params->phy[actual_phy_idx].speed_cap_mask);\n \t}\n }\n \n@@ -3201,38 +4319,57 @@ static void elink_ext_phy_set_pause(struct elink_params *params,\n \t/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */\n \telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n \tif ((vars->ieee_fc &\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n+\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n \t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {\n \t\tval |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;\n \t}\n \tif ((vars->ieee_fc &\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n+\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n \t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {\n \t\tval |= MDIO_AN_REG_ADV_PAUSE_PAUSE;\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"Ext phy AN advertize 0x%x\", val);\n+\tELINK_DEBUG_P1(sc, \"Ext phy AN advertize 0x%x\", val);\n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);\n }\n \n-static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)\n-{\t\t\t\t/* LD LP */\n-\tswitch (pause_result) {\t/* ASYM P ASYM P */\n-\tcase 0xb:\t\t/* 1 0 1 1 */\n+static void elink_pause_resolve(__rte_unused struct elink_phy *phy,\n+\t\t\t\tstruct elink_params *params,\n+\t\t\t\tstruct elink_vars *vars,\n+\t\t\t\tuint32_t pause_result)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\t\t\t\t\t\t/* LD\t LP\t */\n+\tswitch (pause_result) {\t\t\t/* ASYM P ASYM P */\n+\tcase 0xb:\t\t\t\t/* 1 0 1 1 */\n+\t\tELINK_DEBUG_P0(sc, \"Flow Control: TX only\");\n \t\tvars->flow_ctrl = ELINK_FLOW_CTRL_TX;\n \t\tbreak;\n \n-\tcase 0xe:\t\t/* 1 1 1 0 */\n+\tcase 0xe:\t\t\t\t/* 1 1 1 0 */\n+\t\tELINK_DEBUG_P0(sc, \"Flow Control: RX only\");\n \t\tvars->flow_ctrl = ELINK_FLOW_CTRL_RX;\n \t\tbreak;\n \n-\tcase 0x5:\t\t/* 0 1 0 1 */\n-\tcase 0x7:\t\t/* 0 1 1 1 */\n-\tcase 0xd:\t\t/* 1 1 0 1 */\n-\tcase 0xf:\t\t/* 1 1 1 1 */\n+\tcase 0x5:\t\t\t\t/* 0 1 0 1 */\n+\tcase 0x7:\t\t\t\t/* 0 1 1 1 */\n+\tcase 0xd:\t\t\t\t/* 1 1 0 1 */\n+\tcase 0xf:\t\t\t\t/* 1 1 1 1 */\n+\t\t/* If the user selected to advertise RX ONLY,\n+\t\t * although we advertised both, need to enable\n+\t\t * RX only.\n+\t\t */\n+\n+\t\tif (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) {\n+\t\t\tELINK_DEBUG_P0(sc, \"Flow Control: RX & TX\");\n \t\tvars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;\n+\t\t} else {\n+\t\t\tELINK_DEBUG_P0(sc, \"Flow Control: RX only\");\n+\t\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_RX;\n+\t\t}\n \t\tbreak;\n-\n \tdefault:\n+\t\tELINK_DEBUG_P0(sc, \"Flow Control: None\");\n+\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n \t\tbreak;\n \t}\n \tif (pause_result & (1 << 0))\n@@ -3246,22 +4383,23 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,\n \t\t\t\t\tstruct elink_params *params,\n \t\t\t\t\tstruct elink_vars *vars)\n {\n-\tuint16_t ld_pause;\t/* local */\n-\tuint16_t lp_pause;\t/* link partner */\n+\tuint16_t ld_pause;\t\t/* local */\n+\tuint16_t lp_pause;\t\t/* link partner */\n \tuint16_t pause_result;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {\n+\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) {\n \t\telink_cl22_read(sc, phy, 0x4, &ld_pause);\n \t\telink_cl22_read(sc, phy, 0x5, &lp_pause);\n-\t} else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {\n-\t\tuint8_t lane = elink_get_warpcore_lane(params);\n+\t} else if (CHIP_IS_E3(sc) &&\n+\t\tELINK_SINGLE_MEDIA_DIRECT(params)) {\n+\t\tuint8_t lane = elink_get_warpcore_lane(phy, params);\n \t\tuint16_t gp_status, gp_mask;\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,\n \t\t\t\t&gp_status);\n \t\tgp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |\n \t\t\t MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<\n-\t\t lane;\n+\t\t\tlane;\n \t\tif ((gp_status & gp_mask) == gp_mask) {\n \t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n \t\t\t\t\tMDIO_AN_REG_ADV_PAUSE, &ld_pause);\n@@ -3287,16 +4425,18 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,\n \t\t\t\tMDIO_AN_DEVAD,\n \t\t\t\tMDIO_AN_REG_LP_AUTO_NEG, &lp_pause);\n \t}\n-\tpause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;\n-\tpause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Ext PHY pause result 0x%x\", pause_result);\n-\telink_pause_resolve(vars, pause_result);\n+\tpause_result = (ld_pause &\n+\t\t\tMDIO_AN_REG_ADV_PAUSE_MASK) >> 8;\n+\tpause_result |= (lp_pause &\n+\t\t\t MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;\n+\tELINK_DEBUG_P1(sc, \"Ext PHY pause result 0x%x\", pause_result);\n+\telink_pause_resolve(phy, params, vars, pause_result);\n \n }\n \n static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,\n-\t\t\t\t\tstruct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tuint8_t ret = 0;\n \tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n@@ -3314,7 +4454,6 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,\n \t}\n \treturn ret;\n }\n-\n /******************************************************************/\n /*\t\t\tWarpcore section\t\t\t */\n /******************************************************************/\n@@ -3323,19 +4462,31 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,\n * init configuration, and set/clear SGMII flag. Internal\n * phy init is done purely in phy_init stage.\n */\n-#define WC_TX_DRIVER(post2, idriver, ipre) \\\n+#define WC_TX_DRIVER(post2, idriver, ipre, ifir) \\\n \t((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \\\n \t (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \\\n-\t (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))\n+\t (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \\\n+\t (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))\n \n #define WC_TX_FIR(post, main, pre) \\\n \t((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \\\n \t (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \\\n \t (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))\n \n+static void elink_update_link_attr(struct elink_params *params,\n+\t\t\t\t uint32_t link_attr)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\n+\tif (SHMEM2_HAS(sc, link_attr_sync))\n+\t\tREG_WR(sc, params->shmem2_base +\n+\t\t offsetof(struct shmem2_region,\n+\t\t\t\tlink_attr_sync[params->port]), link_attr);\n+}\n+\n static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,\n \t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t\t __rte_unused struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t i;\n@@ -3358,7 +4509,7 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}\n \t};\n-\tPMD_DRV_LOG(DEBUG, sc, \"Enabling 20G-KR2\");\n+\tELINK_DEBUG_P0(sc, \"Enabling 20G-KR2\");\n \n \telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));\n@@ -3368,15 +4519,16 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,\n \t\t\t\t reg_set[i].val);\n \n \t/* Start KR2 work-around timer which handles BNX2X8073 link-parner */\n-\tvars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;\n-\telink_update_link_attr(params, vars->link_attr_sync);\n+\tparams->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;\n+\telink_update_link_attr(params, params->link_attr_sync);\n }\n \n static void elink_disable_kr2(struct elink_params *params,\n-\t\t\t struct elink_vars *vars, struct elink_phy *phy)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t struct elink_phy *phy)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tuint32_t i;\n+\tint i;\n \tstatic struct elink_reg_set reg_set[] = {\n \t\t/* Step 1 - Program the TX/RX alignment markers */\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},\n@@ -3395,13 +4547,13 @@ static void elink_disable_kr2(struct elink_params *params,\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}\n \t};\n-\tPMD_DRV_LOG(DEBUG, sc, \"Disabling 20G-KR2\");\n+\tELINK_DEBUG_P0(sc, \"Disabling 20G-KR2\");\n \n-\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n+\tfor (i = 0; i < (int)ARRAY_SIZE(reg_set); i++)\n \t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n \t\t\t\t reg_set[i].val);\n-\tvars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;\n-\telink_update_link_attr(params, vars->link_attr_sync);\n+\tparams->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;\n+\telink_update_link_attr(params, params->link_attr_sync);\n \n \tvars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;\n }\n@@ -3411,7 +4563,7 @@ static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Configure WC for LPI pass through\");\n+\tELINK_DEBUG_P0(sc, \"Configure WC for LPI pass through\");\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);\n \telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n@@ -3423,7 +4575,7 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,\n {\n \t/* Restart autoneg on the leading lane only */\n \tstruct bnx2x_softc *sc = params->sc;\n-\tuint16_t lane = elink_get_warpcore_lane(params);\n+\tuint16_t lane = elink_get_warpcore_lane(phy, params);\n \tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n \t\t\t MDIO_AER_BLOCK_AER_REG, lane);\n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n@@ -3435,9 +4587,9 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,\n \n static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \t\t\t\t\tstruct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars)\n-{\n-\tuint16_t lane, i, cl72_ctrl, an_adv = 0;\n+\t\t\t\t\tstruct elink_vars *vars) {\n+\tuint16_t lane, i, cl72_ctrl, an_adv = 0, val;\n+\tuint32_t wc_lane_config;\n \tstruct bnx2x_softc *sc = params->sc;\n \tstatic struct elink_reg_set reg_set[] = {\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},\n@@ -3449,7 +4601,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \t\t{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},\n \t};\n-\tPMD_DRV_LOG(DEBUG, sc, \"Enable Auto Negotiation for KR\");\n+\tELINK_DEBUG_P0(sc, \"Enable Auto Negotiation for KR\");\n \t/* Set to default registers that may be overridden by 10G force */\n \tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n \t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n@@ -3471,11 +4623,11 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \n \t\t/* Enable CL37 1G Parallel Detect */\n \t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertize 1G\");\n+\t\tELINK_DEBUG_P0(sc, \"Advertize 1G\");\n \t}\n \tif (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&\n \t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||\n-\t (vars->line_speed == ELINK_SPEED_10000)) {\n+\t (vars->line_speed == ELINK_SPEED_10000)) {\n \t\t/* Check adding advertisement for 10G KR */\n \t\tan_adv |= (1 << 7);\n \t\t/* Enable 10G Parallel Detect */\n@@ -3485,23 +4637,25 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n \t\t\t\t MDIO_WC_REG_PAR_DET_10G_CTRL, 1);\n \t\telink_set_aer_mmd(params, phy);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertize 10G\");\n+\t\tELINK_DEBUG_P0(sc, \"Advertize 10G\");\n \t}\n \n \t/* Set Transmit PMD settings */\n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,\n-\t\t\t WC_TX_DRIVER(0x02, 0x06, 0x09));\n+\t\t\t WC_TX_DRIVER(0x02, 0x06, 0x09, 0));\n \t/* Configure the next lane if dual mode */\n \tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)\n \t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),\n-\t\t\t\t WC_TX_DRIVER(0x02, 0x06, 0x09));\n+\t\t\t\t WC_TX_DRIVER(0x02, 0x06, 0x09, 0));\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);\n+\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,\n+\t\t\t 0x03f0);\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);\n+\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,\n+\t\t\t 0x03f0);\n \n \t/* Advertised speeds */\n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n@@ -3515,14 +4669,13 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \n \t/* Enable CL37 BAM */\n \tif (REG_RD(sc, params->shmem_base +\n-\t\t offsetof(struct shmem_region,\n-\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t default_cfg)) &\n+\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t port_hw_config[params->port].default_cfg)) &\n \t PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {\n \t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t\t MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,\n \t\t\t\t\t 1);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Enable CL37 BAM on KR\");\n+\t\tELINK_DEBUG_P0(sc, \"Enable CL37 BAM on KR\");\n \t}\n \n \t/* Advertise pause */\n@@ -3533,7 +4686,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \n \t/* Over 1G - AN local device user page 1 */\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_DIGITAL3_UP1, 0x1f);\n+\t\t\tMDIO_WC_REG_DIGITAL3_UP1, 0x1f);\n \n \tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n \t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||\n@@ -3544,7 +4697,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \n \t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t\t MDIO_WC_REG_RX1_PCI_CTRL +\n-\t\t\t\t\t (0x10 * lane), (1 << 11));\n+\t\t\t\t\t (0x10 * lane),\n+\t\t\t\t\t (1 << 11));\n \n \t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);\n@@ -3552,6 +4706,31 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n \n \t\telink_warpcore_enable_AN_KR2(phy, params, vars);\n \t} else {\n+\t\t/* Enable Auto-Detect to support 1G over CL37 as well */\n+\t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);\n+\t\twc_lane_config = REG_RD(sc, params->shmem_base +\n+\t\t\t\t\toffsetof(struct shmem_region, dev_info.\n+\t\t\t\t\tshared_hw_config.wc_lane_config));\n+\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t\tMDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);\n+\t\t/* Force cl48 sync_status LOW to avoid getting stuck in CL73\n+\t\t * parallel-detect loop when CL73 and CL37 are enabled.\n+\t\t */\n+\t\tval |= 1 << 11;\n+\n+\t\t/* Restore Polarity settings in case it was run over by\n+\t\t * previous link owner\n+\t\t */\n+\t\tif (wc_lane_config &\n+\t\t (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))\n+\t\t\tval |= 3 << 2;\n+\t\telse\n+\t\t\tval &= ~(3 << 2);\n+\t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t\t MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),\n+\t\t\t\t val);\n+\n \t\telink_disable_kr2(params, vars, phy);\n \t}\n \n@@ -3560,7 +4739,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n }\n \n static void elink_warpcore_set_10G_KR(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t __rte_unused struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val16, i, lane;\n@@ -3568,7 +4748,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,\n \t\t/* Disable Autoneg */\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,\n-\t\t 0x3f00},\n+\t\t\t0x3f00},\n \t\t{MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},\n \t\t{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},\n@@ -3581,7 +4761,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n \t\t\t\t reg_set[i].val);\n \n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \t/* Global registers */\n \tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n \t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n@@ -3611,7 +4791,8 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,\n \t\t\t MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);\n \n \t/* Turn TX scramble payload only the 64/66 scrambler */\n-\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);\n+\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t MDIO_WC_REG_TX66_CONTROL, 0x9);\n \n \t/* Turn RX scramble payload only the 64/66 scrambler */\n \telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n@@ -3632,7 +4813,7 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t misc1_val, tap_val, tx_driver_val, lane, val;\n \tuint32_t cfg_tap_val, tx_drv_brdct, tx_equal;\n-\n+\tuint32_t ifir_val, ipost2_val, ipre_driver_val;\n \t/* Hold rxSeqStart */\n \telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);\n@@ -3677,38 +4858,59 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,\n \tif (is_xfi) {\n \t\tmisc1_val |= 0x5;\n \t\ttap_val = WC_TX_FIR(0x08, 0x37, 0x00);\n-\t\ttx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);\n+\t\ttx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);\n \t} else {\n \t\tcfg_tap_val = REG_RD(sc, params->shmem_base +\n-\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[params->\n-\t\t\t\t\t\t\t\t port].sfi_tap_values));\n+\t\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t\t port_hw_config[params->port].\n+\t\t\t\t\t sfi_tap_values));\n \n \t\ttx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;\n \n-\t\ttx_drv_brdct = (cfg_tap_val &\n-\t\t\t\tPORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>\n-\t\t PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;\n-\n \t\tmisc1_val |= 0x9;\n \n \t\t/* TAP values are controlled by nvram, if value there isn't 0 */\n \t\tif (tx_equal)\n-\t\t\ttap_val = (uint16_t) tx_equal;\n+\t\t\ttap_val = (uint16_t)tx_equal;\n \t\telse\n \t\t\ttap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);\n \n-\t\tif (tx_drv_brdct)\n-\t\t\ttx_driver_val =\n-\t\t\t WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);\n-\t\telse\n-\t\t\ttx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);\n+\t\tifir_val = DEFAULT_TX_DRV_IFIR;\n+\t\tipost2_val = DEFAULT_TX_DRV_POST2;\n+\t\tipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;\n+\t\ttx_drv_brdct = DEFAULT_TX_DRV_BRDCT;\n+\n+\t\t/* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all\n+\t\t * configuration.\n+\t\t */\n+\t\tif (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |\n+\t\t\t\t PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |\n+\t\t\t\t PORT_HW_CFG_TX_DRV_POST2_MASK)) {\n+\t\t\tifir_val = (cfg_tap_val &\n+\t\t\t\t PORT_HW_CFG_TX_DRV_IFIR_MASK) >>\n+\t\t\t\tPORT_HW_CFG_TX_DRV_IFIR_SHIFT;\n+\t\t\tipre_driver_val = (cfg_tap_val &\n+\t\t\t\t\t PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)\n+\t\t\t>> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;\n+\t\t\tipost2_val = (cfg_tap_val &\n+\t\t\t\t PORT_HW_CFG_TX_DRV_POST2_MASK) >>\n+\t\t\t\tPORT_HW_CFG_TX_DRV_POST2_SHIFT;\n+\t\t}\n+\n+\t\tif (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {\n+\t\t\ttx_drv_brdct = (cfg_tap_val &\n+\t\t\t\t\tPORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>\n+\t\t\t\tPORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;\n+\t\t}\n+\n+\t\ttx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,\n+\t\t\t\t\t ipre_driver_val, ifir_val);\n \t}\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);\n \n \t/* Set Transmit PMD settings */\n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_TX_FIR_TAP,\n \t\t\t tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);\n@@ -3756,7 +4958,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,\n \n \telink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,\n \t\t\t\t MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));\n-\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);\n+\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n+\t\t\t MDIO_AN_REG_CTRL, 0);\n \t/* Turn off CL73 */\n \telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\tMDIO_WC_REG_CL73_USERB0_CTRL, &val);\n@@ -3792,7 +4995,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,\n }\n \n static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,\n-\t\t\t\t\t struct elink_phy *phy, uint16_t lane)\n+\t\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t\t uint16_t lane)\n {\n \t/* Rx0 anaRxControl1G */\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n@@ -3802,13 +5006,17 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);\n \n-\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);\n+\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t MDIO_WC_REG_RX66_SCW0, 0xE070);\n \n-\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);\n+\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t MDIO_WC_REG_RX66_SCW1, 0xC0D0);\n \n-\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);\n+\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t MDIO_WC_REG_RX66_SCW2, 0xA0B0);\n \n-\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);\n+\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t MDIO_WC_REG_RX66_SCW3, 0x8090);\n \n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);\n@@ -3837,7 +5045,7 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,\n \t\t\t MDIO_WC_REG_TX_FIR_TAP_ENABLE));\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,\n-\t\t\t WC_TX_DRIVER(0x02, 0x02, 0x02));\n+\t\t\t WC_TX_DRIVER(0x02, 0x02, 0x02, 0));\n }\n \n static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,\n@@ -3859,7 +5067,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,\n \t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t\t MDIO_WC_REG_COMBO_IEEE0_MIICTRL,\n \t\t\t\t\t 0x1000);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"set SGMII AUTONEG\");\n+\t\tELINK_DEBUG_P0(sc, \"set SGMII AUTONEG\");\n \t} else {\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);\n@@ -3874,9 +5082,8 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,\n \t\t\tval16 |= 0x0040;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"Speed not supported: 0x%x\",\n-\t\t\t\t phy->req_line_speed);\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"Speed not supported: 0x%x\", phy->req_line_speed);\n \t\t\treturn;\n \t\t}\n \n@@ -3884,13 +5091,13 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,\n \t\t\tval16 |= 0x0100;\n \n \t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t\t MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);\n+\t\t\t\tMDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"set SGMII force speed %d\",\n-\t\t\t phy->req_line_speed);\n+\t\tELINK_DEBUG_P1(sc, \"set SGMII force speed %d\",\n+\t\t\t phy->req_line_speed);\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \" (readback) %x\", val16);\n+\t\tELINK_DEBUG_P1(sc, \" (readback) %x\", val16);\n \t}\n \n \t/* SGMII Slave mode and disable signal detect */\n@@ -3902,28 +5109,31 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,\n \t\tdigctrl_kx1 &= 0xff4a;\n \n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);\n+\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n+\t\t\tdigctrl_kx1);\n \n \t/* Turn off parallel detect */\n \telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n-\t\t\t (digctrl_kx2 & ~(1 << 2)));\n+\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n+\t\t\t(digctrl_kx2 & ~(1 << 2)));\n \n \t/* Re-enable parallel detect */\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n-\t\t\t (digctrl_kx2 | (1 << 2)));\n+\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n+\t\t\t(digctrl_kx2 | (1 << 2)));\n \n \t/* Enable autodet */\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n-\t\t\t (digctrl_kx1 | 0x10));\n+\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n+\t\t\t(digctrl_kx1 | 0x10));\n }\n \n+\n static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,\n-\t\t\t\t struct elink_phy *phy, uint8_t reset)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint8_t reset)\n {\n \tuint16_t val;\n \t/* Take lane out of reset after configuration is finished */\n@@ -3936,7 +5146,7 @@ static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_DIGITAL5_MISC6, val);\n \telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n-\t\t\tMDIO_WC_REG_DIGITAL5_MISC6, &val);\n+\t\t\t MDIO_WC_REG_DIGITAL5_MISC6, &val);\n }\n \n /* Clear SFI/XFI link settings registers */\n@@ -3952,11 +5162,11 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy,\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n-\t\t 0x0195},\n+\t\t\t0x0195},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n-\t\t 0x0007},\n+\t\t\t0x0007},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,\n-\t\t 0x0002},\n+\t\t\t0x0002},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},\n \t\t{MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},\n@@ -3970,28 +5180,28 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,\n \t\t\t\t wc_regs[i].val);\n \n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);\n \n }\n \n static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,\n+\t\t\t\t\t\t__rte_unused uint32_t chip_id,\n \t\t\t\t\t\tuint32_t shmem_base,\n \t\t\t\t\t\tuint8_t port,\n-\t\t\t\t\t\tuint8_t * gpio_num,\n-\t\t\t\t\t\tuint8_t * gpio_port)\n+\t\t\t\t\t\tuint8_t *gpio_num,\n+\t\t\t\t\t\tuint8_t *gpio_port)\n {\n \tuint32_t cfg_pin;\n \t*gpio_num = 0;\n \t*gpio_port = 0;\n \tif (CHIP_IS_E3(sc)) {\n \t\tcfg_pin = (REG_RD(sc, shmem_base +\n-\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t e3_sfp_ctrl)) &\n-\t\t\t PORT_HW_CFG_E3_MOD_ABS_MASK) >>\n-\t\t PORT_HW_CFG_E3_MOD_ABS_SHIFT;\n+\t\t\t\toffsetof(struct shmem_region,\n+\t\t\t\tdev_info.port_hw_config[port].e3_sfp_ctrl)) &\n+\t\t\t\tPORT_HW_CFG_E3_MOD_ABS_MASK) >>\n+\t\t\t\tPORT_HW_CFG_E3_MOD_ABS_SHIFT;\n \n \t\t/* Should not happen. This function called upon interrupt\n \t\t * triggered by GPIO ( since EPIO can only generate interrupts\n@@ -4001,9 +5211,9 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,\n \t\t */\n \t\tif ((cfg_pin < PIN_CFG_GPIO0_P0) ||\n \t\t (cfg_pin > PIN_CFG_GPIO3_P1)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"No cfg pin %x for module detect indication\",\n-\t\t\t\t cfg_pin);\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"No cfg pin %x for module detect indication\",\n+\t\t\t cfg_pin);\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \n@@ -4017,12 +5227,13 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,\n \treturn ELINK_STATUS_OK;\n }\n \n-static int elink_is_sfp_module_plugged(struct elink_params *params)\n+static int elink_is_sfp_module_plugged(__rte_unused struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t gpio_num, gpio_port;\n \tuint32_t gpio_val;\n-\tif (elink_get_mod_abs_int_cfg(sc,\n+\tif (elink_get_mod_abs_int_cfg(sc, params->chip_id,\n \t\t\t\t params->shmem_base, params->port,\n \t\t\t\t &gpio_num, &gpio_port) != ELINK_STATUS_OK)\n \t\treturn 0;\n@@ -4034,17 +5245,16 @@ static int elink_is_sfp_module_plugged(struct elink_params *params)\n \telse\n \t\treturn 0;\n }\n-\n static int elink_warpcore_get_sigdet(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params)\n {\n \tuint16_t gp2_status_reg0, lane;\n \tstruct bnx2x_softc *sc = params->sc;\n \n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \n \telink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,\n-\t\t\t&gp2_status_reg0);\n+\t\t\t\t &gp2_status_reg0);\n \n \treturn (gp2_status_reg0 >> (8 + lane)) & 0x1;\n }\n@@ -4063,38 +5273,35 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,\n \t\treturn;\n \n \tif (vars->rx_tx_asic_rst) {\n-\t\tuint16_t lane = elink_get_warpcore_lane(params);\n+\t\tuint16_t lane = elink_get_warpcore_lane(phy, params);\n \t\tserdes_net_if = (REG_RD(sc, params->shmem_base +\n-\t\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.port_hw_config\n-\t\t\t\t\t\t [params->port].\n-\t\t\t\t\t\t default_cfg)) &\n-\t\t\t\t PORT_HW_CFG_NET_SERDES_IF_MASK);\n+\t\t\t\toffsetof(struct shmem_region, dev_info.\n+\t\t\t\tport_hw_config[params->port].default_cfg)) &\n+\t\t\t\tPORT_HW_CFG_NET_SERDES_IF_MASK);\n \n \t\tswitch (serdes_net_if) {\n \t\tcase PORT_HW_CFG_NET_SERDES_IF_KR:\n \t\t\t/* Do we get link yet? */\n \t\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,\n \t\t\t\t\t&gp_status1);\n-\t\t\tlnkup = (gp_status1 >> (8 + lane)) & 0x1;\t/* 1G */\n-\t\t\t/*10G KR */\n+\t\t\tlnkup = (gp_status1 >> (8 + lane)) & 0x1;/* 1G */\n+\t\t\t\t/*10G KR*/\n \t\t\tlnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;\n \n \t\t\tif (lnkup_kr || lnkup) {\n \t\t\t\tvars->rx_tx_asic_rst = 0;\n \t\t\t} else {\n-\t\t\t\t/* Reset the lane to see if link comes up. */\n+\t\t\t\t/* Reset the lane to see if link comes up.*/\n \t\t\t\telink_warpcore_reset_lane(sc, phy, 1);\n \t\t\t\telink_warpcore_reset_lane(sc, phy, 0);\n \n \t\t\t\t/* Restart Autoneg */\n \t\t\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n-\t\t\t\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL,\n-\t\t\t\t\t\t 0x1200);\n+\t\t\t\t\tMDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);\n \n \t\t\t\tvars->rx_tx_asic_rst--;\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"0x%x retry left\",\n-\t\t\t\t\t vars->rx_tx_asic_rst);\n+\t\t\t\tELINK_DEBUG_P1(sc, \"0x%x retry left\",\n+\t\t\t\tvars->rx_tx_asic_rst);\n \t\t\t}\n \t\t\tbreak;\n \n@@ -4102,29 +5309,29 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,\n \t\t\tbreak;\n \t\t}\n \n-\t}\n-\t/*params->rx_tx_asic_rst */\n+\t} /*params->rx_tx_asic_rst*/\n }\n \n static void elink_warpcore_config_sfi(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params)\n {\n-\tuint16_t lane = elink_get_warpcore_lane(params);\n-\n+\tuint16_t lane = elink_get_warpcore_lane(phy, params);\n+\tstruct bnx2x_softc *sc = params->sc;\n \telink_warpcore_clear_regs(phy, params, lane);\n \tif ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==\n \t ELINK_SPEED_10000) &&\n \t (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"Setting 10G SFI\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 10G SFI\");\n \t\telink_warpcore_set_10G_XFI(phy, params, 0);\n \t} else {\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"Setting 1G Fiber\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 1G Fiber\");\n \t\telink_warpcore_set_sgmii_speed(phy, params, 1, 0);\n \t}\n }\n \n static void elink_sfp_e3_set_transmitter(struct elink_params *params,\n-\t\t\t\t\t struct elink_phy *phy, uint8_t tx_en)\n+\t\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t\t uint8_t tx_en)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t cfg_pin;\n@@ -4133,9 +5340,9 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,\n \tcfg_pin = REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n \t\t\t\t dev_info.port_hw_config[port].e3_sfp_ctrl)) &\n-\t PORT_HW_CFG_E3_TX_LASER_MASK;\n+\t\tPORT_HW_CFG_E3_TX_LASER_MASK;\n \t/* Set the !tx_en since this pin is DISABLE_TX_LASER */\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting WC TX to %d\", tx_en);\n+\tELINK_DEBUG_P1(sc, \"Setting WC TX to %d\", tx_en);\n \n \t/* For 20G, the expected pin to be used is 3 pins after the current */\n \telink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);\n@@ -4143,22 +5350,21 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,\n \t\telink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);\n }\n \n-static uint8_t elink_warpcore_config_init(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+static void elink_warpcore_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t serdes_net_if;\n \tuint8_t fiber_mode;\n-\tuint16_t lane = elink_get_warpcore_lane(params);\n+\tuint16_t lane = elink_get_warpcore_lane(phy, params);\n \tserdes_net_if = (REG_RD(sc, params->shmem_base +\n-\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t\t\t default_cfg)) &\n+\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t port_hw_config[params->port].default_cfg)) &\n \t\t\t PORT_HW_CFG_NET_SERDES_IF_MASK);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"Begin Warpcore init, link_speed %d, \"\n-\t\t \"serdes_net_if = 0x%x\", vars->line_speed, serdes_net_if);\n+\tELINK_DEBUG_P2(sc, \"Begin Warpcore init, link_speed %d, \"\n+\t\t\t \"serdes_net_if = 0x%x\",\n+\t\t vars->line_speed, serdes_net_if);\n \telink_set_aer_mmd(params, phy);\n \telink_warpcore_reset_lane(sc, phy, 1);\n \tvars->phy_flags |= PHY_XGXS_FLAG;\n@@ -4167,7 +5373,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,\n \t ((phy->req_line_speed == ELINK_SPEED_100) ||\n \t (phy->req_line_speed == ELINK_SPEED_10)))) {\n \t\tvars->phy_flags |= PHY_SGMII_FLAG;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting SGMII mode\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting SGMII mode\");\n \t\telink_warpcore_clear_regs(phy, params, lane);\n \t\telink_warpcore_set_sgmii_speed(phy, params, 0, 1);\n \t} else {\n@@ -4177,27 +5383,28 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,\n \t\t\tif (params->loopback_mode != ELINK_LOOPBACK_EXT)\n \t\t\t\telink_warpcore_enable_AN_KR(phy, params, vars);\n \t\t\telse {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting KR 10G-Force\");\n-\t\t\t\telink_warpcore_set_10G_KR(phy, params);\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Setting KR 10G-Force\");\n+\t\t\t\telink_warpcore_set_10G_KR(phy, params, vars);\n \t\t\t}\n \t\t\tbreak;\n \n \t\tcase PORT_HW_CFG_NET_SERDES_IF_XFI:\n \t\t\telink_warpcore_clear_regs(phy, params, lane);\n \t\t\tif (vars->line_speed == ELINK_SPEED_10000) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 10G XFI\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Setting 10G XFI\");\n \t\t\t\telink_warpcore_set_10G_XFI(phy, params, 1);\n \t\t\t} else {\n \t\t\t\tif (ELINK_SINGLE_MEDIA_DIRECT(params)) {\n-\t\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"1G Fiber\");\n+\t\t\t\t\tELINK_DEBUG_P0(sc, \"1G Fiber\");\n \t\t\t\t\tfiber_mode = 1;\n \t\t\t\t} else {\n-\t\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"10/100/1G SGMII\");\n+\t\t\t\t\tELINK_DEBUG_P0(sc, \"10/100/1G SGMII\");\n \t\t\t\t\tfiber_mode = 0;\n \t\t\t\t}\n \t\t\t\telink_warpcore_set_sgmii_speed(phy,\n-\t\t\t\t\t\t\t params,\n-\t\t\t\t\t\t\t fiber_mode, 0);\n+\t\t\t\t\t\t\t\tparams,\n+\t\t\t\t\t\t\t\tfiber_mode,\n+\t\t\t\t\t\t\t\t0);\n \t\t\t}\n \n \t\t\tbreak;\n@@ -4209,7 +5416,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,\n \t\t\t */\n \t\t\tif ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||\n \t\t\t (params->loopback_mode == ELINK_LOOPBACK_EXT)) {\n-\t\t\t\tif (elink_is_sfp_module_plugged(params))\n+\t\t\t\tif (elink_is_sfp_module_plugged(phy, params))\n \t\t\t\t\telink_sfp_module_detection(phy, params);\n \t\t\t\telse\n \t\t\t\t\telink_sfp_e3_set_transmitter(params,\n@@ -4221,10 +5428,10 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,\n \n \t\tcase PORT_HW_CFG_NET_SERDES_IF_DXGXS:\n \t\t\tif (vars->line_speed != ELINK_SPEED_20000) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Speed not supported yet\");\n-\t\t\t\treturn 0;\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Speed not supported yet\");\n+\t\t\t\treturn;\n \t\t\t}\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 20G DXGXS\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Setting 20G DXGXS\");\n \t\t\telink_warpcore_set_20G_DXGXS(sc, phy, lane);\n \t\t\t/* Issue Module detection */\n \n@@ -4234,23 +5441,21 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,\n \t\t\tif (!params->loopback_mode) {\n \t\t\t\telink_warpcore_enable_AN_KR(phy, params, vars);\n \t\t\t} else {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting KR 20G-Force\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Setting KR 20G-Force\");\n \t\t\t\telink_warpcore_set_20G_force_KR2(phy, params);\n \t\t\t}\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"Unsupported Serdes Net Interface 0x%x\",\n-\t\t\t\t serdes_net_if);\n-\t\t\treturn 0;\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"Unsupported Serdes Net Interface 0x%x\",\n+\t\t\t serdes_net_if);\n+\t\t\treturn;\n \t\t}\n \t}\n \n \t/* Take lane out of reset after configuration is finished */\n \telink_warpcore_reset_lane(sc, phy, 0);\n-\tPMD_DRV_LOG(DEBUG, sc, \"Exit config init\");\n-\n-\treturn 0;\n+\tELINK_DEBUG_P0(sc, \"Exit config init\");\n }\n \n static void elink_warpcore_link_reset(struct elink_phy *phy,\n@@ -4277,11 +5482,12 @@ static void elink_warpcore_link_reset(struct elink_phy *phy,\n \t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n \t/* Enable 1G MDIO (1-copy) */\n \telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);\n+\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,\n+\t\t\t\t ~0x10);\n \n \telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);\n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \t/* Disable CL36 PCS Tx */\n \telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);\n@@ -4313,8 +5519,8 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val16;\n \tuint32_t lane;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting Warpcore loopback type %x, speed %d\",\n-\t\t params->loopback_mode, phy->req_line_speed);\n+\tELINK_DEBUG_P2(sc, \"Setting Warpcore loopback type %x, speed %d\",\n+\t\t params->loopback_mode, phy->req_line_speed);\n \n \tif (phy->req_line_speed < ELINK_SPEED_10000 ||\n \t phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {\n@@ -4328,14 +5534,15 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,\n \t\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,\n \t\t\t\t\t 0x10);\n \t\t/* Set 1G loopback based on lane (1-copy) */\n-\t\tlane = elink_get_warpcore_lane(params);\n+\t\tlane = elink_get_warpcore_lane(phy, params);\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);\n \t\tval16 |= (1 << lane);\n \t\tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)\n \t\t\tval16 |= (2 << lane);\n \t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);\n+\t\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL2,\n+\t\t\t\t val16);\n \n \t\t/* Switch back to 4-copy registers */\n \t\telink_set_aer_mmd(params, phy);\n@@ -4349,8 +5556,10 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,\n \t}\n }\n \n+\n+\n static void elink_sync_link(struct elink_params *params,\n-\t\t\t struct elink_vars *vars)\n+\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t link_10g_plus;\n@@ -4358,21 +5567,23 @@ static void elink_sync_link(struct elink_params *params,\n \t\tvars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;\n \tvars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);\n \tif (vars->link_up) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"phy link up\");\n+\t\tELINK_DEBUG_P0(sc, \"phy link up\");\n+\t\tELINK_DEBUG_P1(sc, \"link status = %x\", vars->link_status);\n \n \t\tvars->phy_link_up = 1;\n \t\tvars->duplex = DUPLEX_FULL;\n-\t\tswitch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {\n+\t\tswitch (vars->link_status &\n+\t\t\tLINK_STATUS_SPEED_AND_DUPLEX_MASK) {\n \t\tcase ELINK_LINK_10THD:\n \t\t\tvars->duplex = DUPLEX_HALF;\n-\t\t\t/* Fall through */\n+\t\t\t/* Fall thru */\n \t\tcase ELINK_LINK_10TFD:\n \t\t\tvars->line_speed = ELINK_SPEED_10;\n \t\t\tbreak;\n \n \t\tcase ELINK_LINK_100TXHD:\n \t\t\tvars->duplex = DUPLEX_HALF;\n-\t\t\t/* Fall through */\n+\t\t\t/* Fall thru */\n \t\tcase ELINK_LINK_100T4:\n \t\tcase ELINK_LINK_100TXFD:\n \t\t\tvars->line_speed = ELINK_SPEED_100;\n@@ -4380,14 +5591,14 @@ static void elink_sync_link(struct elink_params *params,\n \n \t\tcase ELINK_LINK_1000THD:\n \t\t\tvars->duplex = DUPLEX_HALF;\n-\t\t\t/* Fall through */\n+\t\t\t/* Fall thru */\n \t\tcase ELINK_LINK_1000TFD:\n \t\t\tvars->line_speed = ELINK_SPEED_1000;\n \t\t\tbreak;\n \n \t\tcase ELINK_LINK_2500THD:\n \t\t\tvars->duplex = DUPLEX_HALF;\n-\t\t\t/* Fall through */\n+\t\t\t/* Fall thru */\n \t\tcase ELINK_LINK_2500TFD:\n \t\t\tvars->line_speed = ELINK_SPEED_2500;\n \t\t\tbreak;\n@@ -4419,7 +5630,8 @@ static void elink_sync_link(struct elink_params *params,\n \t\t\tvars->phy_flags &= ~PHY_SGMII_FLAG;\n \t\t}\n \t\tif (vars->line_speed &&\n-\t\t USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))\n+\t\t USES_WARPCORE(sc) &&\n+\t\t (vars->line_speed == ELINK_SPEED_1000))\n \t\t\tvars->phy_flags |= PHY_SGMII_FLAG;\n \t\t/* Anything 10 and over uses the bmac */\n \t\tlink_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);\n@@ -4435,8 +5647,8 @@ static void elink_sync_link(struct elink_params *params,\n \t\t\telse\n \t\t\t\tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n \t\t}\n-\t} else {\t\t/* Link down */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"phy link down\");\n+\t} else { /* Link down */\n+\t\tELINK_DEBUG_P0(sc, \"phy link down\");\n \n \t\tvars->phy_link_up = 0;\n \n@@ -4480,44 +5692,44 @@ void elink_link_status_update(struct elink_params *params,\n \telink_sync_link(params, vars);\n \t/* Sync media type */\n \tsync_offset = params->shmem_base +\n-\t offsetof(struct shmem_region,\n-\t\t dev_info.port_hw_config[port].media_type);\n+\t\t\toffsetof(struct shmem_region,\n+\t\t\t\t dev_info.port_hw_config[port].media_type);\n \tmedia_types = REG_RD(sc, sync_offset);\n \n \tparams->phy[ELINK_INT_PHY].media_type =\n-\t (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>\n-\t PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;\n+\t\t(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>\n+\t\tPORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;\n \tparams->phy[ELINK_EXT_PHY1].media_type =\n-\t (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>\n-\t PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;\n+\t\t(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>\n+\t\tPORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;\n \tparams->phy[ELINK_EXT_PHY2].media_type =\n-\t (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>\n-\t PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;\n-\tPMD_DRV_LOG(DEBUG, sc, \"media_types = 0x%x\", media_types);\n+\t\t(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>\n+\t\tPORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;\n+\tELINK_DEBUG_P1(sc, \"media_types = 0x%x\", media_types);\n \n \t/* Sync AEU offset */\n \tsync_offset = params->shmem_base +\n-\t offsetof(struct shmem_region,\n-\t\t dev_info.port_hw_config[port].aeu_int_mask);\n+\t\t\toffsetof(struct shmem_region,\n+\t\t\t\t dev_info.port_hw_config[port].aeu_int_mask);\n \n \tvars->aeu_int_mask = REG_RD(sc, sync_offset);\n \n \t/* Sync PFC status */\n \tif (vars->link_status & LINK_STATUS_PFC_ENABLED)\n \t\tparams->feature_config_flags |=\n-\t\t ELINK_FEATURE_CONFIG_PFC_ENABLED;\n+\t\t\t\t\tELINK_FEATURE_CONFIG_PFC_ENABLED;\n \telse\n \t\tparams->feature_config_flags &=\n-\t\t ~ELINK_FEATURE_CONFIG_PFC_ENABLED;\n+\t\t\t\t\t~ELINK_FEATURE_CONFIG_PFC_ENABLED;\n \n \tif (SHMEM2_HAS(sc, link_attr_sync))\n-\t\tvars->link_attr_sync = SHMEM2_RD(sc,\n+\t\tparams->link_attr_sync = SHMEM2_RD(sc,\n \t\t\t\t\t\t link_attr_sync[params->port]);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"link_status 0x%x phy_link_up %x int_mask 0x%x\",\n-\t\t vars->link_status, vars->phy_link_up, vars->aeu_int_mask);\n-\tPMD_DRV_LOG(DEBUG, sc, \"line_speed %x duplex %x flow_ctrl 0x%x\",\n-\t\t vars->line_speed, vars->duplex, vars->flow_ctrl);\n+\tELINK_DEBUG_P3(sc, \"link_status 0x%x phy_link_up %x int_mask 0x%x\",\n+\t\t vars->link_status, vars->phy_link_up, vars->aeu_int_mask);\n+\tELINK_DEBUG_P3(sc, \"line_speed %x duplex %x flow_ctrl 0x%x\",\n+\t\t vars->line_speed, vars->duplex, vars->flow_ctrl);\n }\n \n static void elink_set_master_ln(struct elink_params *params,\n@@ -4532,7 +5744,8 @@ static void elink_set_master_ln(struct elink_params *params,\n \t/* Set the master_ln for AN */\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n-\t\t\t MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);\n+\t\t\t MDIO_XGXS_BLOCK2_TEST_MODE_LANE,\n+\t\t\t &new_master_ln);\n \n \tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n@@ -4541,8 +5754,8 @@ static void elink_set_master_ln(struct elink_params *params,\n }\n \n static elink_status_t elink_reset_unicore(struct elink_params *params,\n-\t\t\t\t\t struct elink_phy *phy,\n-\t\t\t\t\t uint8_t set_serdes)\n+\t\t\t struct elink_phy *phy,\n+\t\t\t uint8_t set_serdes)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t mii_control;\n@@ -4555,7 +5768,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,\n \tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n \t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n-\t\t\t (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));\n+\t\t\t (mii_control |\n+\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_RESET));\n \tif (set_serdes)\n \t\telink_set_serdes_access(sc, params->port);\n \n@@ -4566,7 +5780,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,\n \t\t/* The reset erased the previous bank value */\n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n-\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n+\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n+\t\t\t\t &mii_control);\n \n \t\tif (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {\n \t\t\tDELAY(5);\n@@ -4574,10 +5789,12 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,\n \t\t}\n \t}\n \n-\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);\t// \"Warning: PHY was not initialized,\"\n-\t// \" Port %d\",\n+\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);\n+\t\t\t /* \"Warning: PHY was not initialized,\"\n+\t\t\t * \" Port %d\",\n+\t\t\t */\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"BUG! XGXS is still in reset!\");\n+\tELINK_DEBUG_P0(sc, \"BUG! XGXS is still in reset!\");\n \treturn ELINK_STATUS_ERROR;\n \n }\n@@ -4631,31 +5848,35 @@ static void elink_set_parallel_detection(struct elink_phy *phy,\n \tuint16_t control2;\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n-\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);\n+\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,\n+\t\t\t &control2);\n \tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)\n \t\tcontrol2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;\n \telse\n \t\tcontrol2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;\n-\tPMD_DRV_LOG(DEBUG, sc, \"phy->speed_cap_mask = 0x%x, control2 = 0x%x\",\n-\t\t phy->speed_cap_mask, control2);\n+\tELINK_DEBUG_P2(sc, \"phy->speed_cap_mask = 0x%x, control2 = 0x%x\",\n+\t\tphy->speed_cap_mask, control2);\n \tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n-\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);\n+\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,\n+\t\t\t control2);\n \n \tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&\n-\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XGXS\");\n+\t (phy->speed_cap_mask &\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n+\t\tELINK_DEBUG_P0(sc, \"XGXS\");\n \n \t\tCL22_WR_OVER_CL45(sc, phy,\n-\t\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n-\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,\n-\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);\n+\t\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n+\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,\n+\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);\n \n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n \t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,\n \t\t\t\t &control2);\n \n+\n \t\tcontrol2 |=\n \t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;\n \n@@ -4675,7 +5896,8 @@ static void elink_set_parallel_detection(struct elink_phy *phy,\n \n static void elink_set_autoneg(struct elink_phy *phy,\n \t\t\t struct elink_params *params,\n-\t\t\t struct elink_vars *vars, uint8_t enable_cl73)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t uint8_t enable_cl73)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t reg_val;\n@@ -4688,7 +5910,7 @@ static void elink_set_autoneg(struct elink_phy *phy,\n \t/* CL37 Autoneg Enabled */\n \tif (vars->line_speed == ELINK_SPEED_AUTO_NEG)\n \t\treg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;\n-\telse\t\t\t/* CL37 Autoneg Disabled */\n+\telse /* CL37 Autoneg Disabled */\n \t\treg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |\n \t\t\t MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);\n \n@@ -4702,7 +5924,7 @@ static void elink_set_autoneg(struct elink_phy *phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n \t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);\n \treg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |\n-\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);\n+\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);\n \treg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;\n \tif (vars->line_speed == ELINK_SPEED_AUTO_NEG)\n \t\treg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;\n@@ -4716,7 +5938,8 @@ static void elink_set_autoneg(struct elink_phy *phy,\n \t/* Enable TetonII and BAM autoneg */\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_BAM_NEXT_PAGE,\n-\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);\n+\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,\n+\t\t\t ®_val);\n \tif (vars->line_speed == ELINK_SPEED_AUTO_NEG) {\n \t\t/* Enable BAM aneg Mode and TetonII aneg Mode */\n \t\treg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |\n@@ -4728,40 +5951,45 @@ static void elink_set_autoneg(struct elink_phy *phy,\n \t}\n \tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_BAM_NEXT_PAGE,\n-\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);\n+\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,\n+\t\t\t reg_val);\n \n \tif (enable_cl73) {\n \t\t/* Enable Cl73 FSM status bits */\n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_CL73_USERB0,\n-\t\t\t\t MDIO_CL73_USERB0_CL73_UCTRL, 0xe);\n+\t\t\t\t MDIO_CL73_USERB0_CL73_UCTRL,\n+\t\t\t\t 0xe);\n \n-\t\t/* Enable BAM Station Manager */\n+\t\t/* Enable BAM Station Manager*/\n \t\tCL22_WR_OVER_CL45(sc, phy,\n-\t\t\t\t MDIO_REG_BANK_CL73_USERB0,\n-\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1,\n-\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |\n-\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN\n-\t\t\t\t |\n-\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);\n+\t\t\tMDIO_REG_BANK_CL73_USERB0,\n+\t\t\tMDIO_CL73_USERB0_CL73_BAM_CTRL1,\n+\t\t\tMDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |\n+\t\t\tMDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |\n+\t\t\tMDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);\n \n \t\t/* Advertise CL73 link speeds */\n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n-\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV2, ®_val);\n-\t\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n+\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV2,\n+\t\t\t\t ®_val);\n+\t\tif (phy->speed_cap_mask &\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n \t\t\treg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;\n-\t\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)\n+\t\tif (phy->speed_cap_mask &\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)\n \t\t\treg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;\n \n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n-\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV2, reg_val);\n+\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV2,\n+\t\t\t\t reg_val);\n \n \t\t/* CL73 Autoneg Enabled */\n \t\treg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;\n \n-\t} else\t\t\t/* CL73 Autoneg Disabled */\n+\t} else /* CL73 Autoneg Disabled */\n \t\treg_val = 0;\n \n \tCL22_WR_OVER_CL45(sc, phy,\n@@ -4777,7 +6005,7 @@ static void elink_program_serdes(struct elink_phy *phy,\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t reg_val;\n \n-\t/* Program duplex, disable autoneg and sgmii */\n+\t/* Program duplex, disable autoneg and sgmii*/\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n \t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);\n@@ -4797,7 +6025,7 @@ static void elink_program_serdes(struct elink_phy *phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n \t\t\t MDIO_SERDES_DIGITAL_MISC1, ®_val);\n \t/* Clearing the speed value before setting the right speed */\n-\tPMD_DRV_LOG(DEBUG, sc, \"MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\", reg_val);\n+\tELINK_DEBUG_P1(sc, \"MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\", reg_val);\n \n \treg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |\n \t\t MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);\n@@ -4810,7 +6038,7 @@ static void elink_program_serdes(struct elink_phy *phy,\n \t\t\t MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);\n \t\tif (vars->line_speed == ELINK_SPEED_10000)\n \t\t\treg_val |=\n-\t\t\t MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;\n+\t\t\t\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;\n \t}\n \n \tCL22_WR_OVER_CL45(sc, phy,\n@@ -4831,10 +6059,12 @@ static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,\n \tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n \t\tval |= MDIO_OVER_1G_UP1_10G;\n \tCL22_WR_OVER_CL45(sc, phy,\n-\t\t\t MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);\n+\t\t\t MDIO_REG_BANK_OVER_1G,\n+\t\t\t MDIO_OVER_1G_UP1, val);\n \n \tCL22_WR_OVER_CL45(sc, phy,\n-\t\t\t MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);\n+\t\t\t MDIO_REG_BANK_OVER_1G,\n+\t\t\t MDIO_OVER_1G_UP3, 0x400);\n }\n \n static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,\n@@ -4865,7 +6095,7 @@ static void elink_restart_autoneg(struct elink_phy *phy,\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t mii_control;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"elink_restart_autoneg\");\n+\tELINK_DEBUG_P0(sc, \"elink_restart_autoneg\");\n \t/* Enable and restart BAM/CL37 aneg */\n \n \tif (enable_cl73) {\n@@ -4878,16 +6108,17 @@ static void elink_restart_autoneg(struct elink_phy *phy,\n \t\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n \t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL,\n \t\t\t\t (mii_control |\n-\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |\n-\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));\n+\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |\n+\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));\n \t} else {\n \n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n-\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"elink_restart_autoneg mii_control before = 0x%x\",\n-\t\t\t mii_control);\n+\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n+\t\t\t\t &mii_control);\n+\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"elink_restart_autoneg mii_control before = 0x%x\",\n+\t\t\t mii_control);\n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n \t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n@@ -4908,7 +6139,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,\n \n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n-\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);\n+\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,\n+\t\t\t &control1);\n \tcontrol1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;\n \t/* Set sgmii mode (and not fiber) */\n \tcontrol1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |\n@@ -4916,7 +6148,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,\n \t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);\n \tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n-\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);\n+\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,\n+\t\t\t control1);\n \n \t/* If forced speed */\n \tif (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {\n@@ -4925,7 +6158,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,\n \n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n-\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n+\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n+\t\t\t\t &mii_control);\n \t\tmii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |\n \t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |\n \t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);\n@@ -4933,30 +6167,32 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,\n \t\tswitch (vars->line_speed) {\n \t\tcase ELINK_SPEED_100:\n \t\t\tmii_control |=\n-\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;\n+\t\t\t\tMDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;\n \t\t\tbreak;\n \t\tcase ELINK_SPEED_1000:\n \t\t\tmii_control |=\n-\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;\n+\t\t\t\tMDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;\n \t\t\tbreak;\n \t\tcase ELINK_SPEED_10:\n \t\t\t/* There is nothing to set for 10M */\n \t\t\tbreak;\n \t\tdefault:\n \t\t\t/* Invalid speed for SGMII */\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid line_speed 0x%x\",\n-\t\t\t\t vars->line_speed);\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid line_speed 0x%x\",\n+\t\t\t\t vars->line_speed);\n \t\t\tbreak;\n \t\t}\n \n \t\t/* Setting the full duplex */\n \t\tif (phy->req_duplex == DUPLEX_FULL)\n-\t\t\tmii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;\n+\t\t\tmii_control |=\n+\t\t\t\tMDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;\n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n-\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);\n+\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n+\t\t\t\t mii_control);\n \n-\t} else {\t\t/* AN mode */\n+\t} else { /* AN mode */\n \t\t/* Enable and restart AN */\n \t\telink_restart_autoneg(phy, params, 0);\n \t}\n@@ -4965,8 +6201,7 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,\n /* Link management\n */\n static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,\n-\t\t\t\t\t\t\tstruct elink_params\n-\t\t\t\t\t\t\t*params)\n+\t\t\t\t\t struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t pd_10g, status2_1000x;\n@@ -4974,34 +6209,38 @@ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,\n \t\treturn ELINK_STATUS_OK;\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n-\t\t\t MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);\n+\t\t\t MDIO_SERDES_DIGITAL_A_1000X_STATUS2,\n+\t\t\t &status2_1000x);\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n-\t\t\t MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);\n+\t\t\t MDIO_SERDES_DIGITAL_A_1000X_STATUS2,\n+\t\t\t &status2_1000x);\n \tif (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"1G parallel detect link on port %d\",\n-\t\t\t params->port);\n-\t\treturn ELINK_STATUS_ERROR;\n+\t\tELINK_DEBUG_P1(sc, \"1G parallel detect link on port %d\",\n+\t\t\t params->port);\n+\t\treturn 1;\n \t}\n \n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n-\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);\n+\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,\n+\t\t\t &pd_10g);\n \n \tif (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"10G parallel detect link on port %d\",\n-\t\t\t params->port);\n-\t\treturn ELINK_STATUS_ERROR;\n+\t\tELINK_DEBUG_P1(sc, \"10G parallel detect link on port %d\",\n+\t\t\t params->port);\n+\t\treturn 1;\n \t}\n \treturn ELINK_STATUS_OK;\n }\n \n static void elink_update_adv_fc(struct elink_phy *phy,\n \t\t\t\tstruct elink_params *params,\n-\t\t\t\tstruct elink_vars *vars, uint32_t gp_status)\n+\t\t\t\tstruct elink_vars *vars,\n+\t\t\t\tuint32_t gp_status)\n {\n-\tuint16_t ld_pause;\t/* local driver */\n-\tuint16_t lp_pause;\t/* link partner */\n+\tuint16_t ld_pause; /* local driver */\n+\tuint16_t lp_pause; /* link partner */\n \tuint16_t pause_result;\n \tstruct bnx2x_softc *sc = params->sc;\n \tif ((gp_status &\n@@ -5012,37 +6251,42 @@ static void elink_update_adv_fc(struct elink_phy *phy,\n \n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n-\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);\n+\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV1,\n+\t\t\t\t &ld_pause);\n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n-\t\t\t\t MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);\n+\t\t\t\t MDIO_CL73_IEEEB1_AN_LP_ADV1,\n+\t\t\t\t &lp_pause);\n \t\tpause_result = (ld_pause &\n \t\t\t\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;\n \t\tpause_result |= (lp_pause &\n \t\t\t\t MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"pause_result CL73 0x%x\", pause_result);\n+\t\tELINK_DEBUG_P1(sc, \"pause_result CL73 0x%x\", pause_result);\n \t} else {\n \t\tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n-\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);\n+\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV,\n+\t\t\t\t &ld_pause);\n \t\tCL22_RD_OVER_CL45(sc, phy,\n-\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n-\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,\n-\t\t\t\t &lp_pause);\n+\t\t\tMDIO_REG_BANK_COMBO_IEEE0,\n+\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,\n+\t\t\t&lp_pause);\n \t\tpause_result = (ld_pause &\n \t\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;\n \t\tpause_result |= (lp_pause &\n \t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"pause_result CL37 0x%x\", pause_result);\n+\t\tELINK_DEBUG_P1(sc, \"pause_result CL37 0x%x\", pause_result);\n \t}\n-\telink_pause_resolve(vars, pause_result);\n+\telink_pause_resolve(phy, params, vars, pause_result);\n \n }\n \n static void elink_flow_ctrl_resolve(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars, uint32_t gp_status)\n+\t\t\t\t struct elink_vars *vars,\n+\t\t\t\t uint32_t gp_status)\n {\n+\tstruct bnx2x_softc *sc = params->sc;\n \tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n \n \t/* Resolve from gp_status in case of AN complete and not sgmii */\n@@ -5062,7 +6306,7 @@ static void elink_flow_ctrl_resolve(struct elink_phy *phy,\n \t\t}\n \t\telink_update_adv_fc(phy, params, vars, gp_status);\n \t}\n-\tPMD_DRV_LOG(DEBUG, params->sc, \"flow_ctrl 0x%x\", vars->flow_ctrl);\n+\tELINK_DEBUG_P1(sc, \"flow_ctrl 0x%x\", vars->flow_ctrl);\n }\n \n static void elink_check_fallback_to_cl37(struct elink_phy *phy,\n@@ -5070,14 +6314,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t rx_status, ustat_val, cl37_fsm_received;\n-\tPMD_DRV_LOG(DEBUG, sc, \"elink_check_fallback_to_cl37\");\n+\tELINK_DEBUG_P0(sc, \"elink_check_fallback_to_cl37\");\n \t/* Step 1: Make sure signal is detected */\n \tCL22_RD_OVER_CL45(sc, phy,\n-\t\t\t MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);\n+\t\t\t MDIO_REG_BANK_RX0,\n+\t\t\t MDIO_RX0_RX_STATUS,\n+\t\t\t &rx_status);\n \tif ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=\n \t (MDIO_RX0_RX_STATUS_SIGDET)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Signal is not detected. Restoring CL73.\"\n-\t\t\t \"rx_status(0x80b0) = 0x%x\", rx_status);\n+\t\tELINK_DEBUG_P1(sc, \"Signal is not detected. Restoring CL73.\"\n+\t\t\t \"rx_status(0x80b0) = 0x%x\", rx_status);\n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n \t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL,\n@@ -5087,14 +6333,15 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,\n \t/* Step 2: Check CL73 state machine */\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_CL73_USERB0,\n-\t\t\t MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);\n+\t\t\t MDIO_CL73_USERB0_CL73_USTAT1,\n+\t\t\t &ustat_val);\n \tif ((ustat_val &\n \t (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |\n \t MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=\n \t (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |\n-\t MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"CL73 state-machine is not stable. \"\n-\t\t\t \"ustat_val(0x8371) = 0x%x\", ustat_val);\n+\t MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {\n+\t\tELINK_DEBUG_P1(sc, \"CL73 state-machine is not stable. \"\n+\t\t\t \"ustat_val(0x8371) = 0x%x\", ustat_val);\n \t\treturn;\n \t}\n \t/* Step 3: Check CL37 Message Pages received to indicate LP\n@@ -5102,14 +6349,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,\n \t */\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_REMOTE_PHY,\n-\t\t\t MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);\n+\t\t\t MDIO_REMOTE_PHY_MISC_RX_STATUS,\n+\t\t\t &cl37_fsm_received);\n \tif ((cl37_fsm_received &\n \t (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |\n-\t MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=\n+\t MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=\n \t (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |\n-\t MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"No CL37 FSM were received. \"\n-\t\t\t \"misc_rx_status(0x8330) = 0x%x\", cl37_fsm_received);\n+\t MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {\n+\t\tELINK_DEBUG_P1(sc, \"No CL37 FSM were received. \"\n+\t\t\t \"misc_rx_status(0x8330) = 0x%x\",\n+\t\t\t cl37_fsm_received);\n \t\treturn;\n \t}\n \t/* The combined cl37/cl73 fsm state information indicating that\n@@ -5121,34 +6370,38 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,\n \t/* Disable CL73 */\n \tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n-\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);\n+\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL,\n+\t\t\t 0);\n \t/* Restart CL37 autoneg */\n \telink_restart_autoneg(phy, params, 0);\n-\tPMD_DRV_LOG(DEBUG, sc, \"Disabling CL73, and restarting CL37 autoneg\");\n+\tELINK_DEBUG_P0(sc, \"Disabling CL73, and restarting CL37 autoneg\");\n }\n \n static void elink_xgxs_an_resolve(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars, uint32_t gp_status)\n+\t\t\t\t struct elink_vars *vars,\n+\t\t\t\t uint32_t gp_status)\n {\n \tif (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)\n-\t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n+\t\tvars->link_status |=\n+\t\t\tLINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n \n \tif (elink_direct_parallel_detect_used(phy, params))\n-\t\tvars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;\n+\t\tvars->link_status |=\n+\t\t\tLINK_STATUS_PARALLEL_DETECTION_USED;\n }\n-\n static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,\n-\t\t\t\t\t\t struct elink_params *params __rte_unused,\n-\t\t\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t\t\t uint16_t is_link_up,\n-\t\t\t\t\t\t uint16_t speed_mask,\n-\t\t\t\t\t\t uint16_t is_duplex)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars,\n+\t\t\t\t uint16_t is_link_up,\n+\t\t\t\t uint16_t speed_mask,\n+\t\t\t\t uint16_t is_duplex)\n {\n+\tstruct bnx2x_softc *sc = params->sc;\n \tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)\n \t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;\n \tif (is_link_up) {\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"phy link up\");\n+\t\tELINK_DEBUG_P0(sc, \"phy link up\");\n \n \t\tvars->phy_link_up = 1;\n \t\tvars->link_status |= LINK_STATUS_LINK_UP;\n@@ -5189,9 +6442,9 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,\n \n \t\tcase ELINK_GP_STATUS_5G:\n \t\tcase ELINK_GP_STATUS_6G:\n-\t\t\tPMD_DRV_LOG(DEBUG, params->sc,\n-\t\t\t\t \"link speed unsupported gp_status 0x%x\",\n-\t\t\t\t speed_mask);\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t\t \"link speed unsupported gp_status 0x%x\",\n+\t\t\t\t speed_mask);\n \t\t\treturn ELINK_STATUS_ERROR;\n \n \t\tcase ELINK_GP_STATUS_10G_KX4:\n@@ -5209,13 +6462,13 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,\n \t\t\tvars->link_status |= ELINK_LINK_20GTFD;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, params->sc,\n-\t\t\t\t \"link speed unsupported gp_status 0x%x\",\n-\t\t\t\t speed_mask);\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t\t \"link speed unsupported gp_status 0x%x\",\n+\t\t\t\t speed_mask);\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n-\t} else {\t\t/* link_down */\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"phy link down\");\n+\t} else { /* link_down */\n+\t\tELINK_DEBUG_P0(sc, \"phy link down\");\n \n \t\tvars->phy_link_up = 0;\n \n@@ -5223,14 +6476,16 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,\n \t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n \t\tvars->mac_type = ELINK_MAC_TYPE_NONE;\n \t}\n-\tPMD_DRV_LOG(DEBUG, params->sc, \" phy_link_up %x line_speed %d\",\n+\tELINK_DEBUG_P2(sc, \" in elink_get_link_speed_duplex vars->link_status = %x, vars->duplex = %x\",\n+\t\t\tvars->link_status, vars->duplex);\n+\tELINK_DEBUG_P2(sc, \" phy_link_up %x line_speed %d\",\n \t\t vars->phy_link_up, vars->line_speed);\n \treturn ELINK_STATUS_OK;\n }\n \n-static uint8_t elink_link_settings_status(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_link_settings_status(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \n@@ -5240,14 +6495,23 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,\n \t/* Read gp_status */\n \tCL22_RD_OVER_CL45(sc, phy,\n \t\t\t MDIO_REG_BANK_GP_STATUS,\n-\t\t\t MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);\n-\tif (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)\n+\t\t\t MDIO_GP_STATUS_TOP_AN_STATUS1,\n+\t\t\t &gp_status);\n+\tif (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) {\n \t\tduplex = DUPLEX_FULL;\n+\t\tELINK_DEBUG_P1(sc, \"duplex status read from phy is = %x\",\n+\t\t\t\tduplex);\n+\t} else {\n+\t\tELINK_DEBUG_P1(sc, \"phy status does not allow interface to be FULL_DUPLEX : %x\",\n+\t\t\tgp_status);\n+\t}\n+\n+\n \tif (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)\n \t\tlink_up = 1;\n \tspeed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;\n-\tPMD_DRV_LOG(DEBUG, sc, \"gp_status 0x%x, is_link_up %d, speed_mask 0x%x\",\n-\t\t gp_status, link_up, speed_mask);\n+\tELINK_DEBUG_P3(sc, \"gp_status 0x%x, is_link_up %d, speed_mask 0x%x\",\n+\t\t gp_status, link_up, speed_mask);\n \trc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,\n \t\t\t\t\t duplex);\n \tif (rc == ELINK_STATUS_ERROR)\n@@ -5261,7 +6525,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,\n \t\t\t\telink_xgxs_an_resolve(phy, params, vars,\n \t\t\t\t\t\t gp_status);\n \t\t}\n-\t} else {\t\t/* Link_down */\n+\t} else { /* Link_down */\n \t\tif ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n \t\t ELINK_SINGLE_MEDIA_DIRECT(params)) {\n \t\t\t/* Check signal is detected */\n@@ -5269,7 +6533,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,\n \t\t}\n \t}\n \n-\t/* Read LP advertised speeds */\n+\t/* Read LP advertised speeds*/\n \tif (ELINK_SINGLE_MEDIA_DIRECT(params) &&\n \t (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {\n \t\tuint16_t val;\n@@ -5279,61 +6543,69 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,\n \n \t\tif (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n \t\tif (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |\n \t\t\t MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n \n \t\tCL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,\n \t\t\t\t MDIO_OVER_1G_LP_UP1, &val);\n \n \t\tif (val & MDIO_OVER_1G_UP1_2_5G)\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;\n \t\tif (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n \t}\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n-\t\t vars->duplex, vars->flow_ctrl, vars->link_status);\n+\tELINK_DEBUG_P3(sc, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n+\t\t vars->duplex, vars->flow_ctrl, vars->link_status);\n \treturn rc;\n }\n \n-static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t lane;\n \tuint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;\n \telink_status_t rc = ELINK_STATUS_OK;\n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \t/* Read gp_status */\n-\tif ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {\n+\tif ((params->loopback_mode) &&\n+\t (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);\n \t\tlink_up &= 0x1;\n+\t\tELINK_DEBUG_P1(sc, \"params->loopback_mode link_up read = %x\",\n+\t\t\t\tlink_up);\n \t} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&\n-\t\t (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {\n+\t\t(phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {\n \t\tuint16_t temp_link_up;\n-\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);\n-\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"PCS RX link status = 0x%x-->0x%x\",\n-\t\t\t temp_link_up, link_up);\n+\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t\t1, &temp_link_up);\n+\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n+\t\t\t\t1, &link_up);\n+\t\tELINK_DEBUG_P2(sc, \"PCS RX link status = 0x%x-->0x%x\",\n+\t\t\t temp_link_up, link_up);\n \t\tlink_up &= (1 << 2);\n \t\tif (link_up)\n \t\t\telink_ext_phy_resolve_fc(phy, params, vars);\n \t} else {\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n-\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"0x81d1 = 0x%x\", gp_status1);\n+\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_1,\n+\t\t\t\t&gp_status1);\n+\t\tELINK_DEBUG_P1(sc, \"0x81d1 = 0x%x\", gp_status1);\n \t\t/* Check for either KR, 1G, or AN up. */\n \t\tlink_up = ((gp_status1 >> 8) |\n-\t\t\t (gp_status1 >> 12) | (gp_status1)) & (1 << lane);\n+\t\t\t (gp_status1 >> 12) |\n+\t\t\t (gp_status1)) &\n+\t\t\t(1 << lane);\n \t\tif (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {\n \t\t\tuint16_t an_link;\n \t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n@@ -5341,6 +6613,8 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n \t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n \t\t\t\t\tMDIO_AN_REG_STATUS, &an_link);\n \t\t\tlink_up |= (an_link & (1 << 2));\n+\t\t\tELINK_DEBUG_P2(sc, \"an_link = %x, link_up = %x\",\n+\t\t\t\t\tan_link, link_up);\n \t\t}\n \t\tif (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {\n \t\t\tuint16_t pd, gp_status4;\n@@ -5351,7 +6625,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n \t\t\t\t\t\t&gp_status4);\n \t\t\t\tif (gp_status4 & ((1 << 12) << lane))\n \t\t\t\t\tvars->link_status |=\n-\t\t\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n+\t\t\t\t\tLINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n \n \t\t\t\t/* Check parallel detect used */\n \t\t\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n@@ -5359,13 +6633,19 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n \t\t\t\t\t\t&pd);\n \t\t\t\tif (pd & (1 << 15))\n \t\t\t\t\tvars->link_status |=\n-\t\t\t\t\t LINK_STATUS_PARALLEL_DETECTION_USED;\n+\t\t\t\t\tLINK_STATUS_PARALLEL_DETECTION_USED;\n+\t\t\t\tELINK_DEBUG_P2(sc, \"pd = %x, link_status = %x\",\n+\t\t\t\t\t\tpd, vars->link_status);\n \t\t\t}\n \t\t\telink_ext_phy_resolve_fc(phy, params, vars);\n \t\t\tvars->duplex = duplex;\n+\t\t\tELINK_DEBUG_P3(sc, \" ELINK_SINGLE_MEDIA_DIRECT duplex %x flow_ctrl 0x%x link_status 0x%x\",\n+\t\t\t\t\tvars->duplex, vars->flow_ctrl,\n+\t\t\t\t\tvars->link_status);\n \t\t}\n \t}\n-\n+\tELINK_DEBUG_P3(sc, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n+\t\t\tvars->duplex, vars->flow_ctrl, vars->link_status);\n \tif ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&\n \t ELINK_SINGLE_MEDIA_DIRECT(params)) {\n \t\tuint16_t val;\n@@ -5375,24 +6655,28 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n \n \t\tif (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n \t\tif (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |\n \t\t\t MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n-\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\tELINK_DEBUG_P2(sc, \"val = %x, link_status = %x\",\n+\t\t\t\tval, vars->link_status);\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_DIGITAL3_LP_UP1, &val);\n \n \t\tif (val & MDIO_OVER_1G_UP1_2_5G)\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;\n \t\tif (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\tELINK_DEBUG_P2(sc, \"val = %x, link_status = %x\",\n+\t\t\t\tval, vars->link_status);\n \n \t}\n \n+\n \tif (lane < 2) {\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);\n@@ -5400,12 +6684,12 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n \t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"lane %d gp_speed 0x%x\", lane, gp_speed);\n+\tELINK_DEBUG_P2(sc, \"lane %d gp_speed 0x%x\", lane, gp_speed);\n \n \tif ((lane & 1) == 0)\n \t\tgp_speed <<= 8;\n \tgp_speed &= 0x3f00;\n-\tlink_up = ! !link_up;\n+\tlink_up = !!link_up;\n \n \t/* Reset the TX FIFO to fix SGMII issue */\n \trc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,\n@@ -5416,11 +6700,10 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,\n \t (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))\n \t\tvars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n-\t\t vars->duplex, vars->flow_ctrl, vars->link_status);\n+\tELINK_DEBUG_P3(sc, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n+\t\t vars->duplex, vars->flow_ctrl, vars->link_status);\n \treturn rc;\n }\n-\n static void elink_set_gmii_tx_driver(struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n@@ -5431,7 +6714,8 @@ static void elink_set_gmii_tx_driver(struct elink_params *params)\n \n \t/* Read precomp */\n \tCL22_RD_OVER_CL45(sc, phy,\n-\t\t\t MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);\n+\t\t\t MDIO_REG_BANK_OVER_1G,\n+\t\t\t MDIO_OVER_1G_LP_UP2, &lp_up2);\n \n \t/* Bits [10:7] at lp_up2, positioned at [15:12] */\n \tlp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>\n@@ -5442,32 +6726,36 @@ static void elink_set_gmii_tx_driver(struct elink_params *params)\n \t\treturn;\n \n \tfor (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;\n-\t bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {\n+\t bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {\n \t\tCL22_RD_OVER_CL45(sc, phy,\n-\t\t\t\t bank, MDIO_TX0_TX_DRIVER, &tx_driver);\n+\t\t\t\t bank,\n+\t\t\t\t MDIO_TX0_TX_DRIVER, &tx_driver);\n \n \t\t/* Replace tx_driver bits [15:12] */\n-\t\tif (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {\n+\t\tif (lp_up2 !=\n+\t\t (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {\n \t\t\ttx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;\n \t\t\ttx_driver |= lp_up2;\n \t\t\tCL22_WR_OVER_CL45(sc, phy,\n-\t\t\t\t\t bank, MDIO_TX0_TX_DRIVER, tx_driver);\n+\t\t\t\t\t bank,\n+\t\t\t\t\t MDIO_TX0_TX_DRIVER, tx_driver);\n \t\t}\n \t}\n }\n \n static elink_status_t elink_emac_program(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n \tuint16_t mode = 0;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"setting link speed & duplex\");\n+\tELINK_DEBUG_P0(sc, \"setting link speed & duplex\");\n \telink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +\n \t\t EMAC_REG_EMAC_MODE,\n \t\t (EMAC_MODE_25G_MODE |\n-\t\t\tEMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));\n+\t\t\tEMAC_MODE_PORT_MII_10M |\n+\t\t\tEMAC_MODE_HALF_DUPLEX));\n \tswitch (vars->line_speed) {\n \tcase ELINK_SPEED_10:\n \t\tmode |= EMAC_MODE_PORT_MII_10M;\n@@ -5487,15 +6775,16 @@ static elink_status_t elink_emac_program(struct elink_params *params,\n \n \tdefault:\n \t\t/* 10G not valid for EMAC */\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Invalid line_speed 0x%x\", vars->line_speed);\n+\t\tELINK_DEBUG_P1(sc, \"Invalid line_speed 0x%x\",\n+\t\t\t vars->line_speed);\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n \tif (vars->duplex == DUPLEX_HALF)\n \t\tmode |= EMAC_MODE_HALF_DUPLEX;\n \telink_bits_en(sc,\n-\t\t GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);\n+\t\t GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE,\n+\t\t mode);\n \n \telink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);\n \treturn ELINK_STATUS_OK;\n@@ -5512,24 +6801,26 @@ static void elink_set_preemphasis(struct elink_phy *phy,\n \t bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {\n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t bank,\n-\t\t\t\t MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);\n+\t\t\t\t MDIO_RX0_RX_EQ_BOOST,\n+\t\t\t\t phy->rx_preemphasis[i]);\n \t}\n \n \tfor (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;\n \t bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {\n \t\tCL22_WR_OVER_CL45(sc, phy,\n \t\t\t\t bank,\n-\t\t\t\t MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);\n+\t\t\t\t MDIO_TX0_TX_DRIVER,\n+\t\t\t\t phy->tx_preemphasis[i]);\n \t}\n }\n \n-static uint8_t elink_xgxs_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+static void elink_xgxs_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n+\tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||\n-\t\t\t (params->loopback_mode == ELINK_LOOPBACK_XGXS));\n-\n+\t\t\t (params->loopback_mode == ELINK_LOOPBACK_XGXS));\n \tif (!(vars->phy_flags & PHY_SGMII_FLAG)) {\n \t\tif (ELINK_SINGLE_MEDIA_DIRECT(params) &&\n \t\t (params->feature_config_flags &\n@@ -5540,7 +6831,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,\n \t\tif (vars->line_speed != ELINK_SPEED_AUTO_NEG ||\n \t\t (ELINK_SINGLE_MEDIA_DIRECT(params) &&\n \t\t params->loopback_mode == ELINK_LOOPBACK_EXT)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, params->sc, \"not SGMII, no AN\");\n+\t\t\tELINK_DEBUG_P0(sc, \"not SGMII, no AN\");\n \n \t\t\t/* Disable autoneg */\n \t\t\telink_set_autoneg(phy, params, vars, 0);\n@@ -5548,8 +6839,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,\n \t\t\t/* Program speed and duplex */\n \t\t\telink_program_serdes(phy, params, vars);\n \n-\t\t} else {\t/* AN_mode */\n-\t\t\tPMD_DRV_LOG(DEBUG, params->sc, \"not SGMII, AN\");\n+\t\t} else { /* AN_mode */\n+\t\t\tELINK_DEBUG_P0(sc, \"not SGMII, AN\");\n \n \t\t\t/* AN enabled */\n \t\t\telink_set_brcm_cl37_advertisement(phy, params);\n@@ -5565,18 +6856,16 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,\n \t\t\telink_restart_autoneg(phy, params, enable_cl73);\n \t\t}\n \n-\t} else {\t\t/* SGMII mode */\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"SGMII\");\n+\t} else { /* SGMII mode */\n+\t\tELINK_DEBUG_P0(sc, \"SGMII\");\n \n \t\telink_initialize_sgmii_process(phy, params, vars);\n \t}\n-\n-\treturn 0;\n }\n \n static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t struct elink_params *params,\n+\t\t\t struct elink_vars *vars)\n {\n \telink_status_t rc;\n \tvars->phy_flags |= PHY_XGXS_FLAG;\n@@ -5614,28 +6903,32 @@ static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,\n }\n \n static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,\n-\t\t\t\t\t struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params)\n {\n \tuint16_t cnt, ctrl;\n \t/* Wait for soft reset to get cleared up to 1 sec */\n \tfor (cnt = 0; cnt < 1000; cnt++) {\n-\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)\n-\t\t\telink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);\n+\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)\n+\t\t\telink_cl22_read(sc, phy,\n+\t\t\t\tMDIO_PMA_REG_CTRL, &ctrl);\n \t\telse\n \t\t\telink_cl45_read(sc, phy,\n-\t\t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\t\tMDIO_PMA_REG_CTRL, &ctrl);\n+\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\tMDIO_PMA_REG_CTRL, &ctrl);\n \t\tif (!(ctrl & (1 << 15)))\n \t\t\tbreak;\n \t\tDELAY(1000 * 1);\n \t}\n \n \tif (cnt == 1000)\n-\t\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);\t// \"Warning: PHY was not initialized,\"\n-\t// \" Port %d\",\n+\t\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED,\n+\t\t\t\t params->port);\n+\t\t\t\t /* \"Warning: PHY was not initialized,\"\n+\t\t\t\t * \" Port %d\",\n+\t\t\t\t */\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"control reg 0x%x (after %d ms)\", ctrl, cnt);\n+\tELINK_DEBUG_P2(sc, \"control reg 0x%x (after %d ms)\", ctrl, cnt);\n \treturn cnt;\n }\n \n@@ -5653,37 +6946,38 @@ static void elink_link_int_enable(struct elink_params *params)\n \t} else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {\n \t\tmask = (ELINK_NIG_MASK_XGXS0_LINK10G |\n \t\t\tELINK_NIG_MASK_XGXS0_LINK_STATUS);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"enabled XGXS interrupt\");\n+\t\tELINK_DEBUG_P0(sc, \"enabled XGXS interrupt\");\n \t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&\n-\t\t params->phy[ELINK_INT_PHY].type !=\n-\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {\n+\t\t\tparams->phy[ELINK_INT_PHY].type !=\n+\t\t\t\tPORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {\n \t\t\tmask |= ELINK_NIG_MASK_MI_INT;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"enabled external phy int\");\n+\t\t\tELINK_DEBUG_P0(sc, \"enabled external phy int\");\n \t\t}\n \n-\t} else {\t\t/* SerDes */\n+\t} else { /* SerDes */\n \t\tmask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"enabled SerDes interrupt\");\n+\t\tELINK_DEBUG_P0(sc, \"enabled SerDes interrupt\");\n \t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&\n-\t\t params->phy[ELINK_INT_PHY].type !=\n-\t\t PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {\n+\t\t\tparams->phy[ELINK_INT_PHY].type !=\n+\t\t\t\tPORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {\n \t\t\tmask |= ELINK_NIG_MASK_MI_INT;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"enabled external phy int\");\n+\t\t\tELINK_DEBUG_P0(sc, \"enabled external phy int\");\n \t\t}\n \t}\n-\telink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);\n+\telink_bits_en(sc,\n+\t\t NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,\n+\t\t mask);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"port %x, is_xgxs %x, int_status 0x%x\", port,\n-\t\t (params->switch_cfg == ELINK_SWITCH_CFG_10G),\n-\t\t REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));\n-\tPMD_DRV_LOG(DEBUG, sc, \" int_mask 0x%x, MI_INT %x, SERDES_LINK %x\",\n-\t\t REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),\n-\t\t REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),\n-\t\t REG_RD(sc,\n-\t\t\t NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));\n-\tPMD_DRV_LOG(DEBUG, sc, \" 10G %x, XGXS_LINK %x\",\n-\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),\n-\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));\n+\tELINK_DEBUG_P3(sc, \"port %x, is_xgxs %x, int_status 0x%x\", port,\n+\t\t (params->switch_cfg == ELINK_SWITCH_CFG_10G),\n+\t\t REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));\n+\tELINK_DEBUG_P3(sc, \" int_mask 0x%x, MI_INT %x, SERDES_LINK %x\",\n+\t\t REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),\n+\t\t REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),\n+\t\t REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));\n+\tELINK_DEBUG_P2(sc, \" 10G %x, XGXS_LINK %x\",\n+\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),\n+\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));\n }\n \n static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,\n@@ -5696,17 +6990,20 @@ static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,\n \t * so in this case we need to write the status to clear the XOR\n \t */\n \t/* Read Latched signals */\n-\tlatch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);\n-\tPMD_DRV_LOG(DEBUG, sc, \"latch_status = 0x%x\", latch_status);\n-\t/* Handle only those with latched-signal=up. */\n+\tlatch_status = REG_RD(sc,\n+\t\t\t\t NIG_REG_LATCH_STATUS_0 + port * 8);\n+\tELINK_DEBUG_P1(sc, \"latch_status = 0x%x\", latch_status);\n+\t/* Handle only those with latched-signal=up.*/\n \tif (exp_mi_int)\n \t\telink_bits_en(sc,\n \t\t\t NIG_REG_STATUS_INTERRUPT_PORT0\n-\t\t\t + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);\n+\t\t\t + port * 4,\n+\t\t\t ELINK_NIG_STATUS_EMAC0_MI_INT);\n \telse\n \t\telink_bits_dis(sc,\n \t\t\t NIG_REG_STATUS_INTERRUPT_PORT0\n-\t\t\t + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);\n+\t\t\t + port * 4,\n+\t\t\t ELINK_NIG_STATUS_EMAC0_MI_INT);\n \n \tif (latch_status & 1) {\n \n@@ -5741,23 +7038,24 @@ static void elink_link_int_ack(struct elink_params *params,\n \t\t\t\t * the relevant lane in the status register\n \t\t\t\t */\n \t\t\t\tuint32_t ser_lane =\n-\t\t\t\t ((params->lane_config &\n-\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n-\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n+\t\t\t\t\t((params->lane_config &\n+\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n+\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n \t\t\t\tmask = ((1 << ser_lane) <<\n-\t\t\t\t\tELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);\n+\t\t\t\t ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);\n \t\t\t} else\n \t\t\t\tmask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;\n \t\t}\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Ack link up interrupt with mask 0x%x\",\n-\t\t\t mask);\n+\t\tELINK_DEBUG_P1(sc, \"Ack link up interrupt with mask 0x%x\",\n+\t\t\t mask);\n \t\telink_bits_en(sc,\n-\t\t\t NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);\n+\t\t\t NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,\n+\t\t\t mask);\n \t}\n }\n \n-static uint8_t elink_format_ver(uint32_t num, uint8_t * str,\n-\t\t\t\tuint16_t * len)\n+static elink_status_t elink_format_ver(uint32_t num, uint8_t *str,\n+\t\t\t\t uint16_t *len)\n {\n \tuint8_t *str_ptr = str;\n \tuint32_t mask = 0xf0000000;\n@@ -5795,14 +7093,57 @@ static uint8_t elink_format_ver(uint32_t num, uint8_t * str,\n \treturn ELINK_STATUS_OK;\n }\n \n-static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,\n-\t\t\t\t uint8_t * str, uint16_t * len)\n+\n+static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,\n+\t\t\t\t uint8_t *str,\n+\t\t\t\t uint16_t *len)\n {\n \tstr[0] = '\\0';\n \t(*len)--;\n \treturn ELINK_STATUS_OK;\n }\n \n+elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params,\n+\t\t\t\t uint8_t *version,\n+\t\t\t\t uint16_t len)\n+{\n+\tstruct bnx2x_softc *sc;\n+\tuint32_t spirom_ver = 0;\n+\telink_status_t status = ELINK_STATUS_OK;\n+\tuint8_t *ver_p = version;\n+\tuint16_t remain_len = len;\n+\tif (version == NULL || params == NULL)\n+\t\treturn ELINK_STATUS_ERROR;\n+\tsc = params->sc;\n+\n+\t/* Extract first external phy*/\n+\tversion[0] = '\\0';\n+\tspirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);\n+\n+\tif (params->phy[ELINK_EXT_PHY1].format_fw_ver) {\n+\t\tstatus |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,\n+\t\t\t\t\t\t\t ver_p,\n+\t\t\t\t\t\t\t &remain_len);\n+\t\tver_p += (len - remain_len);\n+\t}\n+\tif ((params->num_phys == ELINK_MAX_PHYS) &&\n+\t (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {\n+\t\tspirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);\n+\t\tif (params->phy[ELINK_EXT_PHY2].format_fw_ver) {\n+\t\t\t*ver_p = '/';\n+\t\t\tver_p++;\n+\t\t\tremain_len--;\n+\t\t\tstatus |= params->phy[ELINK_EXT_PHY2].format_fw_ver(\n+\t\t\t\tspirom_ver,\n+\t\t\t\tver_p,\n+\t\t\t\t&remain_len);\n+\t\t\tver_p = version + (len - remain_len);\n+\t\t}\n+\t}\n+\t*ver_p = '\\0';\n+\treturn status;\n+}\n+\n static void elink_set_xgxs_loopback(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params)\n {\n@@ -5812,7 +7153,7 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,\n \tif (phy->req_line_speed != ELINK_SPEED_1000) {\n \t\tuint32_t md_devad = 0;\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XGXS 10G loopback enable\");\n+\t\tELINK_DEBUG_P0(sc, \"XGXS 10G loopback enable\");\n \n \t\tif (!CHIP_IS_E3(sc)) {\n \t\t\t/* Change the uni_phy_addr in the nig */\n@@ -5826,7 +7167,8 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t 5,\n \t\t\t\t (MDIO_REG_BANK_AER_BLOCK +\n-\t\t\t\t (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);\n+\t\t\t\t (MDIO_AER_BLOCK_AER_REG & 0xf)),\n+\t\t\t\t 0x2800);\n \n \t\telink_cl45_write(sc, phy,\n \t\t\t\t 5,\n@@ -5844,22 +7186,21 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,\n \t\t}\n \t} else {\n \t\tuint16_t mii_ctrl;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XGXS 1G loopback enable\");\n+\t\tELINK_DEBUG_P0(sc, \"XGXS 1G loopback enable\");\n \t\telink_cl45_read(sc, phy, 5,\n \t\t\t\t(MDIO_REG_BANK_COMBO_IEEE0 +\n-\t\t\t\t (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),\n+\t\t\t\t(MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),\n \t\t\t\t&mii_ctrl);\n \t\telink_cl45_write(sc, phy, 5,\n \t\t\t\t (MDIO_REG_BANK_COMBO_IEEE0 +\n-\t\t\t\t (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),\n+\t\t\t\t (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),\n \t\t\t\t mii_ctrl |\n \t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);\n \t}\n }\n \n elink_status_t elink_set_led(struct elink_params *params,\n-\t\t\t struct elink_vars *vars, uint8_t mode,\n-\t\t\t uint32_t speed)\n+\t\t struct elink_vars *vars, uint8_t mode, uint32_t speed)\n {\n \tuint8_t port = params->port;\n \tuint16_t hw_led_mode = params->hw_led_mode;\n@@ -5868,16 +7209,21 @@ elink_status_t elink_set_led(struct elink_params *params,\n \tuint32_t tmp;\n \tuint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"elink_set_led: port %x, mode %d\", port, mode);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"speed 0x%x, hw_led_mode 0x%x\", speed, hw_led_mode);\n+\tELINK_DEBUG_P2(sc, \"elink_set_led: port %x, mode %d\", port, mode);\n+\tELINK_DEBUG_P2(sc, \"speed 0x%x, hw_led_mode 0x%x\",\n+\t\t speed, hw_led_mode);\n \t/* In case */\n \tfor (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {\n \t\tif (params->phy[phy_idx].set_link_led) {\n-\t\t\tparams->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],\n-\t\t\t\t\t\t\t params, mode);\n+\t\t\tparams->phy[phy_idx].set_link_led(\n+\t\t\t\t¶ms->phy[phy_idx], params, mode);\n \t\t}\n \t}\n+#ifdef ELINK_INCLUDE_EMUL\n+\tif (params->feature_config_flags &\n+\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)\n+\t\treturn rc;\n+#endif\n \n \tswitch (mode) {\n \tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n@@ -5888,10 +7234,10 @@ elink_status_t elink_set_led(struct elink_params *params,\n \n \t\ttmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);\n \t\tif (params->phy[ELINK_EXT_PHY1].type ==\n-\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)\n+\t\t\tPORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)\n \t\t\ttmp &= ~(EMAC_LED_1000MB_OVERRIDE |\n-\t\t\t\t EMAC_LED_100MB_OVERRIDE |\n-\t\t\t\t EMAC_LED_10MB_OVERRIDE);\n+\t\t\t\tEMAC_LED_100MB_OVERRIDE |\n+\t\t\t\tEMAC_LED_10MB_OVERRIDE);\n \t\telse\n \t\t\ttmp |= EMAC_LED_OVERRIDE;\n \n@@ -5904,25 +7250,21 @@ elink_status_t elink_set_led(struct elink_params *params,\n \t\t */\n \t\tif (!vars->link_up)\n \t\t\tbreak;\n-\t\t/* fall-through */\n \tcase ELINK_LED_MODE_ON:\n \t\tif (((params->phy[ELINK_EXT_PHY1].type ==\n-\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||\n-\t\t (params->phy[ELINK_EXT_PHY1].type ==\n-\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&\n+\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||\n+\t\t\t (params->phy[ELINK_EXT_PHY1].type ==\n+\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&\n \t\t CHIP_IS_E2(sc) && params->num_phys == 2) {\n-\t\t\t/* This is a work-around for E2+8727 Configurations */\n+\t\t\t/* This is a work-around for E2 + 8727 Configurations */\n \t\t\tif (mode == ELINK_LED_MODE_ON ||\n-\t\t\t speed == ELINK_SPEED_10000) {\n+\t\t\t\tspeed == ELINK_SPEED_10000){\n \t\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);\n \t\t\t\tREG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);\n \n-\t\t\t\ttmp =\n-\t\t\t\t elink_cb_reg_read(sc,\n-\t\t\t\t\t\t emac_base +\n-\t\t\t\t\t\t EMAC_REG_EMAC_LED);\n-\t\t\t\telink_cb_reg_write(sc,\n-\t\t\t\t\t\t emac_base +\n+\t\t\t\ttmp = elink_cb_reg_read(sc, emac_base +\n+\t\t\t\t\t\t\tEMAC_REG_EMAC_LED);\n+\t\t\t\telink_cb_reg_write(sc, emac_base +\n \t\t\t\t\t\t EMAC_REG_EMAC_LED,\n \t\t\t\t\t\t (tmp | EMAC_LED_OVERRIDE));\n \t\t\t\t/* Return here without enabling traffic\n@@ -5938,22 +7280,23 @@ elink_status_t elink_set_led(struct elink_params *params,\n \t\t\t * is up in CL73\n \t\t\t */\n \t\t\tif ((!CHIP_IS_E3(sc)) ||\n-\t\t\t (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))\n+\t\t\t (CHIP_IS_E3(sc) &&\n+\t\t\t mode == ELINK_LED_MODE_ON))\n \t\t\t\tREG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);\n \n \t\t\tif (CHIP_IS_E1x(sc) ||\n-\t\t\t CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))\n+\t\t\t CHIP_IS_E2(sc) ||\n+\t\t\t (mode == ELINK_LED_MODE_ON))\n \t\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);\n \t\t\telse\n \t\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,\n \t\t\t\t hw_led_mode);\n \t\t} else if ((params->phy[ELINK_EXT_PHY1].type ==\n-\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&\n+\t\t\t PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) &&\n \t\t\t (mode == ELINK_LED_MODE_ON)) {\n \t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);\n-\t\t\ttmp =\n-\t\t\t elink_cb_reg_read(sc,\n-\t\t\t\t\t emac_base + EMAC_REG_EMAC_LED);\n+\t\t\ttmp = elink_cb_reg_read(sc, emac_base +\n+\t\t\t\t\t\tEMAC_REG_EMAC_LED);\n \t\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,\n \t\t\t\t\t tmp | EMAC_LED_OVERRIDE |\n \t\t\t\t\t EMAC_LED_1000MB_OVERRIDE);\n@@ -5963,11 +7306,10 @@ elink_status_t elink_set_led(struct elink_params *params,\n \t\t\tbreak;\n \t\t} else {\n \t\t\tuint32_t nig_led_mode = ((params->hw_led_mode <<\n-\t\t\t\t\t\t SHARED_HW_CFG_LED_MODE_SHIFT)\n-\t\t\t\t\t\t ==\n-\t\t\t\t\t\t SHARED_HW_CFG_LED_EXTPHY2)\n-\t\t\t ? (SHARED_HW_CFG_LED_PHY1 >>\n-\t\t\t SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;\n+\t\t\t\t\t SHARED_HW_CFG_LED_MODE_SHIFT) ==\n+\t\t\t\t\t SHARED_HW_CFG_LED_EXTPHY2) ?\n+\t\t\t\t(SHARED_HW_CFG_LED_PHY1 >>\n+\t\t\t\t SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;\n \t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,\n \t\t\t nig_led_mode);\n \t\t}\n@@ -5981,27 +7323,133 @@ elink_status_t elink_set_led(struct elink_params *params,\n \t\telse\n \t\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,\n \t\t\t LED_BLINK_RATE_VAL_E1X_E2);\n-\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);\n+\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +\n+\t\t port * 4, 1);\n \t\ttmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);\n \t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,\n-\t\t\t\t (tmp & (~EMAC_LED_OVERRIDE)));\n+\t\t\t(tmp & (~EMAC_LED_OVERRIDE)));\n \n+\t\tif (CHIP_IS_E1(sc) &&\n+\t\t ((speed == ELINK_SPEED_2500) ||\n+\t\t (speed == ELINK_SPEED_1000) ||\n+\t\t (speed == ELINK_SPEED_100) ||\n+\t\t (speed == ELINK_SPEED_10))) {\n+\t\t\t/* For speeds less than 10G LED scheme is different */\n+\t\t\tREG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0\n+\t\t\t + port * 4, 1);\n+\t\t\tREG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +\n+\t\t\t port * 4, 0);\n+\t\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +\n+\t\t\t port * 4, 1);\n+\t\t}\n \t\tbreak;\n \n \tdefault:\n \t\trc = ELINK_STATUS_ERROR;\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"elink_set_led: Invalid led mode %d\", mode);\n+\t\tELINK_DEBUG_P1(sc, \"elink_set_led: Invalid led mode %d\",\n+\t\t\t mode);\n \t\tbreak;\n \t}\n \treturn rc;\n \n }\n \n+/* This function comes to reflect the actual link state read DIRECTLY from the\n+ * HW\n+ */\n+elink_status_t elink_test_link(struct elink_params *params,\n+\t\t\t __rte_unused struct elink_vars *vars,\n+\t\t uint8_t is_serdes)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tuint16_t gp_status = 0, phy_index = 0;\n+\tuint8_t ext_phy_link_up = 0, serdes_phy_type;\n+\tstruct elink_vars temp_vars;\n+\tstruct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];\n+#ifdef ELINK_INCLUDE_FPGA\n+\tif (CHIP_REV_IS_FPGA(sc))\n+\t\treturn ELINK_STATUS_OK;\n+#endif\n+#ifdef ELINK_INCLUDE_EMUL\n+\tif (CHIP_REV_IS_EMUL(sc))\n+\t\treturn ELINK_STATUS_OK;\n+#endif\n+\n+\tif (CHIP_IS_E3(sc)) {\n+\t\tuint16_t link_up;\n+\t\tif (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]\n+\t\t > ELINK_SPEED_10000) {\n+\t\t\t/* Check 20G link */\n+\t\t\telink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,\n+\t\t\t\t\t1, &link_up);\n+\t\t\telink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,\n+\t\t\t\t\t1, &link_up);\n+\t\t\tlink_up &= (1 << 2);\n+\t\t} else {\n+\t\t\t/* Check 10G link and below*/\n+\t\t\tuint8_t lane = elink_get_warpcore_lane(int_phy, params);\n+\t\t\telink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,\n+\t\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_1,\n+\t\t\t\t\t&gp_status);\n+\t\t\tgp_status = ((gp_status >> 8) & 0xf) |\n+\t\t\t\t((gp_status >> 12) & 0xf);\n+\t\t\tlink_up = gp_status & (1 << lane);\n+\t\t}\n+\t\tif (!link_up)\n+\t\t\treturn ELINK_STATUS_NO_LINK;\n+\t} else {\n+\t\tCL22_RD_OVER_CL45(sc, int_phy,\n+\t\t\t MDIO_REG_BANK_GP_STATUS,\n+\t\t\t MDIO_GP_STATUS_TOP_AN_STATUS1,\n+\t\t\t &gp_status);\n+\t/* Link is up only if both local phy and external phy are up */\n+\tif (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))\n+\t\treturn ELINK_STATUS_NO_LINK;\n+\t}\n+\t/* In XGXS loopback mode, do not check external PHY */\n+\tif (params->loopback_mode == ELINK_LOOPBACK_XGXS)\n+\t\treturn ELINK_STATUS_OK;\n+\n+\tswitch (params->num_phys) {\n+\tcase 1:\n+\t\t/* No external PHY */\n+\t\treturn ELINK_STATUS_OK;\n+\tcase 2:\n+\t\text_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(\n+\t\t\t¶ms->phy[ELINK_EXT_PHY1],\n+\t\t\tparams, &temp_vars);\n+\t\tbreak;\n+\tcase 3: /* Dual Media */\n+\t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n+\t\t phy_index++) {\n+\t\t\tserdes_phy_type = ((params->phy[phy_index].media_type ==\n+\t\t\t\t\t ELINK_ETH_PHY_SFPP_10G_FIBER) ||\n+\t\t\t\t\t (params->phy[phy_index].media_type ==\n+\t\t\t\t\t ELINK_ETH_PHY_SFP_1G_FIBER) ||\n+\t\t\t\t\t (params->phy[phy_index].media_type ==\n+\t\t\t\t\t ELINK_ETH_PHY_XFP_FIBER) ||\n+\t\t\t\t\t (params->phy[phy_index].media_type ==\n+\t\t\t\t\t ELINK_ETH_PHY_DA_TWINAX));\n+\n+\t\t\tif (is_serdes != serdes_phy_type)\n+\t\t\t\tcontinue;\n+\t\t\tif (params->phy[phy_index].read_status) {\n+\t\t\t\text_phy_link_up |=\n+\t\t\t\t\tparams->phy[phy_index].read_status(\n+\t\t\t\t\t\t¶ms->phy[phy_index],\n+\t\t\t\t\t\tparams, &temp_vars);\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tif (ext_phy_link_up)\n+\t\treturn ELINK_STATUS_OK;\n+\treturn ELINK_STATUS_NO_LINK;\n+}\n+\n static elink_status_t elink_link_initialize(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_vars *vars)\n {\n-\telink_status_t rc = ELINK_STATUS_OK;\n \tuint8_t phy_index, non_ext_phy;\n \tstruct bnx2x_softc *sc = params->sc;\n \t/* In case of external phy existence, the line speed would be the\n@@ -6026,11 +7474,12 @@ static elink_status_t elink_link_initialize(struct elink_params *params,\n \t (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {\n \t\tstruct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];\n \t\tif (vars->line_speed == ELINK_SPEED_AUTO_NEG &&\n-\t\t (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))\n+\t\t (CHIP_IS_E1x(sc) ||\n+\t\t CHIP_IS_E2(sc)))\n \t\t\telink_set_parallel_detection(phy, params);\n \t\tif (params->phy[ELINK_INT_PHY].config_init)\n-\t\t\tparams->phy[ELINK_INT_PHY].config_init(phy,\n-\t\t\t\t\t\t\t params, vars);\n+\t\t\tparams->phy[ELINK_INT_PHY].config_init(phy, params,\n+\t\t\t\t\t\t\t vars);\n \t}\n \n \t/* Re-read this value in case it was changed inside config_init due to\n@@ -6038,14 +7487,14 @@ static elink_status_t elink_link_initialize(struct elink_params *params,\n \t */\n \tvars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;\n \n-\t/* Init external phy */\n+\t/* Init external phy*/\n \tif (non_ext_phy) {\n \t\tif (params->phy[ELINK_INT_PHY].supported &\n \t\t ELINK_SUPPORTED_FIBRE)\n \t\t\tvars->link_status |= LINK_STATUS_SERDES_LINK;\n \t} else {\n \t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n-\t\t phy_index++) {\n+\t\t phy_index++) {\n \t\t\t/* No need to initialize second phy in case of first\n \t\t\t * phy only selection. In case of second phy, we do\n \t\t\t * need to initialize the first phy, since they are\n@@ -6058,13 +7507,13 @@ static elink_status_t elink_link_initialize(struct elink_params *params,\n \t\t\tif (phy_index == ELINK_EXT_PHY2 &&\n \t\t\t (elink_phy_selection(params) ==\n \t\t\t PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t\t \"Not initializing second phy\");\n+\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t \"Not initializing second phy\");\n \t\t\t\tcontinue;\n \t\t\t}\n-\t\t\tparams->phy[phy_index].config_init(¶ms->\n-\t\t\t\t\t\t\t phy[phy_index],\n-\t\t\t\t\t\t\t params, vars);\n+\t\t\tparams->phy[phy_index].config_init(\n+\t\t\t\t¶ms->phy[phy_index],\n+\t\t\t\tparams, vars);\n \t\t}\n \t}\n \t/* Reset the interrupt indication after phy was initialized */\n@@ -6074,7 +7523,7 @@ static elink_status_t elink_link_initialize(struct elink_params *params,\n \t\t\tELINK_NIG_STATUS_XGXS0_LINK_STATUS |\n \t\t\tELINK_NIG_STATUS_SERDES0_LINK_STATUS |\n \t\t\tELINK_NIG_MASK_MI_INT));\n-\treturn rc;\n+\treturn ELINK_STATUS_OK;\n }\n \n static void elink_int_link_reset(__rte_unused struct elink_phy *phy,\n@@ -6096,19 +7545,21 @@ static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,\n \telse\n \t\tgpio_port = params->port;\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW,\n+\t\t gpio_port);\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);\n-\tPMD_DRV_LOG(DEBUG, sc, \"reset external PHY\");\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW,\n+\t\t gpio_port);\n+\tELINK_DEBUG_P0(sc, \"reset external PHY\");\n }\n \n static elink_status_t elink_update_link_down(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port = params->port;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Port %x: Link is down\", port);\n+\tELINK_DEBUG_P1(sc, \"Port %x: Link is down\", port);\n \telink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);\n \tvars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;\n \t/* Indicate no mac active */\n@@ -6128,8 +7579,9 @@ static elink_status_t elink_update_link_down(struct elink_params *params,\n \n \tDELAY(1000 * 10);\n \t/* Reset BigMac/Xmac */\n-\tif (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))\n-\t\telink_set_bmac_rx(sc, params->port, 0);\n+\tif (CHIP_IS_E1x(sc) ||\n+\t CHIP_IS_E2(sc))\n+\t\telink_set_bmac_rx(sc, params->chip_id, params->port, 0);\n \n \tif (CHIP_IS_E3(sc)) {\n \t\t/* Prevent LPI Generation by chip */\n@@ -6149,8 +7601,8 @@ static elink_status_t elink_update_link_down(struct elink_params *params,\n }\n \n static elink_status_t elink_update_link_up(struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t\t uint8_t link_10g)\n+\t\t\t\tstruct elink_vars *vars,\n+\t\t\t\tuint8_t link_10g)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t phy_idx, port = params->port;\n@@ -6161,15 +7613,17 @@ static elink_status_t elink_update_link_up(struct elink_params *params,\n \tvars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;\n \n \tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n-\t\tvars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;\n+\t\tvars->link_status |=\n+\t\t\tLINK_STATUS_TX_FLOW_CONTROL_ENABLED;\n \n \tif (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)\n-\t\tvars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;\n+\t\tvars->link_status |=\n+\t\t\tLINK_STATUS_RX_FLOW_CONTROL_ENABLED;\n \tif (USES_WARPCORE(sc)) {\n \t\tif (link_10g) {\n \t\t\tif (elink_xmac_enable(params, vars, 0) ==\n \t\t\t ELINK_STATUS_NO_LINK) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Found errors on XMAC\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Found errors on XMAC\");\n \t\t\t\tvars->link_up = 0;\n \t\t\t\tvars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;\n \t\t\t\tvars->link_status &= ~LINK_STATUS_LINK_UP;\n@@ -6181,7 +7635,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params,\n \n \t\tif ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&\n \t\t (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Enabling LPI assertion\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Enabling LPI assertion\");\n \t\t\tREG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +\n \t\t\t (params->port << 2), 1);\n \t\t\tREG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);\n@@ -6189,11 +7643,12 @@ static elink_status_t elink_update_link_up(struct elink_params *params,\n \t\t\t (params->port << 2), 0xfc20);\n \t\t}\n \t}\n-\tif ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {\n+\tif ((CHIP_IS_E1x(sc) ||\n+\t CHIP_IS_E2(sc))) {\n \t\tif (link_10g) {\n \t\t\tif (elink_bmac_enable(params, vars, 0, 1) ==\n \t\t\t ELINK_STATUS_NO_LINK) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Found errors on BMAC\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Found errors on BMAC\");\n \t\t\t\tvars->link_up = 0;\n \t\t\t\tvars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;\n \t\t\t\tvars->link_status &= ~LINK_STATUS_LINK_UP;\n@@ -6236,6 +7691,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params,\n \treturn rc;\n }\n \n+static void elink_chng_link_count(struct elink_params *params, uint8_t clear)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tuint32_t addr, val;\n+\n+\t/* Verify the link_change_count is supported by the MFW */\n+\tif (!(SHMEM2_HAS(sc, link_change_count)))\n+\t\treturn;\n+\n+\taddr = params->shmem2_base +\n+\t\toffsetof(struct shmem2_region, link_change_count[params->port]);\n+\tif (clear)\n+\t\tval = 0;\n+\telse\n+\t\tval = REG_RD(sc, addr) + 1;\n+\tREG_WR(sc, addr, val);\n+}\n+\n /* The elink_link_update function should be called upon link\n * interrupt.\n * Link is considered up as follows:\n@@ -6248,24 +7721,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params,\n * external phy needs to be up, and at least one of the 2\n * external phy link must be up.\n */\n-elink_status_t elink_link_update(struct elink_params * params,\n-\t\t\t\t struct elink_vars * vars)\n+elink_status_t elink_link_update(struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tstruct elink_vars phy_vars[ELINK_MAX_PHYS];\n \tuint8_t port = params->port;\n \tuint8_t link_10g_plus, phy_index;\n+\tuint32_t prev_link_status = vars->link_status;\n \tuint8_t ext_phy_link_up = 0, cur_link_up;\n \telink_status_t rc = ELINK_STATUS_OK;\n-\t__rte_unused uint8_t is_mi_int = 0;\n \tuint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;\n \tuint8_t active_external_phy = ELINK_INT_PHY;\n \tvars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;\n \tvars->link_status &= ~ELINK_LINK_UPDATE_MASK;\n \tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n-\t phy_index++) {\n+\t phy_index++) {\n \t\tphy_vars[phy_index].flow_ctrl = 0;\n-\t\tphy_vars[phy_index].link_status = ETH_LINK_DOWN;\n+\t\tphy_vars[phy_index].link_status = 0;\n \t\tphy_vars[phy_index].line_speed = 0;\n \t\tphy_vars[phy_index].duplex = DUPLEX_FULL;\n \t\tphy_vars[phy_index].phy_link_up = 0;\n@@ -6278,21 +7751,18 @@ elink_status_t elink_link_update(struct elink_params * params,\n \tif (USES_WARPCORE(sc))\n \t\telink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"port %x, XGXS?%x, int_status 0x%x\",\n-\t\t port, (vars->phy_flags & PHY_XGXS_FLAG),\n-\t\t REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));\n+\tELINK_DEBUG_P3(sc, \"port %x, XGXS?%x, int_status 0x%x\",\n+\t\t port, (vars->phy_flags & PHY_XGXS_FLAG),\n+\t\t REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));\n \n-\tis_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +\n-\t\t\t\t port * 0x18) > 0);\n-\tPMD_DRV_LOG(DEBUG, sc, \"int_mask 0x%x MI_INT %x, SERDES_LINK %x\",\n-\t\t REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),\n-\t\t is_mi_int,\n-\t\t REG_RD(sc,\n-\t\t\t NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));\n+\tELINK_DEBUG_P3(sc, \"int_mask 0x%x MI_INT %x, SERDES_LINK %x\",\n+\t\t REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),\n+\t\t REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18) > 0,\n+\t\t REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));\n \n-\tPMD_DRV_LOG(DEBUG, sc, \" 10G %x, XGXS_LINK %x\",\n-\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),\n-\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));\n+\tELINK_DEBUG_P2(sc, \" 10G %x, XGXS_LINK %x\",\n+\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),\n+\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));\n \n \t/* Disable emac */\n \tif (!CHIP_IS_E3(sc))\n@@ -6306,7 +7776,7 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t * speed/duplex result\n \t */\n \tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n-\t phy_index++) {\n+\t phy_index++) {\n \t\tstruct elink_phy *phy = ¶ms->phy[phy_index];\n \t\tif (!phy->read_status)\n \t\t\tcontinue;\n@@ -6314,11 +7784,11 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t\tcur_link_up = phy->read_status(phy, params,\n \t\t\t\t\t &phy_vars[phy_index]);\n \t\tif (cur_link_up) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"phy in index %d link is up\",\n-\t\t\t\t phy_index);\n+\t\t\tELINK_DEBUG_P1(sc, \"phy in index %d link is up\",\n+\t\t\t\t phy_index);\n \t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"phy in index %d link is down\",\n-\t\t\t\t phy_index);\n+\t\t\tELINK_DEBUG_P1(sc, \"phy in index %d link is down\",\n+\t\t\t\t phy_index);\n \t\t\tcontinue;\n \t\t}\n \n@@ -6329,30 +7799,30 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t\t\tswitch (elink_phy_selection(params)) {\n \t\t\tcase PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:\n \t\t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:\n-\t\t\t\t/* In this option, the first PHY makes sure to pass the\n-\t\t\t\t * traffic through itself only.\n-\t\t\t\t * Its not clear how to reset the link on the second phy\n-\t\t\t\t */\n+\t\t\t/* In this option, the first PHY makes sure to pass the\n+\t\t\t * traffic through itself only.\n+\t\t\t * Its not clear how to reset the link on the second phy\n+\t\t\t */\n \t\t\t\tactive_external_phy = ELINK_EXT_PHY1;\n \t\t\t\tbreak;\n \t\t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:\n-\t\t\t\t/* In this option, the first PHY makes sure to pass the\n-\t\t\t\t * traffic through the second PHY.\n-\t\t\t\t */\n+\t\t\t/* In this option, the first PHY makes sure to pass the\n+\t\t\t * traffic through the second PHY.\n+\t\t\t */\n \t\t\t\tactive_external_phy = ELINK_EXT_PHY2;\n \t\t\t\tbreak;\n \t\t\tdefault:\n-\t\t\t\t/* Link indication on both PHYs with the following cases\n-\t\t\t\t * is invalid:\n-\t\t\t\t * - FIRST_PHY means that second phy wasn't initialized,\n-\t\t\t\t * hence its link is expected to be down\n-\t\t\t\t * - SECOND_PHY means that first phy should not be able\n-\t\t\t\t * to link up by itself (using configuration)\n-\t\t\t\t * - DEFAULT should be overridden during initialization\n-\t\t\t\t */\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid link indication\"\n-\t\t\t\t\t \"mpc=0x%x. DISABLING LINK !!!\",\n-\t\t\t\t\t params->multi_phy_config);\n+\t\t\t/* Link indication on both PHYs with the following cases\n+\t\t\t * is invalid:\n+\t\t\t * - FIRST_PHY means that second phy wasn't initialized,\n+\t\t\t * hence its link is expected to be down\n+\t\t\t * - SECOND_PHY means that first phy should not be able\n+\t\t\t * to link up by itself (using configuration)\n+\t\t\t * - DEFAULT should be overridden during initialiazation\n+\t\t\t */\n+\t\t\t\tELINK_DEBUG_P1(sc, \"Invalid link indication\"\n+\t\t\t\t\t \" mpc=0x%x. DISABLING LINK !!!\",\n+\t\t\t\t\t params->multi_phy_config);\n \t\t\t\text_phy_link_up = 0;\n \t\t\t\tbreak;\n \t\t\t}\n@@ -6366,9 +7836,9 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t * external phy\n \t */\n \tif (params->phy[ELINK_INT_PHY].read_status)\n-\t\tparams->phy[ELINK_INT_PHY].read_status(¶ms->\n-\t\t\t\t\t\t phy[ELINK_INT_PHY],\n-\t\t\t\t\t\t params, vars);\n+\t\tparams->phy[ELINK_INT_PHY].read_status(\n+\t\t\t¶ms->phy[ELINK_INT_PHY],\n+\t\t\tparams, vars);\n \t/* The INT_PHY flow control reside in the vars. This include the\n \t * case where the speed or flow control are not set to AUTO.\n \t * Otherwise, the active external phy flow control result is set\n@@ -6388,11 +7858,11 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t\t */\n \t\tif (active_external_phy == ELINK_EXT_PHY1) {\n \t\t\tif (params->phy[ELINK_EXT_PHY2].phy_specific_func) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Disabling TX on EXT_PHY2\");\n-\t\t\t\tparams->phy[ELINK_EXT_PHY2].\n-\t\t\t\t phy_specific_func(¶ms->\n-\t\t\t\t\t\t phy[ELINK_EXT_PHY2],\n-\t\t\t\t\t\t params, ELINK_DISABLE_TX);\n+\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t \"Disabling TX on EXT_PHY2\");\n+\t\t\t\tparams->phy[ELINK_EXT_PHY2].phy_specific_func(\n+\t\t\t\t\t¶ms->phy[ELINK_EXT_PHY2],\n+\t\t\t\t\tparams, ELINK_DISABLE_TX);\n \t\t\t}\n \t\t}\n \n@@ -6406,12 +7876,27 @@ elink_status_t elink_link_update(struct elink_params * params,\n \n \t\tvars->eee_status = phy_vars[active_external_phy].eee_status;\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Active external phy selected: %x\",\n-\t\t\t active_external_phy);\n-\t}\n+\t\tELINK_DEBUG_P1(sc, \"Active external phy selected: %x\",\n+\t\t\t active_external_phy);\n+\t}\n+\n+\tELINK_DEBUG_P3(sc, \"vars : phy_flags = %x, mac_type = %x, phy_link_up = %x\",\n+\t\t vars->phy_flags, vars->mac_type, vars->phy_link_up);\n+\tELINK_DEBUG_P3(sc, \"vars : link_up = %x, line_speed = %x, duplex = %x\",\n+\t\t vars->link_up, vars->line_speed, vars->duplex);\n+\tELINK_DEBUG_P3(sc, \"vars : flow_ctrl = %x, ieee_fc = %x, link_status = %x\",\n+\t\t vars->flow_ctrl, vars->ieee_fc, vars->link_status);\n+\tELINK_DEBUG_P3(sc, \"vars : eee_status = %x, fault_detected = %x, check_kr2_recovery_cnt = %x\",\n+\t\t vars->eee_status, vars->fault_detected,\n+\t\t vars->check_kr2_recovery_cnt);\n+\tELINK_DEBUG_P3(sc, \"vars : periodic_flags = %x, aeu_int_mask = %x, rx_tx_asic_rst = %x\",\n+\t\t vars->periodic_flags, vars->aeu_int_mask,\n+\t\t vars->rx_tx_asic_rst);\n+\tELINK_DEBUG_P2(sc, \"vars : turn_to_run_wc_rt = %x, rsrv2 = %x\",\n+\t\t vars->turn_to_run_wc_rt, vars->rsrv2);\n \n \tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n-\t phy_index++) {\n+\t phy_index++) {\n \t\tif (params->phy[phy_index].flags &\n \t\t ELINK_FLAGS_REARM_LATCH_SIGNAL) {\n \t\t\telink_rearm_latch_signal(sc, port,\n@@ -6420,9 +7905,9 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t\t\tbreak;\n \t\t}\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,\"\n-\t\t \" ext_phy_line_speed = %d\", vars->flow_ctrl,\n-\t\t vars->link_status, ext_phy_line_speed);\n+\tELINK_DEBUG_P3(sc, \"vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,\"\n+\t\t \" ext_phy_line_speed = %d\", vars->flow_ctrl,\n+\t\t vars->link_status, ext_phy_line_speed);\n \t/* Upon link speed change set the NIG into drain mode. Comes to\n \t * deals with possible FIFO glitch due to clk change when speed\n \t * is decreased without link down indicator\n@@ -6431,15 +7916,15 @@ elink_status_t elink_link_update(struct elink_params * params,\n \tif (vars->phy_link_up) {\n \t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&\n \t\t (ext_phy_line_speed != vars->line_speed)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Internal link speed %d is\"\n-\t\t\t\t \" different than the external\"\n-\t\t\t\t \" link speed %d\", vars->line_speed,\n-\t\t\t\t ext_phy_line_speed);\n+\t\t\tELINK_DEBUG_P2(sc, \"Internal link speed %d is\"\n+\t\t\t\t \" different than the external\"\n+\t\t\t\t \" link speed %d\", vars->line_speed,\n+\t\t\t\t ext_phy_line_speed);\n \t\t\tvars->phy_link_up = 0;\n+\t\t\tELINK_DEBUG_P0(sc, \"phy_link_up set to 0\");\n \t\t} else if (prev_line_speed != vars->line_speed) {\n-\t\t\tREG_WR(sc,\n-\t\t\t NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,\n-\t\t\t 0);\n+\t\t\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE +\n+\t\t\t params->port * 4, 0);\n \t\t\tDELAY(1000 * 1);\n \t\t}\n \t}\n@@ -6457,11 +7942,11 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t * initialize it\n \t */\n \tif (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"ext_phy_link_up = %d, int_link_up = %d,\"\n-\t\t\t \" init_preceding = %d\", ext_phy_link_up,\n-\t\t\t vars->phy_link_up,\n-\t\t\t params->phy[ELINK_EXT_PHY1].flags &\n-\t\t\t ELINK_FLAGS_INIT_XGXS_FIRST);\n+\t\tELINK_DEBUG_P3(sc, \"ext_phy_link_up = %d, int_link_up = %d,\"\n+\t\t\t \" init_preceding = %d\", ext_phy_link_up,\n+\t\t\t vars->phy_link_up,\n+\t\t\t params->phy[ELINK_EXT_PHY1].flags &\n+\t\t\t ELINK_FLAGS_INIT_XGXS_FIRST);\n \t\tif (!(params->phy[ELINK_EXT_PHY1].flags &\n \t\t ELINK_FLAGS_INIT_XGXS_FIRST)\n \t\t && ext_phy_link_up && !vars->phy_link_up) {\n@@ -6472,11 +7957,9 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t\t\t\tvars->phy_flags &= ~PHY_SGMII_FLAG;\n \n \t\t\tif (params->phy[ELINK_INT_PHY].config_init)\n-\t\t\t\tparams->phy[ELINK_INT_PHY].config_init(¶ms->\n-\t\t\t\t\t\t\t\t phy\n-\t\t\t\t\t\t\t\t [ELINK_INT_PHY],\n-\t\t\t\t\t\t\t\t params,\n-\t\t\t\t\t\t\t\t vars);\n+\t\t\t\tparams->phy[ELINK_INT_PHY].config_init(\n+\t\t\t\t\t¶ms->phy[ELINK_INT_PHY], params,\n+\t\t\t\t\t\tvars);\n \t\t}\n \t}\n \t/* Link is up only if both local phy and external phy (in case of\n@@ -6487,6 +7970,11 @@ elink_status_t elink_link_update(struct elink_params * params,\n \t\t\t ELINK_SINGLE_MEDIA_DIRECT(params)) &&\n \t\t\t (phy_vars[active_external_phy].fault_detected == 0));\n \n+\tif (vars->link_up)\n+\t\tELINK_DEBUG_P0(sc, \"local phy and external phy are up\");\n+\telse\n+\t\tELINK_DEBUG_P0(sc, \"either local phy or external phy or both are down\");\n+\n \t/* Update the PFC configuration in case it was changed */\n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n \t\tvars->link_status |= LINK_STATUS_PFC_ENABLED;\n@@ -6498,9 +7986,12 @@ elink_status_t elink_link_update(struct elink_params * params,\n \telse\n \t\trc = elink_update_link_down(params, vars);\n \n+\tif ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)\n+\t\telink_chng_link_count(params, 0);\n+\n \t/* Update MCP link status was changed */\n-\tif (params->\n-\t feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)\n+\tif (params->feature_config_flags &\n+\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)\n \t\telink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);\n \n \treturn rc;\n@@ -6509,28 +8000,28 @@ elink_status_t elink_link_update(struct elink_params * params,\n /*****************************************************************************/\n /*\t\t\t External Phy section\t\t\t */\n /*****************************************************************************/\n-static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)\n+void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)\n {\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n \tDELAY(1000 * 1);\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n }\n \n-static void elink_save_spirom_version(struct bnx2x_softc *sc,\n-\t\t\t\t __rte_unused uint8_t port,\n+static void elink_save_spirom_version(struct bnx2x_softc *sc, uint8_t port,\n \t\t\t\t uint32_t spirom_ver, uint32_t ver_addr)\n {\n-\tPMD_DRV_LOG(DEBUG, sc, \"FW version 0x%x:0x%x for port %d\",\n-\t\t (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);\n+\tELINK_DEBUG_P3(sc, \"FW version 0x%x:0x%x for port %d\",\n+\t\t (uint16_t)(spirom_ver >> 16), (uint16_t)spirom_ver, port);\n \n \tif (ver_addr)\n \t\tREG_WR(sc, ver_addr, spirom_ver);\n }\n \n static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,\n-\t\t\t\t struct elink_phy *phy, uint8_t port)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint8_t port)\n {\n \tuint16_t fw_ver1, fw_ver2;\n \n@@ -6538,18 +8029,21 @@ static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,\n \t\t\tMDIO_PMA_REG_ROM_VER1, &fw_ver1);\n \telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n \t\t\tMDIO_PMA_REG_ROM_VER2, &fw_ver2);\n-\telink_save_spirom_version(sc, port,\n-\t\t\t\t (uint32_t) (fw_ver1 << 16 | fw_ver2),\n+\telink_save_spirom_version(sc, port, (uint32_t)(fw_ver1 << 16 | fw_ver2),\n \t\t\t\t phy->ver_addr);\n }\n \n static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,\n-\t\t\t\t\t struct elink_phy *phy,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tuint16_t val;\n-\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);\n-\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_AN_DEVAD,\n+\t\t\tMDIO_AN_REG_STATUS, &val);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_AN_DEVAD,\n+\t\t\tMDIO_AN_REG_STATUS, &val);\n \tif (val & (1 << 5))\n \t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n \tif ((val & (1 << 0)) == 0)\n@@ -6573,8 +8067,8 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,\n \tif (elink_ext_phy_resolve_fc(phy, params, vars) &&\n \t (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {\n \t\tuint16_t pause_result;\n-\t\tuint16_t ld_pause;\t/* local */\n-\t\tuint16_t lp_pause;\t/* link partner */\n+\t\tuint16_t ld_pause;\t\t/* local */\n+\t\tuint16_t lp_pause;\t\t/* link partner */\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_AN_DEVAD,\n \t\t\t\tMDIO_AN_REG_CL37_FC_LD, &ld_pause);\n@@ -6587,31 +8081,35 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,\n \t\tpause_result |= (lp_pause &\n \t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;\n \n-\t\telink_pause_resolve(vars, pause_result);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Ext PHY CL37 pause result 0x%x\",\n-\t\t\t pause_result);\n+\t\telink_pause_resolve(phy, params, vars, pause_result);\n+\t\tELINK_DEBUG_P1(sc, \"Ext PHY CL37 pause result 0x%x\",\n+\t\t\t pause_result);\n \t}\n }\n-\n static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t\tstruct elink_phy *phy,\n-\t\t\t\t\t\t\tuint8_t port)\n+\t\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t\t uint8_t port)\n {\n \tuint32_t count = 0;\n-\tuint16_t fw_ver1 = 0, fw_msgout;\n+\tuint16_t fw_ver1, fw_msgout;\n \telink_status_t rc = ELINK_STATUS_OK;\n \n \t/* Boot port from external ROM */\n \t/* EDC grst */\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_GEN_CTRL,\n+\t\t\t 0x0001);\n \n \t/* Ucode reboot and rst */\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_GEN_CTRL,\n+\t\t\t 0x008c);\n \n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_MISC_CTRL1, 0x0001);\n \n \t/* Reset internal microprocessor */\n \telink_cl45_write(sc, phy,\n@@ -6632,10 +8130,10 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,\n \tdo {\n \t\tcount++;\n \t\tif (count > 300) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"elink_8073_8727_external_rom_boot port %x:\"\n-\t\t\t\t \"Download failed. fw version = 0x%x\",\n-\t\t\t\t port, fw_ver1);\n+\t\t\tELINK_DEBUG_P2(sc,\n+\t\t\t\t \"elink_8073_8727_external_rom_boot port %x:\"\n+\t\t\t\t \"Download failed. fw version = 0x%x\",\n+\t\t\t\t port, fw_ver1);\n \t\t\trc = ELINK_STATUS_ERROR;\n \t\t\tbreak;\n \t\t}\n@@ -6649,17 +8147,19 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,\n \n \t\tDELAY(1000 * 1);\n \t} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||\n-\t\t ((fw_msgout & 0xff) != 0x03 && (phy->type ==\n-\t\t\t\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));\n+\t\t\t((fw_msgout & 0xff) != 0x03 && (phy->type ==\n+\t\t\tPORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));\n \n \t/* Clear ser_boot_ctl bit */\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_MISC_CTRL1, 0x0000);\n \telink_save_bnx2x_spirom_ver(sc, phy, port);\n \n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"elink_8073_8727_external_rom_boot port %x:\"\n-\t\t \"Download complete. fw version = 0x%x\", port, fw_ver1);\n+\tELINK_DEBUG_P2(sc,\n+\t\t \"elink_8073_8727_external_rom_boot port %x:\"\n+\t\t \"Download complete. fw version = 0x%x\",\n+\t\t port, fw_ver1);\n \n \treturn rc;\n }\n@@ -6673,22 +8173,25 @@ static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,\n \t/* This is only required for 8073A1, version 102 only */\n \tuint16_t val;\n \n-\t/* Read 8073 HW revision */\n+\t/* Read 8073 HW revision*/\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_8073_CHIP_REV, &val);\n \n \tif (val != 1) {\n \t\t/* No need to workaround in 8073 A1 */\n \t\treturn ELINK_STATUS_OK;\n \t}\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_ROM_VER2, &val);\n \n \t/* SNR should be applied only for version 0x102 */\n \tif (val != 0x102)\n \t\treturn ELINK_STATUS_OK;\n \n-\treturn ELINK_STATUS_ERROR;\n+\treturn 1;\n }\n \n static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,\n@@ -6697,7 +8200,8 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,\n \tuint16_t val, cnt, cnt1;\n \n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_8073_CHIP_REV, &val);\n \n \tif (val > 0) {\n \t\t/* No need to workaround in 8073 A1 */\n@@ -6712,16 +8216,17 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,\n \tfor (cnt = 0; cnt < 1000; cnt++) {\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);\n-\t\t/* If bit [14] = 0 or bit [13] = 0, continue on with\n-\t\t * system initialization (XAUI work-around not required, as\n-\t\t * these bits indicate 2.5G or 1G link up).\n-\t\t */\n+\t\t\t\tMDIO_PMA_REG_8073_SPEED_LINK_STATUS,\n+\t\t\t\t&val);\n+\t\t /* If bit [14] = 0 or bit [13] = 0, continue on with\n+\t\t * system initialization (XAUI work-around not required, as\n+\t\t * these bits indicate 2.5G or 1G link up).\n+\t\t */\n \t\tif (!(val & (1 << 14)) || !(val & (1 << 13))) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"XAUI work-around not required\");\n+\t\t\tELINK_DEBUG_P0(sc, \"XAUI work-around not required\");\n \t\t\treturn ELINK_STATUS_OK;\n \t\t} else if (!(val & (1 << 15))) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"bit 15 went off\");\n+\t\t\tELINK_DEBUG_P0(sc, \"bit 15 went off\");\n \t\t\t/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's\n \t\t\t * MSB (bit15) goes to 1 (indicating that the XAUI\n \t\t\t * workaround has completed), then continue on with\n@@ -6729,12 +8234,11 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,\n \t\t\t */\n \t\t\tfor (cnt1 = 0; cnt1 < 1000; cnt1++) {\n \t\t\t\telink_cl45_read(sc, phy,\n-\t\t\t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\t\t\tMDIO_PMA_REG_8073_XAUI_WA,\n-\t\t\t\t\t\t&val);\n+\t\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\t\tMDIO_PMA_REG_8073_XAUI_WA, &val);\n \t\t\t\tif (val & (1 << 15)) {\n-\t\t\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t\t\t \"XAUI workaround has completed\");\n+\t\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t\t \"XAUI workaround has completed\");\n \t\t\t\t\treturn ELINK_STATUS_OK;\n \t\t\t\t}\n \t\t\t\tDELAY(1000 * 3);\n@@ -6743,19 +8247,21 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,\n \t\t}\n \t\tDELAY(1000 * 3);\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"Warning: XAUI work-around timeout !!!\");\n+\tELINK_DEBUG_P0(sc, \"Warning: XAUI work-around timeout !!!\");\n \treturn ELINK_STATUS_ERROR;\n }\n \n static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)\n {\n \t/* Force KR or KX */\n-\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);\n+\telink_cl45_write(sc, phy,\n+\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);\n-\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);\n+\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);\n+\telink_cl45_write(sc, phy,\n+\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);\n }\n \n static void elink_8073_set_pause_cl37(struct elink_params *params,\n@@ -6771,21 +8277,22 @@ static void elink_8073_set_pause_cl37(struct elink_params *params,\n \t/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */\n \telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n \tif ((vars->ieee_fc &\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==\n+\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==\n \t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {\n-\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;\n+\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;\n \t}\n \tif ((vars->ieee_fc &\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n+\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n \t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {\n-\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n+\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n \t}\n \tif ((vars->ieee_fc &\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n+\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n \t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {\n \t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"Ext phy AN advertize cl37 0x%x\", cl37_val);\n+\tELINK_DEBUG_P1(sc,\n+\t\t \"Ext phy AN advertize cl37 0x%x\", cl37_val);\n \n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);\n@@ -6803,31 +8310,31 @@ static void elink_8073_specific_func(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n \t\t\t\t (1 << 2));\n-\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,\n-\t\t\t\t 0x0004);\n+\t\telink_cl45_write(sc, phy,\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);\n \t\tbreak;\n \t}\n }\n \n-static uint8_t elink_8073_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_8073_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val = 0, tmp1;\n \tuint8_t gpio_port;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Init 8073\");\n+\tELINK_DEBUG_P0(sc, \"Init 8073\");\n \n \tif (CHIP_IS_E2(sc))\n \t\tgpio_port = SC_PATH(sc);\n \telse\n \t\tgpio_port = params->port;\n-\t/* Restore normal power mode */\n+\t/* Restore normal power mode*/\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);\n \n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);\n \n \telink_8073_specific_func(phy, params, ELINK_PHY_INIT);\n \telink_8073_set_pause_cl37(params, phy, vars);\n@@ -6835,14 +8342,15 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Before rom RX_ALARM(port1): 0x%x\", tmp1);\n+\tELINK_DEBUG_P1(sc, \"Before rom RX_ALARM(port1): 0x%x\", tmp1);\n \n \t/* Swap polarity if required - Must be done only in non-1G mode */\n \tif (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {\n \t\t/* Configure the 8073 to swap _P and _N of the KR lines */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Swapping polarity for the 8073\");\n+\t\tELINK_DEBUG_P0(sc, \"Swapping polarity for the 8073\");\n \t\t/* 10G Rx/Tx and 1G Tx signal polarity swap */\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD,\n@@ -6853,31 +8361,33 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,\n \t\t\t\t (val | (3 << 9)));\n \t}\n \n+\n \t/* Enable CL37 BAM */\n \tif (REG_RD(sc, params->shmem_base +\n-\t\t offsetof(struct shmem_region,\n-\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t default_cfg)) &\n+\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t port_hw_config[params->port].default_cfg)) &\n \t PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {\n \n \t\telink_cl45_read(sc, phy,\n-\t\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);\n+\t\t\t\tMDIO_AN_DEVAD,\n+\t\t\t\tMDIO_AN_REG_8073_BAM, &val);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Enable CL37 BAM on KR\");\n+\t\t\t\t MDIO_AN_DEVAD,\n+\t\t\t\t MDIO_AN_REG_8073_BAM, val | 1);\n+\t\tELINK_DEBUG_P0(sc, \"Enable CL37 BAM on KR\");\n \t}\n \tif (params->loopback_mode == ELINK_LOOPBACK_EXT) {\n \t\telink_807x_force_10G(sc, phy);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Forced speed 10G on 807X\");\n+\t\tELINK_DEBUG_P0(sc, \"Forced speed 10G on 807X\");\n \t\treturn ELINK_STATUS_OK;\n \t} else {\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);\n \t}\n \tif (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {\n \t\tif (phy->req_line_speed == ELINK_SPEED_10000) {\n \t\t\tval = (1 << 7);\n-\t\t} else if (phy->req_line_speed == ELINK_SPEED_2500) {\n+\t\t} else if (phy->req_line_speed == ELINK_SPEED_2500) {\n \t\t\tval = (1 << 5);\n \t\t\t/* Note that 2.5G works only when used with 1G\n \t\t\t * advertisement\n@@ -6886,15 +8396,16 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,\n \t\t\tval = (1 << 5);\n \t} else {\n \t\tval = 0;\n-\t\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n+\t\tif (phy->speed_cap_mask &\n+\t\t\tPORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n \t\t\tval |= (1 << 7);\n \n \t\t/* Note that 2.5G works only when used with 1G advertisement */\n \t\tif (phy->speed_cap_mask &\n-\t\t (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |\n-\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))\n+\t\t\t(PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |\n+\t\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))\n \t\t\tval |= (1 << 5);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"807x autoneg val = 0x%x\", val);\n+\t\tELINK_DEBUG_P1(sc, \"807x autoneg val = 0x%x\", val);\n \t}\n \n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);\n@@ -6908,13 +8419,13 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,\n \t\t\t\t&phy_ver);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Add 2.5G\");\n+\t\tELINK_DEBUG_P0(sc, \"Add 2.5G\");\n \t\tif (phy_ver > 0)\n \t\t\ttmp1 |= 1;\n \t\telse\n \t\t\ttmp1 &= 0xfffe;\n \t} else {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Disable 2.5G\");\n+\t\tELINK_DEBUG_P0(sc, \"Disable 2.5G\");\n \t\ttmp1 &= 0xfffe;\n \t}\n \n@@ -6948,14 +8459,14 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,\n \t/* Restart autoneg */\n \tDELAY(1000 * 500);\n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n-\tPMD_DRV_LOG(DEBUG, sc, \"807x Autoneg Restart: Advertise 1G=%x, 10G=%x\",\n-\t\t ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));\n+\tELINK_DEBUG_P2(sc, \"807x Autoneg Restart: Advertise 1G=%x, 10G=%x\",\n+\t\t ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));\n \treturn ELINK_STATUS_OK;\n }\n \n static uint8_t elink_8073_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t link_up = 0;\n@@ -6963,33 +8474,41 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,\n \tuint16_t link_status = 0;\n \tuint16_t an1000_status = 0;\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"8703 LASI status 0x%x\", val1);\n+\tELINK_DEBUG_P1(sc, \"8703 LASI status 0x%x\", val1);\n \n \t/* Clear the interrupt LASI status register */\n-\telink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);\n-\telink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"807x PCS status 0x%x->0x%x\", val2, val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);\n+\tELINK_DEBUG_P2(sc, \"807x PCS status 0x%x->0x%x\", val2, val1);\n \t/* Clear MSG-OUT */\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);\n \n \t/* Check the LASI */\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"KR 0x9003 0x%x\", val2);\n+\tELINK_DEBUG_P1(sc, \"KR 0x9003 0x%x\", val2);\n \n \t/* Check the link status */\n-\telink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);\n-\tPMD_DRV_LOG(DEBUG, sc, \"KR PCS status 0x%x\", val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);\n+\tELINK_DEBUG_P1(sc, \"KR PCS status 0x%x\", val2);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n \tlink_up = ((val1 & 4) == 4);\n-\tPMD_DRV_LOG(DEBUG, sc, \"PMA_REG_STATUS=0x%x\", val1);\n+\tELINK_DEBUG_P1(sc, \"PMA_REG_STATUS=0x%x\", val1);\n \n-\tif (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {\n+\tif (link_up &&\n+\t ((phy->req_line_speed != ELINK_SPEED_10000))) {\n \t\tif (elink_8073_xaui_wa(sc, phy) != 0)\n \t\t\treturn 0;\n \t}\n@@ -6999,10 +8518,12 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,\n \t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);\n \n \t/* Check the link status on 1.1.2 */\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"KR PMA status 0x%x->0x%x,\"\n-\t\t \"an_link_status=0x%x\", val2, val1, an1000_status);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n+\tELINK_DEBUG_P3(sc, \"KR PMA status 0x%x->0x%x,\"\n+\t\t \"an_link_status=0x%x\", val2, val1, an1000_status);\n \n \tlink_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));\n \tif (link_up && elink_8073_is_snr_needed(sc, phy)) {\n@@ -7027,27 +8548,28 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,\n \tif ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {\n \t\tlink_up = 1;\n \t\tvars->line_speed = ELINK_SPEED_10000;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link up in 10G\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link up in 10G\",\n+\t\t\t params->port);\n \t} else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {\n \t\tlink_up = 1;\n \t\tvars->line_speed = ELINK_SPEED_2500;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link up in 2.5G\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link up in 2.5G\",\n+\t\t\t params->port);\n \t} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {\n \t\tlink_up = 1;\n \t\tvars->line_speed = ELINK_SPEED_1000;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link up in 1G\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link up in 1G\",\n+\t\t\t params->port);\n \t} else {\n \t\tlink_up = 0;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link is down\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link is down\",\n+\t\t\t params->port);\n \t}\n \n \tif (link_up) {\n \t\t/* Swap polarity if required */\n-\t\tif (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {\n+\t\tif (params->lane_config &\n+\t\t PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {\n \t\t\t/* Configure the 8073 to swap P and N of the KR lines */\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_XS_DEVAD,\n@@ -7056,15 +8578,16 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,\n \t\t\t * when it`s in 10G mode.\n \t\t\t */\n \t\t\tif (vars->line_speed == ELINK_SPEED_1000) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Swapping 1G polarity for\"\n-\t\t\t\t\t \"the 8073\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Swapping 1G polarity for\"\n+\t\t\t\t\t \" the 8073\");\n \t\t\t\tval1 |= (1 << 3);\n \t\t\t} else\n \t\t\t\tval1 &= ~(1 << 3);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_XS_DEVAD,\n-\t\t\t\t\t MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);\n+\t\t\t\t\t MDIO_XS_REG_8073_RX_CTRL_PCIE,\n+\t\t\t\t\t val1);\n \t\t}\n \t\telink_ext_phy_10G_an_resolve(sc, phy, vars);\n \t\telink_8073_resolve_fc(phy, params, vars);\n@@ -7077,10 +8600,10 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,\n \n \t\tif (val1 & (1 << 5))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n \t\tif (val1 & (1 << 7))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n \t}\n \n \treturn link_up;\n@@ -7095,25 +8618,25 @@ static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,\n \t\tgpio_port = SC_PATH(sc);\n \telse\n \t\tgpio_port = params->port;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting 8073 port %d into low power mode\",\n-\t\t gpio_port);\n+\tELINK_DEBUG_P1(sc, \"Setting 8073 port %d into low power mode\",\n+\t gpio_port);\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW,\n+\t\t gpio_port);\n }\n \n /******************************************************************/\n /*\t\t\tBNX2X8705 PHY SECTION\t\t\t */\n /******************************************************************/\n-static uint8_t elink_8705_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t __rte_unused struct elink_vars\n-\t\t\t\t\t *vars)\n+static elink_status_t elink_8705_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t __rte_unused struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"init 8705\");\n-\t/* Restore normal power mode */\n+\tELINK_DEBUG_P0(sc, \"init 8705\");\n+\t/* Restore normal power mode*/\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n \t/* HW reset */\n \telink_ext_phy_hw_reset(sc, params->port);\n \telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);\n@@ -7125,36 +8648,40 @@ static uint8_t elink_8705_config_init(struct elink_phy *phy,\n \t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);\n-\telink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);\n+\telink_cl45_write(sc, phy,\n+\t\t\t MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);\n \t/* BNX2X8705 doesn't have microcode, hence the 0 */\n \telink_save_spirom_version(sc, params->port, params->shmem_base, 0);\n \treturn ELINK_STATUS_OK;\n }\n \n static uint8_t elink_8705_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tuint8_t link_up = 0;\n \tuint16_t val1, rx_sd;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"read status 8705\");\n+\tELINK_DEBUG_P0(sc, \"read status 8705\");\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"8705 LASI status 0x%x\", val1);\n+\t\t MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);\n+\tELINK_DEBUG_P1(sc, \"8705 LASI status 0x%x\", val1);\n \n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"8705 LASI status 0x%x\", val1);\n+\t\t MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);\n+\tELINK_DEBUG_P1(sc, \"8705 LASI status 0x%x\", val1);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);\n+\telink_cl45_read(sc, phy,\n+\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t MDIO_PMA_DEVAD, 0xc809, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t MDIO_PMA_DEVAD, 0xc809, &val1);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"8705 1.c809 val=0x%x\", val1);\n-\tlink_up = ((rx_sd & 0x1) && (val1 & (1 << 9))\n-\t\t && ((val1 & (1 << 8)) == 0));\n+\tELINK_DEBUG_P1(sc, \"8705 1.c809 val=0x%x\", val1);\n+\tlink_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) &&\n+\t\t ((val1 & (1 << 8)) == 0));\n \tif (link_up) {\n \t\tvars->line_speed = ELINK_SPEED_10000;\n \t\telink_ext_phy_resolve_fc(phy, params, vars);\n@@ -7175,17 +8702,17 @@ static void elink_set_disable_pmd_transmit(struct elink_params *params,\n \t */\n \tif (pmd_dis) {\n \t\tif (params->feature_config_flags &\n-\t\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Disabling PMD transmitter\");\n+\t\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {\n+\t\t\tELINK_DEBUG_P0(sc, \"Disabling PMD transmitter\");\n \t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"NOT disabling PMD transmitter\");\n+\t\t\tELINK_DEBUG_P0(sc, \"NOT disabling PMD transmitter\");\n \t\t\treturn;\n \t\t}\n-\t} else {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Enabling PMD transmitter\");\n-\t}\n+\t} else\n+\t\tELINK_DEBUG_P0(sc, \"Enabling PMD transmitter\");\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_TX_DISABLE, pmd_dis);\n }\n \n static uint8_t elink_get_gpio_port(struct elink_params *params)\n@@ -7193,37 +8720,38 @@ static uint8_t elink_get_gpio_port(struct elink_params *params)\n \tuint8_t gpio_port;\n \tuint32_t swap_val, swap_override;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tif (CHIP_IS_E2(sc)) {\n+\tif (CHIP_IS_E2(sc))\n \t\tgpio_port = SC_PATH(sc);\n-\t} else {\n+\telse\n \t\tgpio_port = params->port;\n-\t}\n \tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n \tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n \treturn gpio_port ^ (swap_val && swap_override);\n }\n \n static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,\n-\t\t\t\t\t struct elink_phy *phy, uint8_t tx_en)\n+\t\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t\t uint8_t tx_en)\n {\n \tuint16_t val;\n \tuint8_t port = params->port;\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t tx_en_mode;\n \n-\t/* Disable/Enable transmitter ( TX laser of the SFP+ module.) */\n+\t/* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/\n \ttx_en_mode = REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n \t\t\t\t dev_info.port_hw_config[port].sfp_ctrl)) &\n-\t PORT_HW_CFG_TX_LASER_MASK;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting transmitter tx_en=%x for port %x \"\n-\t\t \"mode = %x\", tx_en, port, tx_en_mode);\n+\t\tPORT_HW_CFG_TX_LASER_MASK;\n+\tELINK_DEBUG_P3(sc, \"Setting transmitter tx_en=%x for port %x \"\n+\t\t\t \"mode = %x\", tx_en, port, tx_en_mode);\n \tswitch (tx_en_mode) {\n \tcase PORT_HW_CFG_TX_LASER_MDIO:\n \n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &val);\n+\t\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER,\n+\t\t\t\t&val);\n \n \t\tif (tx_en)\n \t\t\tval &= ~(1 << 15);\n@@ -7232,37 +8760,38 @@ static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,\n \n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, val);\n-\t\tbreak;\n+\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER,\n+\t\t\t\t val);\n+\tbreak;\n \tcase PORT_HW_CFG_TX_LASER_GPIO0:\n \tcase PORT_HW_CFG_TX_LASER_GPIO1:\n \tcase PORT_HW_CFG_TX_LASER_GPIO2:\n \tcase PORT_HW_CFG_TX_LASER_GPIO3:\n-\t\t{\n-\t\t\tuint16_t gpio_pin;\n-\t\t\tuint8_t gpio_port, gpio_mode;\n-\t\t\tif (tx_en)\n-\t\t\t\tgpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;\n-\t\t\telse\n-\t\t\t\tgpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;\n+\t{\n+\t\tuint16_t gpio_pin;\n+\t\tuint8_t gpio_port, gpio_mode;\n+\t\tif (tx_en)\n+\t\t\tgpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;\n+\t\telse\n+\t\t\tgpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;\n \n-\t\t\tgpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;\n-\t\t\tgpio_port = elink_get_gpio_port(params);\n-\t\t\telink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);\n-\t\t\tbreak;\n-\t\t}\n+\t\tgpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;\n+\t\tgpio_port = elink_get_gpio_port(params);\n+\t\telink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);\n+\t\tbreak;\n+\t}\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Invalid TX_LASER_MDIO 0x%x\", tx_en_mode);\n+\t\tELINK_DEBUG_P1(sc, \"Invalid TX_LASER_MDIO 0x%x\", tx_en_mode);\n \t\tbreak;\n \t}\n }\n \n static void elink_sfp_set_transmitter(struct elink_params *params,\n-\t\t\t\t struct elink_phy *phy, uint8_t tx_en)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint8_t tx_en)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting SFP+ transmitter to %d\", tx_en);\n+\tELINK_DEBUG_P1(sc, \"Setting SFP+ transmitter to %d\", tx_en);\n \tif (CHIP_IS_E3(sc))\n \t\telink_sfp_e3_set_transmitter(params, phy, tx_en);\n \telse\n@@ -7270,20 +8799,17 @@ static void elink_sfp_set_transmitter(struct elink_params *params,\n }\n \n static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,\n-\t\t\t\t\t\t\tstruct elink_params\n-\t\t\t\t\t\t\t*params,\n-\t\t\t\t\t\t\tuint8_t dev_addr,\n-\t\t\t\t\t\t\tuint16_t addr,\n-\t\t\t\t\t\t\tuint8_t byte_cnt,\n-\t\t\t\t\t\t\tuint8_t * o_buf,\n-\t\t\t\t\t\t\t__rte_unused uint8_t\n-\t\t\t\t\t\t\tis_init)\n+\t\t\t struct elink_params *params,\n+\t\t\t uint8_t dev_addr, uint16_t addr,\n+\t\t\t uint8_t byte_cnt,\n+\t\t\t uint8_t *o_buf, __rte_unused uint8_t is_init)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val = 0;\n \tuint16_t i;\n \tif (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Reading from eeprom is limited to 0xf\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"Reading from eeprom is limited to 0xf\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \t/* Set the read command byte count */\n@@ -7313,10 +8839,10 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,\n \t}\n \n \tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=\n-\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Got bad status 0x%x when reading from SFP+ EEPROM\",\n-\t\t\t (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));\n+\t\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {\n+\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"Got bad status 0x%x when reading from SFP+ EEPROM\",\n+\t\t\t (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n@@ -7325,8 +8851,8 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD,\n \t\t\t\tMDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);\n-\t\to_buf[i] =\n-\t\t (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);\n+\t\to_buf[i] = (uint8_t)\n+\t\t\t\t(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);\n \t}\n \n \tfor (i = 0; i < 100; i++) {\n@@ -7349,29 +8875,27 @@ static void elink_warpcore_power_module(struct elink_params *params,\n \n \tpin_cfg = (REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t\t e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)\n-\t >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;\n+\t\t\tdev_info.port_hw_config[params->port].e3_sfp_ctrl)) &\n+\t\t\tPORT_HW_CFG_E3_PWR_DIS_MASK) >>\n+\t\t\tPORT_HW_CFG_E3_PWR_DIS_SHIFT;\n \n \tif (pin_cfg == PIN_CFG_NA)\n \t\treturn;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting SFP+ module power to %d using pin cfg %d\",\n-\t\t power, pin_cfg);\n+\tELINK_DEBUG_P2(sc, \"Setting SFP+ module power to %d using pin cfg %d\",\n+\t\t power, pin_cfg);\n \t/* Low ==> corresponding SFP+ module is powered\n \t * high ==> the SFP+ module is powered down\n \t */\n \telink_set_cfg_pin(sc, pin_cfg, power ^ 1);\n }\n-\n-static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct\n-\t\t\t\t\t\t\t elink_phy *phy,\n-\t\t\t\t\t\t\t struct elink_params\n-\t\t\t\t\t\t\t *params,\n-\t\t\t\t\t\t\t uint8_t dev_addr,\n-\t\t\t\t\t\t\t uint16_t addr,\n-\t\t\t\t\t\t\t uint8_t byte_cnt,\n-\t\t\t\t\t\t\t uint8_t * o_buf,\n-\t\t\t\t\t\t\t uint8_t is_init)\n+static elink_status_t elink_warpcore_read_sfp_module_eeprom(\n+\t\t\t\t\t __rte_unused struct elink_phy *phy,\n+\t\t\t\t\t struct elink_params *params,\n+\t\t\t\t\t uint8_t dev_addr,\n+\t\t\t\t\t uint16_t addr,\n+\t\t\t\t\t uint8_t byte_cnt,\n+\t\t\t\t\t uint8_t *o_buf,\n+\t\t\t\t\t uint8_t is_init)\n {\n \telink_status_t rc = ELINK_STATUS_OK;\n \tuint8_t i, j = 0, cnt = 0;\n@@ -7380,8 +8904,8 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct\n \tstruct bnx2x_softc *sc = params->sc;\n \n \tif (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Reading from eeprom is limited to 16 bytes\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"Reading from eeprom is limited to 16 bytes\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n@@ -7394,13 +8918,15 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct\n \t\t\tDELAY(1000 * 1);\n \t\t\telink_warpcore_power_module(params, 1);\n \t\t}\n-\t\trc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,\n+\n+\t\telink_bsc_module_sel(params);\n+\t\trc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt,\n \t\t\t\t data_array);\n \t} while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));\n \n \tif (rc == ELINK_STATUS_OK) {\n \t\tfor (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {\n-\t\t\to_buf[j] = *((uint8_t *) data_array + i);\n+\t\t\to_buf[j] = *((uint8_t *)data_array + i);\n \t\t\tj++;\n \t\t}\n \t}\n@@ -7409,20 +8935,18 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct\n }\n \n static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n-\t\t\t\t\t\t\tstruct elink_params\n-\t\t\t\t\t\t\t*params,\n-\t\t\t\t\t\t\tuint8_t dev_addr,\n-\t\t\t\t\t\t\tuint16_t addr,\n-\t\t\t\t\t\t\tuint8_t byte_cnt,\n-\t\t\t\t\t\t\tuint8_t * o_buf,\n-\t\t\t\t\t\t\t__rte_unused uint8_t\n-\t\t\t\t\t\t\tis_init)\n+\t\t\t\t\t struct elink_params *params,\n+\t\t\t\t\t uint8_t dev_addr, uint16_t addr,\n+\t\t\t\t\t uint8_t byte_cnt,\n+\t\t\t\t\t uint8_t *o_buf,\n+\t\t\t\t\t __rte_unused uint8_t is_init)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val, i;\n \n \tif (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Reading from eeprom is limited to 0xf\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"Reading from eeprom is limited to 0xf\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n@@ -7437,7 +8961,9 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n \n \t/* Need to read from 1.8000 to clear it */\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_SFP_TWO_WIRE_CTRL,\n+\t\t\t&val);\n \n \t/* Set the read command byte count */\n \telink_cl45_write(sc, phy,\n@@ -7448,16 +8974,19 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n \t/* Set the read command address */\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD,\n-\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);\n+\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,\n+\t\t\t addr);\n \t/* Set the destination address */\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD,\n-\t\t\t 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);\n+\t\t\t 0x8004,\n+\t\t\t MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);\n \n \t/* Activate read command */\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD,\n-\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);\n+\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,\n+\t\t\t 0x8002);\n \t/* Wait appropriate time for two-wire command to finish before\n \t * polling the status register\n \t */\n@@ -7475,10 +9004,10 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n \t}\n \n \tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=\n-\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Got bad status 0x%x when reading from SFP+ EEPROM\",\n-\t\t\t (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));\n+\t\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {\n+\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"Got bad status 0x%x when reading from SFP+ EEPROM\",\n+\t\t\t (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));\n \t\treturn ELINK_STATUS_TIMEOUT;\n \t}\n \n@@ -7487,8 +9016,8 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD,\n \t\t\t\tMDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);\n-\t\to_buf[i] =\n-\t\t (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);\n+\t\to_buf[i] = (uint8_t)\n+\t\t\t\t(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);\n \t}\n \n \tfor (i = 0; i < 100; i++) {\n@@ -7503,22 +9032,18 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n \n \treturn ELINK_STATUS_ERROR;\n }\n-\n-static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,\n-\t\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t\t uint8_t dev_addr,\n-\t\t\t\t\t\t uint16_t addr,\n-\t\t\t\t\t\t uint16_t byte_cnt,\n-\t\t\t\t\t\t uint8_t * o_buf)\n+elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params, uint8_t dev_addr,\n+\t\t\t\t uint16_t addr, uint16_t byte_cnt,\n+\t\t\t\t uint8_t *o_buf)\n {\n-\telink_status_t rc = ELINK_STATUS_OK;\n+\telink_status_t rc = 0;\n+\tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t xfer_size;\n \tuint8_t *user_data = o_buf;\n \tread_sfp_module_eeprom_func_p read_func;\n-\n \tif ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {\n-\t\tPMD_DRV_LOG(DEBUG, params->sc,\n-\t\t\t \"invalid dev_addr 0x%x\", dev_addr);\n+\t\tELINK_DEBUG_P1(sc, \"invalid dev_addr 0x%x\", dev_addr);\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n@@ -7539,7 +9064,7 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,\n \n \twhile (!rc && (byte_cnt > 0)) {\n \t\txfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?\n-\t\t ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;\n+\t\t\tELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;\n \t\trc = read_func(phy, params, dev_addr, addr, xfer_size,\n \t\t\t user_data, 0);\n \t\tbyte_cnt -= xfer_size;\n@@ -7550,91 +9075,105 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,\n }\n \n static elink_status_t elink_get_edc_mode(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t uint16_t * edc_mode)\n+\t\t\t struct elink_params *params,\n+\t\t\t uint16_t *edc_mode)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t sync_offset = 0, phy_idx, media_types;\n-\tuint8_t gport, val[2], check_limiting_mode = 0;\n+\tuint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1];\n+\tuint8_t check_limiting_mode = 0;\n \t*edc_mode = ELINK_EDC_MODE_LIMITING;\n \tphy->media_type = ELINK_ETH_PHY_UNSPECIFIED;\n \t/* First check for copper cable */\n \tif (elink_read_sfp_module_eeprom(phy,\n \t\t\t\t\t params,\n \t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n-\t\t\t\t\t ELINK_SFP_EEPROM_CON_TYPE_ADDR,\n-\t\t\t\t\t 2, (uint8_t *) val) != 0) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to read from SFP+ module EEPROM\");\n+\t\t\t\t\t 0,\n+\t\t\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1,\n+\t\t\t\t\t (uint8_t *)val) != 0) {\n+\t\tELINK_DEBUG_P0(sc, \"Failed to read from SFP+ module EEPROM\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n-\n-\tswitch (val[0]) {\n+\tparams->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;\n+\tparams->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] <<\n+\t\tLINK_SFP_EEPROM_COMP_CODE_SHIFT;\n+\telink_update_link_attr(params, params->link_attr_sync);\n+\tswitch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) {\n \tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:\n-\t\t{\n-\t\t\tuint8_t copper_module_type;\n-\t\t\tphy->media_type = ELINK_ETH_PHY_DA_TWINAX;\n-\t\t\t/* Check if its active cable (includes SFP+ module)\n-\t\t\t * of passive cable\n+\t{\n+\t\tuint8_t copper_module_type;\n+\t\tphy->media_type = ELINK_ETH_PHY_DA_TWINAX;\n+\t\t/* Check if its active cable (includes SFP+ module)\n+\t\t * of passive cable\n+\t\t */\n+\t\tcopper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR];\n+\t\tif (copper_module_type &\n+\t\t ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {\n+\t\t\tELINK_DEBUG_P0(sc, \"Active Copper cable detected\");\n+\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)\n+\t\t\t\t*edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;\n+\t\t\telse\n+\t\t\t\tcheck_limiting_mode = 1;\n+\t\t} else {\n+\t\t\t*edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;\n+\t\t\t/* Even in case PASSIVE_DAC indication is not set,\n+\t\t\t * treat it as a passive DAC cable, since some cables\n+\t\t\t * don't have this indication.\n \t\t\t */\n-\t\t\tif (elink_read_sfp_module_eeprom(phy,\n-\t\t\t\t\t\t\t params,\n-\t\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n-\t\t\t\t\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,\n-\t\t\t\t\t\t\t 1,\n-\t\t\t\t\t\t\t &copper_module_type) !=\n-\t\t\t 0) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t\t \"Failed to read copper-cable-type\"\n-\t\t\t\t\t \" from SFP+ EEPROM\");\n-\t\t\t\treturn ELINK_STATUS_ERROR;\n-\t\t\t}\n-\n \t\t\tif (copper_module_type &\n-\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t\t \"Active Copper cable detected\");\n-\t\t\t\tif (phy->type ==\n-\t\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)\n-\t\t\t\t\t*edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;\n-\t\t\t\telse\n-\t\t\t\t\tcheck_limiting_mode = 1;\n-\t\t\t} else if (copper_module_type &\n-\t\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)\n-\t\t\t{\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t\t \"Passive Copper cable detected\");\n-\t\t\t\t*edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;\n+\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {\n+\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t\t \"Passive Copper cable detected\");\n \t\t\t} else {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t\t \"Unknown copper-cable-type 0x%x !!!\",\n-\t\t\t\t\t copper_module_type);\n-\t\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t\t\t \"Unknown copper-cable-type\");\n \t\t\t}\n-\t\t\tbreak;\n \t\t}\n+\t\tbreak;\n+\t}\n+\tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:\n \tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:\n \tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:\n \t\tcheck_limiting_mode = 1;\n-\t\tif ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |\n-\t\t\t ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |\n-\t\t\t ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"1G SFP module detected\");\n-\t\t\tgport = params->port;\n+\t\t/* Module is considered as 1G in case it's NOT compliant with\n+\t\t * any 10G ethernet protocol, but is 1G Ethernet compliant.\n+\t\t */\n+\t\tif (((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] &\n+\t\t (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK |\n+\t\t ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK |\n+\t\t ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&\n+\t\t (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {\n+\t\t\tELINK_DEBUG_P0(sc, \"1G SFP module detected\");\n \t\t\tphy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;\n \t\t\tif (phy->req_line_speed != ELINK_SPEED_1000) {\n+\t\t\t\tuint8_t gport = params->port;\n \t\t\t\tphy->req_line_speed = ELINK_SPEED_1000;\n \t\t\t\tif (!CHIP_IS_E1x(sc)) {\n \t\t\t\t\tgport = SC_PATH(sc) +\n-\t\t\t\t\t (params->port << 1);\n+\t\t\t\t\t(params->port << 1);\n \t\t\t\t}\n-\t\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport);\t//\"Warning: Link speed was forced to 1000Mbps.\"\n-\t\t\t\t// \" Current SFP module in port %d is not\"\n-\t\t\t\t// \" compliant with 10G Ethernet\",\n+\t\t\t\telink_cb_event_log(sc,\n+\t\t\t\t\t\t ELINK_LOG_ID_NON_10G_MODULE,\n+\t\t\t\t\t\t gport);\n+\t\t\t\t /*\"Warning: Link speed was forced to 1000Mbps.\"\n+\t\t\t\t *\" Current SFP module in port %d is not\"\n+\t\t\t\t *\" compliant with 10G Ethernet\",\n+\t\t\t\t */\n+\t\t\t}\n \n+\t\t\tif (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] &\n+\t\t\t ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) {\n+\t\t\t\t/* Some 1G-baseT modules will not link up,\n+\t\t\t\t * unless TX_EN is toggled with long delay in\n+\t\t\t\t * between.\n+\t\t\t\t */\n+\t\t\t\telink_sfp_set_transmitter(params, phy, 0);\n+\t\t\t\tDELAY(1000 * 40);\n+\t\t\t\telink_sfp_set_transmitter(params, phy, 1);\n \t\t\t}\n \t\t} else {\n \t\t\tint idx, cfg_idx = 0;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"10G Optic module detected\");\n+\t\t\tELINK_DEBUG_P0(sc, \"10G Optic module detected\");\n \t\t\tfor (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {\n \t\t\t\tif (params->phy[idx].type == phy->type) {\n \t\t\t\t\tcfg_idx = ELINK_LINK_CONFIG_IDX(idx);\n@@ -7646,24 +9185,22 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,\n \t\t}\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Unable to determine module type 0x%x !!!\",\n-\t\t\t val[0]);\n+\t\tELINK_DEBUG_P1(sc, \"Unable to determine module type 0x%x !!!\",\n+\t\t\t val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]);\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \tsync_offset = params->shmem_base +\n-\t offsetof(struct shmem_region,\n-\t\t dev_info.port_hw_config[params->port].media_type);\n+\t\toffsetof(struct shmem_region,\n+\t\t\t dev_info.port_hw_config[params->port].media_type);\n \tmedia_types = REG_RD(sc, sync_offset);\n \t/* Update media type for non-PMF sync */\n \tfor (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {\n \t\tif (&(params->phy[phy_idx]) == phy) {\n \t\t\tmedia_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<\n-\t\t\t\t\t (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n-\t\t\t\t\t phy_idx));\n-\t\t\tmedia_types |=\n-\t\t\t ((phy->\n-\t\t\t media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<\n-\t\t\t (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));\n+\t\t\t\t(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));\n+\t\t\tmedia_types |= ((phy->media_type &\n+\t\t\t\t\tPORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<\n+\t\t\t\t(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));\n \t\t\tbreak;\n \t\t}\n \t}\n@@ -7676,8 +9213,8 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,\n \t\t\t\t\t\t ELINK_SFP_EEPROM_OPTIONS_ADDR,\n \t\t\t\t\t\t ELINK_SFP_EEPROM_OPTIONS_SIZE,\n \t\t\t\t\t\t options) != 0) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"Failed to read Option field from module EEPROM\");\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"Failed to read Option field from module EEPROM\");\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \t\tif ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))\n@@ -7685,15 +9222,14 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,\n \t\telse\n \t\t\t*edc_mode = ELINK_EDC_MODE_LIMITING;\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"EDC mode is set to 0x%x\", *edc_mode);\n+\tELINK_DEBUG_P1(sc, \"EDC mode is set to 0x%x\", *edc_mode);\n \treturn ELINK_STATUS_OK;\n }\n-\n /* This function read the relevant field from the module (SFP+), and verify it\n * is compliant with this board\n */\n static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params)\n+\t\t\t\t struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t val, cmd;\n@@ -7702,12 +9238,11 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n \tchar vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];\n \tphy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;\n \tval = REG_RD(sc, params->shmem_base +\n-\t\t offsetof(struct shmem_region,\n-\t\t\t dev_info.port_feature_config[params->port].\n-\t\t\t config));\n+\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t port_feature_config[params->port].config));\n \tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n \t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"NOT enforcing module verification\");\n+\t\tELINK_DEBUG_P0(sc, \"NOT enforcing module verification\");\n \t\treturn ELINK_STATUS_OK;\n \t}\n \n@@ -7717,23 +9252,24 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n \t\tcmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;\n \t} else if (params->feature_config_flags &\n \t\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {\n-\t\t/* Use first phy request only in case of non-dual media */\n+\t\t/* Use first phy request only in case of non-dual media*/\n \t\tif (ELINK_DUAL_MEDIA(params)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"FW does not support OPT MDL verification\");\n+\t\t\tELINK_DEBUG_P0(sc,\n+\t\t\t \"FW does not support OPT MDL verification\");\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \t\tcmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;\n \t} else {\n \t\t/* No support in OPT MDL detection */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"FW does not support OPT MDL verification\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"FW does not support OPT MDL verification\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n \tfw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);\n \tfw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);\n \tif (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Approved module\");\n+\t\tELINK_DEBUG_P0(sc, \"Approved module\");\n \t\treturn ELINK_STATUS_OK;\n \t}\n \n@@ -7743,7 +9279,7 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n \t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n \t\t\t\t\t ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,\n \t\t\t\t\t ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,\n-\t\t\t\t\t (uint8_t *) vendor_name))\n+\t\t\t\t\t (uint8_t *)vendor_name))\n \t\tvendor_name[0] = '\\0';\n \telse\n \t\tvendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\\0';\n@@ -7752,13 +9288,16 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n \t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n \t\t\t\t\t ELINK_SFP_EEPROM_PART_NO_ADDR,\n \t\t\t\t\t ELINK_SFP_EEPROM_PART_NO_SIZE,\n-\t\t\t\t\t (uint8_t *) vendor_pn))\n+\t\t\t\t\t (uint8_t *)vendor_pn))\n \t\tvendor_pn[0] = '\\0';\n \telse\n \t\tvendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\\0';\n \n-\telink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn);\t// \"Warning: Unqualified SFP+ module detected,\"\n-\t// \" Port %d from %s part number %s\",\n+\telink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port,\n+\t\t\t vendor_name, vendor_pn);\n+\t\t\t /* \"Warning: Unqualified SFP+ module detected,\"\n+\t\t\t * \" Port %d from %s part number %s\",\n+\t\t\t */\n \n \tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=\n \t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)\n@@ -7766,13 +9305,14 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n \treturn ELINK_STATUS_ERROR;\n }\n \n-static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy\n-\t\t\t\t\t\t\t *phy,\n-\t\t\t\t\t\t\t struct elink_params\n-\t\t\t\t\t\t\t *params)\n+static elink_status_t elink_wait_for_sfp_module_initialized(\n+\t\t\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t\t\t struct elink_params *params)\n+\n {\n \tuint8_t val;\n \telink_status_t rc;\n+\tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t timeout;\n \t/* Initialization time after hot-plug may take up to 300ms for\n \t * some phys type ( e.g. JDSU )\n@@ -7780,18 +9320,17 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy\n \n \tfor (timeout = 0; timeout < 60; timeout++) {\n \t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)\n-\t\t\trc = elink_warpcore_read_sfp_module_eeprom(phy, params,\n-\t\t\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n-\t\t\t\t\t\t\t\t 1, 1, &val,\n-\t\t\t\t\t\t\t\t 1);\n+\t\t\trc = elink_warpcore_read_sfp_module_eeprom(\n+\t\t\t\tphy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,\n+\t\t\t\t1);\n \t\telse\n \t\t\trc = elink_read_sfp_module_eeprom(phy, params,\n \t\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n \t\t\t\t\t\t\t 1, 1, &val);\n \t\tif (rc == 0) {\n-\t\t\tPMD_DRV_LOG(DEBUG, params->sc,\n-\t\t\t\t \"SFP+ module initialization took %d ms\",\n-\t\t\t\t timeout * 5);\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"SFP+ module initialization took %d ms\",\n+\t\t\t timeout * 5);\n \t\t\treturn ELINK_STATUS_OK;\n \t\t}\n \t\tDELAY(1000 * 5);\n@@ -7802,8 +9341,8 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy\n }\n \n static void elink_8727_power_module(struct bnx2x_softc *sc,\n-\t\t\t\t struct elink_phy *phy, uint8_t is_power_up)\n-{\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint8_t is_power_up) {\n \t/* Make sure GPIOs are not using for LED mode */\n \tuint16_t val;\n \t/* In the GPIO register, bit 4 is use to determine if the GPIOs are\n@@ -7828,30 +9367,33 @@ static void elink_8727_power_module(struct bnx2x_softc *sc,\n \t\tval = (1 << 1);\n \n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_8727_GPIO_CTRL,\n+\t\t\t val);\n }\n \n static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t struct elink_phy *phy,\n-\t\t\t\t\t\t uint16_t edc_mode)\n+\t\t\t\t\tstruct elink_phy *phy,\n+\t\t\t\t\tuint16_t edc_mode)\n {\n \tuint16_t cur_limiting_mode;\n \n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PMA_DEVAD,\n-\t\t\tMDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"Current Limiting mode is 0x%x\", cur_limiting_mode);\n+\t\t\tMDIO_PMA_REG_ROM_VER2,\n+\t\t\t&cur_limiting_mode);\n+\tELINK_DEBUG_P1(sc, \"Current Limiting mode is 0x%x\",\n+\t\t cur_limiting_mode);\n \n \tif (edc_mode == ELINK_EDC_MODE_LIMITING) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting LIMITING MODE\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting LIMITING MODE\");\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD,\n \t\t\t\t MDIO_PMA_REG_ROM_VER2,\n \t\t\t\t ELINK_EDC_MODE_LIMITING);\n-\t} else {\t\t/* LRM mode ( default ) */\n+\t} else { /* LRM mode ( default )*/\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting LRM MODE\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting LRM MODE\");\n \n \t\t/* Changing to LRM mode takes quite few seconds. So do it only\n \t\t * if current mode is limiting (default is LRM)\n@@ -7860,27 +9402,35 @@ static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,\n \t\t\treturn ELINK_STATUS_OK;\n \n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);\n+\t\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t\t MDIO_PMA_REG_LRM_MODE,\n+\t\t\t\t 0);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);\n+\t\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t\t MDIO_PMA_REG_ROM_VER2,\n+\t\t\t\t 0x128);\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t MDIO_PMA_REG_MISC_CTRL0, 0x4008);\n+\t\t\t\t MDIO_PMA_REG_MISC_CTRL0,\n+\t\t\t\t 0x4008);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);\n+\t\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t\t MDIO_PMA_REG_LRM_MODE,\n+\t\t\t\t 0xaaaa);\n \t}\n \treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t struct elink_phy *phy,\n-\t\t\t\t\t\t uint16_t edc_mode)\n+\t\t\t\t\tstruct elink_phy *phy,\n+\t\t\t\t\tuint16_t edc_mode)\n {\n \tuint16_t phy_identifier;\n \tuint16_t rom_ver2_val;\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PMA_DEVAD,\n-\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);\n+\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER,\n+\t\t\t&phy_identifier);\n \n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD,\n@@ -7888,7 +9438,9 @@ static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,\n \t\t\t (phy_identifier & ~(1 << 9)));\n \n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_ROM_VER2,\n+\t\t\t&rom_ver2_val);\n \t/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD,\n@@ -7922,12 +9474,14 @@ static void elink_8727_specific_func(struct elink_phy *phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n \t\t\t\t (1 << 2) | (1 << 5));\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,\n+\t\t\t\t 0);\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);\n \t\t/* Make MOD_ABS give interrupt on change */\n \t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);\n+\t\t\t\tMDIO_PMA_REG_8727_PCS_OPT_CTRL,\n+\t\t\t\t&val);\n \t\tval |= (1 << 12);\n \t\tif (phy->flags & ELINK_FLAGS_NOC)\n \t\t\tval |= (3 << 5);\n@@ -7935,29 +9489,27 @@ static void elink_8727_specific_func(struct elink_phy *phy,\n \t\t * status which reflect SFP+ module over-current\n \t\t */\n \t\tif (!(phy->flags & ELINK_FLAGS_NOC))\n-\t\t\tval &= 0xff8f;\t/* Reset bits 4-6 */\n+\t\t\tval &= 0xff8f; /* Reset bits 4-6 */\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,\n \t\t\t\t val);\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Function 0x%x not supported by 8727\",\n-\t\t\t action);\n+\t\tELINK_DEBUG_P1(sc, \"Function 0x%x not supported by 8727\",\n+\t\t action);\n \t\treturn;\n \t}\n }\n \n static void elink_set_e1e2_module_fault_led(struct elink_params *params,\n-\t\t\t\t\t uint8_t gpio_mode)\n+\t\t\t\t\t uint8_t gpio_mode)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \n \tuint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +\n-\t\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.\n-\t\t\t\t\t\t port_hw_config[params->port].\n-\t\t\t\t\t\t sfp_ctrl)) &\n-\t PORT_HW_CFG_FAULT_MODULE_LED_MASK;\n+\t\t\t offsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[params->port].sfp_ctrl)) &\n+\t\tPORT_HW_CFG_FAULT_MODULE_LED_MASK;\n \tswitch (fault_led_gpio) {\n \tcase PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:\n \t\treturn;\n@@ -7965,19 +9517,19 @@ static void elink_set_e1e2_module_fault_led(struct elink_params *params,\n \tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:\n \tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:\n \tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:\n-\t\t{\n-\t\t\tuint8_t gpio_port = elink_get_gpio_port(params);\n-\t\t\tuint16_t gpio_pin = fault_led_gpio -\n-\t\t\t PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Set fault module-detected led \"\n-\t\t\t\t \"pin %x port %x mode %x\",\n-\t\t\t\t gpio_pin, gpio_port, gpio_mode);\n-\t\t\telink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);\n-\t\t}\n-\t\tbreak;\n+\t{\n+\t\tuint8_t gpio_port = elink_get_gpio_port(params);\n+\t\tuint16_t gpio_pin = fault_led_gpio -\n+\t\t\tPORT_HW_CFG_FAULT_MODULE_LED_GPIO0;\n+\t\tELINK_DEBUG_P3(sc, \"Set fault module-detected led \"\n+\t\t\t\t \"pin %x port %x mode %x\",\n+\t\t\t gpio_pin, gpio_port, gpio_mode);\n+\t\telink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);\n+\t}\n+\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Error: Invalid fault led mode 0x%x\",\n-\t\t\t fault_led_gpio);\n+\t\tELINK_DEBUG_P1(sc, \"Error: Invalid fault led mode 0x%x\",\n+\t\t\t fault_led_gpio);\n \t}\n }\n \n@@ -7988,12 +9540,12 @@ static void elink_set_e3_module_fault_led(struct elink_params *params,\n \tuint8_t port = params->port;\n \tstruct bnx2x_softc *sc = params->sc;\n \tpin_cfg = (REG_RD(sc, params->shmem_base +\n-\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[port].e3_sfp_ctrl)) &\n-\t\t PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>\n-\t PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting Fault LED to %d using pin cfg %d\",\n-\t\t gpio_mode, pin_cfg);\n+\t\t\t offsetof(struct shmem_region,\n+\t\t\t\t dev_info.port_hw_config[port].e3_sfp_ctrl)) &\n+\t\tPORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>\n+\t\tPORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;\n+\tELINK_DEBUG_P2(sc, \"Setting Fault LED to %d using pin cfg %d\",\n+\t\t gpio_mode, pin_cfg);\n \telink_set_cfg_pin(sc, pin_cfg, gpio_mode);\n }\n \n@@ -8001,8 +9553,7 @@ static void elink_set_sfp_module_fault_led(struct elink_params *params,\n \t\t\t\t\t uint8_t gpio_mode)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"Setting SFP+ module fault LED to %d\", gpio_mode);\n+\tELINK_DEBUG_P1(sc, \"Setting SFP+ module fault LED to %d\", gpio_mode);\n \tif (CHIP_IS_E3(sc)) {\n \t\t/* Low ==> if SFP+ module is supported otherwise\n \t\t * High ==> if SFP+ module is not on the approved vendor list\n@@ -8027,9 +9578,11 @@ static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,\n }\n \n static void elink_power_sfp_module(struct elink_params *params,\n-\t\t\t\t struct elink_phy *phy, uint8_t power)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint8_t power)\n {\n-\tPMD_DRV_LOG(DEBUG, params->sc, \"Setting SFP+ power to %x\", power);\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tELINK_DEBUG_P1(sc, \"Setting SFP+ power to %x\", power);\n \n \tswitch (phy->type) {\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:\n@@ -8043,7 +9596,6 @@ static void elink_power_sfp_module(struct elink_params *params,\n \t\tbreak;\n \t}\n }\n-\n static void elink_warpcore_set_limiting_mode(struct elink_params *params,\n \t\t\t\t\t struct elink_phy *phy,\n \t\t\t\t\t uint16_t edc_mode)\n@@ -8052,7 +9604,7 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params,\n \tuint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;\n \tstruct bnx2x_softc *sc = params->sc;\n \n-\tuint8_t lane = elink_get_warpcore_lane(params);\n+\tuint8_t lane = elink_get_warpcore_lane(phy, params);\n \t/* This is a global register which controls all lanes */\n \telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n \t\t\tMDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);\n@@ -8085,7 +9637,8 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params,\n }\n \n static void elink_set_limiting_mode(struct elink_params *params,\n-\t\t\t\t struct elink_phy *phy, uint16_t edc_mode)\n+\t\t\t\t struct elink_phy *phy,\n+\t\t\t\t uint16_t edc_mode)\n {\n \tswitch (phy->type) {\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:\n@@ -8101,30 +9654,28 @@ static void elink_set_limiting_mode(struct elink_params *params,\n \t}\n }\n \n-static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n-\t\t\t\t\t\t struct elink_params *params)\n+elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n+\t\t\t struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t edc_mode;\n \telink_status_t rc = ELINK_STATUS_OK;\n \n \tuint32_t val = REG_RD(sc, params->shmem_base +\n-\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_feature_config[params->\n-\t\t\t\t\t\t\t\t port].\n-\t\t\t\t config));\n+\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t port_feature_config[params->port].config));\n \t/* Enabled transmitter by default */\n \telink_sfp_set_transmitter(params, phy, 1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"SFP+ module plugged in/out detected on port %d\",\n-\t\t params->port);\n+\tELINK_DEBUG_P1(sc, \"SFP+ module plugged in/out detected on port %d\",\n+\t\t params->port);\n \t/* Power up module */\n \telink_power_sfp_module(params, phy, 1);\n \tif (elink_get_edc_mode(phy, params, &edc_mode) != 0) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to get valid module type\");\n+\t\tELINK_DEBUG_P0(sc, \"Failed to get valid module type\");\n \t\treturn ELINK_STATUS_ERROR;\n \t} else if (elink_verify_sfp_module(phy, params) != 0) {\n \t\t/* Check SFP+ module compatibility */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Module verification failed!!\");\n+\t\tELINK_DEBUG_P0(sc, \"Module verification failed!!\");\n \t\trc = ELINK_STATUS_ERROR;\n \t\t/* Turn on fault module-detected led */\n \t\telink_set_sfp_module_fault_led(params,\n@@ -8132,8 +9683,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n \n \t\t/* Check if need to power down the SFP+ module */\n \t\tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n-\t\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Shutdown SFP+ module!!\");\n+\t\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {\n+\t\t\tELINK_DEBUG_P0(sc, \"Shutdown SFP+ module!!\");\n \t\t\telink_power_sfp_module(params, phy, 0);\n \t\t\treturn rc;\n \t\t}\n@@ -8166,22 +9717,22 @@ void elink_handle_module_detect_int(struct elink_params *params)\n \tuint8_t gpio_num, gpio_port;\n \tif (CHIP_IS_E3(sc)) {\n \t\tphy = ¶ms->phy[ELINK_INT_PHY];\n-\t\t/* Always enable TX laser,will be disabled in case of fault */\n+\t\t/* Always enable TX laser, will be disabled in case of fault */\n \t\telink_sfp_set_transmitter(params, phy, 1);\n \t} else {\n \t\tphy = ¶ms->phy[ELINK_EXT_PHY1];\n \t}\n-\tif (elink_get_mod_abs_int_cfg(sc, params->shmem_base,\n+\tif (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,\n \t\t\t\t params->port, &gpio_num, &gpio_port) ==\n \t ELINK_STATUS_ERROR) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to get MOD_ABS interrupt config\");\n+\t\tELINK_DEBUG_P0(sc, \"Failed to get MOD_ABS interrupt config\");\n \t\treturn;\n \t}\n \n \t/* Set valid module led off */\n \telink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);\n \n-\t/* Get current gpio val reflecting module plugged in / out */\n+\t/* Get current gpio val reflecting module plugged in / out*/\n \tgpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);\n \n \t/* Call the handling function in case module is detected */\n@@ -8191,8 +9742,8 @@ void elink_handle_module_detect_int(struct elink_params *params)\n \n \t\telink_power_sfp_module(params, phy, 1);\n \t\telink_cb_gpio_int_write(sc, gpio_num,\n-\t\t\t\t\tMISC_REGISTERS_GPIO_INT_OUTPUT_CLR,\n-\t\t\t\t\tgpio_port);\n+\t\t\t\t MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,\n+\t\t\t\t gpio_port);\n \t\tif (elink_wait_for_sfp_module_initialized(phy, params) == 0) {\n \t\t\telink_sfp_module_detection(phy, params);\n \t\t\tif (CHIP_IS_E3(sc)) {\n@@ -8214,12 +9765,12 @@ void elink_handle_module_detect_int(struct elink_params *params)\n \t\t\t\t}\n \t\t\t}\n \t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"SFP+ module is not initialized\");\n+\t\t\tELINK_DEBUG_P0(sc, \"SFP+ module is not initialized\");\n \t\t}\n \t} else {\n \t\telink_cb_gpio_int_write(sc, gpio_num,\n-\t\t\t\t\tMISC_REGISTERS_GPIO_INT_OUTPUT_SET,\n-\t\t\t\t\tgpio_port);\n+\t\t\t\t MISC_REGISTERS_GPIO_INT_OUTPUT_SET,\n+\t\t\t\t gpio_port);\n \t\t/* Module was plugged out.\n \t\t * Disable transmit for this module\n \t\t */\n@@ -8237,9 +9788,11 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc,\n {\n \tuint16_t alarm_status, val;\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);\n+\t\t\tMDIO_PMA_DEVAD, alarm_status_offset,\n+\t\t\t&alarm_status);\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);\n+\t\t\tMDIO_PMA_DEVAD, alarm_status_offset,\n+\t\t\t&alarm_status);\n \t/* Mask or enable the fault event. */\n \telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);\n \tif (alarm_status & (1 << 0))\n@@ -8248,38 +9801,42 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc,\n \t\tval |= (1 << 0);\n \telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);\n }\n-\n /******************************************************************/\n /*\t\tcommon BNX2X8706/BNX2X8726 PHY SECTION\t\t */\n /******************************************************************/\n static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tuint8_t link_up = 0;\n \tuint16_t val1, val2, rx_sd, pcs_status;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"XGXS 8706/8726\");\n-\t/* Clear RX Alarm */\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);\n+\tELINK_DEBUG_P0(sc, \"XGXS 8706/8726\");\n+\t/* Clear RX Alarm*/\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);\n \n \telink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,\n \t\t\t MDIO_PMA_LASI_TXCTRL);\n \n-\t/* Clear LASI indication */\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"8706/8726 LASI status 0x%x--> 0x%x\", val1, val2);\n+\t/* Clear LASI indication*/\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);\n+\tELINK_DEBUG_P2(sc, \"8706/8726 LASI status 0x%x--> 0x%x\", val1, val2);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);\n-\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);\n-\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps\"\n-\t\t \" link_status 0x%x\", rx_sd, pcs_status, val2);\n+\tELINK_DEBUG_P3(sc, \"8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps\"\n+\t\t\t\" link_status 0x%x\", rx_sd, pcs_status, val2);\n \t/* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status\n \t * are set, or if the autoneg bit 1 is set\n \t */\n@@ -8296,9 +9853,9 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,\n \t/* Capture 10G link fault. Read twice to clear stale value. */\n \tif (vars->line_speed == ELINK_SPEED_10000) {\n \t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n+\t\t\t MDIO_PMA_LASI_TXSTAT, &val1);\n \t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n+\t\t\t MDIO_PMA_LASI_TXSTAT, &val1);\n \t\tif (val1 & (1 << 0))\n \t\t\tvars->fault_detected = 1;\n \t}\n@@ -8310,15 +9867,15 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,\n /*\t\t\tBNX2X8706 PHY SECTION\t\t\t */\n /******************************************************************/\n static uint8_t elink_8706_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t __rte_unused struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t __rte_unused struct elink_vars *vars)\n {\n \tuint32_t tx_en_mode;\n \tuint16_t cnt, val, tmp1;\n \tstruct bnx2x_softc *sc = params->sc;\n \n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n \t/* HW reset */\n \telink_ext_phy_hw_reset(sc, params->port);\n \telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);\n@@ -8332,34 +9889,35 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,\n \t\t\tbreak;\n \t\tDELAY(1000 * 10);\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"XGXS 8706 is initialized after %d ms\", cnt);\n+\tELINK_DEBUG_P1(sc, \"XGXS 8706 is initialized after %d ms\", cnt);\n \tif ((params->feature_config_flags &\n \t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {\n \t\tuint8_t i;\n \t\tuint16_t reg;\n \t\tfor (i = 0; i < 4; i++) {\n \t\t\treg = MDIO_XS_8706_REG_BANK_RX0 +\n-\t\t\t i * (MDIO_XS_8706_REG_BANK_RX1 -\n-\t\t\t\t MDIO_XS_8706_REG_BANK_RX0);\n+\t\t\t\ti * (MDIO_XS_8706_REG_BANK_RX1 -\n+\t\t\t\t MDIO_XS_8706_REG_BANK_RX0);\n \t\t\telink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);\n \t\t\t/* Clear first 3 bits of the control */\n \t\t\tval &= ~0x7;\n \t\t\t/* Set control bits according to configuration */\n \t\t\tval |= (phy->rx_preemphasis[i] & 0x7);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting RX Equalizer to BNX2X8706\"\n-\t\t\t\t \" reg 0x%x <-- val 0x%x\", reg, val);\n+\t\t\tELINK_DEBUG_P2(sc, \"Setting RX Equalizer to BNX2X8706\"\n+\t\t\t\t \" reg 0x%x <-- val 0x%x\", reg, val);\n \t\t\telink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);\n \t\t}\n \t}\n \t/* Force speed */\n \tif (phy->req_line_speed == ELINK_SPEED_10000) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XGXS 8706 force 10Gbps\");\n+\t\tELINK_DEBUG_P0(sc, \"XGXS 8706 force 10Gbps\");\n \n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD,\n \t\t\t\t MDIO_PMA_REG_DIGITAL_CTRL, 0x400);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,\n+\t\t\t\t 0);\n \t\t/* Arm LASI for link and Tx fault. */\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);\n@@ -8367,7 +9925,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,\n \t\t/* Force 1Gbps using autoneg with 1G advertisement */\n \n \t\t/* Allow CL37 through CL73 */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"XGXS 8706 AutoNeg\");\n+\t\tELINK_DEBUG_P0(sc, \"XGXS 8706 AutoNeg\");\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);\n \n@@ -8385,9 +9943,11 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n+\t\t\t\t 0x0400);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,\n+\t\t\t\t 0x0004);\n \t}\n \telink_save_bnx2x_spirom_ver(sc, phy, params->port);\n \n@@ -8397,27 +9957,24 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,\n \n \ttx_en_mode = REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t\t sfp_ctrl))\n-\t& PORT_HW_CFG_TX_LASER_MASK;\n+\t\t\t\tdev_info.port_hw_config[params->port].sfp_ctrl))\n+\t\t\t& PORT_HW_CFG_TX_LASER_MASK;\n \n \tif (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Enabling TXONOFF_PWRDN_DIS\");\n+\t\tELINK_DEBUG_P0(sc, \"Enabling TXONOFF_PWRDN_DIS\");\n \t\telink_cl45_read(sc, phy,\n-\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,\n-\t\t\t\t&tmp1);\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);\n \t\ttmp1 |= 0x1;\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,\n-\t\t\t\t tmp1);\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);\n \t}\n \n \treturn ELINK_STATUS_OK;\n }\n \n-static uint8_t elink_8706_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_8706_read_status(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \treturn elink_8706_8726_read_status(phy, params, vars);\n }\n@@ -8429,7 +9986,7 @@ static void elink_8726_config_loopback(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"PMA/PMD ext_phy_loopback: 8726\");\n+\tELINK_DEBUG_P0(sc, \"PMA/PMD ext_phy_loopback: 8726\");\n \telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);\n }\n \n@@ -8451,7 +10008,8 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy,\n \t\t\t MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);\n \n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_MISC_CTRL1, 0x0001);\n \n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD,\n@@ -8463,15 +10021,16 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy,\n \n \t/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_MISC_CTRL1, 0x0000);\n \n \tDELAY(1000 * 200);\n \telink_save_bnx2x_spirom_ver(sc, phy, params->port);\n }\n \n static uint8_t elink_8726_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val1;\n@@ -8481,7 +10040,7 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,\n \t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,\n \t\t\t\t&val1);\n \t\tif (val1 & (1 << 15)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Tx is disabled\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Tx is disabled\");\n \t\t\tlink_up = 0;\n \t\t\tvars->line_speed = 0;\n \t\t}\n@@ -8489,12 +10048,13 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,\n \treturn link_up;\n }\n \n-static uint8_t elink_8726_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\n+static elink_status_t elink_8726_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Initializing BNX2X8726\");\n+\tELINK_DEBUG_P0(sc, \"Initializing BNX2X8726\");\n \n \telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n \telink_wait_reset_complete(sc, phy, params);\n@@ -8509,7 +10069,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,\n \telink_sfp_module_detection(phy, params);\n \n \tif (phy->req_line_speed == ELINK_SPEED_1000) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 1G force\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 1G force\");\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);\n \t\telink_cl45_write(sc, phy,\n@@ -8517,17 +10077,19 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n+\t\t\t\t 0x400);\n \t} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n \t\t (phy->speed_cap_mask &\n-\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&\n \t\t ((phy->speed_cap_mask &\n-\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=\n \t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 1G clause37\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 1G clause37\");\n \t\t/* Set Flow control */\n \t\telink_ext_phy_set_pause(params, phy, vars);\n-\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);\n+\t\telink_cl45_write(sc, phy,\n+\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);\n \t\telink_cl45_write(sc, phy,\n@@ -8535,16 +10097,17 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n+\t\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n \t\t/* Enable RX-ALARM control to receive interrupt for 1G speed\n \t\t * change\n \t\t */\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n+\t\t\t\t 0x400);\n \n-\t} else {\t\t/* Default 10G. Set only LASI control */\n+\t} else { /* Default 10G. Set only LASI control */\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);\n \t}\n@@ -8552,9 +10115,10 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,\n \t/* Set TX PreEmphasis if needed */\n \tif ((params->feature_config_flags &\n \t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\",\n-\t\t\t phy->tx_preemphasis[0], phy->tx_preemphasis[1]);\n+\t\tELINK_DEBUG_P2(sc,\n+\t\t \"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\",\n+\t\t\t phy->tx_preemphasis[0],\n+\t\t\t phy->tx_preemphasis[1]);\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD,\n \t\t\t\t MDIO_PMA_REG_8726_TX_CTRL1,\n@@ -8574,10 +10138,11 @@ static void elink_8726_link_reset(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"elink_8726_link_reset port %d\", params->port);\n+\tELINK_DEBUG_P1(sc, \"elink_8726_link_reset port %d\", params->port);\n \t/* Set serial boot control for external load */\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_GEN_CTRL, 0x0001);\n }\n \n /******************************************************************/\n@@ -8610,22 +10175,28 @@ static void elink_8727_set_link_led(struct elink_phy *phy,\n \t\tbreak;\n \t}\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_8727_PCS_OPT_CTRL,\n+\t\t\t&val);\n \tval &= 0xff8f;\n \tval |= led_mode_bitmask;\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_8727_PCS_OPT_CTRL,\n+\t\t\t val);\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_8727_GPIO_CTRL,\n+\t\t\t&val);\n \tval &= 0xffe0;\n \tval |= gpio_pins_bitmask;\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_8727_GPIO_CTRL,\n+\t\t\t val);\n }\n-\n static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,\n-\t\t\t\tstruct elink_params *params)\n-{\n+\t\t\t\tstruct elink_params *params) {\n \tuint32_t swap_val, swap_override;\n \tuint8_t port;\n \t/* The PHY reset is controlled by GPIO 1. Fake the port number\n@@ -8636,7 +10207,7 @@ static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,\n \tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n \tport = (swap_val && swap_override) ^ 1;\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n }\n \n static void elink_8727_config_speed(struct elink_phy *phy,\n@@ -8647,14 +10218,14 @@ static void elink_8727_config_speed(struct elink_phy *phy,\n \t/* Set option 1G speed */\n \tif ((phy->req_line_speed == ELINK_SPEED_1000) ||\n \t (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 1G force\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 1G force\");\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"1.7 = 0x%x\", tmp1);\n+\t\tELINK_DEBUG_P1(sc, \"1.7 = 0x%x\", tmp1);\n \t\t/* Power down the XAUI until link is up in case of dual-media\n \t\t * and 1G\n \t\t */\n@@ -8671,10 +10242,10 @@ static void elink_8727_config_speed(struct elink_phy *phy,\n \t\t ((phy->speed_cap_mask &\n \t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&\n \t\t ((phy->speed_cap_mask &\n-\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=\n-\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 1G clause37\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 1G clause37\");\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);\n \t\telink_cl45_write(sc, phy,\n@@ -8696,10 +10267,9 @@ static void elink_8727_config_speed(struct elink_phy *phy,\n \t}\n }\n \n-static uint8_t elink_8727_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t __rte_unused struct elink_vars\n-\t\t\t\t\t *vars)\n+static elink_status_t elink_8727_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t __rte_unused struct elink_vars *vars)\n {\n \tuint32_t tx_en_mode;\n \tuint16_t tmp1, mod_abs, tmp2;\n@@ -8708,7 +10278,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,\n \n \telink_wait_reset_complete(sc, phy, params);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Initializing BNX2X8727\");\n+\tELINK_DEBUG_P0(sc, \"Initializing BNX2X8727\");\n \n \telink_8727_specific_func(phy, params, ELINK_PHY_INIT);\n \t/* Initially configure MOD_ABS to interrupt when module is\n@@ -8734,15 +10304,18 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);\n \n \telink_8727_config_speed(phy, params);\n \n+\n \t/* Set TX PreEmphasis if needed */\n \tif ((params->feature_config_flags &\n \t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\",\n-\t\t\t phy->tx_preemphasis[0], phy->tx_preemphasis[1]);\n+\t\tELINK_DEBUG_P2(sc, \"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\",\n+\t\t\t phy->tx_preemphasis[0],\n+\t\t\t phy->tx_preemphasis[1]);\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,\n \t\t\t\t phy->tx_preemphasis[0]);\n@@ -8757,25 +10330,24 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,\n \t */\n \ttx_en_mode = REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t\t sfp_ctrl))\n-\t& PORT_HW_CFG_TX_LASER_MASK;\n+\t\t\t\tdev_info.port_hw_config[params->port].sfp_ctrl))\n+\t\t\t& PORT_HW_CFG_TX_LASER_MASK;\n \n \tif (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Enabling TXONOFF_PWRDN_DIS\");\n+\t\tELINK_DEBUG_P0(sc, \"Enabling TXONOFF_PWRDN_DIS\");\n \t\telink_cl45_read(sc, phy,\n-\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,\n-\t\t\t\t&tmp2);\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);\n \t\ttmp2 |= 0x1000;\n \t\ttmp2 &= 0xFFEF;\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,\n-\t\t\t\t tmp2);\n-\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);\n-\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);\n+\t\telink_cl45_read(sc, phy,\n+\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,\n+\t\t\t\t&tmp2);\n+\t\telink_cl45_write(sc, phy,\n+\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,\n+\t\t\t\t (tmp2 & 0x7fff));\n \t}\n \n \treturn ELINK_STATUS_OK;\n@@ -8787,15 +10359,17 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t mod_abs, rx_alarm_status;\n \tuint32_t val = REG_RD(sc, params->shmem_base +\n-\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_feature_config[params->\n-\t\t\t\t\t\t\t\t port].config));\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,\n-\t\t\t&mod_abs);\n+\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\t port_feature_config[params->port].\n+\t\t\t\t config));\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);\n \tif (mod_abs & (1 << 8)) {\n \n \t\t/* Module is absent */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"MOD_ABS indication show module is absent\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"MOD_ABS indication show module is absent\");\n \t\tphy->media_type = ELINK_ETH_PHY_NOT_PRESENT;\n \t\t/* 1. Set mod_abs to detect next module\n \t\t * presence event\n@@ -8820,7 +10394,8 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,\n \n \t} else {\n \t\t/* Module is present */\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"MOD_ABS indication show module is present\");\n+\t\tELINK_DEBUG_P0(sc,\n+\t\t \"MOD_ABS indication show module is present\");\n \t\t/* First disable transmitter, and if the module is ok, the\n \t\t * module_detection will enable it\n \t\t * 1. Set mod_abs to detect next module absent event ( bit 8)\n@@ -8844,51 +10419,56 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,\n \t\t\t\tMDIO_PMA_DEVAD,\n \t\t\t\tMDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n \n+\n \t\tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n \t\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)\n \t\t\telink_sfp_set_transmitter(params, phy, 0);\n \n-\t\tif (elink_wait_for_sfp_module_initialized(phy, params) == 0) {\n+\t\tif (elink_wait_for_sfp_module_initialized(phy, params) == 0)\n \t\t\telink_sfp_module_detection(phy, params);\n-\t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"SFP+ module is not initialized\");\n-\t\t}\n+\t\telse\n+\t\t\tELINK_DEBUG_P0(sc, \"SFP+ module is not initialized\");\n \n \t\t/* Reconfigure link speed based on module type limitations */\n \t\telink_8727_config_speed(phy, params);\n \t}\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"8727 RX_ALARM_STATUS 0x%x\", rx_alarm_status);\n+\tELINK_DEBUG_P1(sc, \"8727 RX_ALARM_STATUS 0x%x\",\n+\t\t rx_alarm_status);\n \t/* No need to check link status in case of module plugged in/out */\n }\n \n static uint8_t elink_8727_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n+\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tuint8_t link_up = 0, oc_port = params->port;\n+\tuint8_t link_up = 0;\n \tuint16_t link_status = 0;\n \tuint16_t rx_alarm_status, lasi_ctrl, val1;\n \n \t/* If PHY is not initialized, do not check link status */\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,\n+\t\t\t&lasi_ctrl);\n \tif (!lasi_ctrl)\n \t\treturn 0;\n \n \t/* Check the LASI on Rx */\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,\n+\t\t\t&rx_alarm_status);\n \tvars->line_speed = 0;\n-\tPMD_DRV_LOG(DEBUG, sc, \"8727 RX_ALARM_STATUS 0x%x\", rx_alarm_status);\n+\tELINK_DEBUG_P1(sc, \"8727 RX_ALARM_STATUS 0x%x\", rx_alarm_status);\n \n \telink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,\n \t\t\t MDIO_PMA_LASI_TXCTRL);\n \n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"8727 LASI status 0x%x\", val1);\n+\tELINK_DEBUG_P1(sc, \"8727 LASI status 0x%x\", val1);\n \n \t/* Clear MSG-OUT */\n \telink_cl45_read(sc, phy,\n@@ -8898,24 +10478,28 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,\n \t * for over current\n \t */\n \tif (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {\n-\t\t/* Check over-current using 8727 GPIO0 input */\n+\t\t/* Check over-current using 8727 GPIO0 input*/\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,\n \t\t\t\t&val1);\n \n \t\tif ((val1 & (1 << 8)) == 0) {\n+\t\t\tuint8_t oc_port = params->port;\n \t\t\tif (!CHIP_IS_E1x(sc))\n \t\t\t\toc_port = SC_PATH(sc) + (params->port << 1);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"8727 Power fault has been detected on port %d\",\n-\t\t\t\t oc_port);\n-\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port);\t//\"Error: Power fault on Port %d has \"\n-\t\t\t// \"been detected and the power to \"\n-\t\t\t// \"that SFP+ module has been removed \"\n-\t\t\t// \"to prevent failure of the card. \"\n-\t\t\t// \"Please remove the SFP+ module and \"\n-\t\t\t// \"restart the system to clear this \"\n-\t\t\t// \"error.\",\n+\t\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"8727 Power fault has been detected on port %d\",\n+\t\t\t oc_port);\n+\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT,\n+\t\t\t\t\t oc_port);\n+\t\t\t\t\t/* \"Error: Power fault on Port %d has \"\n+\t\t\t\t\t * \"been detected and the power to \"\n+\t\t\t\t\t * \"that SFP+ module has been removed \"\n+\t\t\t\t\t * \"to prevent failure of the card. \"\n+\t\t\t\t\t * \"Please remove the SFP+ module and \"\n+\t\t\t\t\t * \"restart the system to clear this \"\n+\t\t\t\t\t * \"error.\",\n+\t\t\t\t\t */\n \t\t\t/* Disable all RX_ALARMs except for mod_abs */\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n@@ -8931,14 +10515,13 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,\n \t\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, val1);\n \t\t\t/* Clear RX alarm */\n \t\t\telink_cl45_read(sc, phy,\n-\t\t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\t\tMDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n+\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\tMDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n \t\t\telink_8727_power_module(params->sc, phy, 0);\n \t\t\treturn 0;\n \t\t}\n-\t}\n+\t} /* Over current check */\n \n-\t/* Over current check */\n \t/* When module absent bit is set, check module */\n \tif (rx_alarm_status & (1 << 5)) {\n \t\telink_8727_handle_mod_abs(phy, params);\n@@ -8949,10 +10532,10 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,\n \t}\n \n \tif (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Enabling 8727 TX laser\");\n+\t\tELINK_DEBUG_P0(sc, \"Enabling 8727 TX laser\");\n \t\telink_sfp_set_transmitter(params, phy, 1);\n \t} else {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Tx is disabled\");\n+\t\tELINK_DEBUG_P0(sc, \"Tx is disabled\");\n \t\treturn 0;\n \t}\n \n@@ -8966,26 +10549,26 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,\n \tif ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {\n \t\tlink_up = 1;\n \t\tvars->line_speed = ELINK_SPEED_10000;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link up in 10G\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link up in 10G\",\n+\t\t\t params->port);\n \t} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {\n \t\tlink_up = 1;\n \t\tvars->line_speed = ELINK_SPEED_1000;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link up in 1G\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link up in 1G\",\n+\t\t\t params->port);\n \t} else {\n \t\tlink_up = 0;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"port %x: External link is down\",\n-\t\t\t params->port);\n+\t\tELINK_DEBUG_P1(sc, \"port %x: External link is down\",\n+\t\t\t params->port);\n \t}\n \n \t/* Capture 10G link fault. */\n \tif (vars->line_speed == ELINK_SPEED_10000) {\n \t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n+\t\t\t MDIO_PMA_LASI_TXSTAT, &val1);\n \n \t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n-\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n+\t\t\t MDIO_PMA_LASI_TXSTAT, &val1);\n \n \t\tif (val1 & (1 << 0)) {\n \t\t\tvars->fault_detected = 1;\n@@ -8995,7 +10578,7 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,\n \tif (link_up) {\n \t\telink_ext_phy_resolve_fc(phy, params, vars);\n \t\tvars->duplex = DUPLEX_FULL;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"duplex = 0x%x\", vars->duplex);\n+\t\tELINK_DEBUG_P1(sc, \"duplex = 0x%x\", vars->duplex);\n \t}\n \n \tif ((ELINK_DUAL_MEDIA(params)) &&\n@@ -9035,8 +10618,16 @@ static void elink_8727_link_reset(struct elink_phy *phy,\n /******************************************************************/\n /*\t\tBNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION\t */\n /******************************************************************/\n+static int elink_is_8483x_8485x(struct elink_phy *phy)\n+{\n+\treturn ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n+\t\t(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) ||\n+\t\t(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858));\n+}\n+\n static void elink_save_848xx_spirom_version(struct elink_phy *phy,\n-\t\t\t\t\t struct bnx2x_softc *sc, uint8_t port)\n+\t\t\t\t\t struct bnx2x_softc *sc,\n+\t\t\t\t\t uint8_t port)\n {\n \tuint16_t val, fw_ver2, cnt, i;\n \tstatic struct elink_reg_set reg_set[] = {\n@@ -9048,11 +10639,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,\n \t};\n \tuint16_t fw_ver1;\n \n-\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n-\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n+\tif (elink_is_8483x_8485x(phy)) {\n \t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);\n \t\telink_save_spirom_version(sc, port, fw_ver1 & 0xfff,\n-\t\t\t\t\t phy->ver_addr);\n+\t\t\t\tphy->ver_addr);\n \t} else {\n \t\t/* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */\n \t\t/* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */\n@@ -9067,12 +10657,14 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,\n \t\t\tDELAY(5);\n \t\t}\n \t\tif (cnt == 100) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Unable to read 848xx \"\n-\t\t\t\t \"phy fw version(1)\");\n-\t\t\telink_save_spirom_version(sc, port, 0, phy->ver_addr);\n+\t\t\tELINK_DEBUG_P0(sc, \"Unable to read 848xx \"\n+\t\t\t\t\t\"phy fw version(1)\");\n+\t\t\telink_save_spirom_version(sc, port, 0,\n+\t\t\t\t\t\t phy->ver_addr);\n \t\t\treturn;\n \t\t}\n \n+\n \t\t/* 2) read register 0xc200_0000 (SPI_FW_STATUS) */\n \t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);\n \t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);\n@@ -9084,9 +10676,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,\n \t\t\tDELAY(5);\n \t\t}\n \t\tif (cnt == 100) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Unable to read 848xx phy fw \"\n-\t\t\t\t \"version(2)\");\n-\t\t\telink_save_spirom_version(sc, port, 0, phy->ver_addr);\n+\t\t\tELINK_DEBUG_P0(sc, \"Unable to read 848xx phy fw \"\n+\t\t\t\t\t\"version(2)\");\n+\t\t\telink_save_spirom_version(sc, port, 0,\n+\t\t\t\t\t\t phy->ver_addr);\n \t\t\treturn;\n \t\t}\n \n@@ -9100,8 +10693,8 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,\n \t}\n \n }\n-\n-static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)\n+static void elink_848xx_set_led(struct bnx2x_softc *sc,\n+\t\t\t\tstruct elink_phy *phy)\n {\n \tuint16_t val, offset, i;\n \tstatic struct elink_reg_set reg_set[] = {\n@@ -9110,29 +10703,30 @@ static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)\n \t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},\n \t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},\n \t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,\n-\t\t MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},\n+\t\t\tMDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},\n \t\t{MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}\n \t};\n \t/* PHYC_CTL_LED_CTL */\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n \tval &= 0xFE00;\n \tval |= 0x0092;\n \n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n \n \tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n \t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n \t\t\t\t reg_set[i].val);\n \n-\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n-\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))\n+\tif (elink_is_8483x_8485x(phy))\n \t\toffset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;\n \telse\n \t\toffset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;\n \n-\t/* stretch_en for LED3 */\n+\t/* stretch_en for LED3*/\n \telink_cl45_read_or_write(sc, phy,\n \t\t\t\t MDIO_PMA_DEVAD, offset,\n \t\t\t\t MDIO_PMA_REG_84823_LED3_STRETCH_EN);\n@@ -9145,8 +10739,7 @@ static void elink_848xx_specific_func(struct elink_phy *phy,\n \tstruct bnx2x_softc *sc = params->sc;\n \tswitch (action) {\n \tcase ELINK_PHY_INIT:\n-\t\tif ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&\n-\t\t (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n+\t\tif (!elink_is_8483x_8485x(phy)) {\n \t\t\t/* Save spirom version */\n \t\t\telink_save_848xx_spirom_version(phy, sc, params->port);\n \t\t}\n@@ -9163,14 +10756,15 @@ static void elink_848xx_specific_func(struct elink_phy *phy,\n }\n \n static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n-\t\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t autoneg_val, an_1000_val, an_10_100_val;\n \n \telink_848xx_specific_func(phy, params, ELINK_PHY_INIT);\n-\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);\n+\telink_cl45_write(sc, phy,\n+\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);\n \n \t/* set 1000 speed advertisement */\n \telink_cl45_read(sc, phy,\n@@ -9180,24 +10774,25 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \telink_ext_phy_set_pause(params, phy, vars);\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_AN_DEVAD,\n-\t\t\tMDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);\n+\t\t\tMDIO_AN_REG_8481_LEGACY_AN_ADV,\n+\t\t\t&an_10_100_val);\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,\n \t\t\t&autoneg_val);\n \t/* Disable forced speed */\n-\tautoneg_val &=\n-\t ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));\n+\tautoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) |\n+\t\t\t (1 << 13));\n \tan_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));\n \n \tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n \t (phy->speed_cap_mask &\n-\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n+\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n \t (phy->req_line_speed == ELINK_SPEED_1000)) {\n \t\tan_1000_val |= (1 << 8);\n \t\tautoneg_val |= (1 << 9 | 1 << 12);\n \t\tif (phy->req_duplex == DUPLEX_FULL)\n \t\t\tan_1000_val |= (1 << 9);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 1G\");\n+\t\tELINK_DEBUG_P0(sc, \"Advertising 1G\");\n \t} else\n \t\tan_1000_val &= ~((1 << 8) | (1 << 9));\n \n@@ -9213,7 +10808,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \t\t\t */\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n \t\t\tan_10_100_val |= (1 << 8);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 100M-FD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 100M-FD\");\n \t\t}\n \n \t\tif (phy->speed_cap_mask &\n@@ -9222,7 +10817,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \t\t\t */\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n \t\t\tan_10_100_val |= (1 << 7);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 100M-HD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 100M-HD\");\n \t\t}\n \n \t\tif ((phy->speed_cap_mask &\n@@ -9230,7 +10825,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \t\t (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {\n \t\t\tan_10_100_val |= (1 << 6);\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 10M-FD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 10M-FD\");\n \t\t}\n \n \t\tif ((phy->speed_cap_mask &\n@@ -9238,14 +10833,15 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \t\t (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {\n \t\t\tan_10_100_val |= (1 << 5);\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 10M-HD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 10M-HD\");\n \t\t}\n \t}\n \n \t/* Only 10/100 are allowed to work in FORCE mode */\n \tif ((phy->req_line_speed == ELINK_SPEED_100) &&\n \t (phy->supported &\n-\t (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {\n+\t (ELINK_SUPPORTED_100baseT_Half |\n+\t ELINK_SUPPORTED_100baseT_Full))) {\n \t\tautoneg_val |= (1 << 13);\n \t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n \t\telink_cl45_write(sc, phy,\n@@ -9253,16 +10849,17 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \t\t\t\t (1 << 15 | 1 << 9 | 7 << 0));\n \t\t/* The PHY needs this set even for forced link. */\n \t\tan_10_100_val |= (1 << 8) | (1 << 7);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 100M force\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 100M force\");\n \t}\n \tif ((phy->req_line_speed == ELINK_SPEED_10) &&\n \t (phy->supported &\n-\t (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {\n+\t (ELINK_SUPPORTED_10baseT_Half |\n+\t ELINK_SUPPORTED_10baseT_Full))) {\n \t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,\n \t\t\t\t (1 << 15 | 1 << 9 | 7 << 0));\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 10M force\");\n+\t\tELINK_DEBUG_P0(sc, \"Setting 10M force\");\n \t}\n \n \telink_cl45_write(sc, phy,\n@@ -9275,42 +10872,44 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n \t/* Always write this if this is not 84833/4.\n \t * For 84833/4, write it only when it's a forced speed.\n \t */\n-\tif (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&\n-\t (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||\n+\tif (!elink_is_8483x_8485x(phy) ||\n \t ((autoneg_val & (1 << 12)) == 0))\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_AN_DEVAD,\n-\t\t\t\t MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);\n+\t\t\t MDIO_AN_DEVAD,\n+\t\t\t MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);\n \n \tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n \t (phy->speed_cap_mask &\n \t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||\n \t (phy->req_line_speed == ELINK_SPEED_10000)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 10G\");\n-\t\t/* Restart autoneg for 10G */\n+\t\tELINK_DEBUG_P0(sc, \"Advertising 10G\");\n+\t\t/* Restart autoneg for 10G*/\n \n-\t\telink_cl45_read_or_write(sc, phy,\n-\t\t\t\t\t MDIO_AN_DEVAD,\n-\t\t\t\t\t MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,\n-\t\t\t\t\t 0x1000);\n+\t\telink_cl45_read_or_write(\n+\t\t\tsc, phy,\n+\t\t\tMDIO_AN_DEVAD,\n+\t\t\tMDIO_AN_REG_8481_10GBASE_T_AN_CTRL,\n+\t\t\t0x1000);\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);\n+\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,\n+\t\t\t\t 0x3200);\n \t} else\n \t\telink_cl45_write(sc, phy,\n \t\t\t\t MDIO_AN_DEVAD,\n-\t\t\t\t MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);\n+\t\t\t\t MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,\n+\t\t\t\t 1);\n \n \treturn ELINK_STATUS_OK;\n }\n \n-static uint8_t elink_8481_config_init(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_8481_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\t/* Restore normal power mode */\n+\t/* Restore normal power mode*/\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n \n \t/* HW reset */\n \telink_ext_phy_hw_reset(sc, params->port);\n@@ -9320,101 +10919,219 @@ static uint8_t elink_8481_config_init(struct elink_phy *phy,\n \treturn elink_848xx_cmn_config_init(phy, params, vars);\n }\n \n-#define PHY84833_CMDHDLR_WAIT 300\n-#define PHY84833_CMDHDLR_MAX_ARGS 5\n-static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,\n+#define PHY848xx_CMDHDLR_WAIT 300\n+#define PHY848xx_CMDHDLR_MAX_ARGS 5\n+\n+static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,\n \t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t uint16_t fw_cmd, uint16_t cmd_args[],\n-\t\t\t\t\t int argc)\n+\t\t\t\t\t uint16_t fw_cmd,\n+\t\t\t\t\t uint16_t cmd_args[], int argc)\n+{\n+\tint idx;\n+\tuint16_t val;\n+\tstruct bnx2x_softc *sc = params->sc;\n+\n+\t/* Step 1: Poll the STATUS register to see whether the previous command\n+\t * is in progress or the system is busy (CMD_IN_PROGRESS or\n+\t * SYSTEM_BUSY). If previous command is in progress or system is busy,\n+\t * check again until the previous command finishes execution and the\n+\t * system is available for taking command\n+\t */\n+\n+\tfor (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {\n+\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n+\t\t\t\tMDIO_848xx_CMD_HDLR_STATUS, &val);\n+\t\tif ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&\n+\t\t (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))\n+\t\t\tbreak;\n+\t\tDELAY(1000 * 1);\n+\t}\n+\tif (idx >= PHY848xx_CMDHDLR_WAIT) {\n+\t\tELINK_DEBUG_P0(sc, \"FW cmd: FW not ready.\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\n+\t/* Step2: If any parameters are required for the function, write them\n+\t * to the required DATA registers\n+\t */\n+\n+\tfor (idx = 0; idx < argc; idx++) {\n+\t\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n+\t\t\t\t MDIO_848xx_CMD_HDLR_DATA1 + idx,\n+\t\t\t\t cmd_args[idx]);\n+\t}\n+\n+\t/* Step3: When the firmware is ready for commands, write the 'Command\n+\t * code' to the CMD register\n+\t */\n+\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n+\t\t\t MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);\n+\n+\t/* Step4: Once the command has been written, poll the STATUS register\n+\t * to check whether the command has completed (CMD_COMPLETED_PASS/\n+\t * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).\n+\t */\n+\n+\tfor (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {\n+\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n+\t\t\t\tMDIO_848xx_CMD_HDLR_STATUS, &val);\n+\t\tif ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||\n+\t\t (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))\n+\t\t\tbreak;\n+\t\tDELAY(1000 * 1);\n+\t}\n+\tif ((idx >= PHY848xx_CMDHDLR_WAIT) ||\n+\t (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {\n+\t\tELINK_DEBUG_P0(sc, \"FW cmd failed.\");\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\t/* Step5: Once the command has completed, read the specficied DATA\n+\t * registers for any saved results for the command, if applicable\n+\t */\n+\n+\t/* Gather returning data */\n+\tfor (idx = 0; idx < argc; idx++) {\n+\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n+\t\t\t\tMDIO_848xx_CMD_HDLR_DATA1 + idx,\n+\t\t\t\t&cmd_args[idx]);\n+\t}\n+\n+\treturn ELINK_STATUS_OK;\n+}\n+\n+static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,\n+\t\t\t\tstruct elink_params *params, uint16_t fw_cmd,\n+\t\t\t\tuint16_t cmd_args[], int argc, int process)\n {\n \tint idx;\n \tuint16_t val;\n \tstruct bnx2x_softc *sc = params->sc;\n+\telink_status_t rc = ELINK_STATUS_OK;\n+\n+\tif (process == PHY84833_MB_PROCESS2) {\n \t/* Write CMD_OPEN_OVERRIDE to STATUS reg */\n \telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t MDIO_84833_CMD_HDLR_STATUS,\n-\t\t\t PHY84833_STATUS_CMD_OPEN_OVERRIDE);\n-\tfor (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {\n+\t\t\t\t MDIO_848xx_CMD_HDLR_STATUS,\n+\t\t\tPHY84833_STATUS_CMD_OPEN_OVERRIDE);\n+\t}\n+\n+\tfor (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {\n \t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t\tMDIO_84833_CMD_HDLR_STATUS, &val);\n+\t\t\t MDIO_848xx_CMD_HDLR_STATUS, &val);\n \t\tif (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)\n \t\t\tbreak;\n \t\tDELAY(1000 * 1);\n \t}\n-\tif (idx >= PHY84833_CMDHDLR_WAIT) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"FW cmd: FW not ready.\");\n+\tif (idx >= PHY848xx_CMDHDLR_WAIT) {\n+\t\tELINK_DEBUG_P0(sc, \"FW cmd: FW not ready.\");\n+\t\t/* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR\n+\t\t * clear the status to CMD_CLEAR_COMPLETE\n+\t\t */\n+\t\tif (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||\n+\t\t val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {\n+\t\t\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n+\t\t\t\t\t MDIO_848xx_CMD_HDLR_STATUS,\n+\t\t\t\t\t PHY84833_STATUS_CMD_CLEAR_COMPLETE);\n+\t\t}\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n-\n-\t/* Prepare argument(s) and issue command */\n+\tif (process == PHY84833_MB_PROCESS1 ||\n+\t process == PHY84833_MB_PROCESS2) {\n+\t\t/* Prepare argument(s) */\n \tfor (idx = 0; idx < argc; idx++) {\n \t\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t\t MDIO_84833_CMD_HDLR_DATA1 + idx,\n-\t\t\t\t cmd_args[idx]);\n+\t\t\t\t\t MDIO_848xx_CMD_HDLR_DATA1 + idx,\n+\t\t\t\tcmd_args[idx]);\n \t}\n+\t}\n+\n+\t/* Issue command */\n \telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);\n-\tfor (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {\n+\t\t\tMDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);\n+\tfor (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {\n \t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t\tMDIO_84833_CMD_HDLR_STATUS, &val);\n+\t\t\t MDIO_848xx_CMD_HDLR_STATUS, &val);\n \t\tif ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||\n-\t\t (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))\n+\t\t\t(val == PHY84833_STATUS_CMD_COMPLETE_ERROR))\n \t\t\tbreak;\n \t\tDELAY(1000 * 1);\n \t}\n-\tif ((idx >= PHY84833_CMDHDLR_WAIT) ||\n-\t (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"FW cmd failed.\");\n-\t\treturn ELINK_STATUS_ERROR;\n+\tif ((idx >= PHY848xx_CMDHDLR_WAIT) ||\n+\t\t(val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {\n+\t\tELINK_DEBUG_P0(sc, \"FW cmd failed.\");\n+\t\trc = ELINK_STATUS_ERROR;\n \t}\n+\tif (process == PHY84833_MB_PROCESS3 && rc == ELINK_STATUS_OK) {\n \t/* Gather returning data */\n \tfor (idx = 0; idx < argc; idx++) {\n \t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t\tMDIO_84833_CMD_HDLR_DATA1 + idx,\n+\t\t\t\t\tMDIO_848xx_CMD_HDLR_DATA1 + idx,\n \t\t\t\t&cmd_args[idx]);\n \t}\n+\t}\n+\tif (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||\n+\t val == PHY84833_STATUS_CMD_COMPLETE_PASS) {\n \telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n-\t\t\t MDIO_84833_CMD_HDLR_STATUS,\n-\t\t\t PHY84833_STATUS_CMD_CLEAR_COMPLETE);\n-\treturn ELINK_STATUS_OK;\n+\t\t\t\t MDIO_848xx_CMD_HDLR_STATUS,\n+\t\t\tPHY84833_STATUS_CMD_CLEAR_COMPLETE);\n+\t}\n+\treturn rc;\n }\n \n-static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,\n-\t\t\t\t\t\tstruct elink_params *params,\n-\t\t\t\t\t\t__rte_unused struct elink_vars\n-\t\t\t\t\t\t*vars)\n+static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,\n+\t\t\t\t\t struct elink_params *params,\n+\t\t\t\t\t uint16_t fw_cmd,\n+\t\t\t\t\t uint16_t cmd_args[], int argc,\n+\t\t\t\t\t int process)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\n+\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) ||\n+\t (REG_RD(sc, params->shmem2_base +\n+\t\t offsetof(struct shmem2_region,\n+\t\t\t link_attr_sync[params->port])) &\n+\t\t\t LINK_ATTR_84858)) {\n+\t\treturn elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,\n+\t\t\t\t\t argc);\n+\t} else {\n+\t\treturn elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,\n+\t\t\t\t\t argc, process);\n+\t}\n+}\n+\n+static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t __rte_unused struct elink_vars *vars)\n {\n \tuint32_t pair_swap;\n-\tuint16_t data[PHY84833_CMDHDLR_MAX_ARGS];\n+\tuint16_t data[PHY848xx_CMDHDLR_MAX_ARGS];\n \telink_status_t status;\n \tstruct bnx2x_softc *sc = params->sc;\n \n \t/* Check for configuration. */\n \tpair_swap = REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t\t xgbt_phy_cfg)) &\n-\t PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;\n+\t\t\tdev_info.port_hw_config[params->port].xgbt_phy_cfg)) &\n+\t\tPORT_HW_CFG_RJ45_PAIR_SWAP_MASK;\n \n \tif (pair_swap == 0)\n \t\treturn ELINK_STATUS_OK;\n \n \t/* Only the second argument is used for this command */\n-\tdata[1] = (uint16_t) pair_swap;\n+\tdata[1] = (uint16_t)pair_swap;\n \n-\tstatus = elink_84833_cmd_hdlr(phy, params,\n-\t\t\t\t PHY84833_CMD_SET_PAIR_SWAP, data,\n-\t\t\t\t PHY84833_CMDHDLR_MAX_ARGS);\n-\tif (status == ELINK_STATUS_OK) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Pairswap OK, val=0x%x\", data[1]);\n-\t}\n+\tstatus = elink_848xx_cmd_hdlr(phy, params,\n+\t\t\t\t PHY848xx_CMD_SET_PAIR_SWAP, data,\n+\t\t\t\t 2, PHY84833_MB_PROCESS2);\n+\tif (status == ELINK_STATUS_OK)\n+\t\tELINK_DEBUG_P1(sc, \"Pairswap OK, val=0x%x\", data[1]);\n \n \treturn status;\n }\n \n static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,\n-\t\t\t\t\t uint32_t shmem_base_path[],\n-\t\t\t\t\t __rte_unused uint32_t chip_id)\n+\t\t\t\t uint32_t shmem_base_path[],\n+\t\t\t\t __rte_unused uint32_t chip_id)\n {\n \tuint32_t reset_pin[2];\n \tuint32_t idx;\n@@ -9424,54 +11141,50 @@ static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,\n \t\tfor (idx = 0; idx < 2; idx++) {\n \t\t\t/* Map config param to register bit. */\n \t\t\treset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +\n-\t\t\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t\t\t dev_info.\n-\t\t\t\t\t\t\t port_hw_config[0].\n-\t\t\t\t\t\t\t e3_cmn_pin_cfg));\n-\t\t\treset_pin[idx] =\n-\t\t\t (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>\n-\t\t\t PORT_HW_CFG_E3_PHY_RESET_SHIFT;\n+\t\t\t\toffsetof(struct shmem_region,\n+\t\t\t\tdev_info.port_hw_config[0].e3_cmn_pin_cfg));\n+\t\t\treset_pin[idx] = (reset_pin[idx] &\n+\t\t\t\tPORT_HW_CFG_E3_PHY_RESET_MASK) >>\n+\t\t\t\tPORT_HW_CFG_E3_PHY_RESET_SHIFT;\n \t\t\treset_pin[idx] -= PIN_CFG_GPIO0_P0;\n \t\t\treset_pin[idx] = (1 << reset_pin[idx]);\n \t\t}\n-\t\treset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);\n+\t\treset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);\n \t} else {\n \t\t/* E2, look from diff place of shmem. */\n \t\tfor (idx = 0; idx < 2; idx++) {\n \t\t\treset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +\n-\t\t\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t\t\t dev_info.\n-\t\t\t\t\t\t\t port_hw_config[0].\n-\t\t\t\t\t\t\t default_cfg));\n+\t\t\t\toffsetof(struct shmem_region,\n+\t\t\t\tdev_info.port_hw_config[0].default_cfg));\n \t\t\treset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;\n \t\t\treset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;\n \t\t\treset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;\n \t\t\treset_pin[idx] = (1 << reset_pin[idx]);\n \t\t}\n-\t\treset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);\n+\t\treset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);\n \t}\n \n \treturn reset_gpios;\n }\n \n-static void elink_84833_hw_reset_phy(struct elink_phy *phy,\n-\t\t\t\t\tstruct elink_params *params)\n+static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,\n+\t\t\t\tstruct elink_params *params)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t reset_gpios;\n \tuint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +\n-\t\t\t\t\t\toffsetof(struct shmem2_region,\n-\t\t\t\t\t\t\t other_shmem_base_addr));\n+\t\t\t\toffsetof(struct shmem2_region,\n+\t\t\t\tother_shmem_base_addr));\n \n \tuint32_t shmem_base_path[2];\n \n \t/* Work around for 84833 LED failure inside RESET status */\n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n-\t\t\t MDIO_AN_REG_8481_LEGACY_MII_CTRL,\n-\t\t\t MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);\n+\t\tMDIO_AN_REG_8481_LEGACY_MII_CTRL,\n+\t\tMDIO_AN_REG_8481_MII_CTRL_FORCE_1G);\n \telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n-\t\t\t MDIO_AN_REG_8481_1G_100T_EXT_CTRL,\n-\t\t\t MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);\n+\t\tMDIO_AN_REG_8481_1G_100T_EXT_CTRL,\n+\t\tMIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);\n \n \tshmem_base_path[0] = params->shmem_base;\n \tshmem_base_path[1] = other_shmem_base_addr;\n@@ -9482,24 +11195,27 @@ static void elink_84833_hw_reset_phy(struct elink_phy *phy,\n \telink_cb_gpio_mult_write(sc, reset_gpios,\n \t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW);\n \tDELAY(10);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"84833 hw reset on pin values 0x%x\", reset_gpios);\n+\tELINK_DEBUG_P1(sc, \"84833 hw reset on pin values 0x%x\",\n+\t\treset_gpios);\n+\n+\treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \telink_status_t rc;\n+\tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t cmd_args = 0;\n \n-\tPMD_DRV_LOG(DEBUG, params->sc, \"Don't Advertise 10GBase-T EEE\");\n+\tELINK_DEBUG_P0(sc, \"Don't Advertise 10GBase-T EEE\");\n \n \t/* Prevent Phy from working in EEE and advertising it */\n-\trc = elink_84833_cmd_hdlr(phy, params,\n-\t\t\t\t PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);\n+\trc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,\n+\t\t\t\t &cmd_args, 1, PHY84833_MB_PROCESS1);\n \tif (rc != ELINK_STATUS_OK) {\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"EEE disable failed.\");\n+\t\tELINK_DEBUG_P0(sc, \"EEE disable failed.\");\n \t\treturn rc;\n \t}\n \n@@ -9507,16 +11223,17 @@ static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,\n }\n \n static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \telink_status_t rc;\n+\tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t cmd_args = 1;\n \n-\trc = elink_84833_cmd_hdlr(phy, params,\n-\t\t\t\t PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);\n+\trc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,\n+\t\t\t\t &cmd_args, 1, PHY84833_MB_PROCESS1);\n \tif (rc != ELINK_STATUS_OK) {\n-\t\tPMD_DRV_LOG(DEBUG, params->sc, \"EEE enable failed.\");\n+\t\tELINK_DEBUG_P0(sc, \"EEE enable failed.\");\n \t\treturn rc;\n \t}\n \n@@ -9524,15 +11241,15 @@ static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,\n }\n \n #define PHY84833_CONSTANT_LATENCY 1193\n-static uint8_t elink_848x3_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_848x3_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port, initialize = 1;\n \tuint16_t val;\n \tuint32_t actual_phy_selection;\n-\tuint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];\n+\tuint16_t cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];\n \telink_status_t rc = ELINK_STATUS_OK;\n \n \tDELAY(1000 * 1);\n@@ -9544,19 +11261,20 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,\n \n \tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {\n \t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,\n-\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n+\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH,\n+\t\t\t port);\n \t} else {\n \t\t/* MDIO reset */\n \t\telink_cl45_write(sc, phy,\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);\n+\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\tMDIO_PMA_REG_CTRL, 0x8000);\n \t}\n \n \telink_wait_reset_complete(sc, phy, params);\n \n \t/* Wait for GPHY to come out of reset */\n \tDELAY(1000 * 50);\n-\tif ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&\n-\t (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n+\tif (!elink_is_8483x_8485x(phy)) {\n \t\t/* BNX2X84823 requires that XGXS links up first @ 10G for normal\n \t\t * behavior.\n \t\t */\n@@ -9567,7 +11285,19 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,\n \t\telink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);\n \t\tvars->line_speed = temp;\n \t}\n+\t/* Check if this is actually BNX2X84858 */\n+\tif (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) {\n+\t\tuint16_t hw_rev;\n+\n+\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n+\t\t\t\tMDIO_AN_REG_848xx_ID_MSB, &hw_rev);\n+\t\tif (hw_rev == BNX2X84858_PHY_ID) {\n+\t\t\tparams->link_attr_sync |= LINK_ATTR_84858;\n+\t\t\telink_update_link_attr(params, params->link_attr_sync);\n+\t\t}\n+\t}\n \n+\t/* Set dual-media configuration according to configuration */\n \telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n \t\t\tMDIO_CTL_REG_84823_MEDIA, &val);\n \tval &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |\n@@ -9609,39 +11339,33 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,\n \n \telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n \t\t\t MDIO_CTL_REG_84823_MEDIA, val);\n-\tPMD_DRV_LOG(DEBUG, sc, \"Multi_phy config = 0x%x, Media control = 0x%x\",\n-\t\t params->multi_phy_config, val);\n+\tELINK_DEBUG_P2(sc, \"Multi_phy config = 0x%x, Media control = 0x%x\",\n+\t\t params->multi_phy_config, val);\n \n-\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n-\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n-\t\telink_84833_pair_swap_cfg(phy, params, vars);\n+\tif (elink_is_8483x_8485x(phy)) {\n+\t\telink_848xx_pair_swap_cfg(phy, params, vars);\n \n \t\t/* Keep AutogrEEEn disabled. */\n \t\tcmd_args[0] = 0x0;\n \t\tcmd_args[1] = 0x0;\n \t\tcmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;\n \t\tcmd_args[3] = PHY84833_CONSTANT_LATENCY;\n-\t\trc = elink_84833_cmd_hdlr(phy, params,\n-\t\t\t\t\t PHY84833_CMD_SET_EEE_MODE, cmd_args,\n-\t\t\t\t\t PHY84833_CMDHDLR_MAX_ARGS);\n-\t\tif (rc != ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Cfg AutogrEEEn failed.\");\n-\t\t}\n+\t\trc = elink_848xx_cmd_hdlr(phy, params,\n+\t\t\t\t\t PHY848xx_CMD_SET_EEE_MODE, cmd_args,\n+\t\t\t\t\t 4, PHY84833_MB_PROCESS1);\n+\t\tif (rc != ELINK_STATUS_OK)\n+\t\t\tELINK_DEBUG_P0(sc, \"Cfg AutogrEEEn failed.\");\n \t}\n-\tif (initialize) {\n+\tif (initialize)\n \t\trc = elink_848xx_cmn_config_init(phy, params, vars);\n-\t} else {\n+\telse\n \t\telink_save_848xx_spirom_version(phy, sc, params->port);\n-\t}\n \t/* 84833 PHY has a better feature and doesn't need to support this. */\n \tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {\n \t\tuint32_t cms_enable = REG_RD(sc, params->shmem_base +\n-\t\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.\n-\t\t\t\t\t\t port_hw_config[params->\n-\t\t\t\t\t\t\t\t port].\n-\t\t\t\t\t\t default_cfg)) &\n-\t\t PORT_HW_CFG_ENABLE_CMS_MASK;\n+\t\t\toffsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[params->port].default_cfg)) &\n+\t\t\tPORT_HW_CFG_ENABLE_CMS_MASK;\n \n \t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n \t\t\t\tMDIO_CTL_REG_84823_USER_CTRL_REG, &val);\n@@ -9662,7 +11386,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,\n \t elink_eee_has_cap(params)) {\n \t\trc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);\n \t\tif (rc != ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to configure EEE timers\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Failed to configure EEE timers\");\n \t\t\telink_8483x_disable_eee(phy, params, vars);\n \t\t\treturn rc;\n \t\t}\n@@ -9675,39 +11399,40 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,\n \t\telse\n \t\t\trc = elink_8483x_disable_eee(phy, params, vars);\n \t\tif (rc != ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to set EEE advertisement\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Failed to set EEE advertisement\");\n \t\t\treturn rc;\n \t\t}\n \t} else {\n \t\tvars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;\n \t}\n \n-\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n-\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n+\tif (elink_is_8483x_8485x(phy)) {\n \t\t/* Bring PHY out of super isolate mode as the final step. */\n \t\telink_cl45_read_and_write(sc, phy,\n \t\t\t\t\t MDIO_CTL_DEVAD,\n \t\t\t\t\t MDIO_84833_TOP_CFG_XGPHY_STRAP1,\n-\t\t\t\t\t (uint16_t) ~\n-\t\t\t\t\t MDIO_84833_SUPER_ISOLATE);\n+\t\t\t\t\t (uint16_t)~MDIO_84833_SUPER_ISOLATE);\n \t}\n \treturn rc;\n }\n \n static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val, val1, val2;\n \tuint8_t link_up = 0;\n \n+\n \t/* Check 10G-BaseT link status */\n \t/* Check PMD signal ok */\n-\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);\n \telink_cl45_read(sc, phy,\n-\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);\n-\tPMD_DRV_LOG(DEBUG, sc, \"BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x\", val2);\n+\t\t\tMDIO_AN_DEVAD, 0xFFFA, &val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,\n+\t\t\t&val2);\n+\tELINK_DEBUG_P1(sc, \"BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x\", val2);\n \n \t/* Check link 10G */\n \tif (val2 & (1 << 11)) {\n@@ -9715,8 +11440,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n \t\tvars->duplex = DUPLEX_FULL;\n \t\tlink_up = 1;\n \t\telink_ext_phy_10G_an_resolve(sc, phy, vars);\n-\t} else {\t\t/* Check Legacy speed link */\n-\t\tuint16_t legacy_status, legacy_speed, mii_ctrl;\n+\t} else { /* Check Legacy speed link */\n+\t\tuint16_t legacy_status, legacy_speed;\n \n \t\t/* Enable expansion register 0x42 (Operation mode status) */\n \t\telink_cl45_write(sc, phy,\n@@ -9729,8 +11454,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n \t\t\t\tMDIO_AN_REG_8481_EXPANSION_REG_RD_RW,\n \t\t\t\t&legacy_status);\n \n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Legacy speed status = 0x%x\", legacy_status);\n+\t\tELINK_DEBUG_P1(sc, \"Legacy speed status = 0x%x\",\n+\t\t legacy_status);\n \t\tlink_up = ((legacy_status & (1 << 11)) == (1 << 11));\n \t\tlegacy_speed = (legacy_status & (3 << 9));\n \t\tif (legacy_speed == (0 << 9))\n@@ -9739,13 +11464,15 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n \t\t\tvars->line_speed = ELINK_SPEED_100;\n \t\telse if (legacy_speed == (2 << 9))\n \t\t\tvars->line_speed = ELINK_SPEED_1000;\n-\t\telse {\t\t/* Should not happen: Treat as link down */\n+\t\telse { /* Should not happen: Treat as link down */\n \t\t\tvars->line_speed = 0;\n \t\t\tlink_up = 0;\n \t\t}\n \n \t\tif (params->feature_config_flags &\n-\t\t ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {\n+\t\t\tELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {\n+\t\t\tuint16_t mii_ctrl;\n+\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_AN_DEVAD,\n \t\t\t\t\tMDIO_AN_REG_8481_LEGACY_MII_CTRL,\n@@ -9760,10 +11487,10 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n \t\t\telse\n \t\t\t\tvars->duplex = DUPLEX_HALF;\n \n-\t\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t\t \"Link is up in %dMbps, is_duplex_full= %d\",\n-\t\t\t\t vars->line_speed,\n-\t\t\t\t (vars->duplex == DUPLEX_FULL));\n+\t\t\tELINK_DEBUG_P2(sc,\n+\t\t\t \"Link is up in %dMbps, is_duplex_full= %d\",\n+\t\t\t vars->line_speed,\n+\t\t\t (vars->duplex == DUPLEX_FULL));\n \t\t\t/* Check legacy speed AN resolution */\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_AN_DEVAD,\n@@ -9771,19 +11498,19 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n \t\t\t\t\t&val);\n \t\t\tif (val & (1 << 5))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n+\t\t\t\t\tLINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_AN_DEVAD,\n \t\t\t\t\tMDIO_AN_REG_8481_LEGACY_AN_EXPANSION,\n \t\t\t\t\t&val);\n \t\t\tif ((val & (1 << 0)) == 0)\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_PARALLEL_DETECTION_USED;\n+\t\t\t\t\tLINK_STATUS_PARALLEL_DETECTION_USED;\n \t\t}\n \t}\n \tif (link_up) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"BNX2X848x3: link speed is %d\",\n-\t\t\t vars->line_speed);\n+\t\tELINK_DEBUG_P1(sc, \"BNX2X848x3: link speed is %d\",\n+\t\t\t vars->line_speed);\n \t\telink_ext_phy_resolve_fc(phy, params, vars);\n \n \t\t/* Read LP advertised speeds */\n@@ -9791,48 +11518,47 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,\n \t\t\t\tMDIO_AN_REG_CL37_FC_LP, &val);\n \t\tif (val & (1 << 5))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10THD_CAPABLE;\n \t\tif (val & (1 << 6))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;\n \t\tif (val & (1 << 7))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;\n \t\tif (val & (1 << 8))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;\n \t\tif (val & (1 << 9))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_100T4_CAPABLE;\n \n \t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n \t\t\t\tMDIO_AN_REG_1000T_STATUS, &val);\n \n \t\tif (val & (1 << 10))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;\n \t\tif (val & (1 << 11))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n \n \t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n \t\t\t\tMDIO_AN_REG_MASTER_STATUS, &val);\n \n \t\tif (val & (1 << 11))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n \n \t\t/* Determine if EEE was negotiated */\n-\t\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n-\t\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))\n+\t\tif (elink_is_8483x_8485x(phy))\n \t\t\telink_eee_an_resolve(phy, params, vars);\n \t}\n \n \treturn link_up;\n }\n \n-static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,\n-\t\t\t\t\t uint16_t * len)\n+static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str,\n+\t\t\t\t\t uint16_t *len)\n {\n \telink_status_t status = ELINK_STATUS_OK;\n \tuint32_t spirom_ver;\n@@ -9845,17 +11571,18 @@ static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,\n \t\t\t\tstruct elink_params *params)\n {\n \telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);\n \telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);\n }\n \n static void elink_8481_link_reset(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params)\n+\t\t\t\t\tstruct elink_params *params)\n {\n \telink_cl45_write(params->sc, phy,\n \t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);\n-\telink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);\n+\telink_cl45_write(params->sc, phy,\n+\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);\n }\n \n static void elink_848x3_link_reset(struct elink_phy *phy,\n@@ -9872,7 +11599,8 @@ static void elink_848x3_link_reset(struct elink_phy *phy,\n \n \tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {\n \t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,\n-\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n+\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW,\n+\t\t\t port);\n \t} else {\n \t\telink_cl45_read(sc, phy,\n \t\t\t\tMDIO_CTL_DEVAD,\n@@ -9889,48 +11617,52 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val;\n-\t__rte_unused uint8_t port;\n+\tuint8_t port;\n \n \tif (!(CHIP_IS_E1x(sc)))\n \t\tport = SC_PATH(sc);\n \telse\n \t\tport = params->port;\n-\n \tswitch (mode) {\n \tcase ELINK_LED_MODE_OFF:\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Port 0x%x: LED MODE OFF\", port);\n+\t\tELINK_DEBUG_P1(sc, \"Port 0x%x: LED MODE OFF\", port);\n \n \t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n \t\t SHARED_HW_CFG_LED_EXTPHY1) {\n \n \t\t\t/* Set LED masks */\n \t\t\telink_cl45_write(sc, phy,\n-\t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n+\t\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\t\tMDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n-\t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x0);\n+\t\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\t\tMDIO_PMA_REG_8481_LED2_MASK,\n+\t\t\t\t\t0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n-\t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x0);\n+\t\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\t\tMDIO_PMA_REG_8481_LED3_MASK,\n+\t\t\t\t\t0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n-\t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x0);\n+\t\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\t\tMDIO_PMA_REG_8481_LED5_MASK,\n+\t\t\t\t\t0x0);\n \n \t\t} else {\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t 0x0);\n \t\t}\n \t\tbreak;\n \tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n \n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Port 0x%x: LED MODE FRONT PANEL OFF\", port);\n+\t\tELINK_DEBUG_P1(sc, \"Port 0x%x: LED MODE FRONT PANEL OFF\",\n+\t\t port);\n \n \t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n \t\t SHARED_HW_CFG_LED_EXTPHY1) {\n@@ -9938,25 +11670,31 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\t\t/* Set LED masks */\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t 0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x0);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK,\n+\t\t\t\t\t 0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x0);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK,\n+\t\t\t\t\t 0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x20);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK,\n+\t\t\t\t\t 0x20);\n \n \t\t} else {\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n-\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t 0x0);\n+\t\t\tif (phy->type ==\n+\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n \t\t\t\t/* Disable MI_INT interrupt before setting LED4\n \t\t\t\t * source to constant off.\n \t\t\t\t */\n@@ -9964,12 +11702,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\t\t\t\t params->port * 4) &\n \t\t\t\t ELINK_NIG_MASK_MI_INT) {\n \t\t\t\t\tparams->link_flags |=\n-\t\t\t\t\t ELINK_LINK_FLAGS_INT_DISABLED;\n+\t\t\t\t\tELINK_LINK_FLAGS_INT_DISABLED;\n \n-\t\t\t\t\telink_bits_dis(sc,\n-\t\t\t\t\t\t NIG_REG_MASK_INTERRUPT_PORT0\n-\t\t\t\t\t\t + params->port * 4,\n-\t\t\t\t\t\t ELINK_NIG_MASK_MI_INT);\n+\t\t\t\t\telink_bits_dis(\n+\t\t\t\t\t\tsc,\n+\t\t\t\t\t\tNIG_REG_MASK_INTERRUPT_PORT0 +\n+\t\t\t\t\t\tparams->port * 4,\n+\t\t\t\t\t\tELINK_NIG_MASK_MI_INT);\n \t\t\t\t}\n \t\t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t\t MDIO_PMA_DEVAD,\n@@ -9980,42 +11719,50 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\tbreak;\n \tcase ELINK_LED_MODE_ON:\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Port 0x%x: LED MODE ON\", port);\n+\t\tELINK_DEBUG_P1(sc, \"Port 0x%x: LED MODE ON\", port);\n \n \t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n \t\t SHARED_HW_CFG_LED_EXTPHY1) {\n \t\t\t/* Set control reg */\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n+\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL,\n+\t\t\t\t\t&val);\n \t\t\tval &= 0x8000;\n \t\t\tval |= 0x2492;\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL,\n+\t\t\t\t\t val);\n \n \t\t\t/* Set LED masks */\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t 0x0);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x20);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK,\n+\t\t\t\t\t 0x20);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x20);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK,\n+\t\t\t\t\t 0x20);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x0);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK,\n+\t\t\t\t\t 0x0);\n \t\t} else {\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x20);\n-\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t 0x20);\n+\t\t\tif (phy->type ==\n+\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n \t\t\t\t/* Disable MI_INT interrupt before setting LED4\n \t\t\t\t * source to constant on.\n \t\t\t\t */\n@@ -10023,12 +11770,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\t\t\t\t params->port * 4) &\n \t\t\t\t ELINK_NIG_MASK_MI_INT) {\n \t\t\t\t\tparams->link_flags |=\n-\t\t\t\t\t ELINK_LINK_FLAGS_INT_DISABLED;\n+\t\t\t\t\tELINK_LINK_FLAGS_INT_DISABLED;\n \n-\t\t\t\t\telink_bits_dis(sc,\n-\t\t\t\t\t\t NIG_REG_MASK_INTERRUPT_PORT0\n-\t\t\t\t\t\t + params->port * 4,\n-\t\t\t\t\t\t ELINK_NIG_MASK_MI_INT);\n+\t\t\t\t\telink_bits_dis(\n+\t\t\t\t\t\tsc,\n+\t\t\t\t\t\tNIG_REG_MASK_INTERRUPT_PORT0 +\n+\t\t\t\t\t\tparams->port * 4,\n+\t\t\t\t\t\tELINK_NIG_MASK_MI_INT);\n \t\t\t\t}\n \t\t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t\t MDIO_PMA_DEVAD,\n@@ -10040,7 +11788,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \n \tcase ELINK_LED_MODE_OPER:\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Port 0x%x: LED MODE OPER\", port);\n+\t\tELINK_DEBUG_P1(sc, \"Port 0x%x: LED MODE OPER\", port);\n \n \t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n \t\t SHARED_HW_CFG_LED_EXTPHY1) {\n@@ -10048,14 +11796,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\t\t/* Set control reg */\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n+\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL,\n+\t\t\t\t\t&val);\n \n \t\t\tif (!((val &\n \t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)\n-\t\t\t >>\n-\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))\n-\t\t\t{\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting LINK_SIGNAL\");\n+\t\t\t >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Setting LINK_SIGNAL\");\n \t\t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t\t MDIO_PMA_DEVAD,\n \t\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL,\n@@ -10065,19 +11812,23 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\t\t/* Set LED masks */\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x10);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t 0x10);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x80);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK,\n+\t\t\t\t\t 0x80);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x98);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK,\n+\t\t\t\t\t 0x98);\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x40);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK,\n+\t\t\t\t\t 0x40);\n \n \t\t} else {\n \t\t\t/* EXTPHY2 LED mode indicate that the 100M/1G/10G LED\n@@ -10090,18 +11841,22 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, val);\n+\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK,\n+\t\t\t\t\t val);\n \n \t\t\t/* Tell LED3 to blink on source */\n \t\t\telink_cl45_read(sc, phy,\n \t\t\t\t\tMDIO_PMA_DEVAD,\n-\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n+\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL,\n+\t\t\t\t\t&val);\n \t\t\tval &= ~(7 << 6);\n-\t\t\tval |= (1 << 6);\t/* A83B[8:6]= 1 */\n+\t\t\tval |= (1 << 6); /* A83B[8:6]= 1 */\n \t\t\telink_cl45_write(sc, phy,\n \t\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n-\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n+\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL,\n+\t\t\t\t\t val);\n+\t\t\tif (phy->type ==\n+\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n \t\t\t\t/* Restore LED4 source to external link,\n \t\t\t\t * and re-enable interrupts.\n \t\t\t\t */\n@@ -10113,14 +11868,14 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,\n \t\t\t\t ELINK_LINK_FLAGS_INT_DISABLED) {\n \t\t\t\t\telink_link_int_enable(params);\n \t\t\t\t\tparams->link_flags &=\n-\t\t\t\t\t ~ELINK_LINK_FLAGS_INT_DISABLED;\n+\t\t\t\t\t\t~ELINK_LINK_FLAGS_INT_DISABLED;\n \t\t\t\t}\n \t\t\t}\n \t\t}\n \t\tbreak;\n \t}\n \n-\t/* This is a workaround for E3+84833 until autoneg\n+\t/* This is a workaround for E3 + 84833 until autoneg\n \t * restart is fixed in f/w\n \t */\n \tif (CHIP_IS_E3(sc)) {\n@@ -10145,7 +11900,9 @@ static void elink_54618se_specific_func(struct elink_phy *phy,\n \t\telink_cl22_write(sc, phy,\n \t\t\t\t MDIO_REG_GPHY_SHADOW,\n \t\t\t\t MDIO_REG_GPHY_SHADOW_LED_SEL2);\n-\t\telink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);\n+\t\telink_cl22_read(sc, phy,\n+\t\t\t\tMDIO_REG_GPHY_SHADOW,\n+\t\t\t\t&temp);\n \t\ttemp &= ~(0xf << 4);\n \t\ttemp |= (0x6 << 4);\n \t\telink_cl22_write(sc, phy,\n@@ -10159,16 +11916,16 @@ static void elink_54618se_specific_func(struct elink_phy *phy,\n \t}\n }\n \n-static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_54618se_config_init(struct elink_phy *phy,\n+\t\t\t\t\t struct elink_params *params,\n+\t\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t port;\n \tuint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;\n \tuint32_t cfg_pin;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"54618SE cfg init\");\n+\tELINK_DEBUG_P0(sc, \"54618SE cfg init\");\n \tDELAY(1000 * 1);\n \n \t/* This works with E3 only, no need to check the chip\n@@ -10177,11 +11934,10 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n \tport = params->port;\n \n \tcfg_pin = (REG_RD(sc, params->shmem_base +\n-\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t e3_cmn_pin_cfg)) &\n-\t\t PORT_HW_CFG_E3_PHY_RESET_MASK) >>\n-\t PORT_HW_CFG_E3_PHY_RESET_SHIFT;\n+\t\t\toffsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[port].e3_cmn_pin_cfg)) &\n+\t\t\tPORT_HW_CFG_E3_PHY_RESET_MASK) >>\n+\t\t\tPORT_HW_CFG_E3_PHY_RESET_SHIFT;\n \n \t/* Drive pin high to bring the GPHY out of reset. */\n \telink_set_cfg_pin(sc, cfg_pin, 1);\n@@ -10190,63 +11946,76 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n \tDELAY(1000 * 50);\n \n \t/* reset phy */\n-\telink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);\n+\telink_cl22_write(sc, phy,\n+\t\t\t MDIO_PMA_REG_CTRL, 0x8000);\n \telink_wait_reset_complete(sc, phy, params);\n \n \t/* Wait for GPHY to reset */\n \tDELAY(1000 * 50);\n \n+\n \telink_54618se_specific_func(phy, params, ELINK_PHY_INIT);\n \t/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */\n \telink_cl22_write(sc, phy,\n-\t\t\t MDIO_REG_GPHY_SHADOW,\n-\t\t\t MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);\n-\telink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);\n+\t\t\tMDIO_REG_GPHY_SHADOW,\n+\t\t\tMDIO_REG_GPHY_SHADOW_AUTO_DET_MED);\n+\telink_cl22_read(sc, phy,\n+\t\t\tMDIO_REG_GPHY_SHADOW,\n+\t\t\t&temp);\n \ttemp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;\n \telink_cl22_write(sc, phy,\n-\t\t\t MDIO_REG_GPHY_SHADOW,\n-\t\t\t MDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n+\t\t\tMDIO_REG_GPHY_SHADOW,\n+\t\t\tMDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n \n \t/* Set up fc */\n \t/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */\n \telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n \tfc_val = 0;\n \tif ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)\n+\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)\n \t\tfc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;\n \n \tif ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n-\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)\n+\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)\n \t\tfc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;\n \n \t/* Read all advertisement */\n-\telink_cl22_read(sc, phy, 0x09, &an_1000_val);\n+\telink_cl22_read(sc, phy,\n+\t\t\t0x09,\n+\t\t\t&an_1000_val);\n \n-\telink_cl22_read(sc, phy, 0x04, &an_10_100_val);\n+\telink_cl22_read(sc, phy,\n+\t\t\t0x04,\n+\t\t\t&an_10_100_val);\n \n-\telink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);\n+\telink_cl22_read(sc, phy,\n+\t\t\tMDIO_PMA_REG_CTRL,\n+\t\t\t&autoneg_val);\n \n \t/* Disable forced speed */\n-\tautoneg_val &=\n-\t ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));\n-\tan_10_100_val &=\n-\t ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |\n-\t (1 << 11));\n+\tautoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) |\n+\t\t\t (1 << 13));\n+\tan_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |\n+\t\t\t (1 << 10) | (1 << 11));\n \n \tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n-\t (phy->speed_cap_mask &\n-\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n-\t (phy->req_line_speed == ELINK_SPEED_1000)) {\n+\t\t\t(phy->speed_cap_mask &\n+\t\t\tPORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n+\t\t\t(phy->req_line_speed == ELINK_SPEED_1000)) {\n \t\tan_1000_val |= (1 << 8);\n \t\tautoneg_val |= (1 << 9 | 1 << 12);\n \t\tif (phy->req_duplex == DUPLEX_FULL)\n \t\t\tan_1000_val |= (1 << 9);\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 1G\");\n+\t\tELINK_DEBUG_P0(sc, \"Advertising 1G\");\n \t} else\n \t\tan_1000_val &= ~((1 << 8) | (1 << 9));\n \n-\telink_cl22_write(sc, phy, 0x09, an_1000_val);\n-\telink_cl22_read(sc, phy, 0x09, &an_1000_val);\n+\telink_cl22_write(sc, phy,\n+\t\t\t0x09,\n+\t\t\tan_1000_val);\n+\telink_cl22_read(sc, phy,\n+\t\t\t0x09,\n+\t\t\t&an_1000_val);\n \n \t/* Advertise 10/100 link speed */\n \tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {\n@@ -10254,25 +12023,25 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n \t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {\n \t\t\tan_10_100_val |= (1 << 5);\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 10M-HD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 10M-HD\");\n \t\t}\n \t\tif (phy->speed_cap_mask &\n-\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {\n \t\t\tan_10_100_val |= (1 << 6);\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 10M-FD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 10M-FD\");\n \t\t}\n \t\tif (phy->speed_cap_mask &\n \t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {\n \t\t\tan_10_100_val |= (1 << 7);\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 100M-HD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 100M-HD\");\n \t\t}\n \t\tif (phy->speed_cap_mask &\n \t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {\n \t\t\tan_10_100_val |= (1 << 8);\n \t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Advertising 100M-FD\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Advertising 100M-FD\");\n \t\t}\n \t}\n \n@@ -10280,13 +12049,17 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n \tif (phy->req_line_speed == ELINK_SPEED_100) {\n \t\tautoneg_val |= (1 << 13);\n \t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n-\t\telink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 100M force\");\n+\t\telink_cl22_write(sc, phy,\n+\t\t\t\t0x18,\n+\t\t\t\t(1 << 15 | 1 << 9 | 7 << 0));\n+\t\tELINK_DEBUG_P0(sc, \"Setting 100M force\");\n \t}\n \tif (phy->req_line_speed == ELINK_SPEED_10) {\n \t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n-\t\telink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Setting 10M force\");\n+\t\telink_cl22_write(sc, phy,\n+\t\t\t\t0x18,\n+\t\t\t\t(1 << 15 | 1 << 9 | 7 << 0));\n+\t\tELINK_DEBUG_P0(sc, \"Setting 10M force\");\n \t}\n \n \tif ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {\n@@ -10301,7 +12074,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n \n \t\trc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);\n \t\tif (rc != ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to configure EEE timers\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Failed to configure EEE timers\");\n \t\t\telink_eee_disable(phy, params, vars);\n \t\t} else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&\n \t\t\t (phy->req_duplex == DUPLEX_FULL) &&\n@@ -10315,38 +12088,42 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,\n \t\t\telink_eee_advertise(phy, params, vars,\n \t\t\t\t\t SHMEM_EEE_1G_ADV);\n \t\t} else {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Don't Advertise 1GBase-T EEE\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Don't Advertise 1GBase-T EEE\");\n \t\t\telink_eee_disable(phy, params, vars);\n \t\t}\n \t} else {\n-\t\tvars->eee_status &= ~SHMEM_EEE_1G_ADV <<\n-\t\t SHMEM_EEE_SUPPORTED_SHIFT;\n+\t\tvars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) <<\n+\t\t\t\t SHMEM_EEE_SUPPORTED_SHIFT);\n \n \t\tif (phy->flags & ELINK_FLAGS_EEE) {\n \t\t\t/* Handle legacy auto-grEEEn */\n \t\t\tif (params->feature_config_flags &\n \t\t\t ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {\n \t\t\t\ttemp = 6;\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Enabling Auto-GrEEEn\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Enabling Auto-GrEEEn\");\n \t\t\t} else {\n \t\t\t\ttemp = 0;\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Don't Adv. EEE\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Don't Adv. EEE\");\n \t\t\t}\n \t\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n \t\t\t\t\t MDIO_AN_REG_EEE_ADV, temp);\n \t\t}\n \t}\n \n-\telink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);\n+\telink_cl22_write(sc, phy,\n+\t\t\t0x04,\n+\t\t\tan_10_100_val | fc_val);\n \n \tif (phy->req_duplex == DUPLEX_FULL)\n \t\tautoneg_val |= (1 << 8);\n \n-\telink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);\n+\telink_cl22_write(sc, phy,\n+\t\t\tMDIO_PMA_REG_CTRL, autoneg_val);\n \n \treturn ELINK_STATUS_OK;\n }\n \n+\n static void elink_5461x_set_link_led(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params, uint8_t mode)\n {\n@@ -10354,11 +12131,14 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,\n \tuint16_t temp;\n \n \telink_cl22_write(sc, phy,\n-\t\t\t MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);\n-\telink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);\n+\t\tMDIO_REG_GPHY_SHADOW,\n+\t\tMDIO_REG_GPHY_SHADOW_LED_SEL1);\n+\telink_cl22_read(sc, phy,\n+\t\tMDIO_REG_GPHY_SHADOW,\n+\t\t&temp);\n \ttemp &= 0xff00;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"54618x set link led (mode=%x)\", mode);\n+\tELINK_DEBUG_P1(sc, \"54618x set link led (mode=%x)\", mode);\n \tswitch (mode) {\n \tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n \tcase ELINK_LED_MODE_OFF:\n@@ -10374,11 +12154,12 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,\n \t\tbreak;\n \t}\n \telink_cl22_write(sc, phy,\n-\t\t\t MDIO_REG_GPHY_SHADOW,\n-\t\t\t MDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n+\t\tMDIO_REG_GPHY_SHADOW,\n+\t\tMDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n \treturn;\n }\n \n+\n static void elink_54618se_link_reset(struct elink_phy *phy,\n \t\t\t\t struct elink_params *params)\n {\n@@ -10395,19 +12176,18 @@ static void elink_54618se_link_reset(struct elink_phy *phy,\n \t */\n \tport = params->port;\n \tcfg_pin = (REG_RD(sc, params->shmem_base +\n-\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t e3_cmn_pin_cfg)) &\n-\t\t PORT_HW_CFG_E3_PHY_RESET_MASK) >>\n-\t PORT_HW_CFG_E3_PHY_RESET_SHIFT;\n+\t\t\toffsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[port].e3_cmn_pin_cfg)) &\n+\t\t\tPORT_HW_CFG_E3_PHY_RESET_MASK) >>\n+\t\t\tPORT_HW_CFG_E3_PHY_RESET_SHIFT;\n \n \t/* Drive pin low to put GPHY in reset. */\n \telink_set_cfg_pin(sc, cfg_pin, 0);\n }\n \n static uint8_t elink_54618se_read_status(struct elink_phy *phy,\n-\t\t\t\t\t struct elink_params *params,\n-\t\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t val;\n@@ -10415,11 +12195,15 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,\n \tuint16_t legacy_status, legacy_speed;\n \n \t/* Get speed operation status */\n-\telink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);\n-\tPMD_DRV_LOG(DEBUG, sc, \"54618SE read_status: 0x%x\", legacy_status);\n+\telink_cl22_read(sc, phy,\n+\t\t\tMDIO_REG_GPHY_AUX_STATUS,\n+\t\t\t&legacy_status);\n+\tELINK_DEBUG_P1(sc, \"54618SE read_status: 0x%x\", legacy_status);\n \n \t/* Read status to clear the PHY interrupt. */\n-\telink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);\n+\telink_cl22_read(sc, phy,\n+\t\t\tMDIO_REG_INTR_STATUS,\n+\t\t\t&val);\n \n \tlink_up = ((legacy_status & (1 << 2)) == (1 << 2));\n \n@@ -10445,25 +12229,30 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,\n \t\t} else if (legacy_speed == (1 << 8)) {\n \t\t\tvars->line_speed = ELINK_SPEED_10;\n \t\t\tvars->duplex = DUPLEX_HALF;\n-\t\t} else\t\t/* Should not happen */\n+\t\t} else /* Should not happen */\n \t\t\tvars->line_speed = 0;\n \n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Link is up in %dMbps, is_duplex_full= %d\",\n-\t\t\t vars->line_speed, (vars->duplex == DUPLEX_FULL));\n+\t\tELINK_DEBUG_P2(sc,\n+\t\t \"Link is up in %dMbps, is_duplex_full= %d\",\n+\t\t vars->line_speed,\n+\t\t (vars->duplex == DUPLEX_FULL));\n \n \t\t/* Check legacy speed AN resolution */\n-\t\telink_cl22_read(sc, phy, 0x01, &val);\n+\t\telink_cl22_read(sc, phy,\n+\t\t\t\t0x01,\n+\t\t\t\t&val);\n \t\tif (val & (1 << 5))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n-\t\telink_cl22_read(sc, phy, 0x06, &val);\n+\t\t\t\tLINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n+\t\telink_cl22_read(sc, phy,\n+\t\t\t\t0x06,\n+\t\t\t\t&val);\n \t\tif ((val & (1 << 0)) == 0)\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_PARALLEL_DETECTION_USED;\n+\t\t\t\tLINK_STATUS_PARALLEL_DETECTION_USED;\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"BNX2X54618SE: link speed is %d\",\n-\t\t\t vars->line_speed);\n+\t\tELINK_DEBUG_P1(sc, \"BNX2X4618SE: link speed is %d\",\n+\t\t\t vars->line_speed);\n \n \t\telink_ext_phy_resolve_fc(phy, params, vars);\n \n@@ -10473,27 +12262,27 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,\n \n \t\t\tif (val & (1 << 5))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;\n \t\t\tif (val & (1 << 6))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;\n \t\t\tif (val & (1 << 7))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;\n \t\t\tif (val & (1 << 8))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;\n \t\t\tif (val & (1 << 9))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;\n \n \t\t\telink_cl22_read(sc, phy, 0xa, &val);\n \t\t\tif (val & (1 << 10))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;\n \t\t\tif (val & (1 << 11))\n \t\t\t\tvars->link_status |=\n-\t\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n+\t\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n \n \t\t\tif ((phy->flags & ELINK_FLAGS_EEE) &&\n \t\t\t elink_eee_has_cap(params))\n@@ -10510,7 +12299,7 @@ static void elink_54618se_config_loopback(struct elink_phy *phy,\n \tuint16_t val;\n \tuint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"2PMA/PMD ext_phy_loopback: 54618se\");\n+\tELINK_DEBUG_P0(sc, \"2PMA/PMD ext_phy_loopback: 54618se\");\n \n \t/* Enable master/slave manual mmode and set to master */\n \t/* mii write 9 [bits set 11 12] */\n@@ -10555,31 +12344,34 @@ static void elink_7101_config_loopback(struct elink_phy *phy,\n \t\t\t MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);\n }\n \n-static uint8_t elink_7101_config_init(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+static elink_status_t elink_7101_config_init(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tuint16_t fw_ver1, fw_ver2, val;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting the SFX7101 LASI indication\");\n+\tELINK_DEBUG_P0(sc, \"Setting the SFX7101 LASI indication\");\n \n-\t/* Restore normal power mode */\n+\t/* Restore normal power mode*/\n \telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n \t/* HW reset */\n \telink_ext_phy_hw_reset(sc, params->port);\n \telink_wait_reset_complete(sc, phy, params);\n \n-\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting the SFX7101 LED to blink on traffic\");\n+\telink_cl45_write(sc, phy,\n+\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);\n+\tELINK_DEBUG_P0(sc, \"Setting the SFX7101 LED to blink on traffic\");\n \telink_cl45_write(sc, phy,\n \t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));\n \n \telink_ext_phy_set_pause(params, phy, vars);\n \t/* Restart autoneg */\n-\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);\n \tval |= 0x200;\n-\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);\n+\telink_cl45_write(sc, phy,\n+\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);\n \n \t/* Save spirom version */\n \telink_cl45_read(sc, phy,\n@@ -10588,24 +12380,30 @@ static uint8_t elink_7101_config_init(struct elink_phy *phy,\n \telink_cl45_read(sc, phy,\n \t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);\n \telink_save_spirom_version(sc, params->port,\n-\t\t\t\t (uint32_t) (fw_ver1 << 16 | fw_ver2),\n+\t\t\t\t (uint32_t)(fw_ver1 << 16 | fw_ver2),\n \t\t\t\t phy->ver_addr);\n \treturn ELINK_STATUS_OK;\n }\n \n static uint8_t elink_7101_read_status(struct elink_phy *phy,\n-\t\t\t\t struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+\t\t\t\t struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t link_up;\n \tuint16_t val1, val2;\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"10G-base-T LASI status 0x%x->0x%x\", val2, val1);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n-\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"10G-base-T PMA status 0x%x->0x%x\", val2, val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n+\tELINK_DEBUG_P2(sc, \"10G-base-T LASI status 0x%x->0x%x\",\n+\t\t val2, val1);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n+\tELINK_DEBUG_P2(sc, \"10G-base-T PMA status 0x%x->0x%x\",\n+\t\t val2, val1);\n \tlink_up = ((val1 & 4) == 4);\n \t/* If link is up print the AN outcome of the SFX7101 PHY */\n \tif (link_up) {\n@@ -10614,21 +12412,21 @@ static uint8_t elink_7101_read_status(struct elink_phy *phy,\n \t\t\t\t&val2);\n \t\tvars->line_speed = ELINK_SPEED_10000;\n \t\tvars->duplex = DUPLEX_FULL;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"SFX7101 AN status 0x%x->Master=%x\",\n-\t\t\t val2, (val2 & (1 << 14)));\n+\t\tELINK_DEBUG_P2(sc, \"SFX7101 AN status 0x%x->Master=%x\",\n+\t\t\t val2, (val2 & (1 << 14)));\n \t\telink_ext_phy_10G_an_resolve(sc, phy, vars);\n \t\telink_ext_phy_resolve_fc(phy, params, vars);\n \n \t\t/* Read LP advertised speeds */\n \t\tif (val2 & (1 << 11))\n \t\t\tvars->link_status |=\n-\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n+\t\t\t\tLINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n \t}\n \treturn link_up;\n }\n \n-static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,\n-\t\t\t\t uint16_t * len)\n+static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str,\n+\t\t\t\t\t uint16_t *len)\n {\n \tif (*len < 5)\n \t\treturn ELINK_STATUS_ERROR;\n@@ -10641,15 +12439,39 @@ static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,\n \treturn ELINK_STATUS_OK;\n }\n \n-static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,\n-\t\t\t\tstruct elink_params *params)\n+void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy)\n {\n+\tuint16_t val, cnt;\n+\n+\telink_cl45_read(sc, phy,\n+\t\t\tMDIO_PMA_DEVAD,\n+\t\t\tMDIO_PMA_REG_7101_RESET, &val);\n+\n+\tfor (cnt = 0; cnt < 10; cnt++) {\n+\t\tDELAY(1000 * 50);\n+\t\t/* Writes a self-clearing reset */\n+\t\telink_cl45_write(sc, phy,\n+\t\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t\t MDIO_PMA_REG_7101_RESET,\n+\t\t\t\t (val | (1 << 15)));\n+\t\t/* Wait for clear */\n+\t\telink_cl45_read(sc, phy,\n+\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\tMDIO_PMA_REG_7101_RESET, &val);\n+\n+\t\tif ((val & (1 << 15)) == 0)\n+\t\t\tbreak;\n+\t}\n+}\n+\n+static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,\n+\t\t\t\tstruct elink_params *params) {\n \t/* Low power mode is controlled by GPIO 2 */\n \telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);\n \t/* The PHY reset is controlled by GPIO 1 */\n \telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,\n-\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);\n+\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);\n }\n \n static void elink_7101_set_link_led(struct elink_phy *phy,\n@@ -10670,7 +12492,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy,\n \t\tbreak;\n \t}\n \telink_cl45_write(sc, phy,\n-\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);\n+\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t MDIO_PMA_REG_7107_LINK_LED_CNTL,\n+\t\t\t val);\n }\n \n /******************************************************************/\n@@ -10678,482 +12502,532 @@ static void elink_7101_set_link_led(struct elink_phy *phy,\n /******************************************************************/\n \n static const struct elink_phy phy_null = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,\n-\t.addr = 0,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = 0,\n-\t.media_type = ELINK_ETH_PHY_NOT_PRESENT,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = NULL,\n-\t.read_status = NULL,\n-\t.link_reset = NULL,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = NULL,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,\n+\t.addr\t\t= 0,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_INIT_XGXS_FIRST,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= 0,\n+\t.media_type\t= ELINK_ETH_PHY_NOT_PRESENT,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)NULL,\n+\t.read_status\t= (read_status_t)NULL,\n+\t.link_reset\t= (link_reset_t)NULL,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)NULL,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n \n static const struct elink_phy phy_serdes = {\n-\t.type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = 0,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n-\t\t ELINK_SUPPORTED_10baseT_Full |\n-\t\t ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_2500baseX_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_xgxs_config_init,\n-\t.read_status = elink_link_settings_status,\n-\t.link_reset = elink_int_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = NULL,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= 0,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10baseT_Half |\n+\t\t\t ELINK_SUPPORTED_10baseT_Full |\n+\t\t\t ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_2500baseX_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_xgxs_config_init,\n+\t.read_status\t= (read_status_t)elink_link_settings_status,\n+\t.link_reset\t= (link_reset_t)elink_int_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)NULL,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n \n static const struct elink_phy phy_xgxs = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = 0,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n-\t\t ELINK_SUPPORTED_10baseT_Full |\n-\t\t ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_2500baseX_Full |\n-\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_CX4,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_xgxs_config_init,\n-\t.read_status = elink_link_settings_status,\n-\t.link_reset = elink_int_link_reset,\n-\t.config_loopback = elink_set_xgxs_loopback,\n-\t.format_fw_ver = NULL,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = elink_xgxs_specific_func\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= 0,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10baseT_Half |\n+\t\t\t ELINK_SUPPORTED_10baseT_Full |\n+\t\t\t ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_2500baseX_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_CX4,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_xgxs_config_init,\n+\t.read_status\t= (read_status_t)elink_link_settings_status,\n+\t.link_reset\t= (link_reset_t)elink_int_link_reset,\n+\t.config_loopback = (config_loopback_t)elink_set_xgxs_loopback,\n+\t.format_fw_ver\t= (format_fw_ver_t)NULL,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func\n };\n-\n static const struct elink_phy phy_warpcore = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_TX_ERROR_CHECK,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n-\t\t ELINK_SUPPORTED_10baseT_Full |\n-\t\t ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_20000baseKR2_Full |\n-\t\t ELINK_SUPPORTED_20000baseMLD2_Full |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_UNSPECIFIED,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t/* req_duplex = */ 0,\n-\t/* rsrv = */ 0,\n-\t.config_init = elink_warpcore_config_init,\n-\t.read_status = elink_warpcore_read_status,\n-\t.link_reset = elink_warpcore_link_reset,\n-\t.config_loopback = elink_set_warpcore_loopback,\n-\t.format_fw_ver = NULL,\n-\t.hw_reset = elink_warpcore_hw_reset,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_TX_ERROR_CHECK,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10baseT_Half |\n+\t\t\t ELINK_SUPPORTED_10baseT_Full |\n+\t\t\t ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseKX_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseKR_Full |\n+\t\t\t ELINK_SUPPORTED_20000baseKR2_Full |\n+\t\t\t ELINK_SUPPORTED_20000baseMLD2_Full |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_UNSPECIFIED,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t/* req_duplex = */0,\n+\t/* rsrv = */0,\n+\t.config_init\t= (config_init_t)elink_warpcore_config_init,\n+\t.read_status\t= (read_status_t)elink_warpcore_read_status,\n+\t.link_reset\t= (link_reset_t)elink_warpcore_link_reset,\n+\t.config_loopback = (config_loopback_t)elink_set_warpcore_loopback,\n+\t.format_fw_ver\t= (format_fw_ver_t)NULL,\n+\t.hw_reset\t= (hw_reset_t)elink_warpcore_hw_reset,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n \n+\n static const struct elink_phy phy_7101 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_7101_config_init,\n-\t.read_status = elink_7101_read_status,\n-\t.link_reset = elink_common_ext_link_reset,\n-\t.config_loopback = elink_7101_config_loopback,\n-\t.format_fw_ver = elink_7101_format_ver,\n-\t.hw_reset = elink_7101_hw_reset,\n-\t.set_link_led = elink_7101_set_link_led,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_FAN_FAILURE_DET_REQ,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_7101_config_init,\n+\t.read_status\t= (read_status_t)elink_7101_read_status,\n+\t.link_reset\t= (link_reset_t)elink_common_ext_link_reset,\n+\t.config_loopback = (config_loopback_t)elink_7101_config_loopback,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_7101_format_ver,\n+\t.hw_reset\t= (hw_reset_t)elink_7101_hw_reset,\n+\t.set_link_led\t= (set_link_led_t)elink_7101_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n-\n static const struct elink_phy phy_8073 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = 0,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_2500baseX_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_KR,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_8073_config_init,\n-\t.read_status = elink_8073_read_status,\n-\t.link_reset = elink_8073_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_format_ver,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = elink_8073_specific_func\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= 0,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_2500baseX_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_KR,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_8073_config_init,\n+\t.read_status\t= (read_status_t)elink_8073_read_status,\n+\t.link_reset\t= (link_reset_t)elink_8073_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_format_ver,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)elink_8073_specific_func\n };\n-\n static const struct elink_phy phy_8705 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_XFP_FIBER,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_8705_config_init,\n-\t.read_status = elink_8705_read_status,\n-\t.link_reset = elink_common_ext_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_null_format_ver,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_INIT_XGXS_FIRST,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_XFP_FIBER,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_8705_config_init,\n+\t.read_status\t= (read_status_t)elink_8705_read_status,\n+\t.link_reset\t= (link_reset_t)elink_common_ext_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_null_format_ver,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n-\n static const struct elink_phy phy_8706 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_8706_config_init,\n-\t.read_status = elink_8706_read_status,\n-\t.link_reset = elink_common_ext_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_format_ver,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_INIT_XGXS_FIRST,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_SFPP_10G_FIBER,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_8706_config_init,\n+\t.read_status\t= (read_status_t)elink_8706_read_status,\n+\t.link_reset\t= (link_reset_t)elink_common_ext_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_format_ver,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n \n static const struct elink_phy phy_8726 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_NOT_PRESENT,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_8726_config_init,\n-\t.read_status = elink_8726_read_status,\n-\t.link_reset = elink_8726_link_reset,\n-\t.config_loopback = elink_8726_config_loopback,\n-\t.format_fw_ver = elink_format_ver,\n-\t.hw_reset = NULL,\n-\t.set_link_led = NULL,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= (ELINK_FLAGS_INIT_XGXS_FIRST |\n+\t\t\t ELINK_FLAGS_TX_ERROR_CHECK),\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_NOT_PRESENT,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_8726_config_init,\n+\t.read_status\t= (read_status_t)elink_8726_read_status,\n+\t.link_reset\t= (link_reset_t)elink_8726_link_reset,\n+\t.config_loopback = (config_loopback_t)elink_8726_config_loopback,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_format_ver,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)NULL,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n \n static const struct elink_phy phy_8727 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_FIBRE |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_NOT_PRESENT,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_8727_config_init,\n-\t.read_status = elink_8727_read_status,\n-\t.link_reset = elink_8727_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_format_ver,\n-\t.hw_reset = elink_8727_hw_reset,\n-\t.set_link_led = elink_8727_set_link_led,\n-\t.phy_specific_func = elink_8727_specific_func\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n+\t\t\t ELINK_FLAGS_TX_ERROR_CHECK),\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_FIBRE |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_NOT_PRESENT,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_8727_config_init,\n+\t.read_status\t= (read_status_t)elink_8727_read_status,\n+\t.link_reset\t= (link_reset_t)elink_8727_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_format_ver,\n+\t.hw_reset\t= (hw_reset_t)elink_8727_hw_reset,\n+\t.set_link_led\t= (set_link_led_t)elink_8727_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)elink_8727_specific_func\n };\n-\n static const struct elink_phy phy_8481 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n-\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n-\t\t ELINK_SUPPORTED_10baseT_Full |\n-\t\t ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_8481_config_init,\n-\t.read_status = elink_848xx_read_status,\n-\t.link_reset = elink_8481_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_848xx_format_ver,\n-\t.hw_reset = elink_8481_hw_reset,\n-\t.set_link_led = elink_848xx_set_link_led,\n-\t.phy_specific_func = NULL\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n+\t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10baseT_Half |\n+\t\t\t ELINK_SUPPORTED_10baseT_Full |\n+\t\t\t ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_8481_config_init,\n+\t.read_status\t= (read_status_t)elink_848xx_read_status,\n+\t.link_reset\t= (link_reset_t)elink_8481_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_848xx_format_ver,\n+\t.hw_reset\t= (hw_reset_t)elink_8481_hw_reset,\n+\t.set_link_led\t= (set_link_led_t)elink_848xx_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)NULL\n };\n \n static const struct elink_phy phy_84823 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n-\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n-\t\t ELINK_SUPPORTED_10baseT_Full |\n-\t\t ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_848x3_config_init,\n-\t.read_status = elink_848xx_read_status,\n-\t.link_reset = elink_848x3_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_848xx_format_ver,\n-\t.hw_reset = NULL,\n-\t.set_link_led = elink_848xx_set_link_led,\n-\t.phy_specific_func = elink_848xx_specific_func\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n+\t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL |\n+\t\t\t ELINK_FLAGS_TX_ERROR_CHECK),\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10baseT_Half |\n+\t\t\t ELINK_SUPPORTED_10baseT_Full |\n+\t\t\t ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_848x3_config_init,\n+\t.read_status\t= (read_status_t)elink_848xx_read_status,\n+\t.link_reset\t= (link_reset_t)elink_848x3_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_848xx_format_ver,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)elink_848xx_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func\n };\n \n static const struct elink_phy phy_84833 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n-\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL |\n-\t\t ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_848x3_config_init,\n-\t.read_status = elink_848xx_read_status,\n-\t.link_reset = elink_848x3_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_848xx_format_ver,\n-\t.hw_reset = elink_84833_hw_reset_phy,\n-\t.set_link_led = elink_848xx_set_link_led,\n-\t.phy_specific_func = elink_848xx_specific_func\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n+\t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL |\n+\t\t\t ELINK_FLAGS_TX_ERROR_CHECK |\n+\t\t\t ELINK_FLAGS_TEMPERATURE),\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_848x3_config_init,\n+\t.read_status\t= (read_status_t)elink_848xx_read_status,\n+\t.link_reset\t= (link_reset_t)elink_848x3_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_848xx_format_ver,\n+\t.hw_reset\t= (hw_reset_t)elink_84833_hw_reset_phy,\n+\t.set_link_led\t= (set_link_led_t)elink_848xx_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func\n };\n \n static const struct elink_phy phy_84834 = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n-\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t.req_duplex = 0,\n-\t.rsrv = 0,\n-\t.config_init = elink_848x3_config_init,\n-\t.read_status = elink_848xx_read_status,\n-\t.link_reset = elink_848x3_link_reset,\n-\t.config_loopback = NULL,\n-\t.format_fw_ver = elink_848xx_format_ver,\n-\t.hw_reset = elink_84833_hw_reset_phy,\n-\t.set_link_led = elink_848xx_set_link_led,\n-\t.phy_specific_func = elink_848xx_specific_func\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n+\t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_848x3_config_init,\n+\t.read_status\t= (read_status_t)elink_848xx_read_status,\n+\t.link_reset\t= (link_reset_t)elink_848x3_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_848xx_format_ver,\n+\t.hw_reset\t= (hw_reset_t)elink_84833_hw_reset_phy,\n+\t.set_link_led\t= (set_link_led_t)elink_848xx_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func\n };\n \n-static const struct elink_phy phy_54618se = {\n-\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,\n-\t.addr = 0xff,\n-\t.def_md_devad = 0,\n-\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n-\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n-\t.mdio_ctrl = 0,\n-\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n-\t\t ELINK_SUPPORTED_10baseT_Full |\n-\t\t ELINK_SUPPORTED_100baseT_Half |\n-\t\t ELINK_SUPPORTED_100baseT_Full |\n-\t\t ELINK_SUPPORTED_1000baseT_Full |\n-\t\t ELINK_SUPPORTED_TP |\n-\t\t ELINK_SUPPORTED_Autoneg |\n-\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n-\t.media_type = ELINK_ETH_PHY_BASE_T,\n-\t.ver_addr = 0,\n-\t.req_flow_ctrl = 0,\n-\t.req_line_speed = 0,\n-\t.speed_cap_mask = 0,\n-\t/* req_duplex = */ 0,\n-\t/* rsrv = */ 0,\n-\t.config_init = elink_54618se_config_init,\n-\t.read_status = elink_54618se_read_status,\n-\t.link_reset = elink_54618se_link_reset,\n-\t.config_loopback = elink_54618se_config_loopback,\n-\t.format_fw_ver = NULL,\n-\t.hw_reset = NULL,\n-\t.set_link_led = elink_5461x_set_link_led,\n-\t.phy_specific_func = elink_54618se_specific_func\n+static const struct elink_phy phy_84858 = {\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n+\t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t.req_duplex\t= 0,\n+\t.rsrv\t\t= 0,\n+\t.config_init\t= (config_init_t)elink_848x3_config_init,\n+\t.read_status\t= (read_status_t)elink_848xx_read_status,\n+\t.link_reset\t= (link_reset_t)elink_848x3_link_reset,\n+\t.config_loopback = (config_loopback_t)NULL,\n+\t.format_fw_ver\t= (format_fw_ver_t)elink_848xx_format_ver,\n+\t.hw_reset\t= (hw_reset_t)elink_84833_hw_reset_phy,\n+\t.set_link_led\t= (set_link_led_t)elink_848xx_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func\n };\n \n+\n+static const struct elink_phy phy_54618se = {\n+\t.type\t\t= PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE,\n+\t.addr\t\t= 0xff,\n+\t.def_md_devad\t= 0,\n+\t.flags\t\t= ELINK_FLAGS_INIT_XGXS_FIRST,\n+\t.rx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.tx_preemphasis\t= {0xffff, 0xffff, 0xffff, 0xffff},\n+\t.mdio_ctrl\t= 0,\n+\t.supported\t= (ELINK_SUPPORTED_10baseT_Half |\n+\t\t\t ELINK_SUPPORTED_10baseT_Full |\n+\t\t\t ELINK_SUPPORTED_100baseT_Half |\n+\t\t\t ELINK_SUPPORTED_100baseT_Full |\n+\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t ELINK_SUPPORTED_TP |\n+\t\t\t ELINK_SUPPORTED_Autoneg |\n+\t\t\t ELINK_SUPPORTED_Pause |\n+\t\t\t ELINK_SUPPORTED_Asym_Pause),\n+\t.media_type\t= ELINK_ETH_PHY_BASE_T,\n+\t.ver_addr\t= 0,\n+\t.req_flow_ctrl\t= 0,\n+\t.req_line_speed\t= 0,\n+\t.speed_cap_mask\t= 0,\n+\t/* req_duplex = */0,\n+\t/* rsrv = */0,\n+\t.config_init\t= (config_init_t)elink_54618se_config_init,\n+\t.read_status\t= (read_status_t)elink_54618se_read_status,\n+\t.link_reset\t= (link_reset_t)elink_54618se_link_reset,\n+\t.config_loopback = (config_loopback_t)elink_54618se_config_loopback,\n+\t.format_fw_ver\t= (format_fw_ver_t)NULL,\n+\t.hw_reset\t= (hw_reset_t)NULL,\n+\t.set_link_led\t= (set_link_led_t)elink_5461x_set_link_led,\n+\t.phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func\n+};\n /*****************************************************************/\n /* */\n /* Populate the phy according. Main function: elink_populate_phy */\n@@ -11161,9 +13035,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy,\n /*****************************************************************/\n \n static void elink_populate_preemphasis(struct bnx2x_softc *sc,\n-\t\t\t\t uint32_t shmem_base,\n-\t\t\t\t struct elink_phy *phy, uint8_t port,\n-\t\t\t\t uint8_t phy_index)\n+\t\t\t\t uint32_t shmem_base,\n+\t\t\t\t struct elink_phy *phy, uint8_t port,\n+\t\t\t\t uint8_t phy_index)\n {\n \t/* Get the 4 lanes xgxs config rx and tx */\n \tuint32_t rx = 0, tx = 0, i;\n@@ -11175,23 +13049,19 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc,\n \t\tif (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {\n \t\t\trx = REG_RD(sc, shmem_base +\n \t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t xgxs_config_rx[i << 1]));\n+\t\t\tdev_info.port_hw_config[port].xgxs_config_rx[i << 1]));\n \n \t\t\ttx = REG_RD(sc, shmem_base +\n \t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t xgxs_config_tx[i << 1]));\n+\t\t\tdev_info.port_hw_config[port].xgxs_config_tx[i << 1]));\n \t\t} else {\n \t\t\trx = REG_RD(sc, shmem_base +\n \t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t xgxs_config2_rx[i << 1]));\n+\t\t\tdev_info.port_hw_config[port].xgxs_config2_rx[i << 1]));\n \n \t\t\ttx = REG_RD(sc, shmem_base +\n \t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t xgxs_config2_rx[i << 1]));\n+\t\t\tdev_info.port_hw_config[port].xgxs_config2_rx[i << 1]));\n \t\t}\n \n \t\tphy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);\n@@ -11199,65 +13069,62 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc,\n \n \t\tphy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);\n \t\tphy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);\n+\t\tELINK_DEBUG_P2(sc, \"phy->rx_preemphasis = %x, phy->tx_preemphasis = %x\",\n+\t\t\tphy->rx_preemphasis[i << 1],\n+\t\t\tphy->tx_preemphasis[i << 1]);\n \t}\n }\n \n static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,\n-\t\t\t\t\t uint32_t shmem_base, uint8_t phy_index,\n-\t\t\t\t\t uint8_t port)\n+\t\t\t\t uint32_t shmem_base,\n+\t\t\t\t uint8_t phy_index, uint8_t port)\n {\n \tuint32_t ext_phy_config = 0;\n \tswitch (phy_index) {\n \tcase ELINK_EXT_PHY1:\n \t\text_phy_config = REG_RD(sc, shmem_base +\n-\t\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t\t external_phy_config));\n+\t\t\t\t\t offsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[port].external_phy_config));\n \t\tbreak;\n \tcase ELINK_EXT_PHY2:\n \t\text_phy_config = REG_RD(sc, shmem_base +\n-\t\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t\t external_phy_config2));\n+\t\t\t\t\t offsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[port].external_phy_config2));\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid phy_index %d\", phy_index);\n+\t\tELINK_DEBUG_P1(sc, \"Invalid phy_index %d\", phy_index);\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \n \treturn ext_phy_config;\n }\n-\n static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t uint32_t shmem_base, uint8_t port,\n-\t\t\t\t\t struct elink_phy *phy)\n+\t\t\t\t uint32_t shmem_base, uint8_t port,\n+\t\t\t\t struct elink_phy *phy)\n {\n \tuint32_t phy_addr;\n-\t__rte_unused uint32_t chip_id;\n+\tuint32_t chip_id;\n \tuint32_t switch_cfg = (REG_RD(sc, shmem_base +\n-\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.\n-\t\t\t\t\t port_feature_config[port].\n-\t\t\t\t\t link_config)) &\n-\t\t\t PORT_FEATURE_CONNECTED_SWITCH_MASK);\n-\tchip_id =\n-\t (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |\n-\t ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);\n-\n-\tPMD_DRV_LOG(DEBUG, sc, \":chip_id = 0x%x\", chip_id);\n+\t\t\t\t offsetof(struct shmem_region,\n+\t\t\tdev_info.port_feature_config[port].link_config)) &\n+\t\t\t PORT_FEATURE_CONNECTED_SWITCH_MASK);\n+\tchip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |\n+\t\t((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);\n+\n+\tELINK_DEBUG_P1(sc, \":chip_id = 0x%x\", chip_id);\n \tif (USES_WARPCORE(sc)) {\n \t\tuint32_t serdes_net_if;\n-\t\tphy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);\n+\t\tphy_addr = REG_RD(sc,\n+\t\t\t\t MISC_REG_WC0_CTRL_PHY_ADDR);\n \t\t*phy = phy_warpcore;\n \t\tif (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)\n \t\t\tphy->flags |= ELINK_FLAGS_4_PORT_MODE;\n \t\telse\n \t\t\tphy->flags &= ~ELINK_FLAGS_4_PORT_MODE;\n-\t\t/* Check Dual mode */\n+\t\t\t/* Check Dual mode */\n \t\tserdes_net_if = (REG_RD(sc, shmem_base +\n-\t\t\t\t\toffsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t\t\t default_cfg)) &\n+\t\t\t\t\toffsetof(struct shmem_region, dev_info.\n+\t\t\t\t\tport_hw_config[port].default_cfg)) &\n \t\t\t\t PORT_HW_CFG_NET_SERDES_IF_MASK);\n \t\t/* Set the appropriate supported and flags indications per\n \t\t * interface type of the chip\n@@ -11293,8 +13160,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n \t\t\tbreak;\n \t\tcase PORT_HW_CFG_NET_SERDES_IF_KR:\n \t\t\tphy->media_type = ELINK_ETH_PHY_KR;\n-\t\t\tphy->supported &= (ELINK_SUPPORTED_1000baseT_Full |\n-\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n+\t\t\tphy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |\n+\t\t\t\t\t ELINK_SUPPORTED_10000baseKR_Full |\n \t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n \t\t\t\t\t ELINK_SUPPORTED_Autoneg |\n \t\t\t\t\t ELINK_SUPPORTED_Pause |\n@@ -11312,8 +13179,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n \t\t\tphy->media_type = ELINK_ETH_PHY_KR;\n \t\t\tphy->flags |= ELINK_FLAGS_WC_DUAL_MODE;\n \t\t\tphy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |\n-\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n-\t\t\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n+\t\t\t\t\t ELINK_SUPPORTED_10000baseKR_Full |\n+\t\t\t\t\t ELINK_SUPPORTED_1000baseKX_Full |\n \t\t\t\t\t ELINK_SUPPORTED_Autoneg |\n \t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n \t\t\t\t\t ELINK_SUPPORTED_Pause |\n@@ -11321,8 +13188,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n \t\t\tphy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Unknown WC interface type 0x%x\",\n-\t\t\t\t serdes_net_if);\n+\t\t\tELINK_DEBUG_P1(sc, \"Unknown WC interface type 0x%x\",\n+\t\t\t\t serdes_net_if);\n \t\t\tbreak;\n \t\t}\n \n@@ -11334,6 +13201,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n \t\t\tphy->flags |= ELINK_FLAGS_MDC_MDIO_WA;\n \t\telse\n \t\t\tphy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;\n+\t\tELINK_DEBUG_P3(sc, \"media_type = %x, flags = %x, supported = %x\",\n+\t\t\t\tphy->media_type, phy->flags, phy->supported);\n \t} else {\n \t\tswitch (switch_cfg) {\n \t\tcase ELINK_SWITCH_CFG_1G:\n@@ -11349,32 +13218,32 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n \t\t\t*phy = phy_xgxs;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Invalid switch_cfg\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Invalid switch_cfg\");\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \t}\n-\tphy->addr = (uint8_t) phy_addr;\n+\tphy->addr = (uint8_t)phy_addr;\n \tphy->mdio_ctrl = elink_get_emac_base(sc,\n-\t\t\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,\n-\t\t\t\t\t port);\n+\t\t\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,\n+\t\t\t\t\t port);\n \tif (CHIP_IS_E2(sc))\n \t\tphy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;\n \telse\n \t\tphy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\",\n-\t\t port, phy->addr, phy->mdio_ctrl);\n+\tELINK_DEBUG_P3(sc, \"Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\",\n+\t\t port, phy->addr, phy->mdio_ctrl);\n \n \telink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);\n \treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t uint8_t phy_index,\n-\t\t\t\t\t uint32_t shmem_base,\n-\t\t\t\t\t uint32_t shmem2_base,\n-\t\t\t\t\t uint8_t port,\n-\t\t\t\t\t struct elink_phy *phy)\n+\t\t\t\t uint8_t phy_index,\n+\t\t\t\t uint32_t shmem_base,\n+\t\t\t\t uint32_t shmem2_base,\n+\t\t\t\t uint8_t port,\n+\t\t\t\t struct elink_phy *phy)\n {\n \tuint32_t ext_phy_config, phy_type, config2;\n \tuint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;\n@@ -11420,10 +13289,13 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:\n \t\t*phy = phy_84834;\n \t\tbreak;\n+\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858:\n+\t\t*phy = phy_84858;\n+\t\tbreak;\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:\n-\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:\n+\tcase PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE:\n \t\t*phy = phy_54618se;\n-\t\tif (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)\n+\t\tif (phy_type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)\n \t\t\tphy->flags |= ELINK_FLAGS_EEE;\n \t\tbreak;\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:\n@@ -11449,21 +13321,20 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,\n \t * the address\n \t */\n \tconfig2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.shared_hw_config.\n-\t\t\t\t\t\t config2));\n+\t\t\t\t\tdev_info.shared_hw_config.config2));\n \tif (phy_index == ELINK_EXT_PHY1) {\n \t\tphy->ver_addr = shmem_base + offsetof(struct shmem_region,\n-\t\t\t\t\t\t port_mb[port].\n-\t\t\t\t\t\t ext_phy_fw_version);\n+\t\t\t\tport_mb[port].ext_phy_fw_version);\n \n \t\t/* Check specific mdc mdio settings */\n \t\tif (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)\n \t\t\tmdc_mdio_access = config2 &\n-\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;\n+\t\t\tSHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;\n \t} else {\n \t\tuint32_t size = REG_RD(sc, shmem2_base);\n \n-\t\tif (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {\n+\t\tif (size >\n+\t\t offsetof(struct shmem2_region, ext_phy_fw_version2)) {\n \t\t\tphy->ver_addr = shmem2_base +\n \t\t\t offsetof(struct shmem2_region,\n \t\t\t\t ext_phy_fw_version2[port]);\n@@ -11471,35 +13342,34 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,\n \t\t/* Check specific mdc mdio settings */\n \t\tif (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)\n \t\t\tmdc_mdio_access = (config2 &\n-\t\t\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)\n-\t\t\t >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -\n-\t\t\t\tSHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);\n+\t\t\tSHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>\n+\t\t\t(SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -\n+\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);\n \t}\n \tphy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);\n \n-\tif (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n-\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&\n-\t (phy->ver_addr)) {\n+\tif (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {\n \t\t/* Remove 100Mb link supported for BNX2X84833/4 when phy fw\n \t\t * version lower than or equal to 1.39\n \t\t */\n \t\tuint32_t raw_ver = REG_RD(sc, phy->ver_addr);\n-\t\tif (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))\n+\t\tif (((raw_ver & 0x7F) <= 39) &&\n+\t\t (((raw_ver & 0xF80) >> 7) <= 1))\n \t\t\tphy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |\n \t\t\t\t\t ELINK_SUPPORTED_100baseT_Full);\n \t}\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"phy_type 0x%x port %d found in index %d\",\n-\t\t phy_type, port, phy_index);\n-\tPMD_DRV_LOG(DEBUG, sc, \" addr=0x%x, mdio_ctl=0x%x\",\n-\t\t phy->addr, phy->mdio_ctrl);\n+\tELINK_DEBUG_P3(sc, \"phy_type 0x%x port %d found in index %d\",\n+\t\t phy_type, port, phy_index);\n+\tELINK_DEBUG_P2(sc, \" addr=0x%x, mdio_ctl=0x%x\",\n+\t\t phy->addr, phy->mdio_ctrl);\n \treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t uint8_t phy_index, uint32_t shmem_base,\n-\t\t\t\t\t uint32_t shmem2_base, uint8_t port,\n-\t\t\t\t\t struct elink_phy *phy)\n+\t\t\t uint8_t phy_index, uint32_t shmem_base,\n+\t\t\t uint32_t shmem2_base, uint8_t port,\n+\t\t\t struct elink_phy *phy)\n {\n \telink_status_t status = ELINK_STATUS_OK;\n \tphy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;\n@@ -11511,50 +13381,42 @@ static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,\n }\n \n static void elink_phy_def_cfg(struct elink_params *params,\n-\t\t\t struct elink_phy *phy, uint8_t phy_index)\n+\t\t\t struct elink_phy *phy,\n+\t\t\t uint8_t phy_index)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t link_config;\n \t/* Populate the default phy configuration for MF mode */\n \tif (phy_index == ELINK_EXT_PHY2) {\n \t\tlink_config = REG_RD(sc, params->shmem_base +\n-\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_feature_config\n-\t\t\t\t\t [params->port].link_config2));\n-\t\tphy->speed_cap_mask =\n-\t\t REG_RD(sc,\n-\t\t\t params->shmem_base + offsetof(struct shmem_region,\n-\t\t\t\t\t\t\t dev_info.port_hw_config\n-\t\t\t\t\t\t\t [params->port].\n-\t\t\t\t\t\t\t speed_capability_mask2));\n+\t\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\tport_feature_config[params->port].link_config2));\n+\t\tphy->speed_cap_mask = REG_RD(sc, params->shmem_base +\n+\t\t\t\t\t offsetof(struct shmem_region,\n+\t\t\t\t\t\t dev_info.\n+\t\t\tport_hw_config[params->port].speed_capability_mask2));\n \t} else {\n \t\tlink_config = REG_RD(sc, params->shmem_base +\n-\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t dev_info.port_feature_config\n-\t\t\t\t\t [params->port].link_config));\n-\t\tphy->speed_cap_mask =\n-\t\t REG_RD(sc,\n-\t\t\t params->shmem_base + offsetof(struct shmem_region,\n-\t\t\t\t\t\t\t dev_info.port_hw_config\n-\t\t\t\t\t\t\t [params->port].\n-\t\t\t\t\t\t\t speed_capability_mask));\n+\t\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\tport_feature_config[params->port].link_config));\n+\t\tphy->speed_cap_mask = REG_RD(sc, params->shmem_base +\n+\t\t\t\t\t offsetof(struct shmem_region,\n+\t\t\t\t\t\t dev_info.\n+\t\t\tport_hw_config[params->port].speed_capability_mask));\n \t}\n-\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\",\n-\t\t phy_index, link_config, phy->speed_cap_mask);\n+\tELINK_DEBUG_P3(sc,\n+\t \"Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\",\n+\t phy_index, link_config, phy->speed_cap_mask);\n \n \tphy->req_duplex = DUPLEX_FULL;\n-\tswitch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {\n+\tswitch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {\n \tcase PORT_FEATURE_LINK_SPEED_10M_HALF:\n \t\tphy->req_duplex = DUPLEX_HALF;\n-\t\t/* fall-through */\n \tcase PORT_FEATURE_LINK_SPEED_10M_FULL:\n \t\tphy->req_line_speed = ELINK_SPEED_10;\n \t\tbreak;\n \tcase PORT_FEATURE_LINK_SPEED_100M_HALF:\n \t\tphy->req_duplex = DUPLEX_HALF;\n-\t\t/* fall-through */\n \tcase PORT_FEATURE_LINK_SPEED_100M_FULL:\n \t\tphy->req_line_speed = ELINK_SPEED_100;\n \t\tbreak;\n@@ -11572,7 +13434,10 @@ static void elink_phy_def_cfg(struct elink_params *params,\n \t\tbreak;\n \t}\n \n-\tswitch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {\n+\tELINK_DEBUG_P2(sc, \"Default config phy idx %x, req_duplex config %x\",\n+\t\t\tphy_index, phy->req_duplex);\n+\n+\tswitch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {\n \tcase PORT_FEATURE_FLOW_CONTROL_AUTO:\n \t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;\n \t\tbreak;\n@@ -11589,6 +13454,9 @@ static void elink_phy_def_cfg(struct elink_params *params,\n \t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;\n \t\tbreak;\n \t}\n+\tELINK_DEBUG_P3(sc, \"Requested Duplex = %x, line_speed = %x, flow_ctrl = %x\",\n+\t\t phy->req_duplex, phy->req_line_speed,\n+\t\t phy->req_flow_ctrl);\n }\n \n uint32_t elink_phy_selection(struct elink_params *params)\n@@ -11597,25 +13465,24 @@ uint32_t elink_phy_selection(struct elink_params *params)\n \tuint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;\n \n \tphy_config_swapped = params->multi_phy_config &\n-\t PORT_HW_CFG_PHY_SWAPPED_ENABLED;\n+\t\tPORT_HW_CFG_PHY_SWAPPED_ENABLED;\n \n-\tprio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;\n+\tprio_cfg = params->multi_phy_config &\n+\t\t\tPORT_HW_CFG_PHY_SELECTION_MASK;\n \n \tif (phy_config_swapped) {\n \t\tswitch (prio_cfg) {\n \t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:\n-\t\t\treturn_cfg =\n-\t\t\t PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;\n+\t\t return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;\n \t\t\tbreak;\n \t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:\n-\t\t\treturn_cfg =\n-\t\t\t PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;\n+\t\t return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;\n \t\t\tbreak;\n \t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:\n-\t\t\treturn_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;\n+\t\t return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;\n \t\t\tbreak;\n \t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:\n-\t\t\treturn_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;\n+\t\t return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;\n \t\t\tbreak;\n \t\t}\n \t} else\n@@ -11624,19 +13491,23 @@ uint32_t elink_phy_selection(struct elink_params *params)\n \treturn return_cfg;\n }\n \n-elink_status_t elink_phy_probe(struct elink_params * params)\n+elink_status_t elink_phy_probe(struct elink_params *params)\n {\n \tuint8_t phy_index, actual_phy_idx;\n \tuint32_t phy_config_swapped, sync_offset, media_types;\n \tstruct bnx2x_softc *sc = params->sc;\n \tstruct elink_phy *phy;\n \tparams->num_phys = 0;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Begin phy probe\");\n-\n+\tELINK_DEBUG_P0(sc, \"Begin phy probe\");\n+#ifdef ELINK_INCLUDE_EMUL\n+\tif (CHIP_REV_IS_EMUL(sc))\n+\t\treturn ELINK_STATUS_OK;\n+#endif\n \tphy_config_swapped = params->multi_phy_config &\n-\t PORT_HW_CFG_PHY_SWAPPED_ENABLED;\n+\t\tPORT_HW_CFG_PHY_SWAPPED_ENABLED;\n \n-\tfor (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {\n+\tfor (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;\n+\t phy_index++) {\n \t\tactual_phy_idx = phy_index;\n \t\tif (phy_config_swapped) {\n \t\t\tif (phy_index == ELINK_EXT_PHY1)\n@@ -11644,18 +13515,19 @@ elink_status_t elink_phy_probe(struct elink_params * params)\n \t\t\telse if (phy_index == ELINK_EXT_PHY2)\n \t\t\t\tactual_phy_idx = ELINK_EXT_PHY1;\n \t\t}\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"phy_config_swapped %x, phy_index %x,\"\n-\t\t\t \" actual_phy_idx %x\", phy_config_swapped,\n-\t\t\t phy_index, actual_phy_idx);\n+\t\tELINK_DEBUG_P3(sc, \"phy_config_swapped %x, phy_index %x,\"\n+\t\t\t \" actual_phy_idx %x\", phy_config_swapped,\n+\t\t\t phy_index, actual_phy_idx);\n \t\tphy = ¶ms->phy[actual_phy_idx];\n \t\tif (elink_populate_phy(sc, phy_index, params->shmem_base,\n \t\t\t\t params->shmem2_base, params->port,\n \t\t\t\t phy) != ELINK_STATUS_OK) {\n \t\t\tparams->num_phys = 0;\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"phy probe failed in phy index %d\",\n-\t\t\t\t phy_index);\n+\t\t\tELINK_DEBUG_P1(sc, \"phy probe failed in phy index %d\",\n+\t\t\t\t phy_index);\n \t\t\tfor (phy_index = ELINK_INT_PHY;\n-\t\t\t phy_index < ELINK_MAX_PHYS; phy_index++)\n+\t\t\t phy_index < ELINK_MAX_PHYS;\n+\t\t\t phy_index++)\n \t\t\t\t*phy = phy_null;\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n@@ -11671,8 +13543,8 @@ elink_status_t elink_phy_probe(struct elink_params * params)\n \t\t\tphy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;\n \n \t\tsync_offset = params->shmem_base +\n-\t\t offsetof(struct shmem_region,\n-\t\t\t dev_info.port_hw_config[params->port].media_type);\n+\t\t\toffsetof(struct shmem_region,\n+\t\t\tdev_info.port_hw_config[params->port].media_type);\n \t\tmedia_types = REG_RD(sc, sync_offset);\n \n \t\t/* Update media type for non-PMF sync only for the first time\n@@ -11683,9 +13555,9 @@ elink_status_t elink_phy_probe(struct elink_params * params)\n \t\t\t\t (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n \t\t\t\t actual_phy_idx))) == 0) {\n \t\t\tmedia_types |= ((phy->media_type &\n-\t\t\t\t\t PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<\n-\t\t\t\t\t(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n-\t\t\t\t\t actual_phy_idx));\n+\t\t\t\t\tPORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<\n+\t\t\t\t(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n+\t\t\t\t actual_phy_idx));\n \t\t}\n \t\tREG_WR(sc, sync_offset, media_types);\n \n@@ -11693,48 +13565,231 @@ elink_status_t elink_phy_probe(struct elink_params * params)\n \t\tparams->num_phys++;\n \t}\n \n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"End phy probe. #phys found %x\", params->num_phys);\n+\tELINK_DEBUG_P1(sc, \"End phy probe. #phys found %x\", params->num_phys);\n \treturn ELINK_STATUS_OK;\n }\n \n-static void elink_init_bmac_loopback(struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars)\n+#ifdef ELINK_INCLUDE_EMUL\n+static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,\n+\t\t\t\t\t struct elink_vars *vars)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tvars->line_speed = params->req_line_speed[0];\n+\t/* In case link speed is auto, set speed the highest as possible */\n+\tif (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {\n+\t\tif (params->feature_config_flags &\n+\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)\n+\t\t\tvars->line_speed = ELINK_SPEED_2500;\n+\t\telse if (elink_is_4_port_mode(sc))\n+\t\t\tvars->line_speed = ELINK_SPEED_10000;\n+\t\telse\n+\t\t\tvars->line_speed = ELINK_SPEED_20000;\n+\t}\n+\tif (vars->line_speed < ELINK_SPEED_10000) {\n+\t\tif ((params->feature_config_flags &\n+\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid line speed %d while UMAC is\"\n+\t\t\t\t \" disabled!\", params->req_line_speed[0]);\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t}\n+\t\tswitch (vars->line_speed) {\n+\t\tcase ELINK_SPEED_10:\n+\t\t\tvars->link_status = ELINK_LINK_10TFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_100:\n+\t\t\tvars->link_status = ELINK_LINK_100TXFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_1000:\n+\t\t\tvars->link_status = ELINK_LINK_1000TFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_2500:\n+\t\t\tvars->link_status = ELINK_LINK_2500TFD;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid line speed %d for UMAC\",\n+\t\t\t\t vars->line_speed);\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t}\n+\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n+\n+\t\tif (params->loopback_mode == ELINK_LOOPBACK_UMAC)\n+\t\t\telink_umac_enable(params, vars, 1);\n+\t\telse\n+\t\t\telink_umac_enable(params, vars, 0);\n+\t} else {\n+\t\t/* Link speed >= 10000 requires XMAC enabled */\n+\t\tif (params->feature_config_flags &\n+\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid line speed %d while XMAC is\"\n+\t\t\t\t \" disabled!\", params->req_line_speed[0]);\n+\t\treturn ELINK_STATUS_ERROR;\n+\t}\n+\t\t/* Check link speed */\n+\t\tswitch (vars->line_speed) {\n+\t\tcase ELINK_SPEED_10000:\n+\t\t\tvars->link_status = ELINK_LINK_10GTFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_20000:\n+\t\t\tvars->link_status = ELINK_LINK_20GTFD;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid line speed %d for XMAC\",\n+\t\t\t\t vars->line_speed);\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t}\n+\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n+\t\tif (params->loopback_mode == ELINK_LOOPBACK_XMAC)\n+\t\t\telink_xmac_enable(params, vars, 1);\n+\t\telse\n+\t\t\telink_xmac_enable(params, vars, 0);\n+\t}\n+\t\treturn ELINK_STATUS_OK;\n+}\n+\n+static elink_status_t elink_init_emul(struct elink_params *params,\n+\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n+\tif (CHIP_IS_E3(sc)) {\n+\t\tif (elink_init_e3_emul_mac(params, vars) !=\n+\t\t ELINK_STATUS_OK)\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t} else {\n+\t\tif (params->feature_config_flags &\n+\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {\n+\t\t\tvars->line_speed = ELINK_SPEED_1000;\n+\t\t\tvars->link_status = (LINK_STATUS_LINK_UP |\n+\t\t\t\t\t ELINK_LINK_1000XFD);\n+\t\t\tif (params->loopback_mode ==\n+\t\t\t ELINK_LOOPBACK_EMAC)\n+\t\t\t\telink_emac_enable(params, vars, 1);\n+\t\t\telse\n+\t\t\t\telink_emac_enable(params, vars, 0);\n+\t\t} else {\n+\t\t\tvars->line_speed = ELINK_SPEED_10000;\n+\t\t\tvars->link_status = (LINK_STATUS_LINK_UP |\n+\t\t\t\t\t ELINK_LINK_10GTFD);\n+\t\t\tif (params->loopback_mode ==\n+\t\t\t ELINK_LOOPBACK_BMAC)\n+\t\t\t\telink_bmac_enable(params, vars, 1, 1);\n+\t\t\telse\n+\t\t\t\telink_bmac_enable(params, vars, 0, 1);\n+\t\t}\n+\t}\n \tvars->link_up = 1;\n-\tvars->line_speed = ELINK_SPEED_10000;\n \tvars->duplex = DUPLEX_FULL;\n \tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n-\tvars->mac_type = ELINK_MAC_TYPE_BMAC;\n-\n-\tvars->phy_flags = PHY_XGXS_FLAG;\n \n-\telink_xgxs_deassert(params);\n+\t\tif (CHIP_IS_E1x(sc))\n+\t\t\telink_pbf_update(params, vars->flow_ctrl,\n+\t\t\t\t\t vars->line_speed);\n+\t\t/* Disable drain */\n+\t\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n \n-\t/* Set bmac loopback */\n-\telink_bmac_enable(params, vars, 1, 1);\n+\t\t/* update shared memory */\n+\t\telink_update_mng(params, vars->link_status);\n+\treturn ELINK_STATUS_OK;\n+}\n+#endif\n+#ifdef ELINK_INCLUDE_FPGA\n+static elink_status_t elink_init_fpga(struct elink_params *params,\n+\t\t\t struct elink_vars *vars)\n+{\n+\t/* Enable on E1.5 FPGA */\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tvars->duplex = DUPLEX_FULL;\n+\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n+\tif (!(CHIP_IS_E1(sc))) {\n+\t\tvars->flow_ctrl = (ELINK_FLOW_CTRL_TX |\n+\t\t\t\t ELINK_FLOW_CTRL_RX);\n+\t\tvars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |\n+\t\t\t\t LINK_STATUS_RX_FLOW_CONTROL_ENABLED);\n+\t}\n+\tif (CHIP_IS_E3(sc)) {\n+\t\tvars->line_speed = params->req_line_speed[0];\n+\t\tswitch (vars->line_speed) {\n+\t\tcase ELINK_SPEED_AUTO_NEG:\n+\t\t\tvars->line_speed = ELINK_SPEED_2500;\n+\t\tcase ELINK_SPEED_2500:\n+\t\t\tvars->link_status = ELINK_LINK_2500TFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_1000:\n+\t\t\tvars->link_status = ELINK_LINK_1000XFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_100:\n+\t\t\tvars->link_status = ELINK_LINK_100TXFD;\n+\t\t\tbreak;\n+\t\tcase ELINK_SPEED_10:\n+\t\t\tvars->link_status = ELINK_LINK_10TFD;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tELINK_DEBUG_P1(sc, \"Invalid link speed %d\",\n+\t\t\t\t params->req_line_speed[0]);\n+\t\t\treturn ELINK_STATUS_ERROR;\n+\t\t}\n+\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n+\t\tif (params->loopback_mode == ELINK_LOOPBACK_UMAC)\n+\t\t\telink_umac_enable(params, vars, 1);\n+\t\telse\n+\t\t\telink_umac_enable(params, vars, 0);\n+\t} else {\n+\t\tvars->line_speed = ELINK_SPEED_10000;\n+\t\tvars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);\n+\t\tif (params->loopback_mode == ELINK_LOOPBACK_EMAC)\n+\t\t\telink_emac_enable(params, vars, 1);\n+\t\telse\n+\t\t\telink_emac_enable(params, vars, 0);\n+\t}\n+\tvars->link_up = 1;\n \n+\tif (CHIP_IS_E1x(sc))\n+\t\telink_pbf_update(params, vars->flow_ctrl,\n+\t\t\t\t vars->line_speed);\n+\t/* Disable drain */\n \tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n+\n+\t/* Update shared memory */\n+\telink_update_mng(params, vars->link_status);\n+\t\treturn ELINK_STATUS_OK;\n+}\n+#endif\n+static void elink_init_bmac_loopback(struct elink_params *params,\n+\t\t\t\t struct elink_vars *vars)\n+{\n+\tstruct bnx2x_softc *sc = params->sc;\n+\t\tvars->link_up = 1;\n+\t\tvars->line_speed = ELINK_SPEED_10000;\n+\t\tvars->duplex = DUPLEX_FULL;\n+\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n+\t\tvars->mac_type = ELINK_MAC_TYPE_BMAC;\n+\n+\t\tvars->phy_flags = PHY_XGXS_FLAG;\n+\n+\t\telink_xgxs_deassert(params);\n+\n+\t\t/* Set bmac loopback */\n+\t\telink_bmac_enable(params, vars, 1, 1);\n+\n+\t\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n }\n \n static void elink_init_emac_loopback(struct elink_params *params,\n \t\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n-\tvars->link_up = 1;\n-\tvars->line_speed = ELINK_SPEED_1000;\n-\tvars->duplex = DUPLEX_FULL;\n-\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n-\tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n+\t\tvars->link_up = 1;\n+\t\tvars->line_speed = ELINK_SPEED_1000;\n+\t\tvars->duplex = DUPLEX_FULL;\n+\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n+\t\tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n \n-\tvars->phy_flags = PHY_XGXS_FLAG;\n+\t\tvars->phy_flags = PHY_XGXS_FLAG;\n \n-\telink_xgxs_deassert(params);\n-\t/* Set bmac loopback */\n-\telink_emac_enable(params, vars, 1);\n-\telink_emac_program(params, vars);\n-\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n+\t\telink_xgxs_deassert(params);\n+\t\t/* Set bmac loopback */\n+\t\telink_emac_enable(params, vars, 1);\n+\t\telink_emac_program(params, vars);\n+\t\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n }\n \n static void elink_init_xmac_loopback(struct elink_params *params,\n@@ -11755,8 +13810,9 @@ static void elink_init_xmac_loopback(struct elink_params *params,\n \t */\n \telink_set_aer_mmd(params, ¶ms->phy[0]);\n \telink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);\n-\tparams->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],\n-\t\t\t\t\t\t params);\n+\tparams->phy[ELINK_INT_PHY].config_loopback(\n+\t\t\t¶ms->phy[ELINK_INT_PHY],\n+\t\t\tparams);\n \n \telink_xmac_enable(params, vars, 1);\n \tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n@@ -11818,12 +13874,11 @@ static void elink_init_xgxs_loopback(struct elink_params *params,\n \t\t/* Set external phy loopback */\n \t\tuint8_t phy_index;\n \t\tfor (phy_index = ELINK_EXT_PHY1;\n-\t\t phy_index < params->num_phys; phy_index++)\n+\t\t phy_index < params->num_phys; phy_index++)\n \t\t\tif (params->phy[phy_index].config_loopback)\n-\t\t\t\tparams->phy[phy_index].config_loopback(¶ms->\n-\t\t\t\t\t\t\t\t phy\n-\t\t\t\t\t\t\t\t [phy_index],\n-\t\t\t\t\t\t\t\t params);\n+\t\t\t\tparams->phy[phy_index].config_loopback(\n+\t\t\t\t\t¶ms->phy[phy_index],\n+\t\t\t\t\tparams);\n \t}\n \tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n \n@@ -11840,12 +13895,14 @@ void elink_set_rx_filter(struct elink_params *params, uint8_t en)\n \t\tval |= en * 0x20;\n \tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);\n \n-\tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);\n+\tif (!CHIP_IS_E1(sc)) {\n+\t\tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4,\n+\t\t en * 0x3);\n+\t}\n \n \tREG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :\n \t\t NIG_REG_LLH0_BRB1_NOT_MCP), en);\n }\n-\n static elink_status_t elink_avoid_link_flap(struct elink_params *params,\n \t\t\t\t\t struct elink_vars *vars)\n {\n@@ -11853,6 +13910,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,\n \tuint32_t dont_clear_stat, lfa_sts;\n \tstruct bnx2x_softc *sc = params->sc;\n \n+\telink_set_mdio_emac_per_phy(sc, params);\n \t/* Sync the link parameters */\n \telink_link_status_update(params, vars);\n \n@@ -11864,7 +13922,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,\n \tfor (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {\n \t\tstruct elink_phy *phy = ¶ms->phy[phy_idx];\n \t\tif (phy->phy_specific_func) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Calling PHY specific func\");\n+\t\t\tELINK_DEBUG_P0(sc, \"Calling PHY specific func\");\n \t\t\tphy->phy_specific_func(phy, params, ELINK_PHY_INIT);\n \t\t}\n \t\tif ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||\n@@ -11873,7 +13931,8 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,\n \t\t\telink_verify_sfp_module(phy, params);\n \t}\n \tlfa_sts = REG_RD(sc, params->lfa_base +\n-\t\t\t offsetof(struct shmem_lfa, lfa_sts));\n+\t\t\t offsetof(struct shmem_lfa,\n+\t\t\t\t lfa_sts));\n \n \tdont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;\n \n@@ -11984,13 +14043,12 @@ elink_status_t elink_phy_init(struct elink_params *params,\n {\n \tint lfa_status;\n \tstruct bnx2x_softc *sc = params->sc;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Phy Initialization started\");\n-\tPMD_DRV_LOG(DEBUG, sc, \"(1) req_speed %d, req_flowctrl %d\",\n-\t\t params->req_line_speed[0], params->req_flow_ctrl[0]);\n-\tPMD_DRV_LOG(DEBUG, sc, \"(2) req_speed %d, req_flowctrl %d\",\n-\t\t params->req_line_speed[1], params->req_flow_ctrl[1]);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"req_adv_flow_ctrl 0x%x\", params->req_fc_auto_adv);\n+\tELINK_DEBUG_P0(sc, \"Phy Initialization started\");\n+\tELINK_DEBUG_P2(sc, \"(1) req_speed %d, req_flowctrl %d\",\n+\t\t params->req_line_speed[0], params->req_flow_ctrl[0]);\n+\tELINK_DEBUG_P2(sc, \"(2) req_speed %d, req_flowctrl %d\",\n+\t\t params->req_line_speed[1], params->req_flow_ctrl[1]);\n+\tELINK_DEBUG_P1(sc, \"req_adv_flow_ctrl 0x%x\", params->req_fc_auto_adv);\n \tvars->link_status = 0;\n \tvars->phy_link_up = 0;\n \tvars->link_up = 0;\n@@ -12003,17 +14061,33 @@ elink_status_t elink_phy_init(struct elink_params *params,\n \tparams->link_flags = ELINK_PHY_INITIALIZED;\n \t/* Driver opens NIG-BRB filters */\n \telink_set_rx_filter(params, 1);\n+\telink_chng_link_count(params, 1);\n \t/* Check if link flap can be avoided */\n \tlfa_status = elink_check_lfa(params);\n \n+\tELINK_DEBUG_P3(sc, \" params : port = %x, loopback_mode = %x req_duplex = %x\",\n+\t\t params->port, params->loopback_mode,\n+\t\t params->req_duplex[0]);\n+\tELINK_DEBUG_P3(sc, \" params : switch_cfg = %x, lane_config = %x req_duplex[1] = %x\",\n+\t\t params->switch_cfg, params->lane_config,\n+\t\t params->req_duplex[1]);\n+\tELINK_DEBUG_P3(sc, \" params : chip_id = %x, feature_config_flags = %x, num_phys = %x\",\n+\t\t params->chip_id, params->feature_config_flags,\n+\t\t params->num_phys);\n+\tELINK_DEBUG_P3(sc, \" params : rsrv = %x, eee_mode = %x, hw_led_mode = %x\",\n+\t\t params->rsrv, params->eee_mode, params->hw_led_mode);\n+\tELINK_DEBUG_P3(sc, \" params : multi_phy = %x, req_fc_auto_adv = %x, link_flags = %x\",\n+\t\t params->multi_phy_config, params->req_fc_auto_adv,\n+\t\t params->link_flags);\n+\tELINK_DEBUG_P2(sc, \" params : lfa_base = %x, link_attr = %x\",\n+\t\t params->lfa_base, params->link_attr_sync);\n \tif (lfa_status == 0) {\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"Link Flap Avoidance in progress\");\n+\t\tELINK_DEBUG_P0(sc, \"Link Flap Avoidance in progress\");\n \t\treturn elink_avoid_link_flap(params, vars);\n \t}\n \n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"Cannot avoid link flap lfa_sta=0x%x\", lfa_status);\n+\tELINK_DEBUG_P1(sc, \"Cannot avoid link flap lfa_sta=0x%x\",\n+\t\t lfa_status);\n \telink_cannot_avoid_link_flap(params, vars, lfa_status);\n \n \t/* Disable attentions */\n@@ -12022,20 +14096,34 @@ elink_status_t elink_phy_init(struct elink_params *params,\n \t\t\tELINK_NIG_MASK_XGXS0_LINK10G |\n \t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n \t\t\tELINK_NIG_MASK_MI_INT));\n+#ifdef ELINK_INCLUDE_EMUL\n+\tif (!(params->feature_config_flags &\n+\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))\n+#endif\n \n-\telink_emac_init(params);\n+\telink_emac_init(params, vars);\n \n \tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n \t\tvars->link_status |= LINK_STATUS_PFC_ENABLED;\n \n-\tif ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"No phy found for initialization !!\");\n+\tif ((params->num_phys == 0) &&\n+\t !CHIP_REV_IS_SLOW(sc)) {\n+\t\tELINK_DEBUG_P0(sc, \"No phy found for initialization !!\");\n \t\treturn ELINK_STATUS_ERROR;\n \t}\n \tset_phy_vars(params, vars);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Num of phys on board: %d\", params->num_phys);\n-\n+\tELINK_DEBUG_P1(sc, \"Num of phys on board: %d\", params->num_phys);\n+#ifdef ELINK_INCLUDE_FPGA\n+\tif (CHIP_REV_IS_FPGA(sc)) {\n+\t\treturn elink_init_fpga(params, vars);\n+\t} else\n+#endif\n+#ifdef ELINK_INCLUDE_EMUL\n+\tif (CHIP_REV_IS_EMUL(sc)) {\n+\t\treturn elink_init_emul(params, vars);\n+\t} else\n+#endif\n \tswitch (params->loopback_mode) {\n \tcase ELINK_LOOPBACK_BMAC:\n \t\telink_init_bmac_loopback(params, vars);\n@@ -12071,15 +14159,16 @@ elink_status_t elink_phy_init(struct elink_params *params,\n \treturn ELINK_STATUS_OK;\n }\n \n-static elink_status_t elink_link_reset(struct elink_params *params,\n-\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t uint8_t reset_ext_phy)\n+elink_status_t elink_link_reset(struct elink_params *params,\n+\t\t struct elink_vars *vars,\n+\t\t uint8_t reset_ext_phy)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint8_t phy_index, port = params->port, clear_latch_ind = 0;\n-\tPMD_DRV_LOG(DEBUG, sc, \"Resetting the link of port %d\", port);\n+\tELINK_DEBUG_P1(sc, \"Resetting the link of port %d\", port);\n \t/* Disable attentions */\n \tvars->link_status = 0;\n+\telink_chng_link_count(params, 1);\n \telink_update_mng(params, vars->link_status);\n \tvars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |\n \t\t\t SHMEM_EEE_ACTIVE_BIT);\n@@ -12098,12 +14187,24 @@ static elink_status_t elink_link_reset(struct elink_params *params,\n \t\tREG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);\n \t\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);\n \t}\n-\tif (!CHIP_IS_E3(sc))\n-\t\telink_set_bmac_rx(sc, port, 0);\n-\tif (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {\n-\t\telink_set_xmac_rxtx(params, 0);\n-\t\telink_set_umac_rxtx(params, 0);\n-\t}\n+\n+#ifdef ELINK_INCLUDE_EMUL\n+\t/* Stop BigMac rx */\n+\tif (!(params->feature_config_flags &\n+\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))\n+#endif\n+\t\tif (!CHIP_IS_E3(sc))\n+\t\t\telink_set_bmac_rx(sc, params->chip_id, port, 0);\n+#ifdef ELINK_INCLUDE_EMUL\n+\t/* Stop XMAC/UMAC rx */\n+\tif (!(params->feature_config_flags &\n+\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))\n+#endif\n+\t\tif (CHIP_IS_E3(sc) &&\n+\t\t!CHIP_REV_IS_FPGA(sc)) {\n+\t\t\telink_set_xmac_rxtx(params, 0);\n+\t\t\telink_set_umac_rxtx(params, 0);\n+\t\t}\n \t/* Disable emac */\n \tif (!CHIP_IS_E3(sc))\n \t\tREG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);\n@@ -12112,20 +14213,19 @@ static elink_status_t elink_link_reset(struct elink_params *params,\n \t/* The PHY reset is controlled by GPIO 1\n \t * Hold it as vars low\n \t */\n-\t/* Clear link led */\n+\t /* Clear link led */\n \telink_set_mdio_emac_per_phy(sc, params);\n \telink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);\n \n \tif (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {\n \t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n-\t\t phy_index++) {\n+\t\t phy_index++) {\n \t\t\tif (params->phy[phy_index].link_reset) {\n \t\t\t\telink_set_aer_mmd(params,\n \t\t\t\t\t\t ¶ms->phy[phy_index]);\n-\t\t\t\tparams->phy[phy_index].link_reset(¶ms->\n-\t\t\t\t\t\t\t\t phy\n-\t\t\t\t\t\t\t\t [phy_index],\n-\t\t\t\t\t\t\t\t params);\n+\t\t\t\tparams->phy[phy_index].link_reset(\n+\t\t\t\t\t¶ms->phy[phy_index],\n+\t\t\t\t\tparams);\n \t\t\t}\n \t\t\tif (params->phy[phy_index].flags &\n \t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL)\n@@ -12139,11 +14239,12 @@ static elink_status_t elink_link_reset(struct elink_params *params,\n \t\telink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,\n \t\t\t 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);\n \t}\n+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n+\tif (!CHIP_REV_IS_SLOW(sc))\n+#endif\n \tif (params->phy[ELINK_INT_PHY].link_reset)\n-\t\tparams->phy[ELINK_INT_PHY].link_reset(¶ms->\n-\t\t\t\t\t\t phy\n-\t\t\t\t\t\t [ELINK_INT_PHY],\n-\t\t\t\t\t\t params);\n+\t\tparams->phy[ELINK_INT_PHY].link_reset(\n+\t\t\t¶ms->phy[ELINK_INT_PHY], params);\n \n \t/* Disable nig ingress interface */\n \tif (!CHIP_IS_E3(sc)) {\n@@ -12153,8 +14254,8 @@ static elink_status_t elink_link_reset(struct elink_params *params,\n \t\tREG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);\n \t\tREG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);\n \t} else {\n-\t\tuint32_t xmac_base =\n-\t\t (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n+\t\tuint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 :\n+\t\t\t\t\t\t GRCBASE_XMAC0;\n \t\telink_set_xumac_nig(params, 0, 0);\n \t\tif (REG_RD(sc, MISC_REG_RESET_REG_2) &\n \t\t MISC_REGISTERS_RESET_REG_2_XMAC)\n@@ -12165,9 +14266,8 @@ static elink_status_t elink_link_reset(struct elink_params *params,\n \tvars->phy_flags = 0;\n \treturn ELINK_STATUS_OK;\n }\n-\n-elink_status_t elink_lfa_reset(struct elink_params * params,\n-\t\t\t struct elink_vars * vars)\n+elink_status_t elink_lfa_reset(struct elink_params *params,\n+\t\t\t struct elink_vars *vars)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tvars->link_up = 0;\n@@ -12186,13 +14286,13 @@ elink_status_t elink_lfa_reset(struct elink_params * params,\n \t * are passed.\n \t */\n \tif (!CHIP_IS_E3(sc))\n-\t\telink_set_bmac_rx(sc, params->port, 0);\n+\t\telink_set_bmac_rx(sc, params->chip_id, params->port, 0);\n \n \tif (CHIP_IS_E3(sc)) {\n \t\telink_set_xmac_rxtx(params, 0);\n \t\telink_set_umac_rxtx(params, 0);\n \t}\n-\t/* Wait 10ms for the pipe to clean up */\n+\t/* Wait 10ms for the pipe to clean up*/\n \tDELAY(1000 * 10);\n \n \t/* Clean the NIG-BRB using the network filters in a way that will\n@@ -12207,7 +14307,7 @@ elink_status_t elink_lfa_reset(struct elink_params * params,\n \t * minimum management protocol down time.\n \t */\n \tif (!CHIP_IS_E3(sc))\n-\t\telink_set_bmac_rx(sc, params->port, 1);\n+\t\telink_set_bmac_rx(sc, params->chip_id, params->port, 1);\n \n \tif (CHIP_IS_E3(sc)) {\n \t\telink_set_xmac_rxtx(params, 1);\n@@ -12222,10 +14322,10 @@ elink_status_t elink_lfa_reset(struct elink_params * params,\n /*\t\t\t\tCommon function\t\t\t\t */\n /****************************************************************************/\n static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t uint32_t shmem_base_path[],\n-\t\t\t\t\t\t uint32_t shmem2_base_path[],\n-\t\t\t\t\t\t uint8_t phy_index,\n-\t\t\t\t\t\t __rte_unused uint32_t chip_id)\n+\t\t\t\t uint32_t shmem_base_path[],\n+\t\t\t\t uint32_t shmem2_base_path[],\n+\t\t\t\t uint8_t phy_index,\n+\t\t\t\t __rte_unused uint32_t chip_id)\n {\n \tstruct elink_phy phy[PORT_MAX];\n \tstruct elink_phy *phy_blk[PORT_MAX];\n@@ -12233,8 +14333,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \tint8_t port = 0;\n \tint8_t port_of_path = 0;\n \tuint32_t swap_val, swap_override;\n-\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n-\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n+\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n+\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n \tport ^= (swap_val && swap_override);\n \telink_ext_phy_hw_reset(sc, port);\n \t/* PART1 - Reset both phys */\n@@ -12255,7 +14355,7 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n \t\t\t\t port_of_path, &phy[port]) !=\n \t\t ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"populate_phy failed\");\n+\t\t\tELINK_DEBUG_P0(sc, \"populate_phy failed\");\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \t\t/* Disable attentions */\n@@ -12270,11 +14370,14 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \t\t * to write to access its registers\n \t\t */\n \t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n+\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH,\n+\t\t\t port);\n \n \t\t/* Reset the phy */\n \t\telink_cl45_write(sc, &phy[port],\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n+\t\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t\t MDIO_PMA_REG_CTRL,\n+\t\t\t\t 1 << 15);\n \t}\n \n \t/* Add delay of 150ms after reset */\n@@ -12295,8 +14398,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \t\telse\n \t\t\tport_of_path = 0;\n \n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Loading spirom for phy address 0x%x\",\n-\t\t\t phy_blk[port]->addr);\n+\t\tELINK_DEBUG_P1(sc, \"Loading spirom for phy address 0x%x\",\n+\t\t\t phy_blk[port]->addr);\n \t\tif (elink_8073_8727_external_rom_boot(sc, phy_blk[port],\n \t\t\t\t\t\t port_of_path))\n \t\t\treturn ELINK_STATUS_ERROR;\n@@ -12309,7 +14412,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \t\t/* Phase1 of TX_POWER_DOWN reset */\n \t\telink_cl45_write(sc, phy_blk[port],\n \t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));\n+\t\t\t\t MDIO_PMA_REG_TX_POWER_DOWN,\n+\t\t\t\t (val | 1 << 10));\n \t}\n \n \t/* Toggle Transmitter: Power down and then up with 600ms delay\n@@ -12326,9 +14430,9 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \t\t\t\tMDIO_PMA_REG_TX_POWER_DOWN, &val);\n \n \t\telink_cl45_write(sc, phy_blk[port],\n-\t\t\t\t MDIO_PMA_DEVAD,\n-\t\t\t\t MDIO_PMA_REG_TX_POWER_DOWN,\n-\t\t\t\t (val & (~(1 << 10))));\n+\t\t\t\tMDIO_PMA_DEVAD,\n+\t\t\t\tMDIO_PMA_REG_TX_POWER_DOWN,\n+\t\t\t\t(val & (~(1 << 10))));\n \t\tDELAY(1000 * 15);\n \n \t\t/* Read modify write the SPI-ROM version select register */\n@@ -12341,16 +14445,15 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n \n \t\t/* set GPIO2 back to LOW */\n \t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n-\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n+\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n \t}\n \treturn ELINK_STATUS_OK;\n }\n-\n static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t uint32_t shmem_base_path[],\n-\t\t\t\t\t\t uint32_t shmem2_base_path[],\n-\t\t\t\t\t\t uint8_t phy_index,\n-\t\t\t\t\t\t __rte_unused uint32_t chip_id)\n+\t\t\t\t uint32_t shmem_base_path[],\n+\t\t\t\t uint32_t shmem2_base_path[],\n+\t\t\t\t uint8_t phy_index,\n+\t\t\t\t __rte_unused uint32_t chip_id)\n {\n \tuint32_t val;\n \tint8_t port;\n@@ -12359,8 +14462,8 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,\n \t/* Enable the module detection interrupt */\n \tval = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);\n \tval |= ((1 << MISC_REGISTERS_GPIO_3) |\n-\t\t(1 <<\n-\t\t (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));\n+\t\t(1 << (MISC_REGISTERS_GPIO_3 +\n+\t\t MISC_REGISTERS_GPIO_PORT_SHIFT)));\n \tREG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);\n \n \telink_ext_phy_hw_reset(sc, 0);\n@@ -12378,33 +14481,33 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,\n \t\t}\n \t\t/* Extract the ext phy address for the port */\n \t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n-\t\t\t\t port, &phy) != ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"populate phy failed\");\n+\t\t\t\t port, &phy) !=\n+\t\t ELINK_STATUS_OK) {\n+\t\t\tELINK_DEBUG_P0(sc, \"populate phy failed\");\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \n-\t\t/* Reset phy */\n+\t\t/* Reset phy*/\n \t\telink_cl45_write(sc, &phy,\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);\n \n+\n \t\t/* Set fault module detected LED on */\n \t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,\n-\t\t\t\t MISC_REGISTERS_GPIO_HIGH, port);\n+\t\t\t MISC_REGISTERS_GPIO_HIGH,\n+\t\t\t port);\n \t}\n \n \treturn ELINK_STATUS_OK;\n }\n-\n static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,\n-\t\t\t\t\t uint32_t shmem_base, uint8_t * io_gpio,\n-\t\t\t\t\t uint8_t * io_port)\n+\t\t\t\t\t uint32_t shmem_base,\n+\t\t\t\t\t uint8_t *io_gpio, uint8_t *io_port)\n {\n \n \tuint32_t phy_gpio_reset = REG_RD(sc, shmem_base +\n-\t\t\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t\t\t dev_info.\n-\t\t\t\t\t\t port_hw_config[PORT_0].\n-\t\t\t\t\t\t default_cfg));\n+\t\t\t\t\t offsetof(struct shmem_region,\n+\t\t\t\tdev_info.port_hw_config[PORT_0].default_cfg));\n \tswitch (phy_gpio_reset) {\n \tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:\n \t\t*io_gpio = 0;\n@@ -12445,10 +14548,10 @@ static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,\n }\n \n static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t uint32_t shmem_base_path[],\n-\t\t\t\t\t\t uint32_t shmem2_base_path[],\n-\t\t\t\t\t\t uint8_t phy_index,\n-\t\t\t\t\t\t __rte_unused uint32_t chip_id)\n+\t\t\t\t uint32_t shmem_base_path[],\n+\t\t\t\t uint32_t shmem2_base_path[],\n+\t\t\t\t uint8_t phy_index,\n+\t\t\t\t __rte_unused uint32_t chip_id)\n {\n \tint8_t port, reset_gpio;\n \tuint32_t swap_val, swap_override;\n@@ -12465,18 +14568,17 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,\n \t * Default is GPIO1, PORT1\n \t */\n \telink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],\n-\t\t\t\t (uint8_t *) & reset_gpio,\n-\t\t\t\t (uint8_t *) & port);\n+\t\t\t\t (uint8_t *)&reset_gpio, (uint8_t *)&port);\n \n \t/* Calculate the port based on port swap */\n \tport ^= (swap_val && swap_override);\n \n-\t/* Initiate PHY reset */\n+\t/* Initiate PHY reset*/\n \telink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,\n-\t\t\t port);\n+\t\t port);\n \tDELAY(1000 * 1);\n \telink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,\n-\t\t\t port);\n+\t\t port);\n \n \tDELAY(1000 * 5);\n \n@@ -12498,8 +14600,8 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,\n \t\t/* Extract the ext phy address for the port */\n \t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n \t\t\t\t port_of_path, &phy[port]) !=\n-\t\t ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"populate phy failed\");\n+\t\t\t\t ELINK_STATUS_OK) {\n+\t\t\tELINK_DEBUG_P0(sc, \"populate phy failed\");\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t}\n \t\t/* disable attentions */\n@@ -12510,6 +14612,7 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,\n \t\t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n \t\t\t\tELINK_NIG_MASK_MI_INT));\n \n+\n \t\t/* Reset the phy */\n \t\telink_cl45_write(sc, &phy[port],\n \t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n@@ -12530,25 +14633,25 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,\n \t\t\tport_of_path = port;\n \t\telse\n \t\t\tport_of_path = 0;\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Loading spirom for phy address 0x%x\",\n-\t\t\t phy_blk[port]->addr);\n+\t\tELINK_DEBUG_P1(sc, \"Loading spirom for phy address 0x%x\",\n+\t\t\t phy_blk[port]->addr);\n \t\tif (elink_8073_8727_external_rom_boot(sc, phy_blk[port],\n \t\t\t\t\t\t port_of_path))\n \t\t\treturn ELINK_STATUS_ERROR;\n \t\t/* Disable PHY transmitter output */\n \t\telink_cl45_write(sc, phy_blk[port],\n-\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);\n+\t\t\t\t MDIO_PMA_DEVAD,\n+\t\t\t\t MDIO_PMA_REG_TX_DISABLE, 1);\n \n \t}\n \treturn ELINK_STATUS_OK;\n }\n \n static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,\n-\t\t\t\t\t\t uint32_t shmem_base_path[],\n-\t\t\t\t\t\t __rte_unused uint32_t\n-\t\t\t\t\t\t shmem2_base_path[],\n-\t\t\t\t\t\t __rte_unused uint8_t\n-\t\t\t\t\t\t phy_index, uint32_t chip_id)\n+\t\t\t\tuint32_t shmem_base_path[],\n+\t\t\t\t__rte_unused uint32_t shmem2_base_path[],\n+\t\t\t\t__rte_unused uint8_t phy_index,\n+\t\t\t\tuint32_t chip_id)\n {\n \tuint8_t reset_gpios;\n \treset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);\n@@ -12557,17 +14660,15 @@ static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,\n \tDELAY(10);\n \telink_cb_gpio_mult_write(sc, reset_gpios,\n \t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH);\n-\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t \"84833 reset pulse on pin values 0x%x\", reset_gpios);\n+\tELINK_DEBUG_P1(sc, \"84833 reset pulse on pin values 0x%x\",\n+\t\treset_gpios);\n \treturn ELINK_STATUS_OK;\n }\n-\n static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,\n-\t\t\t\t\t\tuint32_t shmem_base_path[],\n-\t\t\t\t\t\tuint32_t shmem2_base_path[],\n-\t\t\t\t\t\tuint8_t phy_index,\n-\t\t\t\t\t\tuint32_t ext_phy_type,\n-\t\t\t\t\t\tuint32_t chip_id)\n+\t\t\t\t uint32_t shmem_base_path[],\n+\t\t\t\t uint32_t shmem2_base_path[],\n+\t\t\t\t uint8_t phy_index,\n+\t\t\t\t uint32_t ext_phy_type, uint32_t chip_id)\n {\n \telink_status_t rc = ELINK_STATUS_OK;\n \n@@ -12595,44 +14696,50 @@ static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,\n \t\tbreak;\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:\n+\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858:\n \t\t/* GPIO3's are linked, and so both need to be toggled\n \t\t * to obtain required 2us pulse.\n \t\t */\n \t\trc = elink_84833_common_init_phy(sc, shmem_base_path,\n-\t\t\t\t\t\t shmem2_base_path,\n-\t\t\t\t\t\t phy_index, chip_id);\n+\t\t\t\t\t\tshmem2_base_path,\n+\t\t\t\t\t\tphy_index, chip_id);\n \t\tbreak;\n \tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:\n \t\trc = ELINK_STATUS_ERROR;\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"ext_phy 0x%x common init not required\",\n-\t\t\t ext_phy_type);\n+\t\tELINK_DEBUG_P1(sc,\n+\t\t\t \"ext_phy 0x%x common init not required\",\n+\t\t\t ext_phy_type);\n \t\tbreak;\n \t}\n \n \tif (rc != ELINK_STATUS_OK)\n-\t\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0);\t// \"Warning: PHY was not initialized,\"\n-\t// \" Port %d\",\n+\t\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0);\n+\t\t\t\t /* \"Warning: PHY was not initialized,\"\n+\t\t\t\t * \" Port %d\",\n+\t\t\t\t */\n \n \treturn rc;\n }\n \n-elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,\n-\t\t\t\t uint32_t shmem_base_path[],\n-\t\t\t\t uint32_t shmem2_base_path[],\n-\t\t\t\t uint32_t chip_id,\n-\t\t\t\t __rte_unused uint8_t one_port_enabled)\n+elink_status_t elink_common_init_phy(struct bnx2x_softc *sc,\n+\t\t\t uint32_t shmem_base_path[],\n+\t\t\t uint32_t shmem2_base_path[], uint32_t chip_id,\n+\t\t\t __rte_unused uint8_t one_port_enabled)\n {\n \telink_status_t rc = ELINK_STATUS_OK;\n \tuint32_t phy_ver, val;\n \tuint8_t phy_index = 0;\n \tuint32_t ext_phy_type, ext_phy_config;\n+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n+\tif (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))\n+\t\treturn ELINK_STATUS_OK;\n+#endif\n \n-\telink_set_mdio_clk(sc, GRCBASE_EMAC0);\n-\telink_set_mdio_clk(sc, GRCBASE_EMAC1);\n-\tPMD_DRV_LOG(DEBUG, sc, \"Begin common phy init\");\n+\telink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);\n+\telink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);\n+\tELINK_DEBUG_P0(sc, \"Begin common phy init\");\n \tif (CHIP_IS_E3(sc)) {\n \t\t/* Enable EPIO */\n \t\tval = REG_RD(sc, MISC_REG_GEN_PURP_HWG);\n@@ -12643,14 +14750,14 @@ elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,\n \t\t\t offsetof(struct shmem_region,\n \t\t\t\t port_mb[PORT_0].ext_phy_fw_version));\n \tif (phy_ver) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Not doing common init; phy ver is 0x%x\",\n-\t\t\t phy_ver);\n+\t\tELINK_DEBUG_P1(sc, \"Not doing common init; phy ver is 0x%x\",\n+\t\t\t phy_ver);\n \t\treturn ELINK_STATUS_OK;\n \t}\n \n \t/* Read the ext_phy_type for arbitrary port(0) */\n \tfor (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;\n-\t phy_index++) {\n+\t phy_index++) {\n \t\text_phy_config = elink_get_ext_phy_config(sc,\n \t\t\t\t\t\t\t shmem_base_path[0],\n \t\t\t\t\t\t\t phy_index, 0);\n@@ -12673,10 +14780,9 @@ static void elink_check_over_curr(struct elink_params *params,\n \n \tcfg_pin = (REG_RD(sc, params->shmem_base +\n \t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[port].\n-\t\t\t\t e3_cmn_pin_cfg1)) &\n+\t\t\t dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &\n \t\t PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>\n-\t PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;\n+\t\tPORT_HW_CFG_E3_OVER_CURRENT_SHIFT;\n \n \t/* Ignore check if no external input PIN available */\n \tif (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)\n@@ -12684,13 +14790,16 @@ static void elink_check_over_curr(struct elink_params *params,\n \n \tif (!pin_val) {\n \t\tif ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {\n-\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port);\t//\"Error: Power fault on Port %d has\"\n-\t\t\t// \" been detected and the power to \"\n-\t\t\t// \"that SFP+ module has been removed\"\n-\t\t\t// \" to prevent failure of the card.\"\n-\t\t\t// \" Please remove the SFP+ module and\"\n-\t\t\t// \" restart the system to clear this\"\n-\t\t\t// \" error.\",\n+\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT,\n+\t\t\t\t\t params->port);\n+\t\t\t\t\t/* \"Error: Power fault on Port %d has\"\n+\t\t\t\t\t * \" been detected and the power to \"\n+\t\t\t\t\t * \"that SFP+ module has been removed\"\n+\t\t\t\t\t * \" to prevent failure of the card.\"\n+\t\t\t\t\t * \" Please remove the SFP+ module and\"\n+\t\t\t\t\t * \" restart the system to clear this\"\n+\t\t\t\t\t * \" error.\",\n+\t\t\t\t\t */\n \t\t\tvars->phy_flags |= PHY_OVER_CURRENT_FLAG;\n \t\t\telink_warpcore_power_module(params, 0);\n \t\t}\n@@ -12700,9 +14809,9 @@ static void elink_check_over_curr(struct elink_params *params,\n \n /* Returns 0 if no change occurred since last check; 1 otherwise. */\n static uint8_t elink_analyze_link_error(struct elink_params *params,\n-\t\t\t\t\tstruct elink_vars *vars,\n-\t\t\t\t\tuint32_t status, uint32_t phy_flag,\n-\t\t\t\t\tuint32_t link_flag, uint8_t notify)\n+\t\t\t\t struct elink_vars *vars, uint32_t status,\n+\t\t\t\t uint32_t phy_flag, uint32_t link_flag,\n+\t\t\t\t uint8_t notify)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \t/* Compare new value with previous value */\n@@ -12715,16 +14824,20 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,\n \t/* If values differ */\n \tswitch (phy_flag) {\n \tcase PHY_HALF_OPEN_CONN_FLAG:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Analyze Remote Fault\");\n+\t\tELINK_DEBUG_P0(sc, \"Analyze Remote Fault\");\n \t\tbreak;\n \tcase PHY_SFP_TX_FAULT_FLAG:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Analyze TX Fault\");\n+\t\tELINK_DEBUG_P0(sc, \"Analyze TX Fault\");\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Analyze UNKNOWN\");\n+\t\tELINK_DEBUG_P0(sc, \"Analyze UNKNOWN\");\n \t}\n-\tPMD_DRV_LOG(DEBUG, sc, \"Link changed:[%x %x]->%x\", vars->link_up,\n-\t\t old_status, status);\n+\tELINK_DEBUG_P3(sc, \"Link changed:[%x %x]->%x\", vars->link_up,\n+\t old_status, status);\n+\n+\t/* Do not touch the link in case physical link down */\n+\tif ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)\n+\t\treturn 1;\n \n \t/* a. Update shmem->link_status accordingly\n \t * b. Update elink_vars->link_up\n@@ -12767,17 +14880,18 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,\n }\n \n /******************************************************************************\n-* Description:\n-*\tThis function checks for half opened connection change indication.\n-*\tWhen such change occurs, it calls the elink_analyze_link_error\n-*\tto check if Remote Fault is set or cleared. Reception of remote fault\n-*\tstatus message in the MAC indicates that the peer's MAC has detected\n-*\ta fault, for example, due to break in the TX side of fiber.\n-*\n-******************************************************************************/\n-static elink_status_t elink_check_half_open_conn(struct elink_params *params,\n-\t\t\t\t\t\t struct elink_vars *vars,\n-\t\t\t\t\t\t uint8_t notify)\n+ * Description:\n+ *\tThis function checks for half opened connection change indication.\n+ *\tWhen such change occurs, it calls the elink_analyze_link_error\n+ *\tto check if Remote Fault is set or cleared. Reception of remote fault\n+ *\tstatus message in the MAC indicates that the peer's MAC has detected\n+ *\ta fault, for example, due to break in the TX side of fiber.\n+ *\n+ ******************************************************************************/\n+static\n+elink_status_t elink_check_half_open_conn(struct elink_params *params,\n+\t\t\t\tstruct elink_vars *vars,\n+\t\t\t\tuint8_t notify)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint32_t lss_status = 0;\n@@ -12789,7 +14903,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,\n \n \tif (CHIP_IS_E3(sc) &&\n \t (REG_RD(sc, MISC_REG_RESET_REG_2) &\n-\t (MISC_REGISTERS_RESET_REG_2_XMAC))) {\n+\t (MISC_REGISTERS_RESET_REG_2_XMAC))) {\n \t\t/* Check E3 XMAC */\n \t\t/* Note that link speed cannot be queried here, since it may be\n \t\t * zero while link is down. In case UMAC is active, LSS will\n@@ -12814,7 +14928,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,\n \t\tuint32_t lss_status_reg;\n \t\tuint32_t wb_data[2];\n \t\tmac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n-\t\t NIG_REG_INGRESS_BMAC0_MEM;\n+\t\t\tNIG_REG_INGRESS_BMAC0_MEM;\n \t\t/* Read BIGMAC_REGISTER_RX_LSS_STATUS */\n \t\tif (CHIP_IS_E2(sc))\n \t\t\tlss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;\n@@ -12830,7 +14944,6 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,\n \t}\n \treturn ELINK_STATUS_OK;\n }\n-\n static void elink_sfp_tx_fault_detection(struct elink_phy *phy,\n \t\t\t\t\t struct elink_params *params,\n \t\t\t\t\t struct elink_vars *vars)\n@@ -12841,15 +14954,12 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,\n \n \t/* Get The SFP+ TX_Fault controlling pin ([eg]pio) */\n \tcfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,\n-\t\t\t\t\t\t\t dev_info.\n-\t\t\t\t\t\t\t port_hw_config\n-\t\t\t\t\t\t\t [port].\n-\t\t\t\t\t\t\t e3_cmn_pin_cfg)) &\n+\t\t\t dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &\n \t\t PORT_HW_CFG_E3_TX_FAULT_MASK) >>\n-\t PORT_HW_CFG_E3_TX_FAULT_SHIFT;\n+\t\t PORT_HW_CFG_E3_TX_FAULT_SHIFT;\n \n \tif (elink_get_cfg_pin(sc, cfg_pin, &value)) {\n-\t\tPMD_DRV_LOG(DEBUG, sc, \"Failed to read pin 0x%02x\", cfg_pin);\n+\t\tELINK_DEBUG_P1(sc, \"Failed to read pin 0x%02x\", cfg_pin);\n \t\treturn;\n \t}\n \n@@ -12871,24 +14981,25 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,\n \n \t\t/* If module is unapproved, led should be on regardless */\n \t\tif (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Change TX_Fault LED: ->%x\",\n-\t\t\t\t led_mode);\n+\t\t\tELINK_DEBUG_P1(sc, \"Change TX_Fault LED: ->%x\",\n+\t\t\t led_mode);\n \t\t\telink_set_e3_module_fault_led(params, led_mode);\n \t\t}\n \t}\n }\n-\n static void elink_kr2_recovery(struct elink_params *params,\n-\t\t\t struct elink_vars *vars, struct elink_phy *phy)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t struct elink_phy *phy)\n {\n-\tPMD_DRV_LOG(DEBUG, params->sc, \"KR2 recovery\");\n-\n+\tstruct bnx2x_softc *sc = params->sc;\n+\tELINK_DEBUG_P0(sc, \"KR2 recovery\");\n \telink_warpcore_enable_AN_KR2(phy, params, vars);\n \telink_warpcore_restart_AN_KR(phy, params);\n }\n \n static void elink_check_kr2_wa(struct elink_params *params,\n-\t\t\t struct elink_vars *vars, struct elink_phy *phy)\n+\t\t\t struct elink_vars *vars,\n+\t\t\t struct elink_phy *phy)\n {\n \tstruct bnx2x_softc *sc = params->sc;\n \tuint16_t base_page, next_page, not_kr2_device, lane;\n@@ -12906,14 +15017,14 @@ static void elink_check_kr2_wa(struct elink_params *params,\n \n \tsigdet = elink_warpcore_get_sigdet(phy, params);\n \tif (!sigdet) {\n-\t\tif (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n+\t\tif (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n \t\t\telink_kr2_recovery(params, vars, phy);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"No sigdet\");\n+\t\t\tELINK_DEBUG_P0(sc, \"No sigdet\");\n \t\t}\n \t\treturn;\n \t}\n \n-\tlane = elink_get_warpcore_lane(params);\n+\tlane = elink_get_warpcore_lane(phy, params);\n \tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n \t\t\t MDIO_AER_BLOCK_AER_REG, lane);\n \telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n@@ -12924,9 +15035,9 @@ static void elink_check_kr2_wa(struct elink_params *params,\n \n \t/* CL73 has not begun yet */\n \tif (base_page == 0) {\n-\t\tif (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n+\t\tif (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n \t\t\telink_kr2_recovery(params, vars, phy);\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"No BP\");\n+\t\t\tELINK_DEBUG_P0(sc, \"No BP\");\n \t\t}\n \t\treturn;\n \t}\n@@ -12940,10 +15051,10 @@ static void elink_check_kr2_wa(struct elink_params *params,\n \t\t\t ((next_page & 0xe0) == 0x20))));\n \n \t/* In case KR2 is already disabled, check if we need to re-enable it */\n-\tif (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n+\tif (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n \t\tif (!not_kr2_device) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"BP=0x%x, NP=0x%x\", base_page,\n-\t\t\t\t next_page);\n+\t\t\tELINK_DEBUG_P2(sc, \"BP=0x%x, NP=0x%x\", base_page,\n+\t\t\t next_page);\n \t\t\telink_kr2_recovery(params, vars, phy);\n \t\t}\n \t\treturn;\n@@ -12951,8 +15062,7 @@ static void elink_check_kr2_wa(struct elink_params *params,\n \t/* KR2 is enabled, but not KR2 device */\n \tif (not_kr2_device) {\n \t\t/* Disable KR2 on both lanes */\n-\t\tPMD_DRV_LOG(DEBUG, sc,\n-\t\t\t \"BP=0x%x, NP=0x%x\", base_page, next_page);\n+\t\tELINK_DEBUG_P2(sc, \"BP=0x%x, NP=0x%x\", base_page, next_page);\n \t\telink_disable_kr2(params, vars, phy);\n \t\t/* Restart AN on leading lane */\n \t\telink_warpcore_restart_AN_KR(phy, params);\n@@ -12968,9 +15078,8 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)\n \t\tif (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {\n \t\t\telink_set_aer_mmd(params, ¶ms->phy[phy_idx]);\n \t\t\tif (elink_check_half_open_conn(params, vars, 1) !=\n-\t\t\t ELINK_STATUS_OK) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"Fault detection failed\");\n-\t\t\t}\n+\t\t\t ELINK_STATUS_OK)\n+\t\t\t\tELINK_DEBUG_P0(sc, \"Fault detection failed\");\n \t\t\tbreak;\n \t\t}\n \t}\n@@ -12978,22 +15087,24 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)\n \tif (CHIP_IS_E3(sc)) {\n \t\tstruct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];\n \t\telink_set_aer_mmd(params, phy);\n-\t\tif ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&\n-\t\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))\n+\t\tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n+\t\t (phy->speed_cap_mask &\n+\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||\n+\t\t (phy->req_line_speed == ELINK_SPEED_20000))\n \t\t\telink_check_kr2_wa(params, vars, phy);\n \t\telink_check_over_curr(params, vars);\n \t\tif (vars->rx_tx_asic_rst)\n \t\t\telink_warpcore_config_runtime(phy, params, vars);\n \n \t\tif ((REG_RD(sc, params->shmem_base +\n-\t\t\t offsetof(struct shmem_region,\n-\t\t\t\t dev_info.port_hw_config[params->port].\n-\t\t\t\t default_cfg))\n-\t\t & PORT_HW_CFG_NET_SERDES_IF_MASK) ==\n+\t\t\t offsetof(struct shmem_region, dev_info.\n+\t\t\t\tport_hw_config[params->port].default_cfg))\n+\t\t & PORT_HW_CFG_NET_SERDES_IF_MASK) ==\n \t\t PORT_HW_CFG_NET_SERDES_IF_SFI) {\n-\t\t\tif (elink_is_sfp_module_plugged(params)) {\n+\t\t\tif (elink_is_sfp_module_plugged(phy, params)) {\n \t\t\t\telink_sfp_tx_fault_detection(phy, params, vars);\n-\t\t\t} else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {\n+\t\t\t} else if (vars->link_status &\n+\t\t\t\tLINK_STATUS_SFP_TX_FAULT) {\n \t\t\t\t/* Clean trail, interrupt corrects the leds */\n \t\t\t\tvars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;\n \t\t\t\tvars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;\n@@ -13005,17 +15116,18 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)\n }\n \n uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,\n-\t\t\t\t uint32_t shmem_base,\n-\t\t\t\t uint32_t shmem2_base, uint8_t port)\n+\t\t\t uint32_t shmem_base,\n+\t\t\t uint32_t shmem2_base,\n+\t\t\t uint8_t port)\n {\n \tuint8_t phy_index, fan_failure_det_req = 0;\n \tstruct elink_phy phy;\n \tfor (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;\n-\t phy_index++) {\n+\t phy_index++) {\n \t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n \t\t\t\t port, &phy)\n \t\t != ELINK_STATUS_OK) {\n-\t\t\tPMD_DRV_LOG(DEBUG, sc, \"populate phy failed\");\n+\t\t\tELINK_DEBUG_P0(sc, \"populate phy failed\");\n \t\t\treturn 0;\n \t\t}\n \t\tfan_failure_det_req |= (phy.flags &\n@@ -13035,24 +15147,27 @@ void elink_hw_reset_phy(struct elink_params *params)\n \t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n \t\t\tELINK_NIG_MASK_MI_INT));\n \n-\tfor (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {\n+\tfor (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;\n+\t phy_index++) {\n \t\tif (params->phy[phy_index].hw_reset) {\n-\t\t\tparams->phy[phy_index].hw_reset(¶ms->phy[phy_index],\n-\t\t\t\t\t\t\tparams);\n+\t\t\tparams->phy[phy_index].hw_reset(\n+\t\t\t\t¶ms->phy[phy_index],\n+\t\t\t\tparams);\n \t\t\tparams->phy[phy_index] = phy_null;\n \t\t}\n \t}\n }\n \n void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,\n-\t\t\t __rte_unused uint32_t chip_id, uint32_t shmem_base,\n-\t\t\t uint32_t shmem2_base, uint8_t port)\n+\t\t\t uint32_t chip_id, uint32_t shmem_base,\n+\t\t\t uint32_t shmem2_base,\n+\t\t\t uint8_t port)\n {\n \tuint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;\n \tuint32_t val;\n \tuint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;\n \tif (CHIP_IS_E3(sc)) {\n-\t\tif (elink_get_mod_abs_int_cfg(sc,\n+\t\tif (elink_get_mod_abs_int_cfg(sc, chip_id,\n \t\t\t\t\t shmem_base,\n \t\t\t\t\t port,\n \t\t\t\t\t &gpio_num,\n@@ -13061,11 +15176,11 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,\n \t} else {\n \t\tstruct elink_phy phy;\n \t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;\n-\t\t phy_index++) {\n+\t\t phy_index++) {\n \t\t\tif (elink_populate_phy(sc, phy_index, shmem_base,\n \t\t\t\t\t shmem2_base, port, &phy)\n \t\t\t != ELINK_STATUS_OK) {\n-\t\t\t\tPMD_DRV_LOG(DEBUG, sc, \"populate phy failed\");\n+\t\t\t\tELINK_DEBUG_P0(sc, \"populate phy failed\");\n \t\t\t\treturn;\n \t\t\t}\n \t\t\tif (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {\n@@ -13088,15 +15203,15 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,\n \tgpio_port ^= (swap_val && swap_override);\n \n \tvars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<\n-\t (gpio_num + (gpio_port << 2));\n+\t\t(gpio_num + (gpio_port << 2));\n \n \tsync_offset = shmem_base +\n-\t offsetof(struct shmem_region,\n-\t\t dev_info.port_hw_config[port].aeu_int_mask);\n+\t\toffsetof(struct shmem_region,\n+\t\t\t dev_info.port_hw_config[port].aeu_int_mask);\n \tREG_WR(sc, sync_offset, vars->aeu_int_mask);\n \n-\tPMD_DRV_LOG(DEBUG, sc, \"Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\",\n-\t\t gpio_num, gpio_port, vars->aeu_int_mask);\n+\tELINK_DEBUG_P3(sc, \"Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\",\n+\t\t gpio_num, gpio_port, vars->aeu_int_mask);\n \n \tif (port == 0)\n \t\toffset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;\ndiff --git a/drivers/net/bnx2x/elink.h b/drivers/net/bnx2x/elink.h\nindex 40000c2..a375d52 100644\n--- a/drivers/net/bnx2x/elink.h\n+++ b/drivers/net/bnx2x/elink.h\n@@ -14,7 +14,7 @@\n #ifndef ELINK_H\n #define ELINK_H\n \n-#define ELINK_DEBUG\n+#include \"bnx2x_logs.h\"\n \n \n \n@@ -29,6 +29,11 @@\n \n extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);\n extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);\n+/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/\n+extern void elink_cb_reg_wb_write(struct bnx2x_softc *sc, uint32_t offset,\n+\t\t\t\tuint32_t *wb_write, uint16_t len);\n+extern void elink_cb_reg_wb_read(struct bnx2x_softc *sc, uint32_t offset,\n+\t\t\t uint32_t *wb_write, uint16_t len);\n \n /* mode - 0( LOW ) /1(HIGH)*/\n extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,\n@@ -45,6 +50,9 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,\n \n extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);\n \n+/* Delay */\n+extern void elink_cb_udelay(struct bnx2x_softc *sc, uint32_t microsecond);\n+\n /* This function is called every 1024 bytes downloading of phy firmware.\n Driver can use it to print to screen indication for download progress */\n extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);\n@@ -69,6 +77,8 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,\n extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);\n extern void elink_cb_load_warpcore_microcode(void);\n \n+extern uint8_t elink_cb_path_id(struct bnx2x_softc *sc);\n+\n extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);\n \n #define ELINK_EVENT_LOG_LEVEL_ERROR \t1\n@@ -78,6 +88,32 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,\n \n #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))\n /* Debug prints */\n+#ifdef ELINK_DEBUG\n+\n+extern void elink_cb_dbg(struct bnx2x_softc *sc, const char *fmt);\n+extern void elink_cb_dbg1(struct bnx2x_softc *sc, const char *fmt,\n+\t\t\t uint32_t arg1);\n+extern void elink_cb_dbg2(struct bnx2x_softc *sc, const char *fmt,\n+\t\t\t uint32_t arg1, uint32_t arg2);\n+extern void elink_cb_dbg3(struct bnx2x_softc *sc, const char *fmt,\n+\t\t\t uint32_t arg1, uint32_t arg2,\n+\t\t\t uint32_t arg3);\n+\n+#define ELINK_DEBUG_P0(sc, fmt)\t\t\telink_cb_dbg(sc, fmt)\n+#define ELINK_DEBUG_P1(sc, fmt, arg1)\t\telink_cb_dbg1(sc, fmt, arg1)\n+#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2)\t\\\n+\telink_cb_dbg2(sc, fmt, arg1, arg2)\n+#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \\\n+\telink_cb_dbg3(sc, fmt, arg1, arg2, arg3)\n+#else\n+#define ELINK_DEBUG_P0(sc, fmt) PMD_DRV_LOG(DEBUG, sc, fmt)\n+#define ELINK_DEBUG_P1(sc, fmt, arg1) \\\n+\tPMD_DRV_LOG(DEBUG, sc, fmt, arg1)\n+#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \\\n+\tPMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2)\n+#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \\\n+\tPMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2, arg3)\n+#endif\n \n /***********************************************************/\n /* Defines */\n@@ -126,9 +162,12 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,\n #define ELINK_SFP_EEPROM_DATE_SIZE\t\t\t6\n #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR\t\t\t0x5c\n #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE\t\t\t1\n-#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ\t\t(1<<2)\n+#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ\t\t(1 << 2)\n #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR\t\t0x5e\n #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE\t\t1\n+#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR\t0x60\n+#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE\t16\n+\n \n #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE\t\t0x5e\n #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR\t\t\t0x5f\n@@ -219,23 +258,23 @@ struct elink_phy {\n \tuint8_t def_md_devad;\n \tuint16_t flags;\n \t/* No Over-Current detection */\n-#define ELINK_FLAGS_NOC\t\t\t(1<<1)\n+#define ELINK_FLAGS_NOC\t\t\t(1 << 1)\n \t/* Fan failure detection required */\n-#define ELINK_FLAGS_FAN_FAILURE_DET_REQ\t(1<<2)\n+#define ELINK_FLAGS_FAN_FAILURE_DET_REQ\t(1 << 2)\n \t/* Initialize first the XGXS and only then the phy itself */\n-#define ELINK_FLAGS_INIT_XGXS_FIRST\t\t(1<<3)\n-#define ELINK_FLAGS_WC_DUAL_MODE\t\t(1<<4)\n-#define ELINK_FLAGS_4_PORT_MODE\t\t(1<<5)\n-#define ELINK_FLAGS_REARM_LATCH_SIGNAL\t\t(1<<6)\n-#define ELINK_FLAGS_SFP_NOT_APPROVED\t\t(1<<7)\n-#define ELINK_FLAGS_MDC_MDIO_WA\t\t(1<<8)\n-#define ELINK_FLAGS_DUMMY_READ\t\t\t(1<<9)\n-#define ELINK_FLAGS_MDC_MDIO_WA_B0\t\t(1<<10)\n-#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC\t(1<<11)\n-#define ELINK_FLAGS_TX_ERROR_CHECK\t\t(1<<12)\n-#define ELINK_FLAGS_EEE\t\t\t(1<<13)\n-#define ELINK_FLAGS_TEMPERATURE\t\t(1<<14)\n-#define ELINK_FLAGS_MDC_MDIO_WA_G\t\t(1<<15)\n+#define ELINK_FLAGS_INIT_XGXS_FIRST\t\t(1 << 3)\n+#define ELINK_FLAGS_WC_DUAL_MODE\t\t(1 << 4)\n+#define ELINK_FLAGS_4_PORT_MODE\t\t(1 << 5)\n+#define ELINK_FLAGS_REARM_LATCH_SIGNAL\t\t(1 << 6)\n+#define ELINK_FLAGS_SFP_NOT_APPROVED\t\t(1 << 7)\n+#define ELINK_FLAGS_MDC_MDIO_WA\t\t(1 << 8)\n+#define ELINK_FLAGS_DUMMY_READ\t\t\t(1 << 9)\n+#define ELINK_FLAGS_MDC_MDIO_WA_B0\t\t(1 << 10)\n+#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC\t(1 << 11)\n+#define ELINK_FLAGS_TX_ERROR_CHECK\t\t(1 << 12)\n+#define ELINK_FLAGS_EEE\t\t\t(1 << 13)\n+#define ELINK_FLAGS_TEMPERATURE\t\t(1 << 14)\n+#define ELINK_FLAGS_MDC_MDIO_WA_G\t\t(1 << 15)\n \n \t/* preemphasis values for the rx side */\n \tuint16_t rx_preemphasis[4];\n@@ -247,20 +286,22 @@ struct elink_phy {\n \tuint32_t mdio_ctrl;\n \n \tuint32_t supported;\n-#define ELINK_SUPPORTED_10baseT_Half\t\t(1<<0)\n-#define ELINK_SUPPORTED_10baseT_Full\t\t(1<<1)\n-#define ELINK_SUPPORTED_100baseT_Half\t\t(1<<2)\n-#define ELINK_SUPPORTED_100baseT_Full \t\t(1<<3)\n-#define ELINK_SUPPORTED_1000baseT_Full \t(1<<4)\n-#define ELINK_SUPPORTED_2500baseX_Full \t(1<<5)\n-#define ELINK_SUPPORTED_10000baseT_Full \t(1<<6)\n-#define ELINK_SUPPORTED_TP \t\t\t(1<<7)\n-#define ELINK_SUPPORTED_FIBRE \t\t\t(1<<8)\n-#define ELINK_SUPPORTED_Autoneg \t\t(1<<9)\n-#define ELINK_SUPPORTED_Pause \t\t\t(1<<10)\n-#define ELINK_SUPPORTED_Asym_Pause\t\t(1<<11)\n-#define ELINK_SUPPORTED_20000baseMLD2_Full\t(1<<21)\n-#define ELINK_SUPPORTED_20000baseKR2_Full\t(1<<22)\n+#define ELINK_SUPPORTED_10baseT_Half\t\t(1 << 0)\n+#define ELINK_SUPPORTED_10baseT_Full\t\t(1 << 1)\n+#define ELINK_SUPPORTED_100baseT_Half\t\t(1 << 2)\n+#define ELINK_SUPPORTED_100baseT_Full\t\t(1 << 3)\n+#define ELINK_SUPPORTED_1000baseT_Full\t\t(1 << 4)\n+#define ELINK_SUPPORTED_2500baseX_Full\t\t(1 << 5)\n+#define ELINK_SUPPORTED_10000baseT_Full\t\t(1 << 6)\n+#define ELINK_SUPPORTED_TP\t\t\t(1 << 7)\n+#define ELINK_SUPPORTED_FIBRE\t\t\t(1 << 8)\n+#define ELINK_SUPPORTED_Autoneg\t\t\t(1 << 9)\n+#define ELINK_SUPPORTED_Pause\t\t\t(1 << 10)\n+#define ELINK_SUPPORTED_Asym_Pause\t\t(1 << 11)\n+#define ELINK_SUPPORTED_1000baseKX_Full\t\t(1 << 17)\n+#define ELINK_SUPPORTED_10000baseKR_Full\t(1 << 19)\n+#define ELINK_SUPPORTED_20000baseMLD2_Full\t(1 << 21)\n+#define ELINK_SUPPORTED_20000baseKR2_Full\t(1 << 22)\n \n \tuint32_t media_type;\n #define\tELINK_ETH_PHY_UNSPECIFIED\t0x0\n@@ -353,17 +394,22 @@ struct elink_params {\n \n \t/* features */\n \tuint32_t feature_config_flags;\n-#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED\t(1<<0)\n-#define ELINK_FEATURE_CONFIG_PFC_ENABLED\t\t\t(1<<1)\n-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY\t\t(1<<2)\n-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY\t(1<<3)\n-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX\t\t\t(1<<8)\n-#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED\t\t(1<<9)\n-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED\t(1<<10)\n-#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET\t\t(1<<11)\n-#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST\t\t\t(1<<12)\n-#define ELINK_FEATURE_CONFIG_MT_SUPPORT\t\t\t(1<<13)\n-#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN\t\t\t(1<<14)\n+#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED\t(1 << 0)\n+#define ELINK_FEATURE_CONFIG_PFC_ENABLED\t\t\t(1 << 1)\n+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY\t\t(1 << 2)\n+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY\t(1 << 3)\n+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC\t\t\t(1 << 4)\n+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC\t\t\t(1 << 5)\n+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC\t\t\t(1 << 6)\n+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC\t\t\t(1 << 7)\n+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX\t\t\t(1 << 8)\n+#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED\t\t(1 << 9)\n+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED\t(1 << 10)\n+#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET\t\t(1 << 11)\n+#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST\t\t\t(1 << 12)\n+#define ELINK_FEATURE_CONFIG_MT_SUPPORT\t\t\t(1 << 13)\n+#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN\t\t\t(1 << 14)\n+#define ELINK_FEATURE_CONFIG_DISABLE_PD\t\t\t\t(1 << 15)\n \n \t/* Will be populated during common init */\n \tstruct elink_phy phy[ELINK_MAX_PHYS];\n@@ -391,10 +437,10 @@ struct elink_params {\n #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME\t\t(0x6000)\n #define ELINK_EEE_MODE_NVRAM_MASK\t\t(0x3)\n #define ELINK_EEE_MODE_TIMER_MASK\t\t(0xfffff)\n-#define ELINK_EEE_MODE_OUTPUT_TIME\t\t(1<<28)\n-#define ELINK_EEE_MODE_OVERRIDE_NVRAM\t\t(1<<29)\n-#define ELINK_EEE_MODE_ENABLE_LPI\t\t(1<<30)\n-#define ELINK_EEE_MODE_ADV_LPI\t\t\t(1<<31)\n+#define ELINK_EEE_MODE_OUTPUT_TIME\t\t(1 << 28)\n+#define ELINK_EEE_MODE_OVERRIDE_NVRAM\t\t(1 << 29)\n+#define ELINK_EEE_MODE_ENABLE_LPI\t\t(1 << 30)\n+#define ELINK_EEE_MODE_ADV_LPI\t\t\t(1 << 31)\n \n \tuint16_t hw_led_mode; /* part of the hw_config read from the shmem */\n \tuint32_t multi_phy_config;\n@@ -404,20 +450,23 @@ struct elink_params {\n \tuint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when\n \t\t\t\treq_flow_ctrl is set to AUTO */\n \tuint16_t link_flags;\n-#define ELINK_LINK_FLAGS_INT_DISABLED\t\t(1<<0)\n-#define ELINK_PHY_INITIALIZED\t\t(1<<1)\n+#define ELINK_LINK_FLAGS_INT_DISABLED\t\t(1 << 0)\n+#define ELINK_PHY_INITIALIZED\t\t(1 << 1)\n \tuint32_t lfa_base;\n+\n+\t/* The same definitions as the shmem2 parameter */\n+\tuint32_t link_attr_sync;\n };\n \n /* Output parameters */\n struct elink_vars {\n \tuint8_t phy_flags;\n-#define PHY_XGXS_FLAG\t\t\t(1<<0)\n-#define PHY_SGMII_FLAG\t\t\t(1<<1)\n-#define PHY_PHYSICAL_LINK_FLAG\t\t(1<<2)\n-#define PHY_HALF_OPEN_CONN_FLAG\t\t(1<<3)\n-#define PHY_OVER_CURRENT_FLAG\t\t(1<<4)\n-#define PHY_SFP_TX_FAULT_FLAG\t\t(1<<5)\n+#define PHY_XGXS_FLAG\t\t\t(1 << 0)\n+#define PHY_SGMII_FLAG\t\t\t(1 << 1)\n+#define PHY_PHYSICAL_LINK_FLAG\t\t(1 << 2)\n+#define PHY_HALF_OPEN_CONN_FLAG\t\t(1 << 3)\n+#define PHY_OVER_CURRENT_FLAG\t\t(1 << 4)\n+#define PHY_SFP_TX_FAULT_FLAG\t\t(1 << 5)\n \n \tuint8_t mac_type;\n #define ELINK_MAC_TYPE_NONE\t\t0\n@@ -448,8 +497,7 @@ struct elink_vars {\n \tuint8_t rx_tx_asic_rst;\n \tuint8_t turn_to_run_wc_rt;\n \tuint16_t rsrv2;\n-\t/* The same definitions as the shmem2 parameter */\n-\tuint32_t link_attr_sync;\n+\n };\n \n /***********************************************************/\n@@ -460,14 +508,32 @@ struct elink_vars {\n /* Reset the link. Should be called when driver or interface goes down\n Before calling phy firmware upgrade, the reset_ext_phy should be set\n to 0 */\n+elink_status_t elink_link_reset(struct elink_params *params,\n+\t\t struct elink_vars *vars,\n+\t\t uint8_t reset_ext_phy);\n elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);\n /* elink_link_update should be called upon link interrupt */\n elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);\n \n+/* use the following phy functions to read/write from external_phy\n+ * In order to use it to read/write internal phy registers, use\n+ * ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as\n+ * the register\n+ */\n+elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,\n+\t\t uint8_t devad, uint16_t reg, uint16_t *ret_val);\n+\n+elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,\n+\t\t uint8_t devad, uint16_t reg, uint16_t val);\n+\n /* Reads the link_status from the shmem,\n and update the link vars accordingly */\n void elink_link_status_update(struct elink_params *input,\n \t\t\t struct elink_vars *output);\n+/* returns string representing the fw_version of the external phy */\n+elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params,\n+\t\t\t\t uint8_t *version,\n+\t\t\t\t uint16_t len);\n \n /* Set/Unset the led\n Basically, the CLC takes care of the led for the link, but in case one needs\n@@ -481,12 +547,34 @@ elink_status_t elink_set_led(struct elink_params *params,\n #define ELINK_LED_MODE_FRONT_PANEL_OFF\t3\n \n /* elink_handle_module_detect_int should be called upon module detection\n- interrupt */\n+ * interrupt\n+ */\n void elink_handle_module_detect_int(struct elink_params *params);\n \n+/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,\n+ * otherwise link is down\n+ */\n+elink_status_t elink_test_link(struct elink_params *params,\n+\t\t struct elink_vars *vars,\n+\t\t uint8_t is_serdes);\n+\n+\n /* One-time initialization for external phy after power up */\n elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],\n-\t\t\t uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);\n+\t\t\t uint32_t shmem2_base_path[], uint32_t chip_id,\n+\t\t\t uint8_t one_port_enabled);\n+\n+/* Reset the external PHY using GPIO */\n+void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port);\n+\n+/* Reset the external of SFX7101 */\n+void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy);\n+\n+/* Read \"byte_cnt\" bytes from address \"addr\" from the SFP+ EEPROM */\n+elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,\n+\t\t\t\t struct elink_params *params, uint8_t dev_addr,\n+\t\t\t\t uint16_t addr, uint16_t byte_cnt,\n+\t\t\t\t uint8_t *o_buf);\n \n void elink_hw_reset_phy(struct elink_params *params);\n \n@@ -569,12 +657,42 @@ elink_status_t elink_update_pfc(struct elink_params *params,\n \t\t struct elink_vars *vars,\n \t\t struct elink_nig_brb_pfc_port_params *pfc_params);\n \n+\n+/* Used to configure the ETS to disable */\n+elink_status_t elink_ets_disabled(struct elink_params *params,\n+\t\t struct elink_vars *vars);\n+\n+/* Used to configure the ETS to BW limited */\n+void elink_ets_bw_limit(const struct elink_params *params,\n+\t\t\tconst uint32_t cos0_bw,\n+\t\t\tconst uint32_t cos1_bw);\n+\n+/* Used to configure the ETS to strict */\n+elink_status_t elink_ets_strict(const struct elink_params *params,\n+\t\t\t\tconst uint8_t strict_cos);\n+\n+\n+/* Configure the COS to ETS according to BW and SP settings.*/\n+elink_status_t elink_ets_e3b0_config(const struct elink_params *params,\n+\t\t\t const struct elink_vars *vars,\n+\t\t\t struct elink_ets_params *ets_params);\n+/* Read pfc statistic*/\n+void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,\n+\t\t\t uint32_t pfc_frames_sent[2],\n+\t\t\t uint32_t pfc_frames_received[2]);\n void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,\n \t\t\t uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,\n \t\t\t uint8_t port);\n+/* elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n+ *\t\t\t struct elink_params *params);\n+ */\n \n void elink_period_func(struct elink_params *params, struct elink_vars *vars);\n \n+/*elink_status_t elink_check_half_open_conn(struct elink_params *params,\n+ *\t\t\t struct elink_vars *vars, uint8_t notify);\n+ */\n+\n void elink_enable_pmd_tx(struct elink_params *params);\n \n \n", "prefixes": [ "2/5" ] }