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GET /api/patches/44780/?format=api
{ "id": 44780, "url": "https://patches.dpdk.org/api/patches/44780/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1537172244-64874-2-git-send-email-gavin.hu@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1537172244-64874-2-git-send-email-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1537172244-64874-2-git-send-email-gavin.hu@arm.com", "date": "2018-09-17T08:17:23", "name": "[v3,2/3] ring: synchronize the load and store of the tail", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8580d823650fecbcd2c0ed02133bee74459f2c63", "submitter": { "id": 1018, "url": "https://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1537172244-64874-2-git-send-email-gavin.hu@arm.com/mbox/", "series": [ { "id": 1347, "url": "https://patches.dpdk.org/api/series/1347/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1347", "date": "2018-09-17T08:17:22", "name": "[v3,1/3] ring: read tail using atomic load", "version": 3, "mbox": "https://patches.dpdk.org/series/1347/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/44780/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/44780/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8FD7B5689;\n\tMon, 17 Sep 2018 10:17:45 +0200 (CEST)", "from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70])\n\tby dpdk.org (Postfix) with ESMTP id 1B7864CE4;\n\tMon, 17 Sep 2018 10:17:43 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8BC5AED1;\n\tMon, 17 Sep 2018 01:17:42 -0700 (PDT)", "from net-arm-thunderx2.shanghai.arm.com\n\t(net-arm-thunderx2.shanghai.arm.com [10.169.40.70])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t288773F5C0; Mon, 17 Sep 2018 01:17:41 -0700 (PDT)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com, steve.capper@arm.com,\n\tOla.Liljedahl@arm.com, jerin.jacob@caviumnetworks.com, nd@arm.com,\n\tstable@dpdk.org", "Date": "Mon, 17 Sep 2018 16:17:23 +0800", "Message-Id": "<1537172244-64874-2-git-send-email-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1537172244-64874-1-git-send-email-gavin.hu@arm.com>", "References": "<20180807031943.5331-1-gavin.hu@arm.com>\n\t<1537172244-64874-1-git-send-email-gavin.hu@arm.com>", "Subject": "[dpdk-dev] [PATCH v3 2/3] ring: synchronize the load and store of\n\tthe tail", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Synchronize the load-acquire of the tail and the store-release\nwithin update_tail, the store release ensures all the ring operations,\nenqueue or dequeue, are seen by the observers on the other side as soon\nas they see the updated tail. The load-acquire is needed here as the\ndata dependency is not a reliable way for ordering as the compiler might\nbreak it by saving to temporary values to boost performance.\nWhen computing the free_entries and avail_entries, use atomic semantics\nto load the heads and tails instead.\n\nThe patch was benchmarked with test/ring_perf_autotest and it decreases\nthe enqueue/dequeue latency by 5% ~ 27.6% with two lcores, the real gains\nare dependent on the number of lcores, depth of the ring, SPSC or MPMC.\nFor 1 lcore, it also improves a little, about 3 ~ 4%.\nIt is a big improvement, in case of MPMC, with two lcores and ring size\nof 32, it saves latency up to (3.26-2.36)/3.26 = 27.6%.\n\nThis patch is a bug fix, while the improvement is a bonus. In our analysis\nthe improvement comes from the cacheline pre-filling after hoisting load-\nacquire from _atomic_compare_exchange_n up above.\n\nThe test command:\n$sudo ./test/test/test -l 16-19,44-47,72-75,100-103 -n 4 --socket-mem=\\\n1024 -- -i\n\nTest result with this patch(two cores):\n SP/SC bulk enq/dequeue (size: 8): 5.86\n MP/MC bulk enq/dequeue (size: 8): 10.15\n SP/SC bulk enq/dequeue (size: 32): 1.94\n MP/MC bulk enq/dequeue (size: 32): 2.36\n\nIn comparison of the test result without this patch:\n SP/SC bulk enq/dequeue (size: 8): 6.67\n MP/MC bulk enq/dequeue (size: 8): 13.12\n SP/SC bulk enq/dequeue (size: 32): 2.04\n MP/MC bulk enq/dequeue (size: 32): 3.26\n\nFixes: 39368ebfc6 (\"ring: introduce C11 memory model barrier option\")\nCc: stable@dpdk.org\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>\nReviewed-by: Steve Capper <steve.capper@arm.com>\nReviewed-by: Ola Liljedahl <Ola.Liljedahl@arm.com>\n---\n lib/librte_ring/rte_ring_c11_mem.h | 20 ++++++++++++++++----\n 1 file changed, 16 insertions(+), 4 deletions(-)", "diff": "diff --git a/lib/librte_ring/rte_ring_c11_mem.h b/lib/librte_ring/rte_ring_c11_mem.h\nindex 234fea0..0eae3b3 100644\n--- a/lib/librte_ring/rte_ring_c11_mem.h\n+++ b/lib/librte_ring/rte_ring_c11_mem.h\n@@ -68,13 +68,18 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,\n \t\t*old_head = __atomic_load_n(&r->prod.head,\n \t\t\t\t\t__ATOMIC_ACQUIRE);\n \n-\t\t/*\n-\t\t * The subtraction is done between two unsigned 32bits value\n+\t\t/* load-acquire synchronize with store-release of ht->tail\n+\t\t * in update_tail.\n+\t\t */\n+\t\tconst uint32_t cons_tail = __atomic_load_n(&r->cons.tail,\n+\t\t\t\t\t\t\t__ATOMIC_ACQUIRE);\n+\n+\t\t/* The subtraction is done between two unsigned 32bits value\n \t\t * (the result is always modulo 32 bits even if we have\n \t\t * *old_head > cons_tail). So 'free_entries' is always between 0\n \t\t * and capacity (which is < size).\n \t\t */\n-\t\t*free_entries = (capacity + r->cons.tail - *old_head);\n+\t\t*free_entries = (capacity + cons_tail - *old_head);\n \n \t\t/* check that we have enough room in ring */\n \t\tif (unlikely(n > *free_entries))\n@@ -132,15 +137,22 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,\n \tdo {\n \t\t/* Restore n as it may change every loop */\n \t\tn = max;\n+\n \t\t*old_head = __atomic_load_n(&r->cons.head,\n \t\t\t\t\t__ATOMIC_ACQUIRE);\n \n+\t\t/* this load-acquire synchronize with store-release of ht->tail\n+\t\t * in update_tail.\n+\t\t */\n+\t\tconst uint32_t prod_tail = __atomic_load_n(&r->prod.tail,\n+\t\t\t\t\t__ATOMIC_ACQUIRE);\n+\n \t\t/* The subtraction is done between two unsigned 32bits value\n \t\t * (the result is always modulo 32 bits even if we have\n \t\t * cons_head > prod_tail). So 'entries' is always between 0\n \t\t * and size(ring)-1.\n \t\t */\n-\t\t*entries = (r->prod.tail - *old_head);\n+\t\t*entries = (prod_tail - *old_head);\n \n \t\t/* Set the actual entries for dequeue */\n \t\tif (n > *entries)\n", "prefixes": [ "v3", "2/3" ] }