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GET /api/patches/44660/?format=api
{ "id": 44660, "url": "https://patches.dpdk.org/api/patches/44660/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1536838528-11800-5-git-send-email-igor.russkikh@aquantia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536838528-11800-5-git-send-email-igor.russkikh@aquantia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536838528-11800-5-git-send-email-igor.russkikh@aquantia.com", "date": "2018-09-13T11:35:12", "name": "[v2,05/21] net/atlantic: b0 hardware layer main logic", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "46d025ee9a119e5b0c8ea606ccdf99f3e9b66e61", "submitter": { "id": 1124, "url": "https://patches.dpdk.org/api/people/1124/?format=api", "name": "Igor Russkikh", "email": "igor.russkikh@aquantia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1536838528-11800-5-git-send-email-igor.russkikh@aquantia.com/mbox/", "series": [ { "id": 1307, "url": "https://patches.dpdk.org/api/series/1307/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1307", "date": "2018-09-13T11:35:08", "name": "[v2,01/21] net/atlantic: atlantic PMD driver skeleton", "version": 2, "mbox": "https://patches.dpdk.org/series/1307/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/44660/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/44660/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 394DA5F2E;\n\tThu, 13 Sep 2018 13:35:56 +0200 (CEST)", "from NAM01-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam01on0085.outbound.protection.outlook.com [104.47.32.85])\n\tby dpdk.org (Postfix) with ESMTP id 192885F29\n\tfor <dev@dpdk.org>; Thu, 13 Sep 2018 13:35:54 +0200 (CEST)", "from ubuntubox.rdc.aquantia.com (95.79.108.179) by\n\tBLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.15;\n\tThu, 13 Sep 2018 11:35:51 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=K0EHGWMIEh27jf7yemQbR1S6VFpnMFQCt0cZR5x8oic=;\n\tb=Qq8bE/OSfB/8VPYC1JIZwQZ66g/A8zviPTfBaN/aE2hMLoHz5P3pJ+A7zO05OkEIQCrnwMFd3r8iSB7U83VyEGzmLsfpGtwT0fZKgINEzoZz3BTTuoE0apkuU46rbydZJ0m0kqzvGwpX9IfezRIF3FSLsEiSW5KahtfykIM6KGQ=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Igor.Russkikh@aquantia.com; ", "From": "Igor Russkikh <igor.russkikh@aquantia.com>", "To": "dev@dpdk.org", "Cc": "pavel.belous@aquantia.com,\n\tigor.russkikh@aquantia.com", "Date": "Thu, 13 Sep 2018 14:35:12 +0300", "Message-Id": "<1536838528-11800-5-git-send-email-igor.russkikh@aquantia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536838528-11800-1-git-send-email-igor.russkikh@aquantia.com>", "References": "<1536838528-11800-1-git-send-email-igor.russkikh@aquantia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[95.79.108.179]", "X-ClientProxiedBy": "VI1PR0202CA0026.eurprd02.prod.outlook.com\n\t(2603:10a6:803:14::39) To BLUPR0701MB1650.namprd07.prod.outlook.com\n\t(2a01:111:e400:58c6::20)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "9bd4f3d8-3d50-44d0-be8e-08d6196d0fa8", "X-Microsoft-Antispam": "BCL:0; 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PCL:0;\n\tRULEID:(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231311)(944501410)(52105095)(10201501046)(3002001)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123564045)(20161123562045)(20161123558120)(201708071742011)(7699050);\n\tSRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; ", "X-Forefront-PRVS": "07943272E1", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(39840400004)(366004)(396003)(376002)(136003)(346002)(199004)(189003)(6666003)(6916009)(97736004)(8936002)(68736007)(25786009)(50226002)(81166006)(81156014)(4326008)(107886003)(6486002)(51416003)(2906002)(53936002)(5660300001)(36756003)(86362001)(575784001)(316002)(52116002)(8676002)(16586007)(7736002)(305945005)(11346002)(446003)(476003)(956004)(47776003)(72206003)(66066001)(44832011)(478600001)(486006)(186003)(26005)(16526019)(14444005)(386003)(48376002)(2351001)(106356001)(2361001)(2616005)(3846002)(105586002)(50466002)(7696005)(6116002)(76176011);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650;\n\tH:ubuntubox.rdc.aquantia.com; \n\tFPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; ", "Received-SPF": "None (protection.outlook.com: aquantia.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "8xqWm9sMZZ5oZPFoRXM6Po2sRj8vvDpPw8N+hclxkK8fQrcP1OLQhd5FZu3qSKxPb92m/g9iSqkBWihK2/R+6v+nHC1Txd5nVj5rDXck/IDOvmnAX7VKfCyZPbmjlPw2LLcUjFjNwdjqXrz01nphG/8zIdlT8uv7i7/imqYaGEjvDazWvl/hoGunlbA+fk4UISfq9YHbu3m+pdfSXW4Suqt1f4rbJyoOBtSH8MEaMS1B5Urt1CWBMfWWMANDRmMaZ6iIKbKYdr9t6WdWO00dna9D9wGjYn3Fmtm2iD5NcKEw/Sv9TGz4o1DkVi/2D65Bb0P8bKMKnh+ICmBhglUk4W/jbwy2EK/Qkz0Pr3t6b04=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "aquantia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Sep 2018 11:35:51.5433\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "9bd4f3d8-3d50-44d0-be8e-08d6196d0fa8", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "83e2e134-991c-4ede-8ced-34d47e38e6b1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR0701MB1650", "Subject": "[dpdk-dev] [PATCH v2 05/21] net/atlantic: b0 hardware layer main\n\tlogic", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is hw_atl logic layer derived from linux atlantic\ndriver. It contains RX/TX hardware initialization\nsequences, various hw configuration.\n\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\n---\n drivers/net/atlantic/hw_atl/hw_atl_b0.c | 537 +++++++++++++++++++++++\n drivers/net/atlantic/hw_atl/hw_atl_b0.h | 40 ++\n drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h | 145 ++++++\n 3 files changed, 722 insertions(+)\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.c\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.h\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h", "diff": "diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/atlantic/hw_atl/hw_atl_b0.c\nnew file mode 100644\nindex 000000000..1df60719b\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.c\n@@ -0,0 +1,537 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (C) 2014-2017 aQuantia Corporation. */\n+\n+/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */\n+\n+#include \"../atl_types.h\"\n+#include \"hw_atl_b0.h\"\n+\n+#include \"../atl_hw_regs.h\"\n+#include \"hw_atl_utils.h\"\n+#include \"hw_atl_llh.h\"\n+#include \"hw_atl_b0_internal.h\"\n+#include \"hw_atl_llh_internal.h\"\n+#include \"../atl_logs.h\"\n+\n+int hw_atl_b0_hw_reset(struct aq_hw_s *self)\n+{\n+\tint err = 0;\n+\n+\terr = hw_atl_utils_soft_reset(self);\n+\tif (err)\n+\t\treturn err;\n+\n+\tself->aq_fw_ops->set_state(self, MPI_RESET);\n+\n+\treturn err;\n+}\n+\n+static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)\n+{\n+\tu32 tc = 0U;\n+\tu32 buff_size = 0U;\n+\tunsigned int i_priority = 0U;\n+\tbool is_rx_flow_control = false;\n+\n+\t/* TPS Descriptor rate init */\n+\thw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);\n+\thw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);\n+\n+\t/* TPS VM init */\n+\thw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);\n+\n+\t/* TPS TC credits init */\n+\thw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);\n+\thw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);\n+\n+\thw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);\n+\thw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);\n+\thw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);\n+\thw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);\n+\n+\t/* Tx buf size */\n+\tbuff_size = HW_ATL_B0_TXBUF_MAX;\n+\n+\thw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);\n+\thw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024 / 32U) * 66U) /\n+\t\t\t\t\t\t 100U, tc);\n+\thw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024 / 32U) * 50U) /\n+\t\t\t\t\t\t 100U, tc);\n+\n+\t/* QoS Rx buf size per TC */\n+\ttc = 0;\n+\tis_rx_flow_control = 0;\n+\tbuff_size = HW_ATL_B0_RXBUF_MAX;\n+\n+\thw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);\n+\thw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024U / 32U) * 66U) /\n+\t\t\t\t\t\t 100U, tc);\n+\thw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024U / 32U) * 50U) /\n+\t\t\t\t\t\t 100U, tc);\n+\thw_atl_rpb_rx_xoff_en_per_tc_set(self,\n+\t\t\t\t\t is_rx_flow_control ? 1U : 0U,\n+\t\t\t\t\t tc);\n+\n+\t/* QoS 802.1p priority -> TC mapping */\n+\tfor (i_priority = 8U; i_priority--;)\n+\t\thw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+/* calc hash only in IPv4 header, regardless of presence of TCP */\n+#define pif_rpf_rss_ipv4_hdr_only_i (1 << 4)\n+/* calc hash only if TCP header and IPv4 */\n+#define pif_rpf_rss_ipv4_tcp_hdr_only_i (1 << 3)\n+/* calc hash only in IPv6 header, regardless of presence of TCP */\n+#define pif_rpf_rss_ipv6_hdr_only_i (1 << 2)\n+/* calc hash only if TCP header and IPv4 */\n+#define pif_rpf_rss_ipv6_tcp_hdr_only_i (1 << 1)\n+/* bug 5124 - rss hashing types - FIXME */\n+#define pif_rpf_rss_dont_use_udp_i (1 << 0)\n+\n+\n+int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self)\n+{\n+\t/* misc */\n+\tunsigned int control_reg_val =\n+\t\tIS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U;\n+\n+\t/* RSS hash type set for IP/TCP */\n+\tcontrol_reg_val |= pif_rpf_rss_ipv4_hdr_only_i;//0x1EU;\n+\n+\taq_hw_write_reg(self, 0x5040U, control_reg_val);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,\n+\t\t\t\t struct aq_rss_parameters *rss_params)\n+{\n+\tstruct aq_hw_cfg_s *cfg = self->aq_nic_cfg;\n+\tint err = 0;\n+\tunsigned int i = 0U;\n+\tunsigned int addr = 0U;\n+\n+\tfor (i = 10, addr = 0U; i--; ++addr) {\n+\t\tu32 key_data = cfg->is_rss ?\n+\t\t\thtonl(rss_params->hash_secret_key[i]) : 0U;\n+\t\thw_atl_rpf_rss_key_wr_data_set(self, key_data);\n+\t\thw_atl_rpf_rss_key_addr_set(self, addr);\n+\t\thw_atl_rpf_rss_key_wr_en_set(self, 1U);\n+\t\tAQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,\n+\t\t\t 1000U, 10U);\n+\t\tif (err < 0)\n+\t\t\tgoto err_exit;\n+\t}\n+\n+\t/* RSS Ring selection */\n+\thw_atl_reg_rx_flr_rss_control1set(self,\n+\t\t\t\tcfg->is_rss ? 0xB3333333U : 0x00000000U);\n+\thw_atl_b0_hw_rss_hash_type_set(self);\n+\n+\terr = aq_hw_err_from_flags(self);\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+\n+int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,\n+\t\t\tstruct aq_rss_parameters *rss_params)\n+{\n+\tu8 *indirection_table = rss_params->indirection_table;\n+\tu32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);\n+\tu32 i = 0;\n+\tu32 addr = 0;\n+\tu32 val = 0;\n+\tu32 shift = 0;\n+\tint err = 0;\n+\n+\tfor (i = 0; i < HW_ATL_B0_RSS_REDIRECTION_MAX; i++) {\n+\t\tval |= (u32)(indirection_table[i] % num_rss_queues) << shift;\n+\t\tshift += 3;\n+\n+\t\tif (shift < 16)\n+\t\t\tcontinue;\n+\n+\t\thw_atl_rpf_rss_redir_tbl_wr_data_set(self, val & 0xffff);\n+\t\thw_atl_rpf_rss_redir_tbl_addr_set(self, addr);\n+\n+\t\thw_atl_rpf_rss_redir_wr_en_set(self, 1U);\n+\t\tAQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,\n+\t\t\t1000U, 10U);\n+\n+\t\tif (err < 0)\n+\t\t\tgoto err_exit;\n+\n+\t\tshift -= 16;\n+\t\tval >>= 16;\n+\t\taddr++;\n+\t}\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self)\n+\t\t\t\t /*struct aq_nic_cfg_s *aq_nic_cfg)*/\n+{\n+\tunsigned int i;\n+\n+\t/* TX checksums offloads*/\n+\thw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);\n+\thw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);\n+\n+\t/* RX checksums offloads*/\n+\thw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);\n+\thw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);\n+\n+\t/* LSO offloads*/\n+\thw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);\n+\n+/* LRO offloads */\n+\t{\n+\t\tunsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :\n+\t\t\t((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :\n+\t\t\t((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));\n+\n+\t\tfor (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)\n+\t\t\thw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);\n+\n+\t\thw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);\n+\t\thw_atl_rpo_lro_inactive_interval_set(self, 0);\n+\t\thw_atl_rpo_lro_max_coalescing_interval_set(self, 2);\n+\n+\t\thw_atl_rpo_lro_qsessions_lim_set(self, 1U);\n+\n+\t\thw_atl_rpo_lro_total_desc_lim_set(self, 2U);\n+\n+\t\thw_atl_rpo_lro_patch_optimization_en_set(self, 0U);\n+\n+\t\thw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);\n+\n+\t\thw_atl_rpo_lro_pkt_lim_set(self, 1U);\n+\n+\t\thw_atl_rpo_lro_en_set(self,\n+\t\t\t\tself->aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);\n+\t}\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+static\n+int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)\n+{\n+\t/* Tx TC/RSS number config */\n+\thw_atl_rpb_tps_tx_tc_mode_set(self, 1U);\n+\n+\thw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);\n+\thw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);\n+\thw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);\n+\n+\t/* Tx interrupts */\n+\thw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);\n+\n+\t/* misc */\n+\taq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?\n+\t\t\t0x00010000U : 0x00000000U);\n+\thw_atl_tdm_tx_dca_en_set(self, 0U);\n+\thw_atl_tdm_tx_dca_mode_set(self, 0U);\n+\n+\thw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+static\n+int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)\n+{\n+\tstruct aq_hw_cfg_s *cfg = self->aq_nic_cfg;\n+\tint i;\n+\n+\t/* Rx TC/RSS number config */\n+\thw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); /* 1: 4TC/8Queues */\n+\n+\t/* Rx flow control */\n+\thw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);\n+\n+\t/* RSS Ring selection */\n+\thw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?\n+\t\t\t\t\t0xB3333333U : 0x00000000U);\n+\n+\t/* Multicast filters */\n+\tfor (i = HW_ATL_B0_MAC_MAX; i--;) {\n+\t\thw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);\n+\t\thw_atl_rpfl2unicast_flr_act_set(self, 1U, i);\n+\t}\n+\n+\thw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);\n+\thw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);\n+\n+\t/* Vlan filters */\n+\thw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);\n+\thw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);\n+\n+\t/* VLAN proimisc bu defauld */\n+\thw_atl_rpf_vlan_prom_mode_en_set(self, 1);\n+\n+\t/* Rx Interrupts */\n+\thw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);\n+\n+\thw_atl_b0_hw_rss_hash_type_set(self);\n+\n+\thw_atl_rpfl2broadcast_flr_act_set(self, 1U);\n+\thw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));\n+\n+\thw_atl_rdm_rx_dca_en_set(self, 0U);\n+\thw_atl_rdm_rx_dca_mode_set(self, 0U);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+/* calc hash only in IPv4 header, regardless of presence of TCP */\n+#define pif_rpf_rss_ipv4_hdr_only_i (1 << 4)\n+/* calc hash only if TCP header and IPv4 */\n+#define pif_rpf_rss_ipv4_tcp_hdr_only_i (1 << 3)\n+/* calc hash only in IPv6 header, regardless of presence of TCP */\n+#define pif_rpf_rss_ipv6_hdr_only_i (1 << 2)\n+/* calc hash only if TCP header and IPv4 */\n+#define pif_rpf_rss_ipv6_tcp_hdr_only_i (1 << 1)\n+/* bug 5124 - rss hashing types - FIXME */\n+#define pif_rpf_rss_dont_use_udp_i (1 << 0)\n+\n+\n+int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self)\n+{\n+\t/* misc */\n+\tunsigned int control_reg_val =\n+\t\tIS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U;\n+\n+\t/* RSS hash type set for IP/TCP */\n+\tcontrol_reg_val |= pif_rpf_rss_ipv4_hdr_only_i;//0x1EU;\n+\n+\taq_hw_write_reg(self, 0x5040U, control_reg_val);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)\n+{\n+\tint err = 0;\n+\tunsigned int h = 0U;\n+\tunsigned int l = 0U;\n+\n+\tif (!mac_addr) {\n+\t\terr = -EINVAL;\n+\t\tgoto err_exit;\n+\t}\n+\th = (mac_addr[0] << 8) | (mac_addr[1]);\n+\tl = (mac_addr[2] << 24) | (mac_addr[3] << 16) |\n+\t\t(mac_addr[4] << 8) | mac_addr[5];\n+\n+\thw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);\n+\thw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);\n+\thw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);\n+\thw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);\n+\n+\terr = aq_hw_err_from_flags(self);\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)\n+{\n+\tstatic u32 aq_hw_atl_igcr_table_[4][2] = {\n+\t\t{ 0x20000080U, 0x20000080U }, /* AQ_IRQ_INVALID */\n+\t\t{ 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */\n+\t\t{ 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */\n+\t\t{ 0x200000A2U, 0x200000A6U } /* AQ_IRQ_MSIX */\n+\t};\n+\n+\tint err = 0;\n+\tu32 val;\n+\n+\tstruct aq_hw_cfg_s *aq_nic_cfg = self->aq_nic_cfg;\n+\n+\thw_atl_b0_hw_init_tx_path(self);\n+\thw_atl_b0_hw_init_rx_path(self);\n+\n+\thw_atl_b0_hw_mac_addr_set(self, mac_addr);\n+\n+\tself->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);\n+\tself->aq_fw_ops->set_state(self, MPI_INIT);\n+\n+\thw_atl_b0_hw_qos_set(self);\n+\thw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);\n+\thw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);\n+\n+\t/* Force limit MRRS on RDM/TDM to 2K */\n+\tval = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);\n+\taq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,\n+\t\t\t(val & ~0x707) | 0x404);\n+\n+\t/* TX DMA total request limit. B0 hardware is not capable to\n+\t * handle more than (8K-MRRS) incoming DMA data.\n+\t * Value 24 in 256byte units\n+\t */\n+\taq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);\n+\n+\t/* Reset link status and read out initial hardware counters */\n+\tself->aq_link_status.mbps = 0;\n+\tself->aq_fw_ops->update_stats(self);\n+\n+\terr = aq_hw_err_from_flags(self);\n+\tif (err < 0)\n+\t\tgoto err_exit;\n+\n+\t/* Interrupts */\n+\thw_atl_reg_irq_glb_ctl_set(self,\n+\t\t\t\t aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]\n+\t\t\t\t\t [(aq_nic_cfg->vecs > 1U) ?\n+\t\t\t\t\t 1 : 0]);\n+\n+\thw_atl_itr_irq_auto_masklsw_set(self, 0xffffffff);\n+\n+\t/* Interrupts */\n+\thw_atl_reg_gen_irq_map_set(self, 0, 0);\n+\thw_atl_reg_gen_irq_map_set(self, 0x80 | ATL_IRQ_CAUSE_LINK, 3);\n+\n+\thw_atl_b0_hw_offload_set(self);\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_tdm_tx_desc_en_set(self, 1, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_rdm_rx_desc_en_set(self, 1, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_start(struct aq_hw_s *self)\n+{\n+\thw_atl_tpb_tx_buff_en_set(self, 1);\n+\thw_atl_rpb_rx_buff_en_set(self, 1);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index)\n+{\n+\thw_atl_reg_tx_dma_desc_tail_ptr_set(self, tail, index);\n+\treturn 0;\n+}\n+\n+int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr,\n+\t\tint index, int size, int buff_size, int cpu, int vec)\n+{\n+\tu32 dma_desc_addr_lsw = (u32)base_addr;\n+\tu32 dma_desc_addr_msw = (u32)(base_addr >> 32);\n+\n+\thw_atl_rdm_rx_desc_en_set(self, false, index);\n+\n+\thw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index);\n+\n+\thw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,\n+\t\t\t\t\t\t index);\n+\n+\thw_atl_reg_rx_dma_desc_base_addressmswset(self, dma_desc_addr_msw,\n+\t\t\t\t\t\t index);\n+\n+\thw_atl_rdm_rx_desc_len_set(self, size / 8U, index);\n+\n+\thw_atl_rdm_rx_desc_data_buff_size_set(self, buff_size / 1024U, index);\n+\n+\thw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, index);\n+\thw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index);\n+\thw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, index);\n+\n+\t/* Rx ring set mode */\n+\n+\t/* Mapping interrupt vector */\n+\thw_atl_itr_irq_map_rx_set(self, vec, index);\n+\thw_atl_itr_irq_map_en_rx_set(self, true, index);\n+\n+\thw_atl_rdm_cpu_id_set(self, cpu, index);\n+\thw_atl_rdm_rx_desc_dca_en_set(self, 0U, index);\n+\thw_atl_rdm_rx_head_dca_en_set(self, 0U, index);\n+\thw_atl_rdm_rx_pld_dca_en_set(self, 0U, index);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr,\n+\t\t\t int index, int size, int cpu, int vec)\n+{\n+\tu32 dma_desc_lsw_addr = (u32)base_addr;\n+\tu32 dma_desc_msw_addr = (u32)(base_addr >> 32);\n+\n+\thw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,\n+\t\t\t\t\t\t index);\n+\n+\thw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,\n+\t\t\t\t\t\t index);\n+\n+\thw_atl_tdm_tx_desc_len_set(self, size / 8U, index);\n+\n+\thw_atl_b0_hw_tx_ring_tail_update(self, 0, index);\n+\n+\t/* Set Tx threshold */\n+\thw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, index);\n+\n+\t/* Mapping interrupt vector */\n+\thw_atl_itr_irq_map_tx_set(self, vec, index);\n+\thw_atl_itr_irq_map_en_tx_set(self, true, index);\n+\n+\thw_atl_tdm_cpu_id_set(self, cpu, index);\n+\thw_atl_tdm_tx_desc_dca_en_set(self, 0U, index);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)\n+{\n+\thw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)\n+{\n+\thw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));\n+\thw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)\n+{\n+\t*mask = hw_atl_itr_irq_statuslsw_get(self);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_tdm_tx_desc_en_set(self, 0U, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_rdm_rx_desc_en_set(self, 0U, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\ndiff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/atlantic/hw_atl/hw_atl_b0.h\nnew file mode 100644\nindex 000000000..6fa7f364b\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (C) 2014-2017 aQuantia Corporation. */\n+\n+/* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware\n+ * specific functions.\n+ */\n+\n+#ifndef HW_ATL_B0_H\n+#define HW_ATL_B0_H\n+\n+int hw_atl_b0_hw_reset(struct aq_hw_s *self);\n+int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr);\n+\n+int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr,\n+\t\tint index, int size, int cpu, int vec);\n+int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr,\n+\t\tint index, int size, int buff_size, int cpu, int vec);\n+\n+int hw_atl_b0_hw_start(struct aq_hw_s *self);\n+\n+int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index);\n+int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index);\n+\n+\n+int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index);\n+int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index);\n+\n+\n+int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index);\n+\n+int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,\n+\t\t\t\t struct aq_rss_parameters *rss_params);\n+int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,\n+\t\t\t\tstruct aq_rss_parameters *rss_params);\n+\n+int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask);\n+int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask);\n+int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask);\n+\n+#endif /* HW_ATL_B0_H */\ndiff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h\nnew file mode 100644\nindex 000000000..0594929a5\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h\n@@ -0,0 +1,145 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (C) 2014-2017 aQuantia Corporation. */\n+\n+/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific\n+ * constants.\n+ */\n+\n+#ifndef HW_ATL_B0_INTERNAL_H\n+#define HW_ATL_B0_INTERNAL_H\n+\n+\n+#define HW_ATL_B0_MTU_JUMBO 16352U\n+#define HW_ATL_B0_MTU 1514U\n+\n+#define HW_ATL_B0_TX_RINGS 4U\n+#define HW_ATL_B0_RX_RINGS 4U\n+\n+#define HW_ATL_B0_RINGS_MAX 32U\n+#define HW_ATL_B0_TXD_SIZE (16U)\n+#define HW_ATL_B0_RXD_SIZE (16U)\n+\n+#define HW_ATL_B0_MAC 0U\n+#define HW_ATL_B0_MAC_MIN 1U\n+#define HW_ATL_B0_MAC_MAX 33U\n+\n+/* Maximum supported VLAN filters */\n+#define HW_ATL_B0_MAX_VLAN_IDS 16\n+\n+/* UCAST/MCAST filters */\n+#define HW_ATL_B0_UCAST_FILTERS_MAX 38\n+#define HW_ATL_B0_MCAST_FILTERS_MAX 8\n+\n+/* interrupts */\n+#define HW_ATL_B0_ERR_INT 8U\n+#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)\n+\n+#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)\n+#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)\n+#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)\n+\n+#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)\n+#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)\n+#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)\n+#define HW_ATL_B0_TXD_CTL_DD (0x00100000)\n+#define HW_ATL_B0_TXD_CTL_EOP (0x00200000)\n+\n+#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)\n+\n+#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)\n+#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)\n+#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)\n+#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)\n+#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)\n+#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)\n+#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)\n+\n+#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)\n+#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)\n+\n+#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U\n+#define HW_ATL_B0_MPI_STATE_ADR 0x036CU\n+\n+#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU\n+#define HW_ATL_B0_MPI_SPEED_SHIFT 16U\n+\n+#define HW_ATL_B0_TXBUF_MAX 160U\n+#define HW_ATL_B0_RXBUF_MAX 320U\n+\n+#define HW_ATL_B0_RXD_BUF_SIZE_MAX (16 * 1024)\n+\n+#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U\n+#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U\n+#define HW_ATL_B0_RSS_HASHKEY_BITS 320U\n+\n+#define HW_ATL_B0_TCRSS_4_8 1\n+#define HW_ATL_B0_TC_MAX 1U\n+#define HW_ATL_B0_RSS_MAX 8U\n+\n+#define HW_ATL_B0_LRO_RXD_MAX 2U\n+#define HW_ATL_B0_RS_SLIP_ENABLED 0U\n+\n+/* (256k -1(max pay_len) - 54(header)) */\n+#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U\n+\n+/* (256k -1(max pay_len) - 74(header)) */\n+#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U\n+\n+#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U\n+#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU\n+\n+#define HW_ATL_B0_FW_SEMA_RAM 0x2U\n+\n+#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)\n+#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)\n+\n+#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)\n+#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)\n+#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)\n+#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)\n+#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)\n+\n+#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000)\t/* L3LEN lsb */\n+#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF)\t/* L3LE upper bits */\n+#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)\n+#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)\n+\n+#define HW_ATL_B0_RXD_DD (0x1)\n+#define HW_ATL_B0_RXD_NCEA0 (0x1)\n+\n+#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)\n+#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)\n+#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)\n+#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)\n+#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)\n+\n+#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)\n+#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)\n+#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)\n+#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)\n+#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)\n+#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)\n+#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)\n+#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)\n+\n+#define L2_FILTER_ACTION_DISCARD (0x0)\n+#define L2_FILTER_ACTION_HOST (0x1)\n+\n+#define HW_ATL_B0_UCP_0X370_REG (0x370)\n+\n+#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)\n+\n+#define HW_ATL_INTR_MODER_MAX 0x1FF\n+#define HW_ATL_INTR_MODER_MIN 0xFF\n+\n+#define HW_ATL_B0_MIN_RXD \\\n+\t(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))\n+#define HW_ATL_B0_MIN_TXD \\\n+\t(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))\n+\n+#define HW_ATL_B0_MAX_RXD 8184U\n+#define HW_ATL_B0_MAX_TXD 8184U\n+\n+/* HW layer capabilities */\n+\n+#endif /* HW_ATL_B0_INTERNAL_H */\n", "prefixes": [ "v2", "05/21" ] }