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Update a patch.
GET /api/patches/44457/?format=api
{ "id": 44457, "url": "https://patches.dpdk.org/api/patches/44457/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1536438666-22184-15-git-send-email-rasesh.mody@cavium.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536438666-22184-15-git-send-email-rasesh.mody@cavium.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536438666-22184-15-git-send-email-rasesh.mody@cavium.com", "date": "2018-09-08T20:31:03", "name": "[14/17] net/qede: fix Rx buffer size calculation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "04c44dad41c1eae72c9aad160db9209767e1d05b", "submitter": { "id": 569, "url": "https://patches.dpdk.org/api/people/569/?format=api", "name": "Mody, Rasesh", "email": "rasesh.mody@cavium.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1536438666-22184-15-git-send-email-rasesh.mody@cavium.com/mbox/", "series": [ { "id": 1239, "url": "https://patches.dpdk.org/api/series/1239/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1239", "date": "2018-09-08T20:30:49", "name": "net/qede: add enhancements and fixes", "version": 1, "mbox": "https://patches.dpdk.org/series/1239/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/44457/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/44457/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C19E36904;\n\tSat, 8 Sep 2018 22:32:11 +0200 (CEST)", "from NAM04-BN3-obe.outbound.protection.outlook.com\n\t(mail-eopbgr680053.outbound.protection.outlook.com [40.107.68.53])\n\tby dpdk.org (Postfix) with ESMTP id 37AB44CC5;\n\tSat, 8 Sep 2018 22:31:57 +0200 (CEST)", "from cavium.com (198.186.1.5) by\n\tDM6PR07MB5372.namprd07.prod.outlook.com (2603:10b6:5:44::17) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.18; Sat, 8 Sep 2018 20:31:55 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=gYimw5iSVnEpxI9SKSFwlNJaqtiO4avtW+hkAbW7FYs=;\n\tb=UckFJBm4KTZjEOZIsYahhE6/GITj0dVGdyG/beFSwVeJElSC3q9HLWb8Ebag/tA03lRPlmS4FQsbvwmOhK98+8ExYHgP5qDk//OlNEN/RAf3kMamykgUd+rvBzK04qxi6MlyCaUFhzBSDvJZ690zA6HKD1Xs9EDogqe3RfAXlJY=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Rasesh.Mody@cavium.com; ", "From": "Rasesh Mody <rasesh.mody@cavium.com>", "To": "dev@dpdk.org", "Cc": "Shahed Shaikh <shahed.shaikh@cavium.com>, ferruh.yigit@intel.com,\n\tDept-EngDPDKDev@cavium.com, stable@dpdk.org", "Date": "Sat, 8 Sep 2018 13:31:03 -0700", "Message-Id": "<1536438666-22184-15-git-send-email-rasesh.mody@cavium.com>", "X-Mailer": "git-send-email 1.7.10.3", "In-Reply-To": "<1536438666-22184-1-git-send-email-rasesh.mody@cavium.com>", "References": "<1536438666-22184-1-git-send-email-rasesh.mody@cavium.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[198.186.1.5]", "X-ClientProxiedBy": "BYAPR02CA0031.namprd02.prod.outlook.com\n\t(2603:10b6:a02:ee::44) To DM6PR07MB5372.namprd07.prod.outlook.com\n\t(2603:10b6:5:44::17)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "eb5526c5-37f1-4844-ebf7-08d615ca1e65", "X-Microsoft-Antispam": "BCL:0; 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PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(823301075)(3002001)(10201501046)(3231311)(944501410)(52105095)(93006095)(93001095)(149027)(150027)(6041310)(20161123562045)(20161123564045)(20161123558120)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050);\n\tSRVR:DM6PR07MB5372; BCL:0; PCL:0; RULEID:; SRVR:DM6PR07MB5372; ", "X-Forefront-PRVS": "07891BF289", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(396003)(366004)(136003)(346002)(376002)(39860400002)(199004)(189003)(4720700003)(97736004)(2351001)(106356001)(105586002)(72206003)(66066001)(47776003)(4326008)(50466002)(48376002)(25786009)(305945005)(7736002)(2361001)(8676002)(478600001)(316002)(52116002)(69596002)(186003)(575784001)(50226002)(44832011)(16526019)(486006)(21086003)(2906002)(55016002)(26005)(8936002)(476003)(956004)(81156014)(81166006)(86362001)(5660300001)(6666003)(36756003)(16586007)(11346002)(446003)(2616005)(76176011)(3846002)(6116002)(6916009)(68736007)(14444005)(386003)(51416003)(53936002)(7696005);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR07MB5372; H:cavium.com; FPR:;\n\tSPF:None; \n\tLANG:en; PTR:InfoNoRecords; A:1; MX:1; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "BgVWhwYm+vU/TroPo1+F9PV6Eljvue7fpfjPhiJ5jqlfTpxaKSdJCYHvpnq2vhDwBqhTG86hPhZ80GMB0fv5xX9bRZ1KNtJh5UkpDGrfMYJYjKmtSe1ubnnvOyIsc6N4GpLM8nI4VTLcI1oAiJgawvlJAUmMycbXtUJcPTt/X4X8e7HmBhuOC/E+7M3nEp3T+vB5OB/gScYniKV7IHx8d6HKMBLrEi1WpQ2thRnjDK804l7WjsvWOq8ehtAdwAQI9zm5Ywv1mrHJlIbRsPJVynPkW6uSFxyvJ6B0DtjrfhezqyW9wNv1rsq7pSYZ6DVuYBatmPaMhb0q0uRtEBdDYM9MPL+vCPQfOM/skxER49o=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "cavium.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Sep 2018 20:31:55.3326\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "eb5526c5-37f1-4844-ebf7-08d615ca1e65", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR07MB5372", "Subject": "[dpdk-dev] [PATCH 14/17] net/qede: fix Rx buffer size calculation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shahed Shaikh <shahed.shaikh@cavium.com>\n\n - HW does not include CRC in received frame when passed to host,\n so no need to consider CRC length while calculating Rx buffer size.\n - In scattered Rx mode, driver may allocate Rx buffer larger than\n the size of mbuf because it tries to adjust the buffer size to cache\n line size by ceiling it. Fix this by flooring the size instead of\n ceiling.\n - Consider the rule imposed by HW regarding the minimum size of Rx buffer\n in scattered Rx mode -\n (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT\n\nFixes: f6033f2497e7 (\"net/qede: fix minimum buffer size and scatter Rx check\")\nCC: stable@dpdk.org\n\nSigned-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>\n---\n drivers/net/qede/qede_ethdev.c | 28 +++++++++----------\n drivers/net/qede/qede_rxtx.c | 59 +++++++++++++++++++++++++++++++++++-----\n drivers/net/qede/qede_rxtx.h | 15 ++++++++--\n 3 files changed, 78 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\nindex d5e162c..259eb45 100644\n--- a/drivers/net/qede/qede_ethdev.c\n+++ b/drivers/net/qede/qede_ethdev.c\n@@ -1210,7 +1210,7 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev)\n \tif (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)\n \t\teth_dev->data->mtu =\n \t\t\teth_dev->data->dev_conf.rxmode.max_rx_pkt_len -\n-\t\t\tETHER_HDR_LEN - ETHER_CRC_LEN;\n+\t\t\tETHER_HDR_LEN - QEDE_ETH_OVERHEAD;\n \n \tif (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\teth_dev->data->scattered_rx = 1;\n@@ -2226,19 +2226,18 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)\n \tstruct qede_fastpath *fp;\n \tuint32_t max_rx_pkt_len;\n \tuint32_t frame_size;\n-\tuint16_t rx_buf_size;\n \tuint16_t bufsz;\n \tbool restart = false;\n-\tint i;\n+\tint i, rc;\n \n \tPMD_INIT_FUNC_TRACE(edev);\n \tqede_dev_info_get(dev, &dev_info);\n-\tmax_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;\n-\tframe_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;\n+\tmax_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;\n+\tframe_size = max_rx_pkt_len;\n \tif ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {\n \t\tDP_ERR(edev, \"MTU %u out of range, %u is maximum allowable\\n\",\n \t\t mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -\n-\t\t\tETHER_CRC_LEN - QEDE_ETH_OVERHEAD);\n+\t\t QEDE_ETH_OVERHEAD);\n \t\treturn -EINVAL;\n \t}\n \tif (!dev->data->scattered_rx &&\n@@ -2266,14 +2265,15 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)\n \t\tif (fp->rxq != NULL) {\n \t\t\tbufsz = (uint16_t)rte_pktmbuf_data_room_size(\n \t\t\t\tfp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;\n-\t\t\tif (dev->data->scattered_rx)\n-\t\t\t\trx_buf_size = bufsz + ETHER_HDR_LEN +\n-\t\t\t\t\t ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;\n-\t\t\telse\n-\t\t\t\trx_buf_size = frame_size;\n-\t\t\trx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);\n-\t\t\tfp->rxq->rx_buf_size = rx_buf_size;\n-\t\t\tDP_INFO(edev, \"RX buffer size %u\\n\", rx_buf_size);\n+\t\t\t/* cache align the mbuf size to simplfy rx_buf_size\n+\t\t\t * calculation\n+\t\t\t */\n+\t\t\tbufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);\n+\t\t\trc = qede_calc_rx_buf_size(dev, bufsz, frame_size);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\n+\t\t\tfp->rxq->rx_buf_size = rc;\n \t\t}\n \t}\n \tif (max_rx_pkt_len > ETHER_MAX_LEN)\ndiff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex 0f157de..675c0a0 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -35,6 +35,49 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)\n \treturn 0;\n }\n \n+/* Criterias for calculating Rx buffer size -\n+ * 1) rx_buf_size should not exceed the size of mbuf\n+ * 2) In scattered_rx mode - minimum rx_buf_size should be\n+ * (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT\n+ * 3) In regular mode - minimum rx_buf_size should be\n+ * (MTU + Maximum L2 Header Size + 2)\n+ * In above cases +2 corrosponds to 2 bytes padding in front of L2\n+ * header.\n+ * 4) rx_buf_size should be cacheline-size aligned. So considering\n+ * criteria 1, we need to adjust the size to floor instead of ceil,\n+ * so that we don't exceed mbuf size while ceiling rx_buf_size.\n+ */\n+int\n+qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,\n+\t\t uint16_t max_frame_size)\n+{\n+\tstruct qede_dev *qdev = QEDE_INIT_QDEV(dev);\n+\tstruct ecore_dev *edev = QEDE_INIT_EDEV(qdev);\n+\tint rx_buf_size;\n+\n+\tif (dev->data->scattered_rx) {\n+\t\t/* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of\n+\t\t * bufferes can be used for single packet. So need to make sure\n+\t\t * mbuf size is sufficient enough for this.\n+\t\t */\n+\t\tif ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <\n+\t\t (max_frame_size + QEDE_ETH_OVERHEAD)) {\n+\t\t\tDP_ERR(edev, \"mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\\n\",\n+\t\t\t mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\trx_buf_size = RTE_MAX(mbufsz,\n+\t\t\t\t (max_frame_size + QEDE_ETH_OVERHEAD) /\n+\t\t\t\t ETH_RX_MAX_BUFF_PER_PKT);\n+\t} else {\n+\t\trx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;\n+\t}\n+\n+\t/* Align to cache-line size if needed */\n+\treturn QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);\n+}\n+\n int\n qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t uint16_t nb_desc, unsigned int socket_id,\n@@ -85,6 +128,8 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)\n \n \t/* Fix up RX buffer size */\n \tbufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;\n+\t/* cache align the mbuf size to simplfy rx_buf_size calculation */\n+\tbufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);\n \tif ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)\t||\n \t (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {\n \t\tif (!dev->data->scattered_rx) {\n@@ -93,13 +138,13 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)\n \t\t}\n \t}\n \n-\tif (dev->data->scattered_rx)\n-\t\trxq->rx_buf_size = bufsz + ETHER_HDR_LEN +\n-\t\t\t\t ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;\n-\telse\n-\t\trxq->rx_buf_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;\n-\t/* Align to cache-line size if needed */\n-\trxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);\n+\trc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);\n+\tif (rc < 0) {\n+\t\trte_free(rxq);\n+\t\treturn rc;\n+\t}\n+\n+\trxq->rx_buf_size = rc;\n \n \tDP_INFO(edev, \"mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\\n\",\n \t\tqdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);\ndiff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h\nindex e710fba..8bd8d1c 100644\n--- a/drivers/net/qede/qede_rxtx.h\n+++ b/drivers/net/qede/qede_rxtx.h\n@@ -61,9 +61,16 @@\n #define QEDE_FW_RX_ALIGN_END\t(1UL << QEDE_RX_ALIGN_SHIFT)\n #define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \\\n \t\t\t\t\t~(QEDE_FW_RX_ALIGN_END - 1))\n-/* Note: QEDE_LLC_SNAP_HDR_LEN is optional */\n-#define QEDE_ETH_OVERHEAD\t(((2 * QEDE_VLAN_TAG_SIZE)) - (ETHER_CRC_LEN) \\\n-\t\t\t\t+ (QEDE_LLC_SNAP_HDR_LEN))\n+#define QEDE_FLOOR_TO_CACHE_LINE_SIZE(n) RTE_ALIGN_FLOOR(n, \\\n+\t\t\t\t\t\t\t QEDE_FW_RX_ALIGN_END)\n+\n+/* Note: QEDE_LLC_SNAP_HDR_LEN is optional,\n+ * +2 is for padding in front of L2 header\n+ */\n+#define QEDE_ETH_OVERHEAD\t(((2 * QEDE_VLAN_TAG_SIZE)) \\\n+\t\t\t\t + (QEDE_LLC_SNAP_HDR_LEN) + 2)\n+\n+#define QEDE_MAX_ETHER_HDR_LEN\t(ETHER_HDR_LEN + QEDE_ETH_OVERHEAD)\n \n #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4\t\t\t|\\\n \t\t\t\t ETH_RSS_NONFRAG_IPV4_TCP\t|\\\n@@ -267,6 +274,8 @@ uint16_t qede_rxtx_pkts_dummy(void *p_rxq,\n int qede_start_queues(struct rte_eth_dev *eth_dev);\n \n void qede_stop_queues(struct rte_eth_dev *eth_dev);\n+int qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,\n+\t\t\t uint16_t max_frame_size);\n \n /* Fastpath resource alloc/dealloc helpers */\n int qede_alloc_fp_resc(struct qede_dev *qdev);\n", "prefixes": [ "14/17" ] }