Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 41037,
    "url": "https://patches.dpdk.org/api/patches/41037/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1528892062-4997-5-git-send-email-tomaszx.jozwiak@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1528892062-4997-5-git-send-email-tomaszx.jozwiak@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1528892062-4997-5-git-send-email-tomaszx.jozwiak@intel.com",
    "date": "2018-06-13T12:13:48",
    "name": "[v3,04/38] crypto/qat: add symmetric session file",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "3cd3be44f5282d60155e49f3262d1f1bf859fc14",
    "submitter": {
        "id": 949,
        "url": "https://patches.dpdk.org/api/people/949/?format=api",
        "name": "Tomasz Jozwiak",
        "email": "tomaszx.jozwiak@intel.com"
    },
    "delegate": {
        "id": 22,
        "url": "https://patches.dpdk.org/api/users/22/?format=api",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1528892062-4997-5-git-send-email-tomaszx.jozwiak@intel.com/mbox/",
    "series": [
        {
            "id": 111,
            "url": "https://patches.dpdk.org/api/series/111/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=111",
            "date": "2018-06-13T12:13:44",
            "name": "crypto/qat: refactor to support multiple services",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/111/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/41037/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/41037/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 482981EE2E;\n\tWed, 13 Jun 2018 14:14:35 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 9A96D1ED87\n\tfor <dev@dpdk.org>; Wed, 13 Jun 2018 14:14:32 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jun 2018 05:14:32 -0700",
            "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:14:30 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,218,1526367600\"; d=\"scan'208\";a=\"63727654\"",
        "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>",
        "To": "fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com,\n\tdev@dpdk.org",
        "Date": "Wed, 13 Jun 2018 14:13:48 +0200",
        "Message-Id": "<1528892062-4997-5-git-send-email-tomaszx.jozwiak@intel.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "References": "<1523040732-3290-1-git-send-email-fiona.trahe@intel.com>\n\t<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 04/38] crypto/qat: add symmetric session file",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nThis commit adds qat_sym_session.c/h files and moves objects\nfrom qat_algs_build_desc and qat_algs.h\n\nFollowing objects were moved:\nqat_adf/qat_algs_build_desc.c => qat_sym_session.c\n- all objects -\nqat_adf/qat_algs.h => qat_sym_session.h\n- enum qat_crypto_proto_flag\n- struct qat_alg_cd\n- struct qat_session\n- int qat_get_inter_state_size()\n- int qat_alg_aead_session_create_content_desc_cipher()\n- int qat_alg_aead_session_create_content_desc_auth()\n- void qat_alg_init_common_hdr()\n- int qat_alg_validate_aes_key()\n- int qat_alg_validate_aes_docsisbpi_key()\n- int qat_alg_validate_snow3g_key()\n- int qat_alg_validate_kasumi_key()\n- int qat_alg_validate_3des_key()\n- int qat_alg_validate_des_key()\n- int qat_cipher_get_block_size()\n- int qat_alg_validate_zuc_key()\n-- all macros\nqat_crypto.h => qat_sym_session.h\nint qat_crypto_sym_configure_session()\nint qat_crypto_set_session_parameters()\nint qat_crypto_sym_configure_session_aead()\nint qat_crypto_sym_configure_session_cipher()\nint qat_crypto_sym_configure_session_auth()\nint qat_alg_aead_session_create_content_desc_cipher()\nint qat_alg_aead_session_create_content_desc_auth()\nstatic struct rte_crypto_auth_xform qat_get_auth_xform()\nstatic struct rte_crypto_cipher_xform qat_get_cipher_xform()\n\nSigned-off-by: ArkadiuszX Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\n---\n drivers/crypto/qat/Makefile                   |   2 +-\n drivers/crypto/qat/meson.build                |   2 +-\n drivers/crypto/qat/qat_crypto.c               | 704 +----------------\n drivers/crypto/qat/qat_crypto.h               |  36 -\n drivers/crypto/qat/qat_qp.c                   |   1 -\n ...at_algs_build_desc.c => qat_sym_session.c} | 728 +++++++++++++++++-\n .../{qat_adf/qat_algs.h => qat_sym_session.h} |  63 +-\n drivers/crypto/qat/rte_qat_cryptodev.c        |   1 +\n 8 files changed, 775 insertions(+), 762 deletions(-)\n rename drivers/crypto/qat/{qat_adf/qat_algs_build_desc.c => qat_sym_session.c} (61%)\n rename drivers/crypto/qat/{qat_adf/qat_algs.h => qat_sym_session.h} (66%)",
    "diff": "diff --git a/drivers/crypto/qat/Makefile b/drivers/crypto/qat/Makefile\nindex 6bdd11679..c63c1515e 100644\n--- a/drivers/crypto/qat/Makefile\n+++ b/drivers/crypto/qat/Makefile\n@@ -24,7 +24,7 @@ LDLIBS += -lrte_pci -lrte_bus_pci\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_crypto.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_device.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_qp.c\n-SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_adf/qat_algs_build_desc.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_sym_session.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += rte_qat_cryptodev.c\n \n # export include files\ndiff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build\nindex 51630e31b..be4282a83 100644\n--- a/drivers/crypto/qat/meson.build\n+++ b/drivers/crypto/qat/meson.build\n@@ -6,7 +6,7 @@ if not dep.found()\n \tbuild = false\n endif\n sources = files('qat_crypto.c', 'qat_qp.c',\n-\t\t'qat_adf/qat_algs_build_desc.c',\n+\t\t'qat_sym_session.c',\n \t\t'rte_qat_cryptodev.c',\n \t\t'qat_device.c')\n includes += include_directories('qat_adf')\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c\nindex 7f2c2c86b..96a1b78f0 100644\n--- a/drivers/crypto/qat/qat_crypto.c\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -13,7 +13,7 @@\n #include <openssl/evp.h>\n \n #include \"qat_logs.h\"\n-#include \"qat_algs.h\"\n+#include \"qat_sym_session.h\"\n #include \"qat_crypto.h\"\n #include \"adf_transport_access_macros.h\"\n \n@@ -23,46 +23,6 @@\n  */\n #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ\n \n-static int\n-qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,\n-\t\tstruct qat_pmd_private *internals) {\n-\tint i = 0;\n-\tconst struct rte_cryptodev_capabilities *capability;\n-\n-\twhile ((capability = &(internals->qat_dev_capabilities[i++]))->op !=\n-\t\t\tRTE_CRYPTO_OP_TYPE_UNDEFINED) {\n-\t\tif (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)\n-\t\t\tcontinue;\n-\n-\t\tif (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)\n-\t\t\tcontinue;\n-\n-\t\tif (capability->sym.cipher.algo == algo)\n-\t\t\treturn 1;\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,\n-\t\tstruct qat_pmd_private *internals) {\n-\tint i = 0;\n-\tconst struct rte_cryptodev_capabilities *capability;\n-\n-\twhile ((capability = &(internals->qat_dev_capabilities[i++]))->op !=\n-\t\t\tRTE_CRYPTO_OP_TYPE_UNDEFINED) {\n-\t\tif (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)\n-\t\t\tcontinue;\n-\n-\t\tif (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)\n-\t\t\tcontinue;\n-\n-\t\tif (capability->sym.auth.algo == algo)\n-\t\t\treturn 1;\n-\t}\n-\treturn 0;\n-}\n-\n /** Encrypt a single partial block\n  *  Depends on openssl libcrypto\n  *  Uses ECB+XOR to do CFB encryption, same result, more performant\n@@ -124,49 +84,6 @@ bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,\n /** Creates a context in either AES or DES in ECB mode\n  *  Depends on openssl libcrypto\n  */\n-static int\n-bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,\n-\t\tenum rte_crypto_cipher_operation direction __rte_unused,\n-\t\tuint8_t *key, void **ctx)\n-{\n-\tconst EVP_CIPHER *algo = NULL;\n-\tint ret;\n-\t*ctx = EVP_CIPHER_CTX_new();\n-\n-\tif (*ctx == NULL) {\n-\t\tret = -ENOMEM;\n-\t\tgoto ctx_init_err;\n-\t}\n-\n-\tif (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)\n-\t\talgo = EVP_des_ecb();\n-\telse\n-\t\talgo = EVP_aes_128_ecb();\n-\n-\t/* IV will be ECB encrypted whether direction is encrypt or decrypt*/\n-\tif (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {\n-\t\tret = -EINVAL;\n-\t\tgoto ctx_init_err;\n-\t}\n-\n-\treturn 0;\n-\n-ctx_init_err:\n-\tif (*ctx != NULL)\n-\t\tEVP_CIPHER_CTX_free(*ctx);\n-\treturn ret;\n-}\n-\n-/** Frees a context previously created\n- *  Depends on openssl libcrypto\n- */\n-static void\n-bpi_cipher_ctx_free(void *bpi_ctx)\n-{\n-\tif (bpi_ctx != NULL)\n-\t\tEVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);\n-}\n-\n static inline uint32_t\n adf_modulo(uint32_t data, uint32_t shift);\n \n@@ -174,625 +91,6 @@ static inline int\n qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\tstruct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);\n \n-void\n-qat_crypto_sym_clear_session(struct rte_cryptodev *dev,\n-\t\tstruct rte_cryptodev_sym_session *sess)\n-{\n-\tPMD_INIT_FUNC_TRACE();\n-\tuint8_t index = dev->driver_id;\n-\tvoid *sess_priv = get_session_private_data(sess, index);\n-\tstruct qat_session *s = (struct qat_session *)sess_priv;\n-\n-\tif (sess_priv) {\n-\t\tif (s->bpi_ctx)\n-\t\t\tbpi_cipher_ctx_free(s->bpi_ctx);\n-\t\tmemset(s, 0, qat_crypto_sym_get_session_private_size(dev));\n-\t\tstruct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);\n-\t\tset_session_private_data(sess, index, NULL);\n-\t\trte_mempool_put(sess_mp, sess_priv);\n-\t}\n-}\n-\n-static int\n-qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)\n-{\n-\t/* Cipher Only */\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)\n-\t\treturn ICP_QAT_FW_LA_CMD_CIPHER;\n-\n-\t/* Authentication Only */\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)\n-\t\treturn ICP_QAT_FW_LA_CMD_AUTH;\n-\n-\t/* AEAD */\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\t/* AES-GCM and AES-CCM works with different direction\n-\t\t * GCM first encrypts and generate hash where AES-CCM\n-\t\t * first generate hash and encrypts. Similar relation\n-\t\t * applies to decryption.\n-\t\t */\n-\t\tif (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)\n-\t\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n-\t\t\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n-\t\t\telse\n-\t\t\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n-\t\telse\n-\t\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n-\t\t\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n-\t\t\telse\n-\t\t\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n-\t}\n-\n-\tif (xform->next == NULL)\n-\t\treturn -1;\n-\n-\t/* Cipher then Authenticate */\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n-\t\t\txform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)\n-\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n-\n-\t/* Authenticate then Cipher */\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n-\t\t\txform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n-\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n-\n-\treturn -1;\n-}\n-\n-static struct rte_crypto_auth_xform *\n-qat_get_auth_xform(struct rte_crypto_sym_xform *xform)\n-{\n-\tdo {\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)\n-\t\t\treturn &xform->auth;\n-\n-\t\txform = xform->next;\n-\t} while (xform);\n-\n-\treturn NULL;\n-}\n-\n-static struct rte_crypto_cipher_xform *\n-qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)\n-{\n-\tdo {\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n-\t\t\treturn &xform->cipher;\n-\n-\t\txform = xform->next;\n-\t} while (xform);\n-\n-\treturn NULL;\n-}\n-\n-int\n-qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_sym_xform *xform,\n-\t\tstruct qat_session *session)\n-{\n-\tstruct qat_pmd_private *internals = dev->data->dev_private;\n-\tstruct rte_crypto_cipher_xform *cipher_xform = NULL;\n-\tint ret;\n-\n-\t/* Get cipher xform from crypto xform chain */\n-\tcipher_xform = qat_get_cipher_xform(xform);\n-\n-\tsession->cipher_iv.offset = cipher_xform->iv.offset;\n-\tsession->cipher_iv.length = cipher_xform->iv.length;\n-\n-\tswitch (cipher_xform->algo) {\n-\tcase RTE_CRYPTO_CIPHER_AES_CBC:\n-\t\tif (qat_alg_validate_aes_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_AES_CTR:\n-\t\tif (qat_alg_validate_aes_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_SNOW3G_UEA2:\n-\t\tif (qat_alg_validate_snow3g_key(cipher_xform->key.length,\n-\t\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid SNOW 3G cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_NULL:\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_KASUMI_F8:\n-\t\tif (qat_alg_validate_kasumi_key(cipher_xform->key.length,\n-\t\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid KASUMI cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_3DES_CBC:\n-\t\tif (qat_alg_validate_3des_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid 3DES cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_DES_CBC:\n-\t\tif (qat_alg_validate_des_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid DES cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_3DES_CTR:\n-\t\tif (qat_alg_validate_3des_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid 3DES cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_DES_DOCSISBPI:\n-\t\tret = bpi_cipher_ctx_init(\n-\t\t\t\t\tcipher_xform->algo,\n-\t\t\t\t\tcipher_xform->op,\n-\t\t\t\t\tcipher_xform->key.data,\n-\t\t\t\t\t&session->bpi_ctx);\n-\t\tif (ret != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"failed to create DES BPI ctx\");\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tif (qat_alg_validate_des_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid DES cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_AES_DOCSISBPI:\n-\t\tret = bpi_cipher_ctx_init(\n-\t\t\t\t\tcipher_xform->algo,\n-\t\t\t\t\tcipher_xform->op,\n-\t\t\t\t\tcipher_xform->key.data,\n-\t\t\t\t\t&session->bpi_ctx);\n-\t\tif (ret != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"failed to create AES BPI ctx\");\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tif (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES DOCSISBPI key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_ZUC_EEA3:\n-\t\tif (!qat_is_cipher_alg_supported(\n-\t\t\tcipher_xform->algo, internals)) {\n-\t\t\tPMD_DRV_LOG(ERR, \"%s not supported on this device\",\n-\t\t\t\trte_crypto_cipher_algorithm_strings\n-\t\t\t\t\t[cipher_xform->algo]);\n-\t\t\tret = -ENOTSUP;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tif (qat_alg_validate_zuc_key(cipher_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid ZUC cipher key size\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_CIPHER_3DES_ECB:\n-\tcase RTE_CRYPTO_CIPHER_AES_ECB:\n-\tcase RTE_CRYPTO_CIPHER_AES_F8:\n-\tcase RTE_CRYPTO_CIPHER_AES_XTS:\n-\tcase RTE_CRYPTO_CIPHER_ARC4:\n-\t\tPMD_DRV_LOG(ERR, \"Crypto QAT PMD: Unsupported Cipher alg %u\",\n-\t\t\t\tcipher_xform->algo);\n-\t\tret = -ENOTSUP;\n-\t\tgoto error_out;\n-\tdefault:\n-\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined Cipher specified %u\\n\",\n-\t\t\t\tcipher_xform->algo);\n-\t\tret = -EINVAL;\n-\t\tgoto error_out;\n-\t}\n-\n-\tif (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n-\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n-\telse\n-\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n-\n-\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n-\t\t\t\t\t\tcipher_xform->key.data,\n-\t\t\t\t\t\tcipher_xform->key.length)) {\n-\t\tret = -EINVAL;\n-\t\tgoto error_out;\n-\t}\n-\n-\treturn 0;\n-\n-error_out:\n-\tif (session->bpi_ctx) {\n-\t\tbpi_cipher_ctx_free(session->bpi_ctx);\n-\t\tsession->bpi_ctx = NULL;\n-\t}\n-\treturn ret;\n-}\n-\n-int\n-qat_crypto_sym_configure_session(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_sym_xform *xform,\n-\t\tstruct rte_cryptodev_sym_session *sess,\n-\t\tstruct rte_mempool *mempool)\n-{\n-\tvoid *sess_private_data;\n-\tint ret;\n-\n-\tif (rte_mempool_get(mempool, &sess_private_data)) {\n-\t\tCDEV_LOG_ERR(\n-\t\t\t\"Couldn't get object from session mempool\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);\n-\tif (ret != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"Crypto QAT PMD: failed to configure \"\n-\t\t\t\t\"session parameters\");\n-\n-\t\t/* Return session to mempool */\n-\t\trte_mempool_put(mempool, sess_private_data);\n-\t\treturn ret;\n-\t}\n-\n-\tset_session_private_data(sess, dev->driver_id,\n-\t\tsess_private_data);\n-\n-\treturn 0;\n-}\n-\n-int\n-qat_crypto_set_session_parameters(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_sym_xform *xform, void *session_private)\n-{\n-\tstruct qat_session *session = session_private;\n-\tint ret;\n-\n-\tint qat_cmd_id;\n-\tPMD_INIT_FUNC_TRACE();\n-\n-\t/* Set context descriptor physical address */\n-\tsession->cd_paddr = rte_mempool_virt2iova(session) +\n-\t\t\toffsetof(struct qat_session, cd);\n-\n-\tsession->min_qat_dev_gen = QAT_GEN1;\n-\n-\t/* Get requested QAT command id */\n-\tqat_cmd_id = qat_get_cmd_id(xform);\n-\tif (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {\n-\t\tPMD_DRV_LOG(ERR, \"Unsupported xform chain requested\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\tsession->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;\n-\tswitch (session->qat_cmd) {\n-\tcase ICP_QAT_FW_LA_CMD_CIPHER:\n-\t\tret = qat_crypto_sym_configure_session_cipher(dev, xform, session);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t\tbreak;\n-\tcase ICP_QAT_FW_LA_CMD_AUTH:\n-\t\tret = qat_crypto_sym_configure_session_auth(dev, xform, session);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t\tbreak;\n-\tcase ICP_QAT_FW_LA_CMD_CIPHER_HASH:\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\t\tret = qat_crypto_sym_configure_session_aead(xform,\n-\t\t\t\t\tsession);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t} else {\n-\t\t\tret = qat_crypto_sym_configure_session_cipher(dev,\n-\t\t\t\t\txform, session);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t\tret = qat_crypto_sym_configure_session_auth(dev,\n-\t\t\t\t\txform, session);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t}\n-\t\tbreak;\n-\tcase ICP_QAT_FW_LA_CMD_HASH_CIPHER:\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\t\tret = qat_crypto_sym_configure_session_aead(xform,\n-\t\t\t\t\tsession);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t} else {\n-\t\t\tret = qat_crypto_sym_configure_session_auth(dev,\n-\t\t\t\t\txform, session);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t\tret = qat_crypto_sym_configure_session_cipher(dev,\n-\t\t\t\t\txform, session);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t}\n-\t\tbreak;\n-\tcase ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:\n-\tcase ICP_QAT_FW_LA_CMD_TRNG_TEST:\n-\tcase ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:\n-\tcase ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:\n-\tcase ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:\n-\tcase ICP_QAT_FW_LA_CMD_MGF1:\n-\tcase ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:\n-\tcase ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:\n-\tcase ICP_QAT_FW_LA_CMD_DELIMITER:\n-\tPMD_DRV_LOG(ERR, \"Unsupported Service %u\",\n-\t\tsession->qat_cmd);\n-\t\treturn -ENOTSUP;\n-\tdefault:\n-\tPMD_DRV_LOG(ERR, \"Unsupported Service %u\",\n-\t\tsession->qat_cmd);\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,\n-\t\t\t\tstruct rte_crypto_sym_xform *xform,\n-\t\t\t\tstruct qat_session *session)\n-{\n-\tstruct rte_crypto_auth_xform *auth_xform = NULL;\n-\tstruct qat_pmd_private *internals = dev->data->dev_private;\n-\tauth_xform = qat_get_auth_xform(xform);\n-\tuint8_t *key_data = auth_xform->key.data;\n-\tuint8_t key_length = auth_xform->key.length;\n-\n-\tswitch (auth_xform->algo) {\n-\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n-\t\tif (qat_alg_validate_aes_key(auth_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES key size\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n-\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_NULL:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_KASUMI_F9:\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_ZUC_EIA3:\n-\t\tif (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {\n-\t\t\tPMD_DRV_LOG(ERR, \"%s not supported on this device\",\n-\t\t\t\trte_crypto_auth_algorithm_strings\n-\t\t\t\t[auth_xform->algo]);\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_SHA1:\n-\tcase RTE_CRYPTO_AUTH_SHA256:\n-\tcase RTE_CRYPTO_AUTH_SHA512:\n-\tcase RTE_CRYPTO_AUTH_SHA224:\n-\tcase RTE_CRYPTO_AUTH_SHA384:\n-\tcase RTE_CRYPTO_AUTH_MD5:\n-\tcase RTE_CRYPTO_AUTH_AES_CMAC:\n-\tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n-\t\tPMD_DRV_LOG(ERR, \"Crypto: Unsupported hash alg %u\",\n-\t\t\t\tauth_xform->algo);\n-\t\treturn -ENOTSUP;\n-\tdefault:\n-\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined Hash algo %u specified\",\n-\t\t\t\tauth_xform->algo);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tsession->auth_iv.offset = auth_xform->iv.offset;\n-\tsession->auth_iv.length = auth_xform->iv.length;\n-\n-\tif (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {\n-\t\tif (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {\n-\t\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n-\t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n-\t\t\t/*\n-\t\t\t * It needs to create cipher desc content first,\n-\t\t\t * then authentication\n-\t\t\t */\n-\t\t\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n-\t\t\t\t\t\tauth_xform->key.data,\n-\t\t\t\t\t\tauth_xform->key.length))\n-\t\t\t\treturn -EINVAL;\n-\n-\t\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n-\t\t\t\t\t\tkey_data,\n-\t\t\t\t\t\tkey_length,\n-\t\t\t\t\t\t0,\n-\t\t\t\t\t\tauth_xform->digest_length,\n-\t\t\t\t\t\tauth_xform->op))\n-\t\t\t\treturn -EINVAL;\n-\t\t} else {\n-\t\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n-\t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n-\t\t\t/*\n-\t\t\t * It needs to create authentication desc content first,\n-\t\t\t * then cipher\n-\t\t\t */\n-\t\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n-\t\t\t\t\tkey_data,\n-\t\t\t\t\tkey_length,\n-\t\t\t\t\t0,\n-\t\t\t\t\tauth_xform->digest_length,\n-\t\t\t\t\tauth_xform->op))\n-\t\t\t\treturn -EINVAL;\n-\n-\t\t\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n-\t\t\t\t\t\tauth_xform->key.data,\n-\t\t\t\t\t\tauth_xform->key.length))\n-\t\t\t\treturn -EINVAL;\n-\t\t}\n-\t\t/* Restore to authentication only only */\n-\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;\n-\t} else {\n-\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n-\t\t\t\tkey_data,\n-\t\t\t\tkey_length,\n-\t\t\t\t0,\n-\t\t\t\tauth_xform->digest_length,\n-\t\t\t\tauth_xform->op))\n-\t\t\treturn -EINVAL;\n-\t}\n-\n-\tsession->digest_length = auth_xform->digest_length;\n-\treturn 0;\n-}\n-\n-int\n-qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,\n-\t\t\t\tstruct qat_session *session)\n-{\n-\tstruct rte_crypto_aead_xform *aead_xform = &xform->aead;\n-\tenum rte_crypto_auth_operation crypto_operation;\n-\n-\t/*\n-\t * Store AEAD IV parameters as cipher IV,\n-\t * to avoid unnecessary memory usage\n-\t */\n-\tsession->cipher_iv.offset = xform->aead.iv.offset;\n-\tsession->cipher_iv.length = xform->aead.iv.length;\n-\n-\tswitch (aead_xform->algo) {\n-\tcase RTE_CRYPTO_AEAD_AES_GCM:\n-\t\tif (qat_alg_validate_aes_key(aead_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES key size\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_AEAD_AES_CCM:\n-\t\tif (qat_alg_validate_aes_key(aead_xform->key.length,\n-\t\t\t\t&session->qat_cipher_alg) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES key size\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;\n-\t\tbreak;\n-\tdefault:\n-\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined AEAD specified %u\\n\",\n-\t\t\t\taead_xform->algo);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&\n-\t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||\n-\t\t\t(aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&\n-\t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_CCM)) {\n-\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n-\t\t/*\n-\t\t * It needs to create cipher desc content first,\n-\t\t * then authentication\n-\t\t */\n-\n-\t\tcrypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?\n-\t\t\tRTE_CRYPTO_AUTH_OP_GENERATE : RTE_CRYPTO_AUTH_OP_VERIFY;\n-\n-\t\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n-\t\t\t\t\taead_xform->key.data,\n-\t\t\t\t\taead_xform->key.length))\n-\t\t\treturn -EINVAL;\n-\n-\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n-\t\t\t\t\taead_xform->key.data,\n-\t\t\t\t\taead_xform->key.length,\n-\t\t\t\t\taead_xform->aad_length,\n-\t\t\t\t\taead_xform->digest_length,\n-\t\t\t\t\tcrypto_operation))\n-\t\t\treturn -EINVAL;\n-\t} else {\n-\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n-\t\t/*\n-\t\t * It needs to create authentication desc content first,\n-\t\t * then cipher\n-\t\t */\n-\n-\t\tcrypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?\n-\t\t\tRTE_CRYPTO_AUTH_OP_VERIFY : RTE_CRYPTO_AUTH_OP_GENERATE;\n-\n-\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n-\t\t\t\t\taead_xform->key.data,\n-\t\t\t\t\taead_xform->key.length,\n-\t\t\t\t\taead_xform->aad_length,\n-\t\t\t\t\taead_xform->digest_length,\n-\t\t\t\t\tcrypto_operation))\n-\t\t\treturn -EINVAL;\n-\n-\t\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n-\t\t\t\t\taead_xform->key.data,\n-\t\t\t\t\taead_xform->key.length))\n-\t\t\treturn -EINVAL;\n-\t}\n-\n-\tsession->digest_length = aead_xform->digest_length;\n-\treturn 0;\n-}\n-\n-unsigned qat_crypto_sym_get_session_private_size(\n-\t\tstruct rte_cryptodev *dev __rte_unused)\n-{\n-\treturn RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);\n-}\n-\n static inline uint32_t\n qat_bpicipher_preprocess(struct qat_session *ctx,\n \t\t\t\tstruct rte_crypto_op *op)\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 46f03ccde..e3873171c 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -75,42 +75,6 @@ int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,\n int qat_crypto_sym_qp_release(struct rte_cryptodev *dev,\n \tuint16_t queue_pair_id);\n \n-int\n-qat_pmd_session_mempool_create(struct rte_cryptodev *dev,\n-\tunsigned nb_objs, unsigned obj_cache_size, int socket_id);\n-\n-extern unsigned\n-qat_crypto_sym_get_session_private_size(struct rte_cryptodev *dev);\n-\n-extern int\n-qat_crypto_sym_configure_session(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_sym_xform *xform,\n-\t\tstruct rte_cryptodev_sym_session *sess,\n-\t\tstruct rte_mempool *mempool);\n-\n-\n-int\n-qat_crypto_set_session_parameters(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_sym_xform *xform, void *session_private);\n-\n-int\n-qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,\n-\t\t\t\tstruct qat_session *session);\n-\n-int\n-qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,\n-\t\t\t\tstruct rte_crypto_sym_xform *xform,\n-\t\t\t\tstruct qat_session *session);\n-\n-int\n-qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_sym_xform *xform,\n-\t\tstruct qat_session *session);\n-\n-\n-extern void\n-qat_crypto_sym_clear_session(struct rte_cryptodev *dev,\n-\t\tstruct rte_cryptodev_sym_session *session);\n \n extern uint16_t\n qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\ndiff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nindex 7fea10c76..ee3b30a36 100644\n--- a/drivers/crypto/qat/qat_qp.c\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -14,7 +14,6 @@\n \n #include \"qat_logs.h\"\n #include \"qat_crypto.h\"\n-#include \"qat_algs.h\"\n #include \"adf_transport_access_macros.h\"\n \n #define ADF_MAX_SYM_DESC\t\t\t4096\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_sym_session.c\nsimilarity index 61%\nrename from drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\nrename to drivers/crypto/qat/qat_sym_session.c\nindex c87ed40fe..5caac5a6f 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -9,13 +9,724 @@\n #include <rte_malloc.h>\n #include <rte_crypto_sym.h>\n \n-#include \"../qat_logs.h\"\n+#include \"qat_logs.h\"\n+#include \"qat_device.h\"\n \n #include <openssl/sha.h>\t/* Needed to calculate pre-compute values */\n #include <openssl/aes.h>\t/* Needed to calculate pre-compute values */\n #include <openssl/md5.h>\t/* Needed to calculate pre-compute values */\n+#include <openssl/evp.h>\n \n-#include \"qat_algs.h\"\n+#include \"qat_sym_session.h\"\n+\n+/** Frees a context previously created\n+ *  Depends on openssl libcrypto\n+ */\n+static void\n+bpi_cipher_ctx_free(void *bpi_ctx)\n+{\n+\tif (bpi_ctx != NULL)\n+\t\tEVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);\n+}\n+\n+static int\n+bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,\n+\t\tenum rte_crypto_cipher_operation direction __rte_unused,\n+\t\tuint8_t *key, void **ctx)\n+{\n+\tconst EVP_CIPHER *algo = NULL;\n+\tint ret;\n+\t*ctx = EVP_CIPHER_CTX_new();\n+\n+\tif (*ctx == NULL) {\n+\t\tret = -ENOMEM;\n+\t\tgoto ctx_init_err;\n+\t}\n+\n+\tif (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)\n+\t\talgo = EVP_des_ecb();\n+\telse\n+\t\talgo = EVP_aes_128_ecb();\n+\n+\t/* IV will be ECB encrypted whether direction is encrypt or decrypt*/\n+\tif (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {\n+\t\tret = -EINVAL;\n+\t\tgoto ctx_init_err;\n+\t}\n+\n+\treturn 0;\n+\n+ctx_init_err:\n+\tif (*ctx != NULL)\n+\t\tEVP_CIPHER_CTX_free(*ctx);\n+\treturn ret;\n+}\n+\n+static int\n+qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,\n+\t\tstruct qat_pmd_private *internals)\n+{\n+\tint i = 0;\n+\tconst struct rte_cryptodev_capabilities *capability;\n+\n+\twhile ((capability = &(internals->qat_dev_capabilities[i++]))->op !=\n+\t\t\tRTE_CRYPTO_OP_TYPE_UNDEFINED) {\n+\t\tif (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)\n+\t\t\tcontinue;\n+\n+\t\tif (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\t\tcontinue;\n+\n+\t\tif (capability->sym.cipher.algo == algo)\n+\t\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,\n+\t\tstruct qat_pmd_private *internals)\n+{\n+\tint i = 0;\n+\tconst struct rte_cryptodev_capabilities *capability;\n+\n+\twhile ((capability = &(internals->qat_dev_capabilities[i++]))->op !=\n+\t\t\tRTE_CRYPTO_OP_TYPE_UNDEFINED) {\n+\t\tif (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)\n+\t\t\tcontinue;\n+\n+\t\tif (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)\n+\t\t\tcontinue;\n+\n+\t\tif (capability->sym.auth.algo == algo)\n+\t\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+void\n+qat_crypto_sym_clear_session(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_sym_session *sess)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tuint8_t index = dev->driver_id;\n+\tvoid *sess_priv = get_session_private_data(sess, index);\n+\tstruct qat_session *s = (struct qat_session *)sess_priv;\n+\n+\tif (sess_priv) {\n+\t\tif (s->bpi_ctx)\n+\t\t\tbpi_cipher_ctx_free(s->bpi_ctx);\n+\t\tmemset(s, 0, qat_crypto_sym_get_session_private_size(dev));\n+\t\tstruct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);\n+\n+\t\tset_session_private_data(sess, index, NULL);\n+\t\trte_mempool_put(sess_mp, sess_priv);\n+\t}\n+}\n+\n+static int\n+qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)\n+{\n+\t/* Cipher Only */\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)\n+\t\treturn ICP_QAT_FW_LA_CMD_CIPHER;\n+\n+\t/* Authentication Only */\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)\n+\t\treturn ICP_QAT_FW_LA_CMD_AUTH;\n+\n+\t/* AEAD */\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n+\t\t/* AES-GCM and AES-CCM works with different direction\n+\t\t * GCM first encrypts and generate hash where AES-CCM\n+\t\t * first generate hash and encrypts. Similar relation\n+\t\t * applies to decryption.\n+\t\t */\n+\t\tif (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)\n+\t\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n+\t\t\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n+\t\t\telse\n+\t\t\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n+\t\telse\n+\t\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n+\t\t\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n+\t\t\telse\n+\t\t\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n+\t}\n+\n+\tif (xform->next == NULL)\n+\t\treturn -1;\n+\n+\t/* Cipher then Authenticate */\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n+\t\t\txform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)\n+\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n+\n+\t/* Authenticate then Cipher */\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n+\t\t\txform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n+\n+\treturn -1;\n+}\n+\n+static struct rte_crypto_auth_xform *\n+qat_get_auth_xform(struct rte_crypto_sym_xform *xform)\n+{\n+\tdo {\n+\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)\n+\t\t\treturn &xform->auth;\n+\n+\t\txform = xform->next;\n+\t} while (xform);\n+\n+\treturn NULL;\n+}\n+\n+static struct rte_crypto_cipher_xform *\n+qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)\n+{\n+\tdo {\n+\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\t\treturn &xform->cipher;\n+\n+\t\txform = xform->next;\n+\t} while (xform);\n+\n+\treturn NULL;\n+}\n+\n+int\n+qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_sym_xform *xform,\n+\t\tstruct qat_session *session)\n+{\n+\tstruct qat_pmd_private *internals = dev->data->dev_private;\n+\tstruct rte_crypto_cipher_xform *cipher_xform = NULL;\n+\tint ret;\n+\n+\t/* Get cipher xform from crypto xform chain */\n+\tcipher_xform = qat_get_cipher_xform(xform);\n+\n+\tsession->cipher_iv.offset = cipher_xform->iv.offset;\n+\tsession->cipher_iv.length = cipher_xform->iv.length;\n+\n+\tswitch (cipher_xform->algo) {\n+\tcase RTE_CRYPTO_CIPHER_AES_CBC:\n+\t\tif (qat_alg_validate_aes_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_CTR:\n+\t\tif (qat_alg_validate_aes_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_SNOW3G_UEA2:\n+\t\tif (qat_alg_validate_snow3g_key(cipher_xform->key.length,\n+\t\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid SNOW 3G cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_NULL:\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_KASUMI_F8:\n+\t\tif (qat_alg_validate_kasumi_key(cipher_xform->key.length,\n+\t\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid KASUMI cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_CBC:\n+\t\tif (qat_alg_validate_3des_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid 3DES cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_DES_CBC:\n+\t\tif (qat_alg_validate_des_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid DES cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_CTR:\n+\t\tif (qat_alg_validate_3des_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid 3DES cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_DES_DOCSISBPI:\n+\t\tret = bpi_cipher_ctx_init(\n+\t\t\t\t\tcipher_xform->algo,\n+\t\t\t\t\tcipher_xform->op,\n+\t\t\t\t\tcipher_xform->key.data,\n+\t\t\t\t\t&session->bpi_ctx);\n+\t\tif (ret != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"failed to create DES BPI ctx\");\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tif (qat_alg_validate_des_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid DES cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_DOCSISBPI:\n+\t\tret = bpi_cipher_ctx_init(\n+\t\t\t\t\tcipher_xform->algo,\n+\t\t\t\t\tcipher_xform->op,\n+\t\t\t\t\tcipher_xform->key.data,\n+\t\t\t\t\t&session->bpi_ctx);\n+\t\tif (ret != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"failed to create AES BPI ctx\");\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tif (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES DOCSISBPI key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_ZUC_EEA3:\n+\t\tif (!qat_is_cipher_alg_supported(\n+\t\t\tcipher_xform->algo, internals)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"%s not supported on this device\",\n+\t\t\t\trte_crypto_cipher_algorithm_strings\n+\t\t\t\t\t[cipher_xform->algo]);\n+\t\t\tret = -ENOTSUP;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tif (qat_alg_validate_zuc_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid ZUC cipher key size\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_ECB:\n+\tcase RTE_CRYPTO_CIPHER_AES_ECB:\n+\tcase RTE_CRYPTO_CIPHER_AES_F8:\n+\tcase RTE_CRYPTO_CIPHER_AES_XTS:\n+\tcase RTE_CRYPTO_CIPHER_ARC4:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto QAT PMD: Unsupported Cipher alg %u\",\n+\t\t\t\tcipher_xform->algo);\n+\t\tret = -ENOTSUP;\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined Cipher specified %u\\n\",\n+\t\t\t\tcipher_xform->algo);\n+\t\tret = -EINVAL;\n+\t\tgoto error_out;\n+\t}\n+\n+\tif (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n+\telse\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n+\n+\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n+\t\t\t\t\t\tcipher_xform->key.data,\n+\t\t\t\t\t\tcipher_xform->key.length)) {\n+\t\tret = -EINVAL;\n+\t\tgoto error_out;\n+\t}\n+\n+\treturn 0;\n+\n+error_out:\n+\tif (session->bpi_ctx) {\n+\t\tbpi_cipher_ctx_free(session->bpi_ctx);\n+\t\tsession->bpi_ctx = NULL;\n+\t}\n+\treturn ret;\n+}\n+\n+int\n+qat_crypto_sym_configure_session(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_sym_xform *xform,\n+\t\tstruct rte_cryptodev_sym_session *sess,\n+\t\tstruct rte_mempool *mempool)\n+{\n+\tvoid *sess_private_data;\n+\tint ret;\n+\n+\tif (rte_mempool_get(mempool, &sess_private_data)) {\n+\t\tCDEV_LOG_ERR(\n+\t\t\t\"Couldn't get object from session mempool\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t    \"Crypto QAT PMD: failed to configure session parameters\");\n+\n+\t\t/* Return session to mempool */\n+\t\trte_mempool_put(mempool, sess_private_data);\n+\t\treturn ret;\n+\t}\n+\n+\tset_session_private_data(sess, dev->driver_id,\n+\t\tsess_private_data);\n+\n+\treturn 0;\n+}\n+\n+int\n+qat_crypto_set_session_parameters(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_sym_xform *xform, void *session_private)\n+{\n+\tstruct qat_session *session = session_private;\n+\tint ret;\n+\tint qat_cmd_id;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Set context descriptor physical address */\n+\tsession->cd_paddr = rte_mempool_virt2iova(session) +\n+\t\t\toffsetof(struct qat_session, cd);\n+\n+\tsession->min_qat_dev_gen = QAT_GEN1;\n+\n+\t/* Get requested QAT command id */\n+\tqat_cmd_id = qat_get_cmd_id(xform);\n+\tif (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {\n+\t\tPMD_DRV_LOG(ERR, \"Unsupported xform chain requested\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tsession->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;\n+\tswitch (session->qat_cmd) {\n+\tcase ICP_QAT_FW_LA_CMD_CIPHER:\n+\t\tret = qat_crypto_sym_configure_session_cipher(dev,\n+\t\t\t\t\t\t\txform, session);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tbreak;\n+\tcase ICP_QAT_FW_LA_CMD_AUTH:\n+\t\tret = qat_crypto_sym_configure_session_auth(dev,\n+\t\t\t\t\t\t\txform, session);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tbreak;\n+\tcase ICP_QAT_FW_LA_CMD_CIPHER_HASH:\n+\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n+\t\t\tret = qat_crypto_sym_configure_session_aead(xform,\n+\t\t\t\t\tsession);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t} else {\n+\t\t\tret = qat_crypto_sym_configure_session_cipher(dev,\n+\t\t\t\t\txform, session);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tret = qat_crypto_sym_configure_session_auth(dev,\n+\t\t\t\t\txform, session);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t\tbreak;\n+\tcase ICP_QAT_FW_LA_CMD_HASH_CIPHER:\n+\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n+\t\t\tret = qat_crypto_sym_configure_session_aead(xform,\n+\t\t\t\t\tsession);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t} else {\n+\t\t\tret = qat_crypto_sym_configure_session_auth(dev,\n+\t\t\t\t\txform, session);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tret = qat_crypto_sym_configure_session_cipher(dev,\n+\t\t\t\t\txform, session);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t\tbreak;\n+\tcase ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:\n+\tcase ICP_QAT_FW_LA_CMD_TRNG_TEST:\n+\tcase ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:\n+\tcase ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:\n+\tcase ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:\n+\tcase ICP_QAT_FW_LA_CMD_MGF1:\n+\tcase ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:\n+\tcase ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:\n+\tcase ICP_QAT_FW_LA_CMD_DELIMITER:\n+\tPMD_DRV_LOG(ERR, \"Unsupported Service %u\",\n+\t\tsession->qat_cmd);\n+\t\treturn -ENOTSUP;\n+\tdefault:\n+\tPMD_DRV_LOG(ERR, \"Unsupported Service %u\",\n+\t\tsession->qat_cmd);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,\n+\t\t\t\tstruct rte_crypto_sym_xform *xform,\n+\t\t\t\tstruct qat_session *session)\n+{\n+\tstruct rte_crypto_auth_xform *auth_xform = qat_get_auth_xform(xform);\n+\tstruct qat_pmd_private *internals = dev->data->dev_private;\n+\tuint8_t *key_data = auth_xform->key.data;\n+\tuint8_t key_length = auth_xform->key.length;\n+\n+\tswitch (auth_xform->algo) {\n+\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n+\t\tif (qat_alg_validate_aes_key(auth_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES key size\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n+\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_NULL:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_KASUMI_F9:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_ZUC_EIA3:\n+\t\tif (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"%s not supported on this device\",\n+\t\t\t\trte_crypto_auth_algorithm_strings\n+\t\t\t\t[auth_xform->algo]);\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA1:\n+\tcase RTE_CRYPTO_AUTH_SHA256:\n+\tcase RTE_CRYPTO_AUTH_SHA512:\n+\tcase RTE_CRYPTO_AUTH_SHA224:\n+\tcase RTE_CRYPTO_AUTH_SHA384:\n+\tcase RTE_CRYPTO_AUTH_MD5:\n+\tcase RTE_CRYPTO_AUTH_AES_CMAC:\n+\tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Unsupported hash alg %u\",\n+\t\t\t\tauth_xform->algo);\n+\t\treturn -ENOTSUP;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined Hash algo %u specified\",\n+\t\t\t\tauth_xform->algo);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsession->auth_iv.offset = auth_xform->iv.offset;\n+\tsession->auth_iv.length = auth_xform->iv.length;\n+\n+\tif (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {\n+\t\tif (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {\n+\t\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n+\t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n+\t\t\t/*\n+\t\t\t * It needs to create cipher desc content first,\n+\t\t\t * then authentication\n+\t\t\t */\n+\t\t\tif (qat_alg_aead_session_create_content_desc_cipher(\n+\t\t\t\t\t\tsession,\n+\t\t\t\t\t\tauth_xform->key.data,\n+\t\t\t\t\t\tauth_xform->key.length))\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tif (qat_alg_aead_session_create_content_desc_auth(\n+\t\t\t\t\t\tsession,\n+\t\t\t\t\t\tkey_data,\n+\t\t\t\t\t\tkey_length,\n+\t\t\t\t\t\t0,\n+\t\t\t\t\t\tauth_xform->digest_length,\n+\t\t\t\t\t\tauth_xform->op))\n+\t\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n+\t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n+\t\t\t/*\n+\t\t\t * It needs to create authentication desc content first,\n+\t\t\t * then cipher\n+\t\t\t */\n+\t\t\tif (qat_alg_aead_session_create_content_desc_auth(\n+\t\t\t\t\tsession,\n+\t\t\t\t\tkey_data,\n+\t\t\t\t\tkey_length,\n+\t\t\t\t\t0,\n+\t\t\t\t\tauth_xform->digest_length,\n+\t\t\t\t\tauth_xform->op))\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tif (qat_alg_aead_session_create_content_desc_cipher(\n+\t\t\t\t\t\tsession,\n+\t\t\t\t\t\tauth_xform->key.data,\n+\t\t\t\t\t\tauth_xform->key.length))\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t\t/* Restore to authentication only only */\n+\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;\n+\t} else {\n+\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n+\t\t\t\tkey_data,\n+\t\t\t\tkey_length,\n+\t\t\t\t0,\n+\t\t\t\tauth_xform->digest_length,\n+\t\t\t\tauth_xform->op))\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tsession->digest_length = auth_xform->digest_length;\n+\treturn 0;\n+}\n+\n+int\n+qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,\n+\t\t\t\tstruct qat_session *session)\n+{\n+\tstruct rte_crypto_aead_xform *aead_xform = &xform->aead;\n+\tenum rte_crypto_auth_operation crypto_operation;\n+\n+\t/*\n+\t * Store AEAD IV parameters as cipher IV,\n+\t * to avoid unnecessary memory usage\n+\t */\n+\tsession->cipher_iv.offset = xform->aead.iv.offset;\n+\tsession->cipher_iv.length = xform->aead.iv.length;\n+\n+\tswitch (aead_xform->algo) {\n+\tcase RTE_CRYPTO_AEAD_AES_GCM:\n+\t\tif (qat_alg_validate_aes_key(aead_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES key size\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AEAD_AES_CCM:\n+\t\tif (qat_alg_validate_aes_key(aead_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES key size\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined AEAD specified %u\\n\",\n+\t\t\t\taead_xform->algo);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&\n+\t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||\n+\t\t\t(aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&\n+\t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_CCM)) {\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n+\t\t/*\n+\t\t * It needs to create cipher desc content first,\n+\t\t * then authentication\n+\t\t */\n+\t\tcrypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?\n+\t\t\tRTE_CRYPTO_AUTH_OP_GENERATE : RTE_CRYPTO_AUTH_OP_VERIFY;\n+\n+\t\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n+\t\t\t\t\taead_xform->key.data,\n+\t\t\t\t\taead_xform->key.length))\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n+\t\t\t\t\taead_xform->key.data,\n+\t\t\t\t\taead_xform->key.length,\n+\t\t\t\t\taead_xform->aad_length,\n+\t\t\t\t\taead_xform->digest_length,\n+\t\t\t\t\tcrypto_operation))\n+\t\t\treturn -EINVAL;\n+\t} else {\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n+\t\t/*\n+\t\t * It needs to create authentication desc content first,\n+\t\t * then cipher\n+\t\t */\n+\n+\t\tcrypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?\n+\t\t\tRTE_CRYPTO_AUTH_OP_VERIFY : RTE_CRYPTO_AUTH_OP_GENERATE;\n+\n+\t\tif (qat_alg_aead_session_create_content_desc_auth(session,\n+\t\t\t\t\taead_xform->key.data,\n+\t\t\t\t\taead_xform->key.length,\n+\t\t\t\t\taead_xform->aad_length,\n+\t\t\t\t\taead_xform->digest_length,\n+\t\t\t\t\tcrypto_operation))\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (qat_alg_aead_session_create_content_desc_cipher(session,\n+\t\t\t\t\taead_xform->key.data,\n+\t\t\t\t\taead_xform->key.length))\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tsession->digest_length = aead_xform->digest_length;\n+\treturn 0;\n+}\n+\n+unsigned int qat_crypto_sym_get_session_private_size(\n+\t\tstruct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);\n+}\n \n /* returns block size in bytes per cipher algo */\n int qat_cipher_get_block_size(enum icp_qat_hw_cipher_algo qat_cipher_alg)\n@@ -77,12 +788,12 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n \tcase ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,\n \t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n-\tcase ICP_QAT_HW_AUTH_ALGO_NULL:\n-\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,\n-\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n \tcase ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ,\n \t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_NULL:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n \tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n \t\t/* return maximum state1 size in this case */\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,\n@@ -854,14 +1565,13 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \n \t\tif (aad_length > 0) {\n \t\t\taad_length += ICP_QAT_HW_CCM_AAD_B0_LEN +\n-\t\t\t\tICP_QAT_HW_CCM_AAD_LEN_INFO;\n+\t\t\tICP_QAT_HW_CCM_AAD_LEN_INFO;\n \t\t\tauth_param->u2.aad_sz =\n-\t\t\t\t\tRTE_ALIGN_CEIL(aad_length,\n-\t\t\t\t\tICP_QAT_HW_CCM_AAD_ALIGNMENT);\n+\t\t\tRTE_ALIGN_CEIL(aad_length,\n+\t\t\tICP_QAT_HW_CCM_AAD_ALIGNMENT);\n \t\t} else {\n \t\t\tauth_param->u2.aad_sz = ICP_QAT_HW_CCM_AAD_B0_LEN;\n \t\t}\n-\n \t\tcdesc->aad_len = aad_length;\n \t\thash->auth_counter.counter = 0;\n \ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_sym_session.h\nsimilarity index 66%\nrename from drivers/crypto/qat/qat_adf/qat_algs.h\nrename to drivers/crypto/qat/qat_sym_session.h\nindex 6c49c6529..f90b1821d 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -1,14 +1,16 @@\n-/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n- * Copyright(c) 2015-2018 Intel Corporation\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n  */\n-#ifndef _ICP_QAT_ALGS_H_\n-#define _ICP_QAT_ALGS_H_\n-#include <rte_memory.h>\n+#ifndef _QAT_SYM_SESSION_H_\n+#define _QAT_SYM_SESSION_H_\n+\n #include <rte_crypto.h>\n+#include <rte_cryptodev_pmd.h>\n+\n+#include \"qat_common.h\"\n #include \"icp_qat_hw.h\"\n #include \"icp_qat_fw.h\"\n #include \"icp_qat_fw_la.h\"\n-#include \"../qat_crypto.h\"\n \n /*\n  * Key Modifier (KM) value used in KASUMI algorithm in F9 mode to XOR\n@@ -56,7 +58,7 @@ struct qat_session {\n \tvoid *bpi_ctx;\n \tstruct qat_alg_cd cd;\n \tuint8_t *cd_cur_ptr;\n-\trte_iova_t cd_paddr;\n+\tphys_addr_t cd_paddr;\n \tstruct icp_qat_fw_la_bulk_req fw_req;\n \tuint8_t aad_len;\n \tstruct qat_crypto_instance *inst;\n@@ -73,19 +75,57 @@ struct qat_session {\n \tenum qat_device_gen min_qat_dev_gen;\n };\n \n-int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);\n+int\n+qat_crypto_sym_configure_session(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_sym_xform *xform,\n+\t\tstruct rte_cryptodev_sym_session *sess,\n+\t\tstruct rte_mempool *mempool);\n+\n+int\n+qat_crypto_set_session_parameters(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_sym_xform *xform, void *session_private);\n+\n+int\n+qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,\n+\t\t\t\tstruct qat_session *session);\n+\n+int\n+qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_sym_xform *xform,\n+\t\tstruct qat_session *session);\n+\n+int\n+qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,\n+\t\t\t\tstruct rte_crypto_sym_xform *xform,\n+\t\t\t\tstruct qat_session *session);\n \n-int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cd,\n+int\n+qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cd,\n \t\t\t\t\t\tuint8_t *enckey,\n \t\t\t\t\t\tuint32_t enckeylen);\n \n-int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n+int\n+qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t\t\t\t\t\tuint8_t *authkey,\n \t\t\t\t\t\tuint32_t authkeylen,\n \t\t\t\t\t\tuint32_t aad_length,\n \t\t\t\t\t\tuint32_t digestsize,\n \t\t\t\t\t\tunsigned int operation);\n \n+int\n+qat_pmd_session_mempool_create(struct rte_cryptodev *dev,\n+\tunsigned int nb_objs, unsigned int obj_cache_size, int socket_id);\n+\n+void\n+qat_crypto_sym_clear_session(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_sym_session *session);\n+\n+unsigned int\n+qat_crypto_sym_get_session_private_size(struct rte_cryptodev *dev);\n+\n+int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);\n+\n+\n void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,\n \t\t\t\t\tenum qat_crypto_proto_flag proto_flags);\n \n@@ -98,4 +138,5 @@ int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg);\n int qat_alg_validate_des_key(int key_len, enum icp_qat_hw_cipher_algo *alg);\n int qat_cipher_get_block_size(enum icp_qat_hw_cipher_algo qat_cipher_alg);\n int qat_alg_validate_zuc_key(int key_len, enum icp_qat_hw_cipher_algo *alg);\n-#endif\n+\n+#endif /* _QAT_SYM_SESSION_H_ */\ndiff --git a/drivers/crypto/qat/rte_qat_cryptodev.c b/drivers/crypto/qat/rte_qat_cryptodev.c\nindex c8da07af6..e425eb43f 100644\n--- a/drivers/crypto/qat/rte_qat_cryptodev.c\n+++ b/drivers/crypto/qat/rte_qat_cryptodev.c\n@@ -10,6 +10,7 @@\n #include <rte_cryptodev_pmd.h>\n \n #include \"qat_crypto.h\"\n+#include \"qat_sym_session.h\"\n #include \"qat_logs.h\"\n \n uint8_t cryptodev_qat_driver_id;\n",
    "prefixes": [
        "v3",
        "04/38"
    ]
}