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GET /api/patches/40841/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40841,
    "url": "https://patches.dpdk.org/api/patches/40841/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20180608124155.140663-16-jasvinder.singh@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20180608124155.140663-16-jasvinder.singh@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180608124155.140663-16-jasvinder.singh@intel.com",
    "date": "2018-06-08T12:41:49",
    "name": "[dpdk-dev,15/21] net/softnic: add cli to enable and disable pipeline",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c979f17fa620fb3d6c9ea43bf836a7801871c964",
    "submitter": {
        "id": 285,
        "url": "https://patches.dpdk.org/api/people/285/?format=api",
        "name": "Jasvinder Singh",
        "email": "jasvinder.singh@intel.com"
    },
    "delegate": {
        "id": 10018,
        "url": "https://patches.dpdk.org/api/users/10018/?format=api",
        "username": "cristian_dumitrescu",
        "first_name": "Cristian",
        "last_name": "Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20180608124155.140663-16-jasvinder.singh@intel.com/mbox/",
    "series": [
        {
            "id": 52,
            "url": "https://patches.dpdk.org/api/series/52/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=52",
            "date": "2018-06-08T12:41:35",
            "name": "[dpdk-dev,01/21] net/softnic: restructuring",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/52/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/40841/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/40841/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B2BF17CFB;\n\tFri,  8 Jun 2018 14:42:40 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 8E8B16CCC\n\tfor <dev@dpdk.org>; Fri,  8 Jun 2018 14:42:13 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t08 Jun 2018 05:42:12 -0700",
            "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.222.149])\n\tby fmsmga005.fm.intel.com with ESMTP; 08 Jun 2018 05:42:12 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.49,490,1520924400\"; d=\"scan'208\";a=\"235505376\"",
        "From": "Jasvinder Singh <jasvinder.singh@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com",
        "Date": "Fri,  8 Jun 2018 13:41:49 +0100",
        "Message-Id": "<20180608124155.140663-16-jasvinder.singh@intel.com>",
        "X-Mailer": "git-send-email 2.9.3",
        "In-Reply-To": "<20180608124155.140663-1-jasvinder.singh@intel.com>",
        "References": "<20180608124155.140663-1-jasvinder.singh@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 15/21] net/softnic: add cli to enable and disable\n\tpipeline",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add cli commands to enable and disable pipelines on specific threads in\nsoftnic.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\n---\n drivers/net/softnic/rte_eth_softnic_cli.c       | 103 ++++++++\n drivers/net/softnic/rte_eth_softnic_internals.h |  10 +\n drivers/net/softnic/rte_eth_softnic_thread.c    | 325 ++++++++++++++++++++++++\n 3 files changed, 438 insertions(+)",
    "diff": "diff --git a/drivers/net/softnic/rte_eth_softnic_cli.c b/drivers/net/softnic/rte_eth_softnic_cli.c\nindex 6ac3c2e..6884eac 100644\n--- a/drivers/net/softnic/rte_eth_softnic_cli.c\n+++ b/drivers/net/softnic/rte_eth_softnic_cli.c\n@@ -1561,6 +1561,93 @@ cmd_pipeline_port_in_disable(struct pmd_internals *softnic,\n \t}\n }\n \n+/**\n+ * thread <thread_id> pipeline <pipeline_name> enable\n+ */\n+static void\n+cmd_thread_pipeline_enable(struct pmd_internals *softnic,\n+\tchar **tokens,\n+\tuint32_t n_tokens,\n+\tchar *out,\n+\tsize_t out_size)\n+{\n+\tchar *pipeline_name;\n+\tuint32_t thread_id;\n+\tint status;\n+\n+\tif (n_tokens != 5) {\n+\t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n+\t\treturn;\n+\t}\n+\n+\tif (parser_read_uint32(&thread_id, tokens[1]) != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"thread_id\");\n+\t\treturn;\n+\t}\n+\n+\tif (strcmp(tokens[2], \"pipeline\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pipeline\");\n+\t\treturn;\n+\t}\n+\n+\tpipeline_name = tokens[3];\n+\n+\tif (strcmp(tokens[4], \"enable\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"enable\");\n+\t\treturn;\n+\t}\n+\n+\tstatus = thread_pipeline_enable(softnic, thread_id, pipeline_name);\n+\tif (status) {\n+\t\tsnprintf(out, out_size, MSG_CMD_FAIL, \"thread pipeline enable\");\n+\t\treturn;\n+\t}\n+}\n+\n+/**\n+ * thread <thread_id> pipeline <pipeline_name> disable\n+ */\n+static void\n+cmd_thread_pipeline_disable(struct pmd_internals *softnic,\n+\tchar **tokens,\n+\tuint32_t n_tokens,\n+\tchar *out,\n+\tsize_t out_size)\n+{\n+\tchar *pipeline_name;\n+\tuint32_t thread_id;\n+\tint status;\n+\n+\tif (n_tokens != 5) {\n+\t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n+\t\treturn;\n+\t}\n+\n+\tif (parser_read_uint32(&thread_id, tokens[1]) != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"thread_id\");\n+\t\treturn;\n+\t}\n+\n+\tif (strcmp(tokens[2], \"pipeline\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pipeline\");\n+\t\treturn;\n+\t}\n+\n+\tpipeline_name = tokens[3];\n+\n+\tif (strcmp(tokens[4], \"disable\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"disable\");\n+\t\treturn;\n+\t}\n+\n+\tstatus = thread_pipeline_disable(softnic, thread_id, pipeline_name);\n+\tif (status) {\n+\t\tsnprintf(out, out_size, MSG_CMD_FAIL,\n+\t\t\t\"thread pipeline disable\");\n+\t\treturn;\n+\t}\n+}\n+\n void\n cli_process(char *in, char *out, size_t out_size, void *arg)\n {\n@@ -1669,6 +1756,22 @@ cli_process(char *in, char *out, size_t out_size, void *arg)\n \t\t}\n \t}\n \n+\tif (strcmp(tokens[0], \"thread\") == 0) {\n+\t\tif ((n_tokens >= 5) &&\n+\t\t\t(strcmp(tokens[4], \"enable\") == 0)) {\n+\t\t\tcmd_thread_pipeline_enable(softnic, tokens, n_tokens,\n+\t\t\t\tout, out_size);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tif ((n_tokens >= 5) &&\n+\t\t\t(strcmp(tokens[4], \"disable\") == 0)) {\n+\t\t\tcmd_thread_pipeline_disable(softnic, tokens, n_tokens,\n+\t\t\t\tout, out_size);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n \tsnprintf(out, out_size, MSG_CMD_UNKNOWN, tokens[0]);\n }\n \ndiff --git a/drivers/net/softnic/rte_eth_softnic_internals.h b/drivers/net/softnic/rte_eth_softnic_internals.h\nindex 069f490..37c8583 100644\n--- a/drivers/net/softnic/rte_eth_softnic_internals.h\n+++ b/drivers/net/softnic/rte_eth_softnic_internals.h\n@@ -796,6 +796,16 @@ thread_init(struct pmd_internals *p);\n void\n thread_free(struct pmd_internals *p);\n \n+int\n+thread_pipeline_enable(struct pmd_internals *p,\n+\tuint32_t thread_id,\n+\tconst char *pipeline_name);\n+\n+int\n+thread_pipeline_disable(struct pmd_internals *p,\n+\tuint32_t thread_id,\n+\tconst char *pipeline_name);\n+\n /**\n  * CLI\n  */\ndiff --git a/drivers/net/softnic/rte_eth_softnic_thread.c b/drivers/net/softnic/rte_eth_softnic_thread.c\nindex 5cffdc2..ecc525a 100644\n--- a/drivers/net/softnic/rte_eth_softnic_thread.c\n+++ b/drivers/net/softnic/rte_eth_softnic_thread.c\n@@ -93,11 +93,30 @@ thread_init(struct pmd_internals *softnic)\n  * Master thread & data plane threads: message passing\n  */\n enum thread_req_type {\n+\tTHREAD_REQ_PIPELINE_ENABLE = 0,\n+\tTHREAD_REQ_PIPELINE_DISABLE,\n \tTHREAD_REQ_MAX\n };\n \n struct thread_msg_req {\n \tenum thread_req_type type;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\tstruct rte_pipeline *p;\n+\t\t\tstruct {\n+\t\t\t\tstruct rte_table_action *a;\n+\t\t\t} table[RTE_PIPELINE_TABLE_MAX];\n+\t\t\tstruct rte_ring *msgq_req;\n+\t\t\tstruct rte_ring *msgq_rsp;\n+\t\t\tuint32_t timer_period_ms;\n+\t\t\tuint32_t n_tables;\n+\t\t} pipeline_enable;\n+\n+\t\tstruct {\n+\t\t\tstruct rte_pipeline *p;\n+\t\t} pipeline_disable;\n+\t};\n };\n \n struct thread_msg_rsp {\n@@ -105,6 +124,231 @@ struct thread_msg_rsp {\n };\n \n /**\n+ * Master thread\n+ */\n+static struct thread_msg_req *\n+thread_msg_alloc(void)\n+{\n+\tsize_t size = RTE_MAX(sizeof(struct thread_msg_req),\n+\t\tsizeof(struct thread_msg_rsp));\n+\n+\treturn calloc(1, size);\n+}\n+\n+static void\n+thread_msg_free(struct thread_msg_rsp *rsp)\n+{\n+\tfree(rsp);\n+}\n+\n+static struct thread_msg_rsp *\n+thread_msg_send_recv(struct pmd_internals *softnic,\n+\tuint32_t thread_id,\n+\tstruct thread_msg_req *req)\n+{\n+\tstruct thread *t = &softnic->thread[thread_id];\n+\tstruct rte_ring *msgq_req = t->msgq_req;\n+\tstruct rte_ring *msgq_rsp = t->msgq_rsp;\n+\tstruct thread_msg_rsp *rsp;\n+\tint status;\n+\n+\t/* send */\n+\tdo {\n+\t\tstatus = rte_ring_sp_enqueue(msgq_req, req);\n+\t} while (status == -ENOBUFS);\n+\n+\t/* recv */\n+\tdo {\n+\t\tstatus = rte_ring_sc_dequeue(msgq_rsp, (void **) &rsp);\n+\t} while (status != 0);\n+\n+\treturn rsp;\n+}\n+\n+int\n+thread_pipeline_enable(struct pmd_internals *softnic,\n+\tuint32_t thread_id,\n+\tconst char *pipeline_name)\n+{\n+\tstruct pipeline *p = pipeline_find(softnic, pipeline_name);\n+\tstruct thread *t;\n+\tstruct thread_msg_req *req;\n+\tstruct thread_msg_rsp *rsp;\n+\tenum rte_lcore_state_t thread_state;\n+\tuint32_t i;\n+\tint status;\n+\n+\t/* Check input params */\n+\tif ((thread_id >= RTE_MAX_LCORE) ||\n+\t\t(p == NULL) ||\n+\t\t(p->n_ports_in == 0) ||\n+\t\t(p->n_ports_out == 0) ||\n+\t\t(p->n_tables == 0))\n+\t\treturn -1;\n+\n+\tt = &softnic->thread[thread_id];\n+\tif ((t->enabled == 0) ||\n+\t\tp->enabled)\n+\t\treturn -1;\n+\n+\tthread_state = rte_eal_get_lcore_state(thread_id);\n+\tif (thread_state != RUNNING) {\n+\t\tstruct thread_data *td = &softnic->thread_data[thread_id];\n+\t\tstruct pipeline_data *tdp = &td->pipeline_data[td->n_pipelines];\n+\n+\t\tif (td->n_pipelines >= THREAD_PIPELINES_MAX)\n+\t\t\treturn -1;\n+\n+\t\t/* Data plane thread */\n+\t\ttd->p[td->n_pipelines] = p->p;\n+\n+\t\ttdp->p = p->p;\n+\t\tfor (i = 0; i < p->n_tables; i++)\n+\t\t\ttdp->table_data[i].a =\n+\t\t\t\tp->table[i].a;\n+\t\ttdp->n_tables = p->n_tables;\n+\n+\t\ttdp->msgq_req = p->msgq_req;\n+\t\ttdp->msgq_rsp = p->msgq_rsp;\n+\t\ttdp->timer_period = (rte_get_tsc_hz() * p->timer_period_ms) / 1000;\n+\t\ttdp->time_next = rte_get_tsc_cycles() + tdp->timer_period;\n+\n+\t\ttd->n_pipelines++;\n+\n+\t\t/* Pipeline */\n+\t\tp->thread_id = thread_id;\n+\t\tp->enabled = 1;\n+\n+\t\treturn 0;\n+\t}\n+\n+\t/* Allocate request */\n+\treq = thread_msg_alloc();\n+\tif (req == NULL)\n+\t\treturn -1;\n+\n+\t/* Write request */\n+\treq->type = THREAD_REQ_PIPELINE_ENABLE;\n+\treq->pipeline_enable.p = p->p;\n+\tfor (i = 0; i < p->n_tables; i++)\n+\t\treq->pipeline_enable.table[i].a =\n+\t\t\tp->table[i].a;\n+\treq->pipeline_enable.msgq_req = p->msgq_req;\n+\treq->pipeline_enable.msgq_rsp = p->msgq_rsp;\n+\treq->pipeline_enable.timer_period_ms = p->timer_period_ms;\n+\treq->pipeline_enable.n_tables = p->n_tables;\n+\n+\t/* Send request and wait for response */\n+\trsp = thread_msg_send_recv(softnic, thread_id, req);\n+\tif (rsp == NULL)\n+\t\treturn -1;\n+\n+\t/* Read response */\n+\tstatus = rsp->status;\n+\n+\t/* Free response */\n+\tthread_msg_free(rsp);\n+\n+\t/* Request completion */\n+\tif (status)\n+\t\treturn status;\n+\n+\tp->thread_id = thread_id;\n+\tp->enabled = 1;\n+\n+\treturn 0;\n+}\n+\n+int\n+thread_pipeline_disable(struct pmd_internals *softnic,\n+\tuint32_t thread_id,\n+\tconst char *pipeline_name)\n+{\n+\tstruct pipeline *p = pipeline_find(softnic, pipeline_name);\n+\tstruct thread *t;\n+\tstruct thread_msg_req *req;\n+\tstruct thread_msg_rsp *rsp;\n+\tenum rte_lcore_state_t thread_state;\n+\tint status;\n+\n+\t/* Check input params */\n+\tif ((thread_id >= RTE_MAX_LCORE) ||\n+\t\t(p == NULL))\n+\t\treturn -1;\n+\n+\tt = &softnic->thread[thread_id];\n+\tif (t->enabled == 0)\n+\t\treturn -1;\n+\n+\tif (p->enabled == 0)\n+\t\treturn 0;\n+\n+\tif (p->thread_id != thread_id)\n+\t\treturn -1;\n+\n+\tthread_state = rte_eal_get_lcore_state(thread_id);\n+\tif (thread_state != RUNNING) {\n+\t\tstruct thread_data *td = &softnic->thread_data[thread_id];\n+\t\tuint32_t i;\n+\n+\t\tfor (i = 0; i < td->n_pipelines; i++) {\n+\t\t\tstruct pipeline_data *tdp = &td->pipeline_data[i];\n+\n+\t\t\tif (tdp->p != p->p)\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Data plane thread */\n+\t\t\tif (i < td->n_pipelines - 1) {\n+\t\t\t\tstruct rte_pipeline *pipeline_last =\n+\t\t\t\t\ttd->p[td->n_pipelines - 1];\n+\t\t\t\tstruct pipeline_data *tdp_last =\n+\t\t\t\t\t&td->pipeline_data[td->n_pipelines - 1];\n+\n+\t\t\t\ttd->p[i] = pipeline_last;\n+\t\t\t\tmemcpy(tdp, tdp_last, sizeof(*tdp));\n+\t\t\t}\n+\n+\t\t\ttd->n_pipelines--;\n+\n+\t\t\t/* Pipeline */\n+\t\t\tp->enabled = 0;\n+\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\treturn 0;\n+\t}\n+\n+\t/* Allocate request */\n+\treq = thread_msg_alloc();\n+\tif (req == NULL)\n+\t\treturn -1;\n+\n+\t/* Write request */\n+\treq->type = THREAD_REQ_PIPELINE_DISABLE;\n+\treq->pipeline_disable.p = p->p;\n+\n+\t/* Send request and wait for response */\n+\trsp = thread_msg_send_recv(softnic, thread_id, req);\n+\tif (rsp == NULL)\n+\t\treturn -1;\n+\n+\t/* Read response */\n+\tstatus = rsp->status;\n+\n+\t/* Free response */\n+\tthread_msg_free(rsp);\n+\n+\t/* Request completion */\n+\tif (status)\n+\t\treturn status;\n+\n+\tp->enabled = 0;\n+\n+\treturn 0;\n+}\n+\n+/**\n  * Data plane threads: message handling\n  */\n static inline struct thread_msg_req *\n@@ -131,6 +375,79 @@ thread_msg_send(struct rte_ring *msgq_rsp,\n \t} while (status == -ENOBUFS);\n }\n \n+static struct thread_msg_rsp *\n+thread_msg_handle_pipeline_enable(struct thread_data *t,\n+\tstruct thread_msg_req *req)\n+{\n+\tstruct thread_msg_rsp *rsp = (struct thread_msg_rsp *) req;\n+\tstruct pipeline_data *p = &t->pipeline_data[t->n_pipelines];\n+\tuint32_t i;\n+\n+\t/* Request */\n+\tif (t->n_pipelines >= THREAD_PIPELINES_MAX) {\n+\t\trsp->status = -1;\n+\t\treturn rsp;\n+\t}\n+\n+\tt->p[t->n_pipelines] = req->pipeline_enable.p;\n+\n+\tp->p = req->pipeline_enable.p;\n+\tfor (i = 0; i < req->pipeline_enable.n_tables; i++)\n+\t\tp->table_data[i].a =\n+\t\t\treq->pipeline_enable.table[i].a;\n+\n+\tp->n_tables = req->pipeline_enable.n_tables;\n+\n+\tp->msgq_req = req->pipeline_enable.msgq_req;\n+\tp->msgq_rsp = req->pipeline_enable.msgq_rsp;\n+\tp->timer_period =\n+\t\t(rte_get_tsc_hz() * req->pipeline_enable.timer_period_ms) / 1000;\n+\tp->time_next = rte_get_tsc_cycles() + p->timer_period;\n+\n+\tt->n_pipelines++;\n+\n+\t/* Response */\n+\trsp->status = 0;\n+\treturn rsp;\n+}\n+\n+static struct thread_msg_rsp *\n+thread_msg_handle_pipeline_disable(struct thread_data *t,\n+\tstruct thread_msg_req *req)\n+{\n+\tstruct thread_msg_rsp *rsp = (struct thread_msg_rsp *) req;\n+\tuint32_t n_pipelines = t->n_pipelines;\n+\tstruct rte_pipeline *pipeline = req->pipeline_disable.p;\n+\tuint32_t i;\n+\n+\t/* find pipeline */\n+\tfor (i = 0; i < n_pipelines; i++) {\n+\t\tstruct pipeline_data *p = &t->pipeline_data[i];\n+\n+\t\tif (p->p != pipeline)\n+\t\t\tcontinue;\n+\n+\t\tif (i < n_pipelines - 1) {\n+\t\t\tstruct rte_pipeline *pipeline_last =\n+\t\t\t\tt->p[n_pipelines - 1];\n+\t\t\tstruct pipeline_data *p_last =\n+\t\t\t\t&t->pipeline_data[n_pipelines - 1];\n+\n+\t\t\tt->p[i] = pipeline_last;\n+\t\t\tmemcpy(p, p_last, sizeof(*p));\n+\t\t}\n+\n+\t\tt->n_pipelines--;\n+\n+\t\trsp->status = 0;\n+\t\treturn rsp;\n+\t}\n+\n+\t/* should not get here */\n+\trsp->status = 0;\n+\treturn rsp;\n+}\n+\n static void\n thread_msg_handle(struct thread_data *t)\n {\n@@ -143,6 +460,14 @@ thread_msg_handle(struct thread_data *t)\n \t\t\tbreak;\n \n \t\tswitch (req->type) {\n+\t\tcase THREAD_REQ_PIPELINE_ENABLE:\n+\t\t\trsp = thread_msg_handle_pipeline_enable(t, req);\n+\t\t\tbreak;\n+\n+\t\tcase THREAD_REQ_PIPELINE_DISABLE:\n+\t\t\trsp = thread_msg_handle_pipeline_disable(t, req);\n+\t\t\tbreak;\n+\n \t\tdefault:\n \t\t\trsp = (struct thread_msg_rsp *) req;\n \t\t\trsp->status = -1;\n",
    "prefixes": [
        "dpdk-dev",
        "15/21"
    ]
}