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GET /api/patches/40835/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40835,
    "url": "https://patches.dpdk.org/api/patches/40835/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20180608124155.140663-10-jasvinder.singh@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20180608124155.140663-10-jasvinder.singh@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180608124155.140663-10-jasvinder.singh@intel.com",
    "date": "2018-06-08T12:41:43",
    "name": "[dpdk-dev,09/21] net/softnic: add pipeline object",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "01292d1d9768b4eea8aa273f79de4ebe879faf9d",
    "submitter": {
        "id": 285,
        "url": "https://patches.dpdk.org/api/people/285/?format=api",
        "name": "Jasvinder Singh",
        "email": "jasvinder.singh@intel.com"
    },
    "delegate": {
        "id": 10018,
        "url": "https://patches.dpdk.org/api/users/10018/?format=api",
        "username": "cristian_dumitrescu",
        "first_name": "Cristian",
        "last_name": "Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20180608124155.140663-10-jasvinder.singh@intel.com/mbox/",
    "series": [
        {
            "id": 52,
            "url": "https://patches.dpdk.org/api/series/52/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=52",
            "date": "2018-06-08T12:41:35",
            "name": "[dpdk-dev,01/21] net/softnic: restructuring",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/52/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/40835/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/40835/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id ECDCA7CA3;\n\tFri,  8 Jun 2018 14:42:26 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 2D8D15F54\n\tfor <dev@dpdk.org>; Fri,  8 Jun 2018 14:42:06 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t08 Jun 2018 05:42:06 -0700",
            "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.222.149])\n\tby fmsmga005.fm.intel.com with ESMTP; 08 Jun 2018 05:42:04 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.49,490,1520924400\"; d=\"scan'208\";a=\"235505348\"",
        "From": "Jasvinder Singh <jasvinder.singh@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com",
        "Date": "Fri,  8 Jun 2018 13:41:43 +0100",
        "Message-Id": "<20180608124155.140663-10-jasvinder.singh@intel.com>",
        "X-Mailer": "git-send-email 2.9.3",
        "In-Reply-To": "<20180608124155.140663-1-jasvinder.singh@intel.com>",
        "References": "<20180608124155.140663-1-jasvinder.singh@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 09/21] net/softnic: add pipeline object",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add pipeline object implementation to the softnic.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\n---\n drivers/net/softnic/Makefile                    |   1 +\n drivers/net/softnic/rte_eth_softnic.c           |   2 +\n drivers/net/softnic/rte_eth_softnic_internals.h | 196 +++++\n drivers/net/softnic/rte_eth_softnic_pipeline.c  | 957 ++++++++++++++++++++++++\n mk/rte.app.mk                                   |   4 +\n 5 files changed, 1160 insertions(+)\n create mode 100644 drivers/net/softnic/rte_eth_softnic_pipeline.c",
    "diff": "diff --git a/drivers/net/softnic/Makefile b/drivers/net/softnic/Makefile\nindex 5387616..c3a3a6f 100644\n--- a/drivers/net/softnic/Makefile\n+++ b/drivers/net/softnic/Makefile\n@@ -30,6 +30,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_SOFTNIC) += rte_eth_softnic_link.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_SOFTNIC) += rte_eth_softnic_tm.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_SOFTNIC) += rte_eth_softnic_tap.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_SOFTNIC) += rte_eth_softnic_action.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_SOFTNIC) += rte_eth_softnic_pipeline.c\n \n #\n # Export include files\ndiff --git a/drivers/net/softnic/rte_eth_softnic.c b/drivers/net/softnic/rte_eth_softnic.c\nindex f7d6087..81a7735 100644\n--- a/drivers/net/softnic/rte_eth_softnic.c\n+++ b/drivers/net/softnic/rte_eth_softnic.c\n@@ -229,6 +229,7 @@ pmd_init(struct pmd_params *params)\n \ttap_init(p);\n \tport_in_action_profile_init(p);\n \ttable_action_profile_init(p);\n+\tpipeline_init(p);\n \n \treturn p;\n }\n@@ -239,6 +240,7 @@ pmd_free(struct pmd_internals *p)\n \tif (p == NULL)\n \t\treturn;\n \n+\tpipeline_free(p);\n \ttable_action_profile_free(p);\n \tport_in_action_profile_free(p);\n \ttap_free(p);\ndiff --git a/drivers/net/softnic/rte_eth_softnic_internals.h b/drivers/net/softnic/rte_eth_softnic_internals.h\nindex 8f7ef19..d805270 100644\n--- a/drivers/net/softnic/rte_eth_softnic_internals.h\n+++ b/drivers/net/softnic/rte_eth_softnic_internals.h\n@@ -16,6 +16,8 @@\n #include <rte_sched.h>\n #include <rte_port_in_action.h>\n #include <rte_table_action.h>\n+#include <rte_pipeline.h>\n+\n #include <rte_ethdev_driver.h>\n #include <rte_tm_driver.h>\n \n@@ -283,6 +285,160 @@ struct table_action_profile {\n TAILQ_HEAD(table_action_profile_list, table_action_profile);\n \n /**\n+ * Pipeline\n+ */\n+struct pipeline_params {\n+\tuint32_t timer_period_ms;\n+\tuint32_t offset_port_id;\n+};\n+\n+enum port_in_type {\n+\tPORT_IN_RXQ,\n+\tPORT_IN_SWQ,\n+\tPORT_IN_TMGR,\n+\tPORT_IN_TAP,\n+\tPORT_IN_SOURCE,\n+};\n+\n+struct port_in_params {\n+\t/* Read */\n+\tenum port_in_type type;\n+\tconst char *dev_name;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t queue_id;\n+\t\t} rxq;\n+\n+\t\tstruct {\n+\t\t\tconst char *mempool_name;\n+\t\t\tuint32_t mtu;\n+\t\t} tap;\n+\n+\t\tstruct {\n+\t\t\tconst char *mempool_name;\n+\t\t\tconst char *file_name;\n+\t\t\tuint32_t n_bytes_per_pkt;\n+\t\t} source;\n+\t};\n+\tuint32_t burst_size;\n+\n+\t/* Action */\n+\tconst char *action_profile_name;\n+};\n+\n+enum port_out_type {\n+\tPORT_OUT_TXQ,\n+\tPORT_OUT_SWQ,\n+\tPORT_OUT_TMGR,\n+\tPORT_OUT_TAP,\n+\tPORT_OUT_SINK,\n+};\n+\n+struct port_out_params {\n+\tenum port_out_type type;\n+\tconst char *dev_name;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t queue_id;\n+\t\t} txq;\n+\n+\t\tstruct {\n+\t\t\tconst char *file_name;\n+\t\t\tuint32_t max_n_pkts;\n+\t\t} sink;\n+\t};\n+\tuint32_t burst_size;\n+\tint retry;\n+\tuint32_t n_retries;\n+};\n+\n+enum table_type {\n+\tTABLE_ACL,\n+\tTABLE_ARRAY,\n+\tTABLE_HASH,\n+\tTABLE_LPM,\n+\tTABLE_STUB,\n+};\n+\n+struct table_acl_params {\n+\tuint32_t n_rules;\n+\tuint32_t ip_header_offset;\n+\tint ip_version;\n+};\n+\n+struct table_array_params {\n+\tuint32_t n_keys;\n+\tuint32_t key_offset;\n+};\n+\n+struct table_hash_params {\n+\tuint32_t n_keys;\n+\tuint32_t key_offset;\n+\tuint32_t key_size;\n+\tuint8_t *key_mask;\n+\tuint32_t n_buckets;\n+\tint extendable_bucket;\n+};\n+\n+struct table_lpm_params {\n+\tuint32_t n_rules;\n+\tuint32_t key_offset;\n+\tuint32_t key_size;\n+};\n+\n+struct table_params {\n+\t/* Match */\n+\tenum table_type match_type;\n+\tunion {\n+\t\tstruct table_acl_params acl;\n+\t\tstruct table_array_params array;\n+\t\tstruct table_hash_params hash;\n+\t\tstruct table_lpm_params lpm;\n+\t} match;\n+\n+\t/* Action */\n+\tconst char *action_profile_name;\n+};\n+\n+struct port_in {\n+\tstruct port_in_params params;\n+\tstruct port_in_action_profile *ap;\n+\tstruct rte_port_in_action *a;\n+};\n+\n+struct table {\n+\tstruct table_params params;\n+\tstruct table_action_profile *ap;\n+\tstruct rte_table_action *a;\n+};\n+\n+struct pipeline {\n+\tTAILQ_ENTRY(pipeline) node;\n+\tchar name[NAME_SIZE];\n+\n+\tstruct rte_pipeline *p;\n+\tstruct port_in port_in[RTE_PIPELINE_PORT_IN_MAX];\n+\tstruct table table[RTE_PIPELINE_TABLE_MAX];\n+\tuint32_t n_ports_in;\n+\tuint32_t n_ports_out;\n+\tuint32_t n_tables;\n+\n+\tstruct rte_ring *msgq_req;\n+\tstruct rte_ring *msgq_rsp;\n+\tuint32_t timer_period_ms;\n+\n+\tint enabled;\n+\tuint32_t thread_id;\n+\tuint32_t cpu_id;\n+};\n+\n+TAILQ_HEAD(pipeline_list, pipeline);\n+\n+#ifndef TABLE_RULE_ACTION_SIZE_MAX\n+#define TABLE_RULE_ACTION_SIZE_MAX                         2048\n+#endif\n+\n+/**\n  * PMD Internals\n  */\n struct pmd_internals {\n@@ -301,6 +457,7 @@ struct pmd_internals {\n \tstruct tap_list tap_list;\n \tstruct port_in_action_profile_list port_in_action_profile_list;\n \tstruct table_action_profile_list table_action_profile_list;\n+\tstruct pipeline_list pipeline_list;\n };\n \n /**\n@@ -443,4 +600,43 @@ table_action_profile_create(struct pmd_internals *p,\n \tconst char *name,\n \tstruct table_action_profile_params *params);\n \n+/**\n+ * Pipeline\n+ */\n+int\n+pipeline_init(struct pmd_internals *p);\n+\n+void\n+pipeline_free(struct pmd_internals *p);\n+\n+struct pipeline *\n+pipeline_find(struct pmd_internals *p, const char *name);\n+\n+struct pipeline *\n+pipeline_create(struct pmd_internals *p,\n+\tconst char *name,\n+\tstruct pipeline_params *params);\n+\n+int\n+pipeline_port_in_create(struct pmd_internals *p,\n+\tconst char *pipeline_name,\n+\tstruct port_in_params *params,\n+\tint enabled);\n+\n+int\n+pipeline_port_in_connect_to_table(struct pmd_internals *p,\n+\tconst char *pipeline_name,\n+\tuint32_t port_id,\n+\tuint32_t table_id);\n+\n+int\n+pipeline_port_out_create(struct pmd_internals *p,\n+\tconst char *pipeline_name,\n+\tstruct port_out_params *params);\n+\n+int\n+pipeline_table_create(struct pmd_internals *p,\n+\tconst char *pipeline_name,\n+\tstruct table_params *params);\n+\n #endif /* __INCLUDE_RTE_ETH_SOFTNIC_INTERNALS_H__ */\ndiff --git a/drivers/net/softnic/rte_eth_softnic_pipeline.c b/drivers/net/softnic/rte_eth_softnic_pipeline.c\nnew file mode 100644\nindex 0000000..7382288\n--- /dev/null\n+++ b/drivers/net/softnic/rte_eth_softnic_pipeline.c\n@@ -0,0 +1,957 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2018 Intel Corporation\n+ */\n+\n+#include <stdlib.h>\n+#include <string.h>\n+\n+#include <rte_common.h>\n+#include <rte_ip.h>\n+#include <rte_tcp.h>\n+\n+#include <rte_string_fns.h>\n+#include <rte_port_ethdev.h>\n+#include <rte_port_ring.h>\n+#include <rte_port_source_sink.h>\n+#include <rte_port_fd.h>\n+#include <rte_port_sched.h>\n+\n+#include <rte_table_acl.h>\n+#include <rte_table_array.h>\n+#include <rte_table_hash.h>\n+#include <rte_table_lpm.h>\n+#include <rte_table_lpm_ipv6.h>\n+#include <rte_table_stub.h>\n+\n+#include \"rte_eth_softnic_internals.h\"\n+\n+#include \"hash_func.h\"\n+\n+#ifndef PIPELINE_MSGQ_SIZE\n+#define PIPELINE_MSGQ_SIZE                                 64\n+#endif\n+\n+#ifndef TABLE_LPM_NUMBER_TBL8\n+#define TABLE_LPM_NUMBER_TBL8                              256\n+#endif\n+\n+int\n+pipeline_init(struct pmd_internals *p)\n+{\n+\tTAILQ_INIT(&p->pipeline_list);\n+\n+\treturn 0;\n+}\n+\n+void\n+pipeline_free(struct pmd_internals *p)\n+{\n+\tfor ( ; ; ) {\n+\t\tstruct pipeline *pipeline;\n+\n+\t\tpipeline = TAILQ_FIRST(&p->pipeline_list);\n+\t\tif (pipeline == NULL)\n+\t\t\tbreak;\n+\n+\t\tTAILQ_REMOVE(&p->pipeline_list, pipeline, node);\n+\t\trte_ring_free(pipeline->msgq_req);\n+\t\trte_ring_free(pipeline->msgq_rsp);\n+\t\trte_pipeline_free(pipeline->p);\n+\t\tfree(pipeline);\n+\t}\n+}\n+\n+struct pipeline *\n+pipeline_find(struct pmd_internals *p,\n+\tconst char *name)\n+{\n+\tstruct pipeline *pipeline;\n+\n+\tif (name == NULL)\n+\t\treturn NULL;\n+\n+\tTAILQ_FOREACH(pipeline, &p->pipeline_list, node)\n+\t\tif (strcmp(name, pipeline->name) == 0)\n+\t\t\treturn pipeline;\n+\n+\treturn NULL;\n+}\n+\n+struct pipeline *\n+pipeline_create(struct pmd_internals *softnic,\n+\tconst char *name,\n+\tstruct pipeline_params *params)\n+{\n+\tchar resource_name[NAME_MAX];\n+\tstruct rte_pipeline_params pp;\n+\tstruct pipeline *pipeline;\n+\tstruct rte_pipeline *p;\n+\tstruct rte_ring *msgq_req;\n+\tstruct rte_ring *msgq_rsp;\n+\n+\t/* Check input params */\n+\tif ((name == NULL) ||\n+\t\tpipeline_find(softnic, name) ||\n+\t\t(params == NULL) ||\n+\t\t(params->timer_period_ms == 0))\n+\t\treturn NULL;\n+\n+\t/* Resource create */\n+\tsnprintf(resource_name, sizeof(resource_name), \"%s-%s-REQ\",\n+\t\tsoftnic->params.name,\n+\t\tname);\n+\n+\tmsgq_req = rte_ring_create(resource_name,\n+\t\tPIPELINE_MSGQ_SIZE,\n+\t\tsoftnic->params.cpu_id,\n+\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n+\tif (msgq_req == NULL)\n+\t\treturn NULL;\n+\n+\tsnprintf(resource_name, sizeof(resource_name), \"%s-%s-RSP\",\n+\t\tsoftnic->params.name,\n+\t\tname);\n+\n+\tmsgq_rsp = rte_ring_create(resource_name,\n+\t\tPIPELINE_MSGQ_SIZE,\n+\t\tsoftnic->params.cpu_id,\n+\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n+\tif (msgq_rsp == NULL) {\n+\t\trte_ring_free(msgq_req);\n+\t\treturn NULL;\n+\t}\n+\n+\tsnprintf(resource_name, sizeof(resource_name), \"%s_%s\",\n+\t\tsoftnic->params.name,\n+\t\tname);\n+\n+\tpp.name = resource_name;\n+\tpp.socket_id = (int) softnic->params.cpu_id;\n+\tpp.offset_port_id = params->offset_port_id;\n+\n+\tp = rte_pipeline_create(&pp);\n+\tif (p == NULL) {\n+\t\trte_ring_free(msgq_rsp);\n+\t\trte_ring_free(msgq_req);\n+\t\treturn NULL;\n+\t}\n+\n+\t/* Node allocation */\n+\tpipeline = calloc(1, sizeof(struct pipeline));\n+\tif (pipeline == NULL) {\n+\t\trte_pipeline_free(p);\n+\t\trte_ring_free(msgq_rsp);\n+\t\trte_ring_free(msgq_req);\n+\t\treturn NULL;\n+\t}\n+\n+\t/* Node fill in */\n+\tstrlcpy(pipeline->name, name, sizeof(pipeline->name));\n+\tpipeline->p = p;\n+\tpipeline->n_ports_in = 0;\n+\tpipeline->n_ports_out = 0;\n+\tpipeline->n_tables = 0;\n+\tpipeline->msgq_req = msgq_req;\n+\tpipeline->msgq_rsp = msgq_rsp;\n+\tpipeline->timer_period_ms = params->timer_period_ms;\n+\tpipeline->enabled = 0;\n+\tpipeline->cpu_id = softnic->params.cpu_id;\n+\n+\t/* Node add to list */\n+\tTAILQ_INSERT_TAIL(&softnic->pipeline_list, pipeline, node);\n+\n+\treturn pipeline;\n+}\n+\n+int\n+pipeline_port_in_create(struct pmd_internals *softnic,\n+\tconst char *pipeline_name,\n+\tstruct port_in_params *params,\n+\tint enabled)\n+{\n+\tstruct rte_pipeline_port_in_params p;\n+\n+\tunion {\n+\t\tstruct rte_port_ethdev_reader_params ethdev;\n+\t\tstruct rte_port_ring_reader_params ring;\n+\t\tstruct rte_port_sched_reader_params sched;\n+\t\tstruct rte_port_fd_reader_params fd;\n+\t\tstruct rte_port_source_params source;\n+\t} pp;\n+\n+\tstruct pipeline *pipeline;\n+\tstruct port_in *port_in;\n+\tstruct port_in_action_profile *ap;\n+\tstruct rte_port_in_action *action;\n+\tuint32_t port_id;\n+\tint status;\n+\n+\tmemset(&p, 0, sizeof(p));\n+\tmemset(&pp, 0, sizeof(pp));\n+\n+\t/* Check input params */\n+\tif ((pipeline_name == NULL) ||\n+\t\t(params == NULL) ||\n+\t\t(params->burst_size == 0) ||\n+\t\t(params->burst_size > RTE_PORT_IN_BURST_SIZE_MAX))\n+\t\treturn -1;\n+\n+\tpipeline = pipeline_find(softnic, pipeline_name);\n+\tif (pipeline == NULL)\n+\t\treturn -1;\n+\n+\tap = NULL;\n+\tif (params->action_profile_name) {\n+\t\tap = port_in_action_profile_find(softnic,\n+\t\t\tparams->action_profile_name);\n+\t\tif (ap == NULL)\n+\t\t\treturn -1;\n+\t}\n+\n+\tswitch (params->type) {\n+\tcase PORT_IN_RXQ:\n+\t{\n+\t\tstruct link *link;\n+\n+\t\tlink = link_find(softnic, params->dev_name);\n+\t\tif (link == NULL)\n+\t\t\treturn -1;\n+\n+\t\tif (params->rxq.queue_id >= link->n_rxq)\n+\t\t\treturn -1;\n+\n+\t\tpp.ethdev.port_id = link->port_id;\n+\t\tpp.ethdev.queue_id = params->rxq.queue_id;\n+\n+\t\tp.ops = &rte_port_ethdev_reader_ops;\n+\t\tp.arg_create = &pp.ethdev;\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_IN_SWQ:\n+\t{\n+\t\tstruct swq *swq;\n+\n+\t\tswq = swq_find(softnic, params->dev_name);\n+\t\tif (swq == NULL)\n+\t\t\treturn -1;\n+\n+\t\tpp.ring.ring = swq->r;\n+\n+\t\tp.ops = &rte_port_ring_reader_ops;\n+\t\tp.arg_create = &pp.ring;\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_IN_TMGR:\n+\t{\n+\t\tstruct tmgr_port *tmgr_port;\n+\n+\t\ttmgr_port = tmgr_port_find(softnic, params->dev_name);\n+\t\tif (tmgr_port == NULL)\n+\t\t\treturn -1;\n+\n+\t\tpp.sched.sched = tmgr_port->s;\n+\n+\t\tp.ops = &rte_port_sched_reader_ops;\n+\t\tp.arg_create = &pp.sched;\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_IN_TAP:\n+\t{\n+\t\tstruct tap *tap;\n+\t\tstruct mempool *mempool;\n+\n+\t\ttap = tap_find(softnic, params->dev_name);\n+\t\tmempool = mempool_find(softnic, params->tap.mempool_name);\n+\t\tif ((tap == NULL) || (mempool == NULL))\n+\t\t\treturn -1;\n+\n+\t\tpp.fd.fd = tap->fd;\n+\t\tpp.fd.mempool = mempool->m;\n+\t\tpp.fd.mtu = params->tap.mtu;\n+\n+\t\tp.ops = &rte_port_fd_reader_ops;\n+\t\tp.arg_create = &pp.fd;\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_IN_SOURCE:\n+\t{\n+\t\tstruct mempool *mempool;\n+\n+\t\tmempool = mempool_find(softnic, params->source.mempool_name);\n+\t\tif (mempool == NULL)\n+\t\t\treturn -1;\n+\n+\t\tpp.source.mempool = mempool->m;\n+\t\tpp.source.file_name = params->source.file_name;\n+\t\tpp.source.n_bytes_per_pkt = params->source.n_bytes_per_pkt;\n+\n+\t\tp.ops = &rte_port_source_ops;\n+\t\tp.arg_create = &pp.source;\n+\t\tbreak;\n+\t}\n+\n+\tdefault:\n+\t\treturn -1;\n+\t}\n+\n+\tp.burst_size = params->burst_size;\n+\n+\t/* Resource create */\n+\taction = NULL;\n+\tp.f_action = NULL;\n+\tp.arg_ah = NULL;\n+\n+\tif (ap) {\n+\t\taction = rte_port_in_action_create(ap->ap,\n+\t\t\tsoftnic->params.cpu_id);\n+\t\tif (action == NULL)\n+\t\t\treturn -1;\n+\n+\t\tstatus = rte_port_in_action_params_get(\n+\t\t\taction,\n+\t\t\t&p);\n+\t\tif (status) {\n+\t\t\trte_port_in_action_free(action);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tstatus = rte_pipeline_port_in_create(pipeline->p,\n+\t\t&p,\n+\t\t&port_id);\n+\tif (status) {\n+\t\trte_port_in_action_free(action);\n+\t\treturn -1;\n+\t}\n+\n+\tif (enabled)\n+\t\trte_pipeline_port_in_enable(pipeline->p, port_id);\n+\n+\t/* Pipeline */\n+\tport_in = &pipeline->port_in[pipeline->n_ports_in];\n+\tmemcpy(&port_in->params, params, sizeof(*params));\n+\tport_in->ap = ap;\n+\tport_in->a = action;\n+\tpipeline->n_ports_in++;\n+\n+\treturn 0;\n+}\n+\n+int\n+pipeline_port_in_connect_to_table(struct pmd_internals *softnic,\n+\tconst char *pipeline_name,\n+\tuint32_t port_id,\n+\tuint32_t table_id)\n+{\n+\tstruct pipeline *pipeline;\n+\tint status;\n+\n+\t/* Check input params */\n+\tif (pipeline_name == NULL)\n+\t\treturn -1;\n+\n+\tpipeline = pipeline_find(softnic, pipeline_name);\n+\tif ((pipeline == NULL) ||\n+\t\t(port_id >= pipeline->n_ports_in) ||\n+\t\t(table_id >= pipeline->n_tables))\n+\t\treturn -1;\n+\n+\t/* Resource */\n+\tstatus = rte_pipeline_port_in_connect_to_table(pipeline->p,\n+\t\tport_id,\n+\t\ttable_id);\n+\n+\treturn status;\n+\n+}\n+\n+int\n+pipeline_port_out_create(struct pmd_internals *softnic,\n+\tconst char *pipeline_name,\n+\tstruct port_out_params *params)\n+{\n+\tstruct rte_pipeline_port_out_params p;\n+\n+\tunion {\n+\t\tstruct rte_port_ethdev_writer_params ethdev;\n+\t\tstruct rte_port_ring_writer_params ring;\n+\t\tstruct rte_port_sched_writer_params sched;\n+\t\tstruct rte_port_fd_writer_params fd;\n+\t\tstruct rte_port_sink_params sink;\n+\t} pp;\n+\n+\tunion {\n+\t\tstruct rte_port_ethdev_writer_nodrop_params ethdev;\n+\t\tstruct rte_port_ring_writer_nodrop_params ring;\n+\t\tstruct rte_port_fd_writer_nodrop_params fd;\n+\t} pp_nodrop;\n+\n+\tstruct pipeline *pipeline;\n+\tuint32_t port_id;\n+\tint status;\n+\n+\tmemset(&p, 0, sizeof(p));\n+\tmemset(&pp, 0, sizeof(pp));\n+\tmemset(&pp_nodrop, 0, sizeof(pp_nodrop));\n+\n+\t/* Check input params */\n+\tif ((pipeline_name == NULL) ||\n+\t\t(params == NULL) ||\n+\t\t(params->burst_size == 0) ||\n+\t\t(params->burst_size > RTE_PORT_IN_BURST_SIZE_MAX))\n+\t\treturn -1;\n+\n+\tpipeline = pipeline_find(softnic, pipeline_name);\n+\tif (pipeline == NULL)\n+\t\treturn -1;\n+\n+\tswitch (params->type) {\n+\tcase PORT_OUT_TXQ:\n+\t{\n+\t\tstruct link *link;\n+\n+\t\tlink = link_find(softnic, params->dev_name);\n+\t\tif (link == NULL)\n+\t\t\treturn -1;\n+\n+\t\tif (params->txq.queue_id >= link->n_txq)\n+\t\t\treturn -1;\n+\n+\t\tpp.ethdev.port_id = link->port_id;\n+\t\tpp.ethdev.queue_id = params->txq.queue_id;\n+\t\tpp.ethdev.tx_burst_sz = params->burst_size;\n+\n+\t\tpp_nodrop.ethdev.port_id = link->port_id;\n+\t\tpp_nodrop.ethdev.queue_id = params->txq.queue_id;\n+\t\tpp_nodrop.ethdev.tx_burst_sz = params->burst_size;\n+\t\tpp_nodrop.ethdev.n_retries = params->n_retries;\n+\n+\t\tif (params->retry == 0) {\n+\t\t\tp.ops = &rte_port_ethdev_writer_ops;\n+\t\t\tp.arg_create = &pp.ethdev;\n+\t\t} else {\n+\t\t\tp.ops = &rte_port_ethdev_writer_nodrop_ops;\n+\t\t\tp.arg_create = &pp_nodrop.ethdev;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_OUT_SWQ:\n+\t{\n+\t\tstruct swq *swq;\n+\n+\t\tswq = swq_find(softnic, params->dev_name);\n+\t\tif (swq == NULL)\n+\t\t\treturn -1;\n+\n+\t\tpp.ring.ring = swq->r;\n+\t\tpp.ring.tx_burst_sz = params->burst_size;\n+\n+\t\tpp_nodrop.ring.ring = swq->r;\n+\t\tpp_nodrop.ring.tx_burst_sz = params->burst_size;\n+\t\tpp_nodrop.ring.n_retries = params->n_retries;\n+\n+\t\tif (params->retry == 0) {\n+\t\t\tp.ops = &rte_port_ring_writer_ops;\n+\t\t\tp.arg_create = &pp.ring;\n+\t\t} else {\n+\t\t\tp.ops = &rte_port_ring_writer_nodrop_ops;\n+\t\t\tp.arg_create = &pp_nodrop.ring;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_OUT_TMGR:\n+\t{\n+\t\tstruct tmgr_port *tmgr_port;\n+\n+\t\ttmgr_port = tmgr_port_find(softnic, params->dev_name);\n+\t\tif (tmgr_port == NULL)\n+\t\t\treturn -1;\n+\n+\t\tpp.sched.sched = tmgr_port->s;\n+\t\tpp.sched.tx_burst_sz = params->burst_size;\n+\n+\t\tp.ops = &rte_port_sched_writer_ops;\n+\t\tp.arg_create = &pp.sched;\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_OUT_TAP:\n+\t{\n+\t\tstruct tap *tap;\n+\n+\t\ttap = tap_find(softnic, params->dev_name);\n+\t\tif (tap == NULL)\n+\t\t\treturn -1;\n+\n+\t\tpp.fd.fd = tap->fd;\n+\t\tpp.fd.tx_burst_sz = params->burst_size;\n+\n+\t\tpp_nodrop.fd.fd = tap->fd;\n+\t\tpp_nodrop.fd.tx_burst_sz = params->burst_size;\n+\t\tpp_nodrop.fd.n_retries = params->n_retries;\n+\n+\t\tif (params->retry == 0) {\n+\t\t\tp.ops = &rte_port_fd_writer_ops;\n+\t\t\tp.arg_create = &pp.fd;\n+\t\t} else {\n+\t\t\tp.ops = &rte_port_fd_writer_nodrop_ops;\n+\t\t\tp.arg_create = &pp_nodrop.fd;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tcase PORT_OUT_SINK:\n+\t{\n+\t\tpp.sink.file_name = params->sink.file_name;\n+\t\tpp.sink.max_n_pkts = params->sink.max_n_pkts;\n+\n+\t\tp.ops = &rte_port_sink_ops;\n+\t\tp.arg_create = &pp.sink;\n+\t\tbreak;\n+\t}\n+\n+\tdefault:\n+\t\treturn -1;\n+\t}\n+\n+\tp.f_action = NULL;\n+\tp.arg_ah = NULL;\n+\n+\t/* Resource create */\n+\tstatus = rte_pipeline_port_out_create(pipeline->p,\n+\t\t&p,\n+\t\t&port_id);\n+\n+\tif (status)\n+\t\treturn -1;\n+\n+\t/* Pipeline */\n+\tpipeline->n_ports_out++;\n+\n+\treturn 0;\n+}\n+\n+static const struct rte_acl_field_def table_acl_field_format_ipv4[] = {\n+\t/* Protocol */\n+\t[0] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n+\t\t.size = sizeof(uint8_t),\n+\t\t.field_index = 0,\n+\t\t.input_index = 0,\n+\t\t.offset = offsetof(struct ipv4_hdr, next_proto_id),\n+\t},\n+\n+\t/* Source IP address (IPv4) */\n+\t[1] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 1,\n+\t\t.input_index = 1,\n+\t\t.offset = offsetof(struct ipv4_hdr, src_addr),\n+\t},\n+\n+\t/* Destination IP address (IPv4) */\n+\t[2] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 2,\n+\t\t.input_index = 2,\n+\t\t.offset = offsetof(struct ipv4_hdr, dst_addr),\n+\t},\n+\n+\t/* Source Port */\n+\t[3] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n+\t\t.size = sizeof(uint16_t),\n+\t\t.field_index = 3,\n+\t\t.input_index = 3,\n+\t\t.offset = sizeof(struct ipv4_hdr) +\n+\t\t\toffsetof(struct tcp_hdr, src_port),\n+\t},\n+\n+\t/* Destination Port */\n+\t[4] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n+\t\t.size = sizeof(uint16_t),\n+\t\t.field_index = 4,\n+\t\t.input_index = 3,\n+\t\t.offset = sizeof(struct ipv4_hdr) +\n+\t\t\toffsetof(struct tcp_hdr, dst_port),\n+\t},\n+};\n+\n+static const struct rte_acl_field_def table_acl_field_format_ipv6[] = {\n+\t/* Protocol */\n+\t[0] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n+\t\t.size = sizeof(uint8_t),\n+\t\t.field_index = 0,\n+\t\t.input_index = 0,\n+\t\t.offset = offsetof(struct ipv6_hdr, proto),\n+\t},\n+\n+\t/* Source IP address (IPv6) */\n+\t[1] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 1,\n+\t\t.input_index = 1,\n+\t\t.offset = offsetof(struct ipv6_hdr, src_addr[0]),\n+\t},\n+\n+\t[2] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 2,\n+\t\t.input_index = 2,\n+\t\t.offset = offsetof(struct ipv6_hdr, src_addr[4]),\n+\t},\n+\n+\t[3] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 3,\n+\t\t.input_index = 3,\n+\t\t.offset = offsetof(struct ipv6_hdr, src_addr[8]),\n+\t},\n+\n+\t[4] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 4,\n+\t\t.input_index = 4,\n+\t\t.offset = offsetof(struct ipv6_hdr, src_addr[12]),\n+\t},\n+\n+\t/* Destination IP address (IPv6) */\n+\t[5] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 5,\n+\t\t.input_index = 5,\n+\t\t.offset = offsetof(struct ipv6_hdr, dst_addr[0]),\n+\t},\n+\n+\t[6] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 6,\n+\t\t.input_index = 6,\n+\t\t.offset = offsetof(struct ipv6_hdr, dst_addr[4]),\n+\t},\n+\n+\t[7] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 7,\n+\t\t.input_index = 7,\n+\t\t.offset = offsetof(struct ipv6_hdr, dst_addr[8]),\n+\t},\n+\n+\t[8] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n+\t\t.size = sizeof(uint32_t),\n+\t\t.field_index = 8,\n+\t\t.input_index = 8,\n+\t\t.offset = offsetof(struct ipv6_hdr, dst_addr[12]),\n+\t},\n+\n+\t/* Source Port */\n+\t[9] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n+\t\t.size = sizeof(uint16_t),\n+\t\t.field_index = 9,\n+\t\t.input_index = 9,\n+\t\t.offset = sizeof(struct ipv6_hdr) +\n+\t\t\toffsetof(struct tcp_hdr, src_port),\n+\t},\n+\n+\t/* Destination Port */\n+\t[10] = {\n+\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n+\t\t.size = sizeof(uint16_t),\n+\t\t.field_index = 10,\n+\t\t.input_index = 9,\n+\t\t.offset = sizeof(struct ipv6_hdr) +\n+\t\t\toffsetof(struct tcp_hdr, dst_port),\n+\t},\n+};\n+\n+int\n+pipeline_table_create(struct pmd_internals *softnic,\n+\tconst char *pipeline_name,\n+\tstruct table_params *params)\n+{\n+\tchar name[NAME_MAX];\n+\tstruct rte_pipeline_table_params p;\n+\n+\tunion {\n+\t\tstruct rte_table_acl_params acl;\n+\t\tstruct rte_table_array_params array;\n+\t\tstruct rte_table_hash_params hash;\n+\t\tstruct rte_table_lpm_params lpm;\n+\t\tstruct rte_table_lpm_ipv6_params lpm_ipv6;\n+\t} pp;\n+\n+\tstruct pipeline *pipeline;\n+\tstruct table *table;\n+\tstruct table_action_profile *ap;\n+\tstruct rte_table_action *action;\n+\tuint32_t table_id;\n+\tint status;\n+\n+\tmemset(&p, 0, sizeof(p));\n+\tmemset(&pp, 0, sizeof(pp));\n+\n+\t/* Check input params */\n+\tif ((pipeline_name == NULL) ||\n+\t\t(params == NULL))\n+\t\treturn -1;\n+\n+\tpipeline = pipeline_find(softnic, pipeline_name);\n+\tif ((pipeline == NULL) ||\n+\t\t(pipeline->n_tables >= RTE_PIPELINE_TABLE_MAX))\n+\t\treturn -1;\n+\n+\tap = NULL;\n+\tif (params->action_profile_name) {\n+\t\tap = table_action_profile_find(softnic,\n+\t\t\tparams->action_profile_name);\n+\t\tif (ap == NULL)\n+\t\t\treturn -1;\n+\t}\n+\n+\tsnprintf(name, NAME_MAX, \"%s_%s_table%u\",\n+\t\tsoftnic->params.name, pipeline_name, pipeline->n_tables);\n+\n+\tswitch (params->match_type) {\n+\tcase TABLE_ACL:\n+\t{\n+\t\tuint32_t ip_header_offset = params->match.acl.ip_header_offset -\n+\t\t\t(sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);\n+\t\tuint32_t i;\n+\n+\t\tif (params->match.acl.n_rules == 0)\n+\t\t\treturn -1;\n+\n+\t\tpp.acl.name = name;\n+\t\tpp.acl.n_rules = params->match.acl.n_rules;\n+\t\tif (params->match.acl.ip_version) {\n+\t\t\tmemcpy(&pp.acl.field_format,\n+\t\t\t\t&table_acl_field_format_ipv4,\n+\t\t\t\tsizeof(table_acl_field_format_ipv4));\n+\t\t\tpp.acl.n_rule_fields =\n+\t\t\t\tRTE_DIM(table_acl_field_format_ipv4);\n+\t\t} else {\n+\t\t\tmemcpy(&pp.acl.field_format,\n+\t\t\t\t&table_acl_field_format_ipv6,\n+\t\t\t\tsizeof(table_acl_field_format_ipv6));\n+\t\t\tpp.acl.n_rule_fields =\n+\t\t\t\tRTE_DIM(table_acl_field_format_ipv6);\n+\t\t}\n+\n+\t\tfor (i = 0; i < pp.acl.n_rule_fields; i++)\n+\t\t\tpp.acl.field_format[i].offset += ip_header_offset;\n+\n+\t\tp.ops = &rte_table_acl_ops;\n+\t\tp.arg_create = &pp.acl;\n+\t\tbreak;\n+\t}\n+\n+\tcase TABLE_ARRAY:\n+\t{\n+\t\tif (params->match.array.n_keys == 0)\n+\t\t\treturn -1;\n+\n+\t\tpp.array.n_entries = params->match.array.n_keys;\n+\t\tpp.array.offset = params->match.array.key_offset;\n+\n+\t\tp.ops = &rte_table_array_ops;\n+\t\tp.arg_create = &pp.array;\n+\t\tbreak;\n+\t}\n+\n+\tcase TABLE_HASH:\n+\t{\n+\t\tstruct rte_table_ops *ops;\n+\t\trte_table_hash_op_hash f_hash;\n+\n+\t\tif (params->match.hash.n_keys == 0)\n+\t\t\treturn -1;\n+\n+\t\tswitch (params->match.hash.key_size) {\n+\t\tcase  8:\n+\t\t\tf_hash = hash_default_key8;\n+\t\t\tbreak;\n+\t\tcase 16:\n+\t\t\tf_hash = hash_default_key16;\n+\t\t\tbreak;\n+\t\tcase 24:\n+\t\t\tf_hash = hash_default_key24;\n+\t\t\tbreak;\n+\t\tcase 32:\n+\t\t\tf_hash = hash_default_key32;\n+\t\t\tbreak;\n+\t\tcase 40:\n+\t\t\tf_hash = hash_default_key40;\n+\t\t\tbreak;\n+\t\tcase 48:\n+\t\t\tf_hash = hash_default_key48;\n+\t\t\tbreak;\n+\t\tcase 56:\n+\t\t\tf_hash = hash_default_key56;\n+\t\t\tbreak;\n+\t\tcase 64:\n+\t\t\tf_hash = hash_default_key64;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tpp.hash.name = name;\n+\t\tpp.hash.key_size = params->match.hash.key_size;\n+\t\tpp.hash.key_offset = params->match.hash.key_offset;\n+\t\tpp.hash.key_mask = params->match.hash.key_mask;\n+\t\tpp.hash.n_keys = params->match.hash.n_keys;\n+\t\tpp.hash.n_buckets = params->match.hash.n_buckets;\n+\t\tpp.hash.f_hash = f_hash;\n+\t\tpp.hash.seed = 0;\n+\n+\t\tif (params->match.hash.extendable_bucket)\n+\t\t\tswitch (params->match.hash.key_size) {\n+\t\t\tcase  8:\n+\t\t\t\tops = &rte_table_hash_key8_ext_ops;\n+\t\t\t\tbreak;\n+\t\t\tcase 16:\n+\t\t\t\tops = &rte_table_hash_key16_ext_ops;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tops = &rte_table_hash_ext_ops;\n+\t\t\t}\n+\t\telse\n+\t\t\tswitch (params->match.hash.key_size) {\n+\t\t\tcase  8:\n+\t\t\t\tops = &rte_table_hash_key8_lru_ops;\n+\t\t\t\tbreak;\n+\t\t\tcase 16:\n+\t\t\t\tops = &rte_table_hash_key16_lru_ops;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tops = &rte_table_hash_lru_ops;\n+\t\t\t}\n+\n+\t\tp.ops = ops;\n+\t\tp.arg_create = &pp.hash;\n+\t\tbreak;\n+\t}\n+\n+\tcase TABLE_LPM:\n+\t{\n+\t\tif (params->match.lpm.n_rules == 0)\n+\t\t\treturn -1;\n+\n+\t\tswitch (params->match.lpm.key_size) {\n+\t\tcase 4:\n+\t\t{\n+\t\t\tpp.lpm.name = name;\n+\t\t\tpp.lpm.n_rules = params->match.lpm.n_rules;\n+\t\t\tpp.lpm.number_tbl8s = TABLE_LPM_NUMBER_TBL8;\n+\t\t\tpp.lpm.flags = 0;\n+\t\t\tpp.lpm.entry_unique_size = p.action_data_size +\n+\t\t\t\tsizeof(struct rte_pipeline_table_entry);\n+\t\t\tpp.lpm.offset = params->match.lpm.key_offset;\n+\n+\t\t\tp.ops = &rte_table_lpm_ops;\n+\t\t\tp.arg_create = &pp.lpm;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tcase 16:\n+\t\t{\n+\t\t\tpp.lpm_ipv6.name = name;\n+\t\t\tpp.lpm_ipv6.n_rules = params->match.lpm.n_rules;\n+\t\t\tpp.lpm_ipv6.number_tbl8s = TABLE_LPM_NUMBER_TBL8;\n+\t\t\tpp.lpm_ipv6.entry_unique_size = p.action_data_size +\n+\t\t\t\tsizeof(struct rte_pipeline_table_entry);\n+\t\t\tpp.lpm_ipv6.offset = params->match.lpm.key_offset;\n+\n+\t\t\tp.ops = &rte_table_lpm_ipv6_ops;\n+\t\t\tp.arg_create = &pp.lpm_ipv6;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tdefault:\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tbreak;\n+\t}\n+\n+\tcase TABLE_STUB:\n+\t{\n+\t\tp.ops = &rte_table_stub_ops;\n+\t\tp.arg_create = NULL;\n+\t\tbreak;\n+\t}\n+\n+\tdefault:\n+\t\treturn -1;\n+\t}\n+\n+\t/* Resource create */\n+\taction = NULL;\n+\tp.f_action_hit = NULL;\n+\tp.f_action_miss = NULL;\n+\tp.arg_ah = NULL;\n+\n+\tif (ap) {\n+\t\taction = rte_table_action_create(ap->ap,\n+\t\t\tsoftnic->params.cpu_id);\n+\t\tif (action == NULL)\n+\t\t\treturn -1;\n+\n+\t\tstatus = rte_table_action_table_params_get(\n+\t\t\taction,\n+\t\t\t&p);\n+\t\tif (status ||\n+\t\t\t((p.action_data_size +\n+\t\t\tsizeof(struct rte_pipeline_table_entry)) >\n+\t\t\tTABLE_RULE_ACTION_SIZE_MAX)) {\n+\t\t\trte_table_action_free(action);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tif (params->match_type == TABLE_LPM) {\n+\t\tif (params->match.lpm.key_size == 4)\n+\t\t\tpp.lpm.entry_unique_size = p.action_data_size +\n+\t\t\t\tsizeof(struct rte_pipeline_table_entry);\n+\n+\t\tif (params->match.lpm.key_size == 16)\n+\t\t\tpp.lpm_ipv6.entry_unique_size = p.action_data_size +\n+\t\t\t\tsizeof(struct rte_pipeline_table_entry);\n+\t}\n+\n+\tstatus = rte_pipeline_table_create(pipeline->p,\n+\t\t&p,\n+\t\t&table_id);\n+\tif (status) {\n+\t\trte_table_action_free(action);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Pipeline */\n+\ttable = &pipeline->table[pipeline->n_tables];\n+\tmemcpy(&table->params, params, sizeof(*params));\n+\ttable->ap = ap;\n+\ttable->a = action;\n+\tpipeline->n_tables++;\n+\n+\treturn 0;\n+}\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 7b2899e..ffd3901 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -34,8 +34,12 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_FLOW_CLASSIFY)  += -lrte_flow_classify\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PIPELINE)       += --whole-archive\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PIPELINE)       += -lrte_pipeline\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PIPELINE)       += --no-whole-archive\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_TABLE)       \t+= --whole-archive\n _LDLIBS-$(CONFIG_RTE_LIBRTE_TABLE)          += -lrte_table\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_TABLE)       \t+= --no-whole-archive\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PORT)       \t+= --whole-archive\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PORT)           += -lrte_port\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PORT)      \t\t+= --no-whole-archive\n \n _LDLIBS-$(CONFIG_RTE_LIBRTE_PDUMP)          += -lrte_pdump\n _LDLIBS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR)    += -lrte_distributor\n",
    "prefixes": [
        "dpdk-dev",
        "09/21"
    ]
}