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{
    "id": 389,
    "url": "https://patches.dpdk.org/api/patches/389/",
    "web_url": "https://patches.dpdk.org/patch/389/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1410940461-17509-3-git-send-email-helin.zhang@intel.com>",
    "date": "2014-09-17T07:54:20",
    "name": "[dpdk-dev,2/3] i40e: rework of PF interrupt cause enable flags processing",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d58f3c2e548239e4337211669d2d65dd078f796c",
    "submitter": {
        "id": 14,
        "url": "https://patches.dpdk.org/api/people/14/",
        "name": "Helin Zhang",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/patch/389/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/389/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/389/checks/",
    "tags": {},
    "headers": {
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Original-To": "patchwork@dpdk.org",
        "Date": "Wed, 17 Sep 2014 15:54:20 +0800",
        "In-Reply-To": "<1410940461-17509-1-git-send-email-helin.zhang@intel.com>",
        "Precedence": "list",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<1410940461-17509-1-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "To": "dev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id B41F8B3A0;\n\tWed, 17 Sep 2014 09:48:55 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id D4565B39D\n\tfor <dev@dpdk.org>; Wed, 17 Sep 2014 09:48:52 +0200 (CEST)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP; 17 Sep 2014 00:48:21 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga002.jf.intel.com with ESMTP; 17 Sep 2014 00:54:30 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8H7sTiI024841;\n\tWed, 17 Sep 2014 15:54:29 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8H7sQTn017559; Wed, 17 Sep 2014 15:54:28 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8H7sQja017555; \n\tWed, 17 Sep 2014 15:54:26 +0800"
        ],
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "X-ExtLoop1": "1",
        "Message-Id": "<1410940461-17509-3-git-send-email-helin.zhang@intel.com>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH 2/3] i40e: rework of PF interrupt cause enable\n\tflags processing",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,539,1406617200\"; d=\"scan'208\";a=\"604030999\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "X-Mailman-Version": "2.1.15"
    },
    "content": "To get the code cleaner and more straightforward, a macro\nis defined for all interrupt cause enable flags. Two more\ncauses are enabled, and all the interrupt causes for\nreporting any errors are compiled conditionally, as they\nare for debug only.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Jing Chen <jing.d.chen@intel.com>\nReviewed-by: Jijiang Liu <jijiang.liu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 72 +++++++++++++++++++--------------------\n 1 file changed, 35 insertions(+), 37 deletions(-)",
    "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 003b084..6df41ea 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -117,6 +117,19 @@\n \t(1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \\\n \t(1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n \n+/* Mask of PF interrupt causes */\n+#define I40E_PFINT_ICR0_ENA_MASK ( \\\n+\t\tI40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_GRST_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_VFLR_MASK | \\\n+\t\tI40E_PFINT_ICR0_ENA_ADMINQ_MASK)\n+\n static int eth_i40e_dev_init(\\\n \t\t\t__attribute__((unused)) struct eth_driver *eth_drv,\n \t\t\tstruct rte_eth_dev *eth_dev);\n@@ -3261,24 +3274,9 @@ i40e_pf_enable_irq0(struct i40e_hw *hw)\n static void\n i40e_pf_config_irq0(struct i40e_hw *hw)\n {\n-\tuint32_t enable;\n-\n \t/* read pending request and disable first */\n \ti40e_pf_disable_irq0(hw);\n-\t/**\n-\t * Enable all interrupt error options to detect possible errors,\n-\t * other informative int are ignored\n-\t */\n-\tenable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |\n-\t         I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |\n-\t         I40E_PFINT_ICR0_ENA_GRST_MASK |\n-\t         I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |\n-\t         I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |\n-\t         I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |\n-\t         I40E_PFINT_ICR0_ENA_VFLR_MASK |\n-\t         I40E_PFINT_ICR0_ENA_ADMINQ_MASK;\n-\n-\tI40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);\n+\tI40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);\n \tI40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,\n \t\tI40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);\n \n@@ -3398,44 +3396,44 @@ i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n \ticr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);\n \ticr0_ena = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);\n \n-\t/* Shared IRQ case, return */\n+\t/* No interrupt event indicated */\n \tif (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {\n-\t\tPMD_DRV_LOG(INFO, \"Port%d INT0:share IRQ case, \"\n-\t\t\t\"no INT event to process\\n\", hw->pf_id);\n+\t\tPMD_DRV_LOG(INFO, \"No interrupt event\\n\");\n \t\tgoto done;\n \t}\n \n-\tif (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {\n-\t\tPMD_DRV_LOG(INFO, \"INT:Link status changed\\n\");\n-\t\ti40e_dev_link_update(dev, 0);\n-\t}\n-\n+#ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER\n \tif (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)\n-\t\tPMD_DRV_LOG(INFO, \"INT:Unrecoverable ECC Error\\n\");\n-\n+\t\tPMD_DRV_LOG(ERR, \"ICR0: unrecoverable ECC error\\n\");\n \tif (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)\n-\t\tPMD_DRV_LOG(INFO, \"INT:Malicious programming detected\\n\");\n-\n+\t\tPMD_DRV_LOG(ERR, \"ICR0: malicious programming detected\\n\");\n \tif (icr0 & I40E_PFINT_ICR0_GRST_MASK)\n-\t\tPMD_DRV_LOG(INFO, \"INT:Global Resets Requested\\n\");\n-\n+\t\tPMD_DRV_LOG(INFO, \"ICR0: global reset requested\\n\");\n \tif (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)\n-\t\tPMD_DRV_LOG(INFO, \"INT:PCI EXCEPTION occured\\n\");\n-\n+\t\tPMD_DRV_LOG(INFO, \"ICR0: PCI exception\\n activated\\n\");\n+\tif (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)\n+\t\tPMD_DRV_LOG(INFO, \"ICR0: a change in the storm control \"\n+\t\t\t\t\t\t\t\t\"state\\n\");\n \tif (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)\n-\t\tPMD_DRV_LOG(INFO, \"INT:HMC error occured\\n\");\n+\t\tPMD_DRV_LOG(ERR, \"ICR0: HMC error\\n\");\n+\tif (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)\n+\t\tPMD_DRV_LOG(ERR, \"ICR0: protocol engine critical error\\n\");\n+#endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */\n \n-\t/* Add processing func to deal with VF reset vent */\n \tif (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {\n-\t\tPMD_DRV_LOG(INFO, \"INT:VF reset detected\\n\");\n+\t\tPMD_DRV_LOG(INFO, \"ICR0: VF reset detected\\n\");\n \t\ti40e_dev_handle_vfr_event(dev);\n \t}\n-\t/* Find admin queue event */\n \tif (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {\n-\t\tPMD_DRV_LOG(INFO, \"INT:ADMINQ event\\n\");\n+\t\tPMD_DRV_LOG(INFO, \"ICR0: adminq event\\n\");\n \t\ti40e_dev_handle_aq_msg(dev);\n \t}\n \n+\tif (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {\n+\t\tPMD_DRV_LOG(INFO, \"INT:Link status changed\\n\");\n+\t\ti40e_dev_link_update(dev, 0);\n+\t}\n+\n done:\n \tI40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, icr0_ena);\n \t/* Re-enable interrupt from device side */\n",
    "prefixes": [
        "dpdk-dev",
        "2/3"
    ]
}