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GET /api/patches/35835/?format=api
{ "id": 35835, "url": "https://patches.dpdk.org/api/patches/35835/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1520584954-130575-16-git-send-email-Ravi1.kumar@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1520584954-130575-16-git-send-email-Ravi1.kumar@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1520584954-130575-16-git-send-email-Ravi1.kumar@amd.com", "date": "2018-03-09T08:42:32", "name": "[dpdk-dev,v3,16/18] net/axgbe: add support for build 32-bit mode", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "498b44d02432fdc3bb424c5591140ef8df563984", "submitter": { "id": 819, "url": "https://patches.dpdk.org/api/people/819/?format=api", "name": "Kumar, Ravi1", "email": "ravi1.kumar@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1520584954-130575-16-git-send-email-Ravi1.kumar@amd.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/35835/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/35835/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 97A82AAC3;\n\tFri, 9 Mar 2018 09:43:29 +0100 (CET)", "from NAM01-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam01on0067.outbound.protection.outlook.com [104.47.34.67])\n\tby dpdk.org (Postfix) with ESMTP id 37E941B024\n\tfor <dev@dpdk.org>; Fri, 9 Mar 2018 09:43:27 +0100 (CET)", "from wallaby-smavila.amd.com (202.56.249.162) by\n\tMWHPR12MB1517.namprd12.prod.outlook.com (2603:10b6:301:b::21) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.567.12;\n\tFri, 9 Mar 2018 08:43:24 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amdcloud.onmicrosoft.com; s=selector1-amd-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=QKyYy1kkwfKx9l4ARnmnWptndasexFQ20D9tzCt61as=;\n\tb=MCJ3s8r4Cr9yap8SZeZm5egyck0EFy6/eZuoi1Mc5j4jLQBWUx+FxDHL2nM2p6mWAou17mAJW5Rjvb85PkpK+/iz1BsV6+0fslz2MToitxVLBDrc+cx51fZhaUfcfZLvgo4hvIv5GVm0XB541uu3315+8LulWvlO/CpnzkVDB50=", "From": "Ravi Kumar <Ravi1.kumar@amd.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com", "Date": "Fri, 9 Mar 2018 03:42:32 -0500", "Message-Id": "<1520584954-130575-16-git-send-email-Ravi1.kumar@amd.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1520584954-130575-1-git-send-email-Ravi1.kumar@amd.com>", "References": "<1515145938-97474-1-git-send-email-Ravi1.kumar@amd.com>\n\t<1520584954-130575-1-git-send-email-Ravi1.kumar@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[202.56.249.162]", "X-ClientProxiedBy": "BM1PR0101CA0057.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:19::19) To MWHPR12MB1517.namprd12.prod.outlook.com\n\t(2603:10b6:301:b::21)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-HT": "Tenant", "X-MS-Office365-Filtering-Correlation-Id": "8dd61824-5034-4bb7-1fe1-08d58599d2f0", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);\n\tSRVR:MWHPR12MB1517; ", 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"ZT0u4tunQTNCPbEO7XisUNegvLXkVd8IMyFauIpuh4aZrDCoVl9vMP8CMOeR/oipGaruTJ2o4LUBV9Gc2DL4faz2ocolmr3rzKXKT5b3Ai8IE0IugX1WU5+kEpvkF7l0ftwdefupmct13lhd4RtwBJ/mFB00FzVapcDHyyZSS0yI7LR932BQaHG+RHLhgLKk", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Mar 2018 08:43:24.8392\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "8dd61824-5034-4bb7-1fe1-08d58599d2f0", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1517", "Subject": "[dpdk-dev] [PATCH v3 16/18] net/axgbe: add support for build 32-bit\n\tmode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Ravi Kumar <Ravi1.kumar@amd.com>\n---\n doc/guides/nics/features/axgbe.ini | 1 +\n drivers/net/axgbe/axgbe_common.h | 53 ++++++++++++++++++++++----------------\n drivers/net/axgbe/axgbe_ethdev.c | 10 ++++---\n drivers/net/axgbe/axgbe_ethdev.h | 8 +++---\n drivers/net/axgbe/axgbe_rxtx.c | 12 ++++-----\n drivers/net/axgbe/axgbe_rxtx.h | 4 +--\n 6 files changed, 50 insertions(+), 38 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/axgbe.ini b/doc/guides/nics/features/axgbe.ini\nindex 042ff1e..ab4da55 100644\n--- a/doc/guides/nics/features/axgbe.ini\n+++ b/doc/guides/nics/features/axgbe.ini\n@@ -15,4 +15,5 @@ L3 checksum offload = Y\n L4 checksum offload = Y\n Basic stats = Y\n Linux UIO = Y\n+x86-32 = Y\n x86-64 = Y\ndiff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h\nindex 294f2e4..189139b 100644\n--- a/drivers/net/axgbe/axgbe_common.h\n+++ b/drivers/net/axgbe/axgbe_common.h\n@@ -1507,7 +1507,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n * register definitions formed using the input names\n */\n #define AXGMAC_IOREAD(_pdata, _reg)\t\t\t\t\t\\\n-\trte_read32((void *)((_pdata)->xgmac_regs + (_reg)))\n+\trte_read32((uint8_t *)((_pdata)->xgmac_regs) + (_reg))\n \n #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field)\t\t\t\\\n \tGET_BITS(AXGMAC_IOREAD((_pdata), _reg),\t\t\t\t\\\n@@ -1515,7 +1515,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define AXGMAC_IOWRITE(_pdata, _reg, _val)\t\t\t\t\\\n-\trte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg)))\n+\trte_write32((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->xgmac_regs) + (_reg))\n \n #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val)\t\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1531,8 +1532,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n * base register value is calculated by the queue or traffic class number\n */\n #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg)\t\t\t\t\\\n-\trte_read32((void *)((_pdata)->xgmac_regs +\t\t\t\\\n-\t\t MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)))\n+\trte_read32((uint8_t *)((_pdata)->xgmac_regs) +\t\t\\\n+\t\t MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))\n \n #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field)\t\t\\\n \tGET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)),\t\t\\\n@@ -1540,8 +1541,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val)\t\t\t\\\n-\trte_write32((_val), (void *)((_pdata)->xgmac_regs +\t\t\\\n-\t\t MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)))\n+\trte_write32((_val), (uint8_t *)((_pdata)->xgmac_regs) +\\\n+\t\t MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))\n \n #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val)\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1557,7 +1558,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n * base register value is obtained from the ring\n */\n #define AXGMAC_DMA_IOREAD(_channel, _reg)\t\t\t\t\\\n-\trte_read32((void *)((_channel)->dma_regs + (_reg)))\n+\trte_read32((uint8_t *)((_channel)->dma_regs) + (_reg))\n \n #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field)\t\t\t\\\n \tGET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg),\t\t\t\\\n@@ -1565,7 +1566,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val)\t\t\t\\\n-\trte_write32((_val), (void *)((_channel)->dma_regs + (_reg)))\n+\trte_write32((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_channel)->dma_regs) + (_reg))\n \n #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val)\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1590,16 +1592,18 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _prefix##_##_field##_WIDTH, (_val))\n \n #define XPCS32_IOWRITE(_pdata, _off, _val)\t\t\t\t\\\n-\trte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off)))\n+\trte_write32(_val,\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->xpcs_regs) + (_off))\n \n #define XPCS32_IOREAD(_pdata, _off)\t\t\t\t\t\\\n-\trte_read32((void *)((_pdata)->xpcs_regs + (_off)))\n+\trte_read32((uint8_t *)((_pdata)->xpcs_regs) + (_off))\n \n #define XPCS16_IOWRITE(_pdata, _off, _val)\t\t\t\t\\\n-\trte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off)))\n+\trte_write16(_val,\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->xpcs_regs) + (_off))\n \n #define XPCS16_IOREAD(_pdata, _off)\t\t\t\t\t\\\n-\trte_read16((void *)((_pdata)->xpcs_regs + (_off)))\n+\trte_read16((uint8_t *)((_pdata)->xpcs_regs) + (_off))\n \n /* Macros for building, reading or writing register values or bits\n * within the register values of SerDes integration registers.\n@@ -1615,7 +1619,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _prefix##_##_field##_WIDTH, (_val))\n \n #define XSIR0_IOREAD(_pdata, _reg)\t\t\t\t\t\\\n-\trte_read16((void *)((_pdata)->sir0_regs + (_reg)))\n+\trte_read16((uint8_t *)((_pdata)->sir0_regs) + (_reg))\n \n #define XSIR0_IOREAD_BITS(_pdata, _reg, _field)\t\t\t\t\\\n \tGET_BITS(XSIR0_IOREAD((_pdata), _reg),\t\t\t\t\\\n@@ -1623,7 +1627,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define XSIR0_IOWRITE(_pdata, _reg, _val)\t\t\t\t\\\n-\trte_write16((_val), (void *)((_pdata)->sir0_regs + (_reg)))\n+\trte_write16((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->sir0_regs) + (_reg))\n \n #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val)\t\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1635,7 +1640,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n } while (0)\n \n #define XSIR1_IOREAD(_pdata, _reg)\t\t\t\t\t\\\n-\trte_read16((void *)((_pdata)->sir1_regs + _reg))\n+\trte_read16((uint8_t *)((_pdata)->sir1_regs) + _reg)\n \n #define XSIR1_IOREAD_BITS(_pdata, _reg, _field)\t\t\t\t\\\n \tGET_BITS(XSIR1_IOREAD((_pdata), _reg),\t\t\t\t\\\n@@ -1643,7 +1648,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define XSIR1_IOWRITE(_pdata, _reg, _val)\t\t\t\t\\\n-\trte_write16((_val), (void *)((_pdata)->sir1_regs + (_reg)))\n+\trte_write16((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->sir1_regs) + (_reg))\n \n #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val)\t\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1658,7 +1664,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n * within the register values of SerDes RxTx registers.\n */\n #define XRXTX_IOREAD(_pdata, _reg)\t\t\t\t\t\\\n-\trte_read16((void *)((_pdata)->rxtx_regs + (_reg)))\n+\trte_read16((uint8_t *)((_pdata)->rxtx_regs) + (_reg))\n \n #define XRXTX_IOREAD_BITS(_pdata, _reg, _field)\t\t\t\t\\\n \tGET_BITS(XRXTX_IOREAD((_pdata), _reg),\t\t\t\t\\\n@@ -1666,7 +1672,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define XRXTX_IOWRITE(_pdata, _reg, _val)\t\t\t\t\\\n-\trte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg)))\n+\trte_write16((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->rxtx_regs) + (_reg))\n \n #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val)\t\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1691,7 +1698,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _prefix##_##_field##_WIDTH, (_val))\n \n #define XP_IOREAD(_pdata, _reg)\t\t\t\t\t\t\\\n-\trte_read32((void *)((_pdata)->xprop_regs + (_reg)))\n+\trte_read32((uint8_t *)((_pdata)->xprop_regs) + (_reg))\n \n #define XP_IOREAD_BITS(_pdata, _reg, _field)\t\t\t\t\\\n \tGET_BITS(XP_IOREAD((_pdata), (_reg)),\t\t\t\t\\\n@@ -1699,7 +1706,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define XP_IOWRITE(_pdata, _reg, _val)\t\t\t\t\t\\\n-\trte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg)))\n+\trte_write32((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->xprop_regs) + (_reg))\n \n #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val)\t\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\n@@ -1724,7 +1732,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _prefix##_##_field##_WIDTH, (_val))\n \n #define XI2C_IOREAD(_pdata, _reg)\t\t\t\t\t\\\n-\trte_read32((void *)((_pdata)->xi2c_regs + (_reg)))\n+\trte_read32((uint8_t *)((_pdata)->xi2c_regs) + (_reg))\n \n #define XI2C_IOREAD_BITS(_pdata, _reg, _field)\t\t\t\t\\\n \tGET_BITS(XI2C_IOREAD((_pdata), (_reg)),\t\t\t\t\\\n@@ -1732,7 +1740,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t _reg##_##_field##_WIDTH)\n \n #define XI2C_IOWRITE(_pdata, _reg, _val)\t\t\t\t\\\n-\trte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg)))\n+\trte_write32((_val),\t\t\t\t\t\t\\\n+\t\t (uint8_t *)((_pdata)->xi2c_regs) + (_reg))\n \n #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val)\t\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c\nindex 9e5114b..d4d437a 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.c\n+++ b/drivers/net/axgbe/axgbe_ethdev.c\n@@ -712,10 +712,12 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)\n \tpdata->pci_dev = pci_dev;\n \n \tpdata->xgmac_regs =\n-\t\t(uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;\n-\tpdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET;\n-\tpdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET;\n-\tpdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;\n+\t\t(void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;\n+\tpdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs\n+\t\t\t\t + AXGBE_MAC_PROP_OFFSET);\n+\tpdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs\n+\t\t\t\t + AXGBE_I2C_CTRL_OFFSET);\n+\tpdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;\n \n \t/* version specific driver data*/\n \tif (pci_dev->id.device_id == 0x1458)\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h\nindex 4091d1a..91260ca 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.h\n+++ b/drivers/net/axgbe/axgbe_ethdev.h\n@@ -567,10 +567,10 @@ struct axgbe_port {\n \tstruct axgbe_version_data *vdata;\n \n \t/* AXGMAC/XPCS related mmio registers */\n-\tuint64_t xgmac_regs;\t/* AXGMAC CSRs */\n-\tuint64_t xpcs_regs;\t/* XPCS MMD registers */\n-\tuint64_t xprop_regs;\t/* AXGBE property registers */\n-\tuint64_t xi2c_regs;\t/* AXGBE I2C CSRs */\n+\tvoid *xgmac_regs;\t/* AXGMAC CSRs */\n+\tvoid *xpcs_regs;\t/* XPCS MMD registers */\n+\tvoid *xprop_regs;\t/* AXGBE property registers */\n+\tvoid *xi2c_regs;\t/* AXGBE I2C CSRs */\n \n \t/* XPCS indirect addressing lock */\n \tunsigned int xpcs_window_def_reg;\ndiff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c\nindex c616fc1..4c38e47 100644\n--- a/drivers/net/axgbe/axgbe_rxtx.c\n+++ b/drivers/net/axgbe/axgbe_rxtx.c\n@@ -192,9 +192,9 @@ int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \trxq->queue_id = queue_idx;\n \trxq->port_id = dev->data->port_id;\n \trxq->nb_desc = rx_desc;\n-\trxq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +\n-\t\t(DMA_CH_INC * rxq->queue_id);\n-\trxq->dma_tail_reg = (volatile uint32_t *)(rxq->dma_regs +\n+\trxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +\n+\t\t(DMA_CH_INC * rxq->queue_id));\n+\trxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs +\n \t\t\t\t\t\t DMA_CH_RDTR_LO);\n \n \trxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :\n@@ -509,9 +509,9 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \ttxq->desc = tz->addr;\n \ttxq->queue_id = queue_idx;\n \ttxq->port_id = dev->data->port_id;\n-\ttxq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +\n-\t\t(DMA_CH_INC * txq->queue_id);\n-\ttxq->dma_tail_reg = (volatile uint32_t *)(txq->dma_regs +\n+\ttxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +\n+\t\t(DMA_CH_INC * txq->queue_id));\n+\ttxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs +\n \t\t\t\t\t\t DMA_CH_TDTR_LO);\n \ttxq->cur = 0;\n \ttxq->dirty = 0;\ndiff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx.h\nindex 45aaf89..e7b3cfd 100644\n--- a/drivers/net/axgbe/axgbe_rxtx.h\n+++ b/drivers/net/axgbe/axgbe_rxtx.h\n@@ -202,7 +202,7 @@ struct axgbe_rx_queue {\n \t/* Ring physical address */\n \tuint64_t ring_phys_addr;\n \t/* Dma Channel register address */\n-\tuint64_t dma_regs;\n+\tvoid *dma_regs;\n \t/* Dma channel tail register address*/\n \tvolatile uint32_t *dma_tail_reg;\n \t/* DPDK queue index */\n@@ -249,7 +249,7 @@ struct axgbe_tx_queue {\n \t/* Physical address of ring */\n \tuint64_t ring_phys_addr;\n \t/* Dma channel register space */\n-\tuint64_t dma_regs;\n+\tvoid *dma_regs;\n \t/* Dma tail register address of ring*/\n \tvolatile uint32_t *dma_tail_reg;\n \t/* Tx queue index/id*/\n", "prefixes": [ "dpdk-dev", "v3", "16/18" ] }