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GET /api/patches/34831/?format=api
{ "id": 34831, "url": "https://patches.dpdk.org/api/patches/34831/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1517486402-81403-3-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517486402-81403-3-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517486402-81403-3-git-send-email-beilei.xing@intel.com", "date": "2018-02-01T12:00:01", "name": "[dpdk-dev,v2,2/3] net/i40e: add debug logs when writing global registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "da01bc2d99bdbab057e96e3316b3e16c02d74da7", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1517486402-81403-3-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/34831/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/34831/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 639061B1AF;\n\tThu, 1 Feb 2018 12:59:31 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 53FDEA499;\n\tThu, 1 Feb 2018 12:59:28 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t01 Feb 2018 03:59:27 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby FMSMGA003.fm.intel.com with ESMTP; 01 Feb 2018 03:59:26 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,444,1511856000\"; d=\"scan'208\";a=\"24110412\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "jingjing.wu@intel.com,\n\tdev@dpdk.org,\n\tstable@dpdk.org", "Date": "Thu, 1 Feb 2018 20:00:01 +0800", "Message-Id": "<1517486402-81403-3-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1517486402-81403-1-git-send-email-beilei.xing@intel.com>", "References": "<1516702905-131472-1-git-send-email-beilei.xing@intel.com>\n\t<1517486402-81403-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 2/3] net/i40e: add debug logs when writing\n\tglobal registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add debug logs when writing global registers.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nCc: stable@dpdk.org\n---\n drivers/net/i40e/i40e_ethdev.c | 131 ++++++++++++++++++++++++++---------------\n drivers/net/i40e/i40e_ethdev.h | 9 +++\n 2 files changed, 92 insertions(+), 48 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 44821f2..6d6d6d2 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -716,6 +716,15 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static inline void\n+i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n+{\n+\ti40e_write_rx_ctl(hw, reg_addr, reg_val);\n+\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is modified \"\n+\t\t \"with value 0x%08x\",\n+\t\t reg_addr, reg_val);\n+}\n+\n RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);\n RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);\n \n@@ -735,9 +744,9 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t * configuration API is added to avoid configuration conflicts\n \t * between ports of the same device.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n \ti40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);\n \n \t/*\n@@ -746,8 +755,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t * configuration API is added to avoid configuration conflicts\n \t * between ports of the same device.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n \ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n@@ -2799,8 +2808,9 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t\t \"I40E_GL_SWT_L2TAGCTRL[%d]\", reg_id);\n \t\treturn ret;\n \t}\n-\tPMD_DRV_LOG(DEBUG, \"Debug write 0x%08\"PRIx64\" to \"\n-\t\t \"I40E_GL_SWT_L2TAGCTRL[%d]\", reg_w, reg_id);\n+\tPMD_DRV_LOG(DEBUG,\n+\t\t \"Global register 0x%08x is changed with value 0x%08x\"\n+\t\t I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);\n \n \ti40e_global_cfg_warning(I40E_WARNING_TPID);\n \n@@ -3030,16 +3040,16 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t}\n \n \t/* config the water marker both based on the packets and bytes */\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_PHW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n \t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_PLW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n \t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_GHW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n \t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_GLW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n \t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n \ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n@@ -6880,6 +6890,9 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n \t\t\t\t\t\t reg, NULL);\n \t\tif (ret != 0)\n \t\t\treturn ret;\n+\t\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is changed \"\n+\t\t\t \"with value 0x%08x\",\n+\t\t\t I40E_GL_PRS_FVBM(2), reg);\n \t\ti40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);\n \t} else {\n \t\tret = 0;\n@@ -7124,41 +7137,43 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\tI40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n \t\tif (hw->mac.type == I40E_MAC_X722) {\n \t\t\tif (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),\n \t\t\t\t reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),\n \t\t\t\t reg);\n \t\t\t} else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),\n \t\t\t\t reg);\n \t\t\t} else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),\n \t\t\t\t reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),\n \t\t\t\t reg);\n \t\t\t} else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),\n \t\t\t\t reg);\n \t\t\t} else {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),\n-\t\t\t\t reg);\n+\t\t\t\ti40e_write_global_rx_ctl(hw,\n+\t\t\t\t\t\t\t I40E_GLQF_HSYM(pctype),\n+\t\t\t\t\t\t\t reg);\n \t\t\t}\n \t\t} else {\n-\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);\n+\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(pctype),\n+\t\t\t\t\t\t reg);\n \t\t}\n \t\ti40e_global_cfg_warning(I40E_WARNING_HSYM);\n \t}\n@@ -7184,7 +7199,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t/* Use the default, and keep it as it is */\n \t\tgoto out;\n \n-\ti40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);\n+\ti40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);\n \ti40e_global_cfg_warning(I40E_WARNING_QF_CTL);\n \n out:\n@@ -7799,6 +7814,18 @@ i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n }\n \n static void\n+i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n+{\n+\tuint32_t reg = i40e_read_rx_ctl(hw, addr);\n+\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\", addr, reg);\n+\tif (reg != val)\n+\t\ti40e_write_global_rx_ctl(hw, addr, val);\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\", addr,\n+\t\t (uint32_t)i40e_read_rx_ctl(hw, addr));\n+}\n+\n+static void\n i40e_filter_input_set_init(struct i40e_pf *pf)\n {\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n@@ -7831,24 +7858,28 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n \t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n \t\tfor (i = 0; i < num; i++) {\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n \t\t}\n \t\t/*clear unused mask registers of the pctype */\n \t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t 0);\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t 0);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n \t\t}\n \t\tI40E_WRITE_FLUSH(hw);\n \n@@ -7920,20 +7951,20 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \n \tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n \n-\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n-\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n-\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n+\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n \n \tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t mask_reg[i]);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t mask_reg[i]);\n \t/*clear unused mask registers of the pctype */\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t 0);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t 0);\n \ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n@@ -8007,12 +8038,12 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n \tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t mask_reg[i]);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t mask_reg[i]);\n \t/*clear unused mask registers of the pctype */\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t 0);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t 0);\n \ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n@@ -9357,6 +9388,10 @@ i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)\n \t/* Check if enabled_tc is same as existing or new TCs */\n \tif (vsi->enabled_tc == tc_map)\n \t\treturn ret;\n+\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t \"cloud l1 type is changed from 0x%x to 0x%x\",\n+\t\t filter_replace.old_filter_type,\n+\t\t filter_replace.new_filter_type);\n \n \t/* configure tc bandwidth */\n \tmemset(&bw_data, 0, sizeof(bw_data));\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 1d813ef..c7a22d7 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -103,6 +103,15 @@\n \t(((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \\\n \t((vf)->version_minor == 1))\n \n+#define I40E_WRITE_GLB_REG(hw, reg, value)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tI40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw),\t\t\\\n+\t\t\t\t\t\t (reg)), (value));\t\\\n+\t\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is modified \" \\\n+\t\t\t \"with value 0x%08x\",\t\t\t\\\n+\t\t\t reg, value);\t\t\t\t\\\n+\t} while (0)\n+\n /* index flex payload per layer */\n enum i40e_flxpld_layer_idx {\n \tI40E_FLXPLD_L2_IDX = 0,\n", "prefixes": [ "dpdk-dev", "v2", "2/3" ] }