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{
    "id": 322,
    "url": "https://patches.dpdk.org/api/patches/322/",
    "web_url": "https://patches.dpdk.org/patch/322/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1410247299-4365-9-git-send-email-helin.zhang@intel.com>",
    "date": "2014-09-09T07:21:32",
    "name": "[dpdk-dev,08/15] i40e: remove code which is for software validation only",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "6ddb7725672550341bf57b3baf4089e24b3edbbd",
    "submitter": {
        "id": 14,
        "url": "https://patches.dpdk.org/api/people/14/",
        "name": "Helin Zhang",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/patch/322/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/322/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/322/checks/",
    "tags": {},
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "References": "<1410247299-4365-1-git-send-email-helin.zhang@intel.com>",
        "X-Mailman-Version": "2.1.15",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,491,1406617200\"; d=\"scan'208\";a=\"570392074\"",
        "Date": "Tue,  9 Sep 2014 15:21:32 +0800",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "X-BeenThere": "dev@dpdk.org",
        "Message-Id": "<1410247299-4365-9-git-send-email-helin.zhang@intel.com>",
        "X-Original-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 28EFEB3B3;\n\tTue,  9 Sep 2014 09:17:13 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 3DE52B3B9\n\tfor <dev@dpdk.org>; Tue,  9 Sep 2014 09:17:09 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP; 09 Sep 2014 00:16:04 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 09 Sep 2014 00:22:08 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s897M7SL008875;\n\tTue, 9 Sep 2014 15:22:07 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s897M4qd004481; Tue, 9 Sep 2014 15:22:06 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s897M4ek004477; \n\tTue, 9 Sep 2014 15:22:04 +0800"
        ],
        "List-Post": "<mailto:dev@dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH 08/15] i40e: remove code which is for software\n\tvalidation only",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "Precedence": "list",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "X-ExtLoop1": "1",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "Delivered-To": "patchwork@dpdk.org",
        "In-Reply-To": "<1410247299-4365-1-git-send-email-helin.zhang@intel.com>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "To": "dev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "The code wrapped in '#ifdef I40E_DCB_SW' is currently for software\nvalidation only, it should be removed at all.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Chen Jing <jing.d.chen@intel.com>\n---\n lib/librte_pmd_i40e/i40e/i40e_common.c    |  27 --\n lib/librte_pmd_i40e/i40e/i40e_dcb.c       | 625 ------------------------------\n lib/librte_pmd_i40e/i40e/i40e_dcb.h       | 103 -----\n lib/librte_pmd_i40e/i40e/i40e_prototype.h |   6 -\n lib/librte_pmd_i40e/i40e/i40e_type.h      |  40 --\n 5 files changed, 801 deletions(-)",
    "diff": "diff --git a/lib/librte_pmd_i40e/i40e/i40e_common.c b/lib/librte_pmd_i40e/i40e/i40e_common.c\nindex 4254aad..4f11542 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_common.c\n+++ b/lib/librte_pmd_i40e/i40e/i40e_common.c\n@@ -4575,33 +4575,6 @@ enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,\n \n \treturn status;\n }\n-#ifdef I40E_DCB_SW\n-\n-/**\n- * i40e_aq_suspend_port_tx\n- * @hw: pointer to the hardware structure\n- * @seid: port seid\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Suspend port's Tx traffic\n- **/\n-enum i40e_status_code i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n-{\n-\tstruct i40e_aq_desc desc;\n-\tenum i40e_status_code status;\n-\tstruct i40e_aqc_tx_sched_ind *cmd =\n-\t\t(struct i40e_aqc_tx_sched_ind *)&desc.params.raw;\n-\n-\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);\n-\n-\tcmd->vsi_seid = CPU_TO_LE16(seid);\n-\n-\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\treturn status;\n-}\n-#endif /* I40E_DCB_SW */\n \n /**\n  * i40e_aq_resume_port_tx\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_dcb.c b/lib/librte_pmd_i40e/i40e/i40e_dcb.c\nindex 435cf80..d067028 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_dcb.c\n+++ b/lib/librte_pmd_i40e/i40e/i40e_dcb.c\n@@ -477,628 +477,3 @@ enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw)\n \n \treturn ret;\n }\n-#ifdef I40E_DCB_SW\n-\n-/**\n- * i40e_dcbx_event_handler\n- * @hw: pointer to the hw struct\n- * @e: event data to be processed (LLDPDU)\n- *\n- * Process LLDP MIB Change event from the Firmware\n- **/\n-enum i40e_status_code i40e_process_lldp_event(struct i40e_hw *hw,\n-\t\t\t\t\t      struct i40e_arq_event_info *e)\n-{\n-\tenum i40e_status_code ret = I40E_SUCCESS;\n-\tUNREFERENCED_2PARAMETER(hw, e);\n-\n-\treturn ret;\n-}\n-\n-/**\n- * i40e_dcb_hw_rx_fifo_config\n- * @hw: pointer to the hw struct\n- * @ets_mode: Strict Priority or Round Robin mode\n- * @non_ets_mode: Strict Priority or Round Robin\n- * @max_exponent: Exponent to calculate max refill credits\n- * @lltc_map: Low latency TC bitmap\n- *\n- * Configure HW Rx FIFO as part of DCB configuration.\n- **/\n-void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,\n-\t\t\t\tenum i40e_dcb_arbiter_mode ets_mode,\n-\t\t\t\tenum i40e_dcb_arbiter_mode non_ets_mode,\n-\t\t\t\tu32 max_exponent,\n-\t\t\t\tu8 lltc_map)\n-{\n-\tu32 reg = 0;\n-\n-\treg = rd32(hw, I40E_PRTDCB_RETSC);\n-\n-\treg &= ~I40E_PRTDCB_RETSC_ETS_MODE_MASK;\n-\treg |= ((u32)ets_mode << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) &\n-\t\tI40E_PRTDCB_RETSC_ETS_MODE_MASK;\n-\n-\treg &= ~I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK;\n-\treg |= ((u32)non_ets_mode << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) &\n-\t\tI40E_PRTDCB_RETSC_NON_ETS_MODE_MASK;\n-\n-\treg &= ~I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK;\n-\treg |= (max_exponent << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) &\n-\t\tI40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK;\n-\n-\treg &= ~I40E_PRTDCB_RETSC_LLTC_MASK;\n-\treg |= (lltc_map << I40E_PRTDCB_RETSC_LLTC_SHIFT) &\n-\t\tI40E_PRTDCB_RETSC_LLTC_MASK;\n-\twr32(hw, I40E_PRTDCB_RETSC, reg);\n-}\n-\n-/**\n- * i40e_dcb_hw_rx_cmd_monitor_config\n- * @hw: pointer to the hw struct\n- * @num_tc: Total number of traffic class\n- * @num_ports: Total number of ports on device\n- *\n- * Configure HW Rx command monitor as part of DCB configuration.\n- **/\n-void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,\n-\t\t\t\t       u8 num_tc, u8 num_ports)\n-{\n-\tu32 threshold = 0;\n-\tu32 fifo_size = 0;\n-\tu32 reg = 0;\n-\n-\t/* Set the threshold and fifo_size based on number of ports */\n-\tswitch (num_ports) {\n-\tcase 1:\n-\t\tthreshold = 0xF;\n-\t\tfifo_size = 0x10;\n-\t\tbreak;\n-\tcase 2:\n-\t\tif (num_tc > 4) {\n-\t\t\tthreshold = 0xC;\n-\t\t\tfifo_size = 0x8;\n-\t\t} else {\n-\t\t\tthreshold = 0xF;\n-\t\t\tfifo_size = 0x10;\n-\t\t}\n-\t\tbreak;\n-\tcase 4:\n-\t\tif (num_tc > 4) {\n-\t\t\tthreshold = 0x6;\n-\t\t\tfifo_size = 0x4;\n-\t\t} else {\n-\t\t\tthreshold = 0x9;\n-\t\t\tfifo_size = 0x8;\n-\t\t}\n-\t\tbreak;\n-\t}\n-\n-\n-\treg = rd32(hw, I40E_PRTDCB_RPPMC);\n-\treg &= ~I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK;\n-\treg |= (fifo_size << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) &\n-\t\tI40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK;\n-\twr32(hw, I40E_PRTDCB_RPPMC, reg);\n-}\n-\n-/**\n- * i40e_dcb_hw_pfc_config\n- * @hw: pointer to the hw struct\n- * @pfc_en: Bitmap of PFC enabled priorities\n- * @prio_tc: priority to tc assignment indexed by priority\n- *\n- * Configure HW Priority Flow Controller as part of DCB configuration.\n- **/\n-void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,\n-\t\t\t    u8 pfc_en, u8 *prio_tc)\n-{\n-\tu16 pause_time = I40E_DEFAULT_PAUSE_TIME;\n-\tu16 refresh_time = pause_time/2;\n-\tu8 first_pfc_prio = 0;\n-\tu32 link_speed = 0;\n-\tu8 num_pfc_tc = 0;\n-\tu8 tc2pfc = 0;\n-\tu32 reg = 0;\n-\tu8 i;\n-\n-\t/* Get Number of PFC TCs and TC2PFC map */\n-\tfor (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {\n-\t\tif (pfc_en & (1 << i)) {\n-\t\t\tif (!first_pfc_prio)\n-\t\t\t\tfirst_pfc_prio = i;\n-\t\t\t/* Set bit for the PFC TC */\n-\t\t\ttc2pfc |= 1 << prio_tc[i];\n-\t\t\tnum_pfc_tc++;\n-\t\t}\n-\t}\n-\n-\tlink_speed = hw->phy.link_info.link_speed;\n-\tswitch (link_speed) {\n-\tcase I40E_LINK_SPEED_10GB:\n-\t\treg = rd32(hw, I40E_PRTDCB_MFLCN);\n-\t\treg |= (1 << I40E_PRTDCB_MFLCN_DPF_SHIFT) &\n-\t\t\tI40E_PRTDCB_MFLCN_DPF_MASK;\n-\t\treg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;\n-\t\treg &= ~I40E_PRTDCB_MFLCN_RPFCE_MASK;\n-\t\tif (pfc_en) {\n-\t\t\treg |= (1 << I40E_PRTDCB_MFLCN_RPFCM_SHIFT) &\n-\t\t\t\tI40E_PRTDCB_MFLCN_RPFCM_MASK;\n-\t\t\treg |= ((u32)pfc_en << I40E_PRTDCB_MFLCN_RPFCE_SHIFT) &\n-\t\t\t\tI40E_PRTDCB_MFLCN_RPFCE_MASK;\n-\t\t}\n-\t\twr32(hw, I40E_PRTDCB_MFLCN, reg);\n-\n-\t\treg = rd32(hw, I40E_PRTDCB_FCCFG);\n-\t\treg &= ~I40E_PRTDCB_FCCFG_TFCE_MASK;\n-\t\tif (pfc_en)\n-\t\t\treg |= (2 << I40E_PRTDCB_FCCFG_TFCE_SHIFT) &\n-\t\t\t\tI40E_PRTDCB_FCCFG_TFCE_MASK;\n-\t\twr32(hw, I40E_PRTDCB_FCCFG, reg);\n-\n-\t\t/* FCTTV and FCRTV to be set by default */\n-\t\tbreak;\n-\tcase I40E_LINK_SPEED_40GB:\n-\t\treg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP);\n-\t\treg &= ~I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK;\n-\t\twr32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP, reg);\n-\n-\t\treg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP);\n-\t\treg &= ~I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK;\n-\t\treg |= (1 <<\n-\t\t\t   I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) &\n-\t\t\tI40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK;\n-\t\twr32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP, reg);\n-\n-\t\treg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE);\n-\t\treg &= ~I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK;\n-\t\treg |= ((u32)pfc_en <<\n-\t\t\t   I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) &\n-\t\t\tI40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK;\n-\t\twr32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, reg);\n-\n-\t\treg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE);\n-\t\treg &= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK;\n-\t\treg |= ((u32)pfc_en <<\n-\t\t\t   I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) &\n-\t\t\tI40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK;\n-\t\twr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, reg);\n-\n-\t\tfor (i = 0; i < I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX; i++) {\n-\t\t\treg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i));\n-\t\t\treg &= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK;\n-\t\t\tif (pfc_en) {\n-\t\t\t\treg |= ((u32)refresh_time <<\n-\t\t\t\t\tI40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) &\n-\t\t\t\t\tI40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK;\n-\t\t\t}\n-\t\t\twr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i), reg);\n-\t\t}\n-\t\t/*\n-\t\t * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA default value is 0xFFFF\n-\t\t * for all user priorities\n-\t\t */\n-\t\tbreak;\n-\t}\n-\n-\treg = rd32(hw, I40E_PRTDCB_TC2PFC);\n-\treg &= ~I40E_PRTDCB_TC2PFC_TC2PFC_MASK;\n-\treg |= ((u32)tc2pfc << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) &\n-\t\tI40E_PRTDCB_TC2PFC_TC2PFC_MASK;\n-\twr32(hw, I40E_PRTDCB_TC2PFC, reg);\n-\n-\treg = rd32(hw, I40E_PRTDCB_RUP);\n-\treg &= ~I40E_PRTDCB_RUP_NOVLANUP_MASK;\n-\treg |= ((u32)first_pfc_prio << I40E_PRTDCB_RUP_NOVLANUP_SHIFT) &\n-\t\t I40E_PRTDCB_RUP_NOVLANUP_MASK;\n-\twr32(hw, I40E_PRTDCB_RUP, reg);\n-\n-\treg = rd32(hw, I40E_PRTDCB_TDPMC);\n-\treg &= ~I40E_PRTDCB_TDPMC_TCPM_MODE_MASK;\n-\tif (num_pfc_tc > 2) {\n-\t\treg |= (1 << I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) &\n-\t\t\tI40E_PRTDCB_TDPMC_TCPM_MODE_MASK;\n-\t}\n-\twr32(hw, I40E_PRTDCB_TDPMC, reg);\n-\n-\treg = rd32(hw, I40E_PRTDCB_TCPMC);\n-\treg &= ~I40E_PRTDCB_TCPMC_TCPM_MODE_MASK;\n-\tif (num_pfc_tc > 2) {\n-\t\treg |= (1 << I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) &\n-\t\t\tI40E_PRTDCB_TCPMC_TCPM_MODE_MASK;\n-\t}\n-\twr32(hw, I40E_PRTDCB_TCPMC, reg);\n-}\n-\n-/**\n- * i40e_dcb_hw_set_num_tc\n- * @hw: pointer to the hw struct\n- * @num_tc: number of traffic classes\n- *\n- * Configure number of traffic classes in HW\n- **/\n-void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc)\n-{\n-\tu32 reg = rd32(hw, I40E_PRTDCB_GENC);\n-\n-\treg &= ~I40E_PRTDCB_GENC_NUMTC_MASK;\n-\treg |= ((u32)num_tc << I40E_PRTDCB_GENC_NUMTC_SHIFT) &\n-\t\tI40E_PRTDCB_GENC_NUMTC_MASK;\n-\twr32(hw, I40E_PRTDCB_GENC, reg);\n-}\n-\n-/**\n- * i40e_dcb_hw_get_num_tc\n- * @hw: pointer to the hw struct\n- *\n- * Returns number of traffic classes configured in HW\n- **/\n-u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw)\n-{\n-\tu32 reg = rd32(hw, I40E_PRTDCB_GENC);\n-\n-\treturn (reg >> I40E_PRTDCB_GENC_NUMTC_SHIFT) &\n-\t\tI40E_PRTDCB_GENC_NUMTC_MASK;\n-}\n-\n-/**\n- * i40e_dcb_hw_rx_ets_bw_config\n- * @hw: pointer to the hw struct\n- * @bw_share: Bandwidth share indexed per traffic class\n- * @mode: Strict Priority or Round Robin mode between UP sharing same\n- * traffic class\n- * @prio_type: TC is ETS enabled or strict priority\n- *\n- * Configure HW Rx ETS bandwidth as part of DCB configuration.\n- **/\n-void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,\n-\t\t\t\t  u8 *mode, u8 *prio_type)\n-{\n-\tu32 reg = 0;\n-\tu8 i = 0;\n-\n-\tfor (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {\n-\t\treg = rd32(hw, I40E_PRTDCB_RETSTCC(i));\n-\t\treg &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |\n-\t\t\t I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |\n-\t\t\t I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);\n-\t\treg |= ((u32)bw_share[i] << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &\n-\t\t\t I40E_PRTDCB_RETSTCC_BWSHARE_MASK;\n-\t\treg |= ((u32)mode[i] << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &\n-\t\t\t I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;\n-\t\treg |= ((u32)prio_type[i] << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &\n-\t\t\t I40E_PRTDCB_RETSTCC_ETSTC_MASK;\n-\t\twr32(hw, I40E_PRTDCB_RETSTCC(i), reg);\n-\t}\n-}\n-\n-/**\n- * i40e_dcb_hw_rx_ets_bw_config\n- * @hw: pointer to the hw struct\n- * @prio_tc: priority to tc assignment indexed by priority\n- *\n- * Configure HW Rx UP2TC map as part of DCB configuration.\n- **/\n-void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc)\n-{\n-\tu32 reg = 0;\n-\n-#define I40E_UP2TC_REG(val, i) \\\n-\t\t((val << I40E_PRTDCB_RUP2TC_UP##i##TC_SHIFT) & \\\n-\t\t  I40E_PRTDCB_RUP2TC_UP##i##TC_MASK)\n-\n-\treg = rd32(hw, I40E_PRTDCB_RUP2TC);\n-\treg |= I40E_UP2TC_REG(prio_tc[0], 0);\n-\treg |= I40E_UP2TC_REG(prio_tc[1], 1);\n-\treg |= I40E_UP2TC_REG(prio_tc[2], 2);\n-\treg |= I40E_UP2TC_REG(prio_tc[3], 3);\n-\treg |= I40E_UP2TC_REG(prio_tc[4], 4);\n-\treg |= I40E_UP2TC_REG(prio_tc[5], 5);\n-\treg |= I40E_UP2TC_REG(prio_tc[6], 6);\n-\treg |= I40E_UP2TC_REG(prio_tc[7], 7);\n-\twr32(hw, I40E_PRTDCB_RUP2TC, reg);\n-}\n-\n-/**\n- * i40e_dcb_hw_calculate_pool_sizes\n- * @hw: pointer to the hw struct\n- * @num_ports: Number of available ports on the device\n- * @eee_enabled: EEE enabled for the given port\n- * @pfc_en: Bit map of PFC enabled traffic classes\n- * @mfs_tc: Array of max frame size for each traffic class\n- *\n- * Calculate the shared and dedicated per TC pool sizes,\n- * watermarks and threshold values.\n- **/\n-void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,\n-\t\t\t\t      u8 num_ports, bool eee_enabled,\n-\t\t\t\t      u8 pfc_en, u32 *mfs_tc,\n-\t\t\t\t      struct i40e_rx_pb_config *pb_cfg)\n-{\n-\tu32 pool_size[I40E_MAX_TRAFFIC_CLASS];\n-\tu32 high_wm[I40E_MAX_TRAFFIC_CLASS];\n-\tu32 low_wm[I40E_MAX_TRAFFIC_CLASS];\n-\tint shared_pool_size = 0; /* Need signed variable */\n-\tu32 total_pool_size = 0;\n-\tu32 port_pb_size = 0;\n-\tu32 mfs_max = 0;\n-\tu32 pcirtt = 0;\n-\tu8 i = 0;\n-\n-\t/* Get the MFS(max) for the port */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tif (mfs_tc[i] > mfs_max)\n-\t\t\tmfs_max = mfs_tc[i];\n-\t}\n-\n-\tpcirtt = I40E_BT2B(I40E_PCIRTT_LINK_SPEED_10G);\n-\n-\t/* Calculate effective Rx PB size per port */\n-\tport_pb_size = (I40E_DEVICE_RPB_SIZE/num_ports);\n-\tif (eee_enabled)\n-\t\tport_pb_size -= I40E_BT2B(I40E_EEE_TX_LPI_EXIT_TIME);\n-\tport_pb_size -= mfs_max;\n-\n-\t/* Step 1 Calculating tc pool/shared pool sizes and watermarks */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tif (pfc_en & (1 << i)) {\n-\t\t\tlow_wm[i] = (2 * mfs_tc[i]) + pcirtt;\n-\t\t\thigh_wm[i] = low_wm[i];\n-\t\t\thigh_wm[i] += ((mfs_max > I40E_MAX_FRAME_SIZE)\n-\t\t\t\t\t? mfs_max : I40E_MAX_FRAME_SIZE);\n-\t\t\tpool_size[i] = high_wm[i];\n-\t\t\tpool_size[i] += I40E_BT2B(I40E_STD_DV_TC(mfs_max,\n-\t\t\t\t\t\t\t\tmfs_tc[i]));\n-\t\t} else {\n-\t\t\tlow_wm[i] = 0;\n-\t\t\tpool_size[i] = (2 * mfs_tc[i]) + pcirtt;\n-\t\t\thigh_wm[i] = pool_size[i];\n-\t\t}\n-\t\ttotal_pool_size += pool_size[i];\n-\t}\n-\n-\tshared_pool_size = port_pb_size - total_pool_size;\n-\tif (shared_pool_size > 0) {\n-\t\tpb_cfg->shared_pool_size = shared_pool_size;\n-\t\tpb_cfg->shared_pool_high_wm = shared_pool_size;\n-\t\tpb_cfg->shared_pool_low_wm = 0;\n-\t\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\t\tpb_cfg->shared_pool_low_thresh[i] = 0;\n-\t\t\tpb_cfg->shared_pool_high_thresh[i] = shared_pool_size;\n-\t\t\tpb_cfg->tc_pool_size[i] = pool_size[i];\n-\t\t\tpb_cfg->tc_pool_high_wm[i] = high_wm[i];\n-\t\t\tpb_cfg->tc_pool_low_wm[i] = low_wm[i];\n-\t\t}\n-\n-\t} else {\n-\t\ti40e_debug(hw, I40E_DEBUG_DCB,\n-\t\t\t   \"The shared pool size for the port is negative %d.\\n\",\n-\t\t\t   shared_pool_size);\n-\t}\n-}\n-\n-/**\n- * i40e_dcb_hw_rx_pb_config\n- * @hw: pointer to the hw struct\n- * @old_pb_cfg: Existing Rx Packet buffer configuration\n- * @new_pb_cfg: New Rx Packet buffer configuration\n- *\n- * Program the Rx Packet Buffer registers.\n- **/\n-void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,\n-\t\t\t      struct i40e_rx_pb_config *old_pb_cfg,\n-\t\t\t      struct i40e_rx_pb_config *new_pb_cfg)\n-{\n-\tu32 old_val = 0;\n-\tu32 new_val = 0;\n-\tu32 reg = 0;\n-\tu8 i = 0;\n-\n-\t/* Program the shared pool low water mark per port if decreasing */\n-\told_val = old_pb_cfg->shared_pool_low_wm;\n-\tnew_val = new_pb_cfg->shared_pool_low_wm;\n-\tif (new_val < old_val) {\n-\t\treg = rd32(hw, I40E_PRTRPB_SLW);\n-\t\treg &= ~I40E_PRTRPB_SLW_SLW_MASK;\n-\t\treg |= (new_val << I40E_PRTRPB_SLW_SLW_SHIFT) &\n-\t\t\tI40E_PRTRPB_SLW_SLW_MASK;\n-\t\twr32(hw, I40E_PRTRPB_SLW, reg);\n-\t}\n-\n-\t/* Program the shared pool low threshold and tc pool\n-\t * low water mark per TC that are decreasing.\n-\t */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\told_val = old_pb_cfg->shared_pool_low_thresh[i];\n-\t\tnew_val = new_pb_cfg->shared_pool_low_thresh[i];\n-\t\tif (new_val < old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_SLT(i));\n-\t\t\treg &= ~I40E_PRTRPB_SLT_SLT_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_SLT_SLT_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_SLT(i), reg);\n-\t\t}\n-\n-\t\told_val = old_pb_cfg->tc_pool_low_wm[i];\n-\t\tnew_val = new_pb_cfg->tc_pool_low_wm[i];\n-\t\tif (new_val < old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_DLW(i));\n-\t\t\treg &= ~I40E_PRTRPB_DLW_DLW_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_DLW_DLW_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_DLW(i), reg);\n-\t\t}\n-\t}\n-\n-\t/* Program the shared pool high water mark per port if decreasing */\n-\told_val = old_pb_cfg->shared_pool_high_wm;\n-\tnew_val = new_pb_cfg->shared_pool_high_wm;\n-\tif (new_val < old_val) {\n-\t\treg = rd32(hw, I40E_PRTRPB_SHW);\n-\t\treg &= ~I40E_PRTRPB_SHW_SHW_MASK;\n-\t\treg |= (new_val << I40E_PRTRPB_SHW_SHW_SHIFT) &\n-\t\t\tI40E_PRTRPB_SHW_SHW_MASK;\n-\t\twr32(hw, I40E_PRTRPB_SHW, reg);\n-\t}\n-\n-\t/* Program the shared pool high threshold and tc pool\n-\t * high water mark per TC that are decreasing.\n-\t */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\told_val = old_pb_cfg->shared_pool_high_thresh[i];\n-\t\tnew_val = new_pb_cfg->shared_pool_high_thresh[i];\n-\t\tif (new_val < old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_SHT(i));\n-\t\t\treg &= ~I40E_PRTRPB_SHT_SHT_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_SHT_SHT_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_SHT(i), reg);\n-\t\t}\n-\n-\t\told_val = old_pb_cfg->tc_pool_high_wm[i];\n-\t\tnew_val = new_pb_cfg->tc_pool_high_wm[i];\n-\t\tif (new_val < old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_DHW(i));\n-\t\t\treg &= ~I40E_PRTRPB_DHW_DHW_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_DHW_DHW_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_DHW(i), reg);\n-\t\t}\n-\t}\n-\n-\t/* Write Dedicated Pool Sizes per TC */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tnew_val = new_pb_cfg->tc_pool_size[i];\n-\t\treg = rd32(hw, I40E_PRTRPB_DPS(i));\n-\t\treg &= ~I40E_PRTRPB_DPS_DPS_TCN_MASK;\n-\t\treg |= (new_val << I40E_PRTRPB_DPS_DPS_TCN_SHIFT) &\n-\t\t\tI40E_PRTRPB_DPS_DPS_TCN_MASK;\n-\t\twr32(hw, I40E_PRTRPB_DPS(i), reg);\n-\t}\n-\n-\t/* Write Shared Pool Size per port */\n-\tnew_val = new_pb_cfg->shared_pool_size;\n-\treg = rd32(hw, I40E_PRTRPB_SPS);\n-\treg &= ~I40E_PRTRPB_SPS_SPS_MASK;\n-\treg |= (new_val << I40E_PRTRPB_SPS_SPS_SHIFT) &\n-\t\tI40E_PRTRPB_SPS_SPS_MASK;\n-\twr32(hw, I40E_PRTRPB_SPS, reg);\n-\n-\t/* Program the shared pool low water mark per port if increasing */\n-\told_val = old_pb_cfg->shared_pool_low_wm;\n-\tnew_val = new_pb_cfg->shared_pool_low_wm;\n-\tif (new_val > old_val) {\n-\t\treg = rd32(hw, I40E_PRTRPB_SLW);\n-\t\treg &= ~I40E_PRTRPB_SLW_SLW_MASK;\n-\t\treg |= (new_val << I40E_PRTRPB_SLW_SLW_SHIFT) &\n-\t\t\tI40E_PRTRPB_SLW_SLW_MASK;\n-\t\twr32(hw, I40E_PRTRPB_SLW, reg);\n-\t}\n-\n-\t/* Program the shared pool low threshold and tc pool\n-\t * low water mark per TC that are increasing.\n-\t */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\told_val = old_pb_cfg->shared_pool_low_thresh[i];\n-\t\tnew_val = new_pb_cfg->shared_pool_low_thresh[i];\n-\t\tif (new_val > old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_SLT(i));\n-\t\t\treg &= ~I40E_PRTRPB_SLT_SLT_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_SLT_SLT_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_SLT(i), reg);\n-\t\t}\n-\n-\t\told_val = old_pb_cfg->tc_pool_low_wm[i];\n-\t\tnew_val = new_pb_cfg->tc_pool_low_wm[i];\n-\t\tif (new_val > old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_DLW(i));\n-\t\t\treg &= ~I40E_PRTRPB_DLW_DLW_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_DLW_DLW_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_DLW(i), reg);\n-\t\t}\n-\t}\n-\n-\t/* Program the shared pool high water mark per port if increasing */\n-\told_val = old_pb_cfg->shared_pool_high_wm;\n-\tnew_val = new_pb_cfg->shared_pool_high_wm;\n-\tif (new_val > old_val) {\n-\t\treg = rd32(hw, I40E_PRTRPB_SHW);\n-\t\treg &= ~I40E_PRTRPB_SHW_SHW_MASK;\n-\t\treg |= (new_val << I40E_PRTRPB_SHW_SHW_SHIFT) &\n-\t\t\tI40E_PRTRPB_SHW_SHW_MASK;\n-\t\twr32(hw, I40E_PRTRPB_SHW, reg);\n-\t}\n-\n-\t/* Program the shared pool high threshold and tc pool\n-\t * high water mark per TC that are increasing.\n-\t */\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\told_val = old_pb_cfg->shared_pool_high_thresh[i];\n-\t\tnew_val = new_pb_cfg->shared_pool_high_thresh[i];\n-\t\tif (new_val > old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_SHT(i));\n-\t\t\treg &= ~I40E_PRTRPB_SHT_SHT_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_SHT_SHT_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_SHT(i), reg);\n-\t\t}\n-\n-\t\told_val = old_pb_cfg->tc_pool_high_wm[i];\n-\t\tnew_val = new_pb_cfg->tc_pool_high_wm[i];\n-\t\tif (new_val > old_val) {\n-\t\t\treg = rd32(hw, I40E_PRTRPB_DHW(i));\n-\t\t\treg &= ~I40E_PRTRPB_DHW_DHW_TCN_MASK;\n-\t\t\treg |= (new_val << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) &\n-\t\t\t\tI40E_PRTRPB_DHW_DHW_TCN_MASK;\n-\t\t\twr32(hw, I40E_PRTRPB_DHW(i), reg);\n-\t\t}\n-\t}\n-}\n-\n-/**\n- * i40e_read_lldp_cfg - read LLDP Configuration data from NVM\n- * @hw: pointer to the HW structure\n- * @lldp_cfg: pointer to hold lldp configuration variables\n- *\n- * Reads the LLDP configuration data from NVM\n- **/\n-enum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw,\n-\t\t\t\t\t struct i40e_lldp_variables *lldp_cfg)\n-{\n-\tenum i40e_status_code ret = I40E_SUCCESS;\n-\tstruct i40e_emp_settings_module emp_ptr;\n-\tu32 offset = 0;\n-\n-\tif (!lldp_cfg)\n-\t\treturn I40E_ERR_PARAM;\n-\n-\tret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);\n-\tif (ret != I40E_SUCCESS)\n-\t\tgoto err_lldp_cfg;\n-\n-\tret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 0,\n-\t\t\t       sizeof(emp_ptr), (u8 *)&emp_ptr,\n-\t\t\t       true, NULL);\n-\ti40e_release_nvm(hw);\n-\tif (ret != I40E_SUCCESS)\n-\t\tgoto err_lldp_cfg;\n-\n-\t/* Calculate the byte offset for LLDP config pointer */\n-\toffset = (2 * emp_ptr.lldp_cfg_ptr);\n-\toffset += (2 * I40E_NVM_LLDP_CFG_PTR);\n-\tret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);\n-\tif (ret != I40E_SUCCESS)\n-\t\tgoto err_lldp_cfg;\n-\n-\tret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, offset,\n-\t\t\t       sizeof(struct i40e_lldp_variables),\n-\t\t\t       (u8 *)lldp_cfg,\n-\t\t\t       true, NULL);\n-\ti40e_release_nvm(hw);\n-\n-err_lldp_cfg:\n-\treturn ret;\n-}\n-#endif /* I40E_DCB_SW */\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_dcb.h b/lib/librte_pmd_i40e/i40e/i40e_dcb.h\nindex 77f1d49..2261e08 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_dcb.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_dcb.h\n@@ -149,109 +149,6 @@ struct i40e_dcbx_variables {\n \tu32 deftsaassignment;\n };\n \n-#ifdef I40E_DCB_SW\n-/* Data structures to pass for SW DCBX */\n-struct i40e_rx_pb_config {\n-\tu32\tshared_pool_size;\n-\tu32\tshared_pool_high_wm;\n-\tu32\tshared_pool_low_wm;\n-\tu32\tshared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS];\n-\tu32\tshared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS];\n-\tu32\ttc_pool_size[I40E_MAX_TRAFFIC_CLASS];\n-\tu32\ttc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS];\n-\tu32\ttc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS];\n-};\n-\n-enum i40e_dcb_arbiter_mode {\n-\tI40E_DCB_ARB_MODE_STRICT_PRIORITY = 0,\n-\tI40E_DCB_ARB_MODE_ROUND_ROBIN = 1\n-};\n-\n-#define I40E_DEFAULT_PAUSE_TIME\t\t\t0xffff\n-#define I40E_MAX_FRAME_SIZE\t\t\t4608 /* 4.5 KB */\n-\n-#define I40E_DEVICE_RPB_SIZE\t\t\t968000 /* 968 KB */\n-\n-/* BitTimes (BT) conversion */\n-#define I40E_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))\n-#define I40E_B2BT(BT) (BT * 8)\n-#define I40E_BT2B(BT) ((BT + (8 - 1)) / (8))\n-\n-/* Max Frame(TC) = MFS(max) + MFS(TC) */\n-#define I40E_MAX_FRAME_TC(mfs_max, mfs_tc)\tI40E_B2BT(mfs_max + mfs_tc)\n-\n-/* EEE Tx LPI Exit time in Bit Times */\n-#define I40E_EEE_TX_LPI_EXIT_TIME\t\t142500\n-\n-/* PCI Round Trip Time in Bit Times */\n-#define I40E_PCIRTT_LINK_SPEED_10G\t\t20000\n-#define I40E_PCIRTT_BYTE_LINK_SPEED_20G\t\t40000\n-#define I40E_PCIRTT_BYTE_LINK_SPEED_40G\t\t80000\n-\n-/* PFC Frame Delay Bit Times */\n-#define I40E_PFC_FRAME_DELAY\t\t\t672\n-\n-/* Worst case Cable (10GBase-T) Delay Bit Times */\n-#define I40E_CABLE_DELAY\t\t\t5556\n-\n-/* Higher Layer Delay @10G Bit Times */\n-#define I40E_HIGHER_LAYER_DELAY_10G\t\t6144\n-\n-/* Interface Delays in Bit Times */\n-/* TODO: Add for other link speeds 20G/40G/etc. */\n-#define I40E_INTERFACE_DELAY_10G_MAC_CONTROL\t8192\n-#define I40E_INTERFACE_DELAY_10G_MAC\t\t8192\n-#define I40E_INTERFACE_DELAY_10G_RS\t\t8192\n-\n-#define I40E_INTERFACE_DELAY_XGXS\t\t2048\n-#define I40E_INTERFACE_DELAY_XAUI\t\t2048\n-\n-#define I40E_INTERFACE_DELAY_10G_BASEX_PCS\t2048\n-#define I40E_INTERFACE_DELAY_10G_BASER_PCS\t3584\n-#define I40E_INTERFACE_DELAY_LX4_PMD\t\t512\n-#define I40E_INTERFACE_DELAY_CX4_PMD\t\t512\n-#define I40E_INTERFACE_DELAY_SERIAL_PMA\t\t512\n-#define I40E_INTERFACE_DELAY_PMD\t\t512\n-\n-#define I40E_INTERFACE_DELAY_10G_BASET\t\t25600\n-\n-/* delay values for with 10G BaseT in Bit Times */\n-#define I40E_INTERFACE_DELAY_10G_COPPER\t\\\n-\t(I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \\\n-\t + I40E_INTERFACE_DELAY_10G_BASET)\n-#define I40E_DV_TC(mfs_max, mfs_tc) \\\n-\t\t((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \\\n-\t\t  + I40E_PFC_FRAME_DELAY \\\n-\t\t  + (2 * I40E_CABLE_DELAY) \\\n-\t\t  + (2 * I40E_INTERFACE_DELAY_10G_COPPER) \\\n-\t\t  + I40E_HIGHER_LAYER_DELAY_10G)\n-#define I40E_STD_DV_TC(mfs_max, mfs_tc) \\\n-\t\t(I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max))\n-\n-enum i40e_status_code i40e_process_lldp_event(struct i40e_hw *hw,\n-\t\t\t\t\t      struct i40e_arq_event_info *e);\n-/* APIs for SW DCBX */\n-void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,\n-\t\t\t\tenum i40e_dcb_arbiter_mode ets_mode,\n-\t\t\t\tenum i40e_dcb_arbiter_mode non_ets_mode,\n-\t\t\t\tu32 max_exponent, u8 lltc_map);\n-void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,\n-\t\t\t\t       u8 num_tc, u8 num_ports);\n-void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,\n-\t\t\t    u8 pfc_en, u8 *prio_tc);\n-void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc);\n-u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw);\n-void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,\n-\t\t\t\t  u8 *mode, u8 *prio_type);\n-void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc);\n-void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,\n-\t\t\t\t      u8 num_ports, bool eee_enabled,\n-\t\t\t\t      u8 pfc_en, u32 *mfs_tc,\n-\t\t\t\t      struct i40e_rx_pb_config *pb_cfg);\n-void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,\n-\t\t\t      struct i40e_rx_pb_config *old_pb_cfg,\n-\t\t\t      struct i40e_rx_pb_config *new_pb_cfg);\n-#endif /* I40E_DCB_SW */\n enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,\n \t\t\t\t\t   u16 *status);\n enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_prototype.h b/lib/librte_pmd_i40e/i40e/i40e_prototype.h\nindex cac5963..e559569 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_prototype.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_prototype.h\n@@ -323,12 +323,6 @@ enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,\n \t\tstruct i40e_asq_cmd_details *cmd_details);\n enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n-#ifdef I40E_DCB_SW\n-enum i40e_status_code i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n-enum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw,\n-\t\t\t\t\tstruct i40e_lldp_variables *lldp_cfg);\n-#endif /* I40E_DCB_SW */\n enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,\n \t\tu16 vsi,\n \t\tstruct i40e_aqc_add_remove_cloud_filters_element_data *filters,\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_type.h b/lib/librte_pmd_i40e/i40e/i40e_type.h\nindex aca8102..004967a 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_type.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_type.h\n@@ -1403,46 +1403,6 @@ enum i40e_reset_type {\n \tI40E_RESET_GLOBR\t= 2,\n \tI40E_RESET_EMPR\t\t= 3,\n };\n-#ifdef I40E_DCB_SW\n-\n-/* EMP Settings Module Header Section */\n-struct i40e_emp_settings_module {\n-\tu16 length;\n-\tu16 fw_params;\n-\tu16 reserved;\n-\tu16 features;\n-\tu16 oem_cfg;\n-\tu16 pfalloc_ptr;\n-\tu16 eee_variables;\n-\tu16 phy_cap_lan0_ptr;\n-\tu16 phy_cap_lan1_ptr;\n-\tu16 phy_cap_lan2_ptr;\n-\tu16 phy_cap_lan3_ptr;\n-\tu16 phy_map_lan0_ptr;\n-\tu16 phy_map_lan1_ptr;\n-\tu16 phy_map_lan2_ptr;\n-\tu16 phy_map_lan3_ptr;\n-\tu16 lldp_cfg_ptr;\n-\tu16 ltr_max_snoop;\n-\tu16 ltr_max_no_snoop;\n-\tu16 ltr_delta;\n-\tu16 ltr_grade_value;\n-\tu16 lldp_tlv_ptr;\n-\tu16 crc8;\n-};\n-\n-/* IEEE 802.1AB LLDP Agent Variables from NVM */\n-#define I40E_NVM_LLDP_CFG_PTR\t\t0xF\n-struct i40e_lldp_variables {\n-\tu16 length;\n-\tu16 adminstatus;\n-\tu16 msgfasttx;\n-\tu16 msgtxinterval;\n-\tu16 txparams;\n-\tu16 timers;\n-\tu16 crc8;\n-};\n-#endif /* I40E_DCB_SW */\n \n /* Offsets into Alternate Ram */\n #define I40E_ALT_STRUCT_FIRST_PF_OFFSET\t\t0   /* in dwords */\n",
    "prefixes": [
        "dpdk-dev",
        "08/15"
    ]
}