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{
    "id": 317,
    "url": "https://patches.dpdk.org/api/patches/317/",
    "web_url": "https://patches.dpdk.org/patch/317/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1410247299-4365-2-git-send-email-helin.zhang@intel.com>",
    "date": "2014-09-09T07:21:25",
    "name": "[dpdk-dev,01/15] i40e: make the indentation more consistent in share code",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "c7fe58ac116a6d9b2ce87a680457b7aeb620c9d4",
    "submitter": {
        "id": 14,
        "url": "https://patches.dpdk.org/api/people/14/",
        "name": "Helin Zhang",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/patch/317/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/317/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/317/checks/",
    "tags": {},
    "headers": {
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Original-To": "patchwork@dpdk.org",
        "Date": "Tue,  9 Sep 2014 15:21:25 +0800",
        "In-Reply-To": "<1410247299-4365-1-git-send-email-helin.zhang@intel.com>",
        "Precedence": "list",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<1410247299-4365-1-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "To": "dev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id EC0ABB3A0;\n\tTue,  9 Sep 2014 09:16:59 +0200 (CEST)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id A5A35B396\n\tfor <dev@dpdk.org>; Tue,  9 Sep 2014 09:16:52 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP; 09 Sep 2014 00:21:55 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 09 Sep 2014 00:16:54 -0700",
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            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s897LnAV004407; Tue, 9 Sep 2014 15:21:51 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s897Lnrn004403; \n\tTue, 9 Sep 2014 15:21:49 +0800"
        ],
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "X-ExtLoop1": "1",
        "Message-Id": "<1410247299-4365-2-git-send-email-helin.zhang@intel.com>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH 01/15] i40e: make the indentation more consistent\n\tin share code",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-IronPort-AV": "E=Sophos;i=\"4.97,862,1389772800\"; d=\"scan'208\";a=\"383381592\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "X-Mailman-Version": "2.1.15"
    },
    "content": "In share code, 'tab' is used to align values rather than 'space'.\nThe changes in i40e_adminq_cmd.h is to make the indentation more\nconsistent in share code.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Chen Jing <jing.d.chen@intel.com>\n---\n lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h | 2132 ++++++++++++++--------------\n 1 file changed, 1066 insertions(+), 1066 deletions(-)",
    "diff": "diff --git a/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h b/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h\nindex d7f65bc..5ea9b7d 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h\n@@ -40,8 +40,8 @@ POSSIBILITY OF SUCH DAMAGE.\n  * This file needs to comply with the Linux Kernel coding style.\n  */\n \n-#define I40E_FW_API_VERSION_MAJOR  0x0001\n-#define I40E_FW_API_VERSION_MINOR  0x0002\n+#define I40E_FW_API_VERSION_MAJOR\t0x0001\n+#define I40E_FW_API_VERSION_MINOR\t0x0002\n \n struct i40e_aq_desc {\n \t__le16 flags;\n@@ -73,216 +73,216 @@ struct i40e_aq_desc {\n  */\n \n /* command flags and offsets*/\n-#define I40E_AQ_FLAG_DD_SHIFT  0\n-#define I40E_AQ_FLAG_CMP_SHIFT 1\n-#define I40E_AQ_FLAG_ERR_SHIFT 2\n-#define I40E_AQ_FLAG_VFE_SHIFT 3\n-#define I40E_AQ_FLAG_LB_SHIFT  9\n-#define I40E_AQ_FLAG_RD_SHIFT  10\n-#define I40E_AQ_FLAG_VFC_SHIFT 11\n-#define I40E_AQ_FLAG_BUF_SHIFT 12\n-#define I40E_AQ_FLAG_SI_SHIFT  13\n-#define I40E_AQ_FLAG_EI_SHIFT  14\n-#define I40E_AQ_FLAG_FE_SHIFT  15\n-\n-#define I40E_AQ_FLAG_DD  (1 << I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */\n-#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */\n-#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */\n-#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */\n-#define I40E_AQ_FLAG_LB  (1 << I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */\n-#define I40E_AQ_FLAG_RD  (1 << I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */\n-#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */\n-#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */\n-#define I40E_AQ_FLAG_SI  (1 << I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */\n-#define I40E_AQ_FLAG_EI  (1 << I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */\n-#define I40E_AQ_FLAG_FE  (1 << I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */\n+#define I40E_AQ_FLAG_DD_SHIFT\t0\n+#define I40E_AQ_FLAG_CMP_SHIFT\t1\n+#define I40E_AQ_FLAG_ERR_SHIFT\t2\n+#define I40E_AQ_FLAG_VFE_SHIFT\t3\n+#define I40E_AQ_FLAG_LB_SHIFT\t9\n+#define I40E_AQ_FLAG_RD_SHIFT\t10\n+#define I40E_AQ_FLAG_VFC_SHIFT\t11\n+#define I40E_AQ_FLAG_BUF_SHIFT\t12\n+#define I40E_AQ_FLAG_SI_SHIFT\t13\n+#define I40E_AQ_FLAG_EI_SHIFT\t14\n+#define I40E_AQ_FLAG_FE_SHIFT\t15\n+\n+#define I40E_AQ_FLAG_DD\t\t(1 << I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */\n+#define I40E_AQ_FLAG_CMP\t(1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */\n+#define I40E_AQ_FLAG_ERR\t(1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */\n+#define I40E_AQ_FLAG_VFE\t(1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */\n+#define I40E_AQ_FLAG_LB\t\t(1 << I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */\n+#define I40E_AQ_FLAG_RD\t\t(1 << I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */\n+#define I40E_AQ_FLAG_VFC\t(1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */\n+#define I40E_AQ_FLAG_BUF\t(1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */\n+#define I40E_AQ_FLAG_SI\t\t(1 << I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */\n+#define I40E_AQ_FLAG_EI\t\t(1 << I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */\n+#define I40E_AQ_FLAG_FE\t\t(1 << I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */\n \n /* error codes */\n enum i40e_admin_queue_err {\n-\tI40E_AQ_RC_OK       = 0,    /* success */\n-\tI40E_AQ_RC_EPERM    = 1,    /* Operation not permitted */\n-\tI40E_AQ_RC_ENOENT   = 2,    /* No such element */\n-\tI40E_AQ_RC_ESRCH    = 3,    /* Bad opcode */\n-\tI40E_AQ_RC_EINTR    = 4,    /* operation interrupted */\n-\tI40E_AQ_RC_EIO      = 5,    /* I/O error */\n-\tI40E_AQ_RC_ENXIO    = 6,    /* No such resource */\n-\tI40E_AQ_RC_E2BIG    = 7,    /* Arg too long */\n-\tI40E_AQ_RC_EAGAIN   = 8,    /* Try again */\n-\tI40E_AQ_RC_ENOMEM   = 9,    /* Out of memory */\n-\tI40E_AQ_RC_EACCES   = 10,   /* Permission denied */\n-\tI40E_AQ_RC_EFAULT   = 11,   /* Bad address */\n-\tI40E_AQ_RC_EBUSY    = 12,   /* Device or resource busy */\n-\tI40E_AQ_RC_EEXIST   = 13,   /* object already exists */\n-\tI40E_AQ_RC_EINVAL   = 14,   /* Invalid argument */\n-\tI40E_AQ_RC_ENOTTY   = 15,   /* Not a typewriter */\n-\tI40E_AQ_RC_ENOSPC   = 16,   /* No space left or alloc failure */\n-\tI40E_AQ_RC_ENOSYS   = 17,   /* Function not implemented */\n-\tI40E_AQ_RC_ERANGE   = 18,   /* Parameter out of range */\n-\tI40E_AQ_RC_EFLUSHED = 19,   /* Cmd flushed because of prev cmd error */\n-\tI40E_AQ_RC_BAD_ADDR = 20,   /* Descriptor contains a bad pointer */\n-\tI40E_AQ_RC_EMODE    = 21,   /* Op not allowed in current dev mode */\n-\tI40E_AQ_RC_EFBIG    = 22,   /* File too large */\n+\tI40E_AQ_RC_OK\t\t= 0,  /* success */\n+\tI40E_AQ_RC_EPERM\t= 1,  /* Operation not permitted */\n+\tI40E_AQ_RC_ENOENT\t= 2,  /* No such element */\n+\tI40E_AQ_RC_ESRCH\t= 3,  /* Bad opcode */\n+\tI40E_AQ_RC_EINTR\t= 4,  /* operation interrupted */\n+\tI40E_AQ_RC_EIO\t\t= 5,  /* I/O error */\n+\tI40E_AQ_RC_ENXIO\t= 6,  /* No such resource */\n+\tI40E_AQ_RC_E2BIG\t= 7,  /* Arg too long */\n+\tI40E_AQ_RC_EAGAIN\t= 8,  /* Try again */\n+\tI40E_AQ_RC_ENOMEM\t= 9,  /* Out of memory */\n+\tI40E_AQ_RC_EACCES\t= 10, /* Permission denied */\n+\tI40E_AQ_RC_EFAULT\t= 11, /* Bad address */\n+\tI40E_AQ_RC_EBUSY\t= 12, /* Device or resource busy */\n+\tI40E_AQ_RC_EEXIST\t= 13, /* object already exists */\n+\tI40E_AQ_RC_EINVAL\t= 14, /* Invalid argument */\n+\tI40E_AQ_RC_ENOTTY\t= 15, /* Not a typewriter */\n+\tI40E_AQ_RC_ENOSPC\t= 16, /* No space left or alloc failure */\n+\tI40E_AQ_RC_ENOSYS\t= 17, /* Function not implemented */\n+\tI40E_AQ_RC_ERANGE\t= 18, /* Parameter out of range */\n+\tI40E_AQ_RC_EFLUSHED\t= 19, /* Cmd flushed due to prev cmd error */\n+\tI40E_AQ_RC_BAD_ADDR\t= 20, /* Descriptor contains a bad pointer */\n+\tI40E_AQ_RC_EMODE\t= 21, /* Op not allowed in current dev mode */\n+\tI40E_AQ_RC_EFBIG\t= 22, /* File too large */\n };\n \n /* Admin Queue command opcodes */\n enum i40e_admin_queue_opc {\n \t/* aq commands */\n-\ti40e_aqc_opc_get_version      = 0x0001,\n-\ti40e_aqc_opc_driver_version   = 0x0002,\n-\ti40e_aqc_opc_queue_shutdown   = 0x0003,\n-\ti40e_aqc_opc_set_pf_context   = 0x0004,\n+\ti40e_aqc_opc_get_version\t= 0x0001,\n+\ti40e_aqc_opc_driver_version\t= 0x0002,\n+\ti40e_aqc_opc_queue_shutdown\t= 0x0003,\n+\ti40e_aqc_opc_set_pf_context\t= 0x0004,\n \n \t/* resource ownership */\n-\ti40e_aqc_opc_request_resource = 0x0008,\n-\ti40e_aqc_opc_release_resource = 0x0009,\n+\ti40e_aqc_opc_request_resource\t= 0x0008,\n+\ti40e_aqc_opc_release_resource\t= 0x0009,\n \n-\ti40e_aqc_opc_list_func_capabilities = 0x000A,\n-\ti40e_aqc_opc_list_dev_capabilities  = 0x000B,\n+\ti40e_aqc_opc_list_func_capabilities\t= 0x000A,\n+\ti40e_aqc_opc_list_dev_capabilities\t= 0x000B,\n \n-\ti40e_aqc_opc_set_cppm_configuration = 0x0103,\n-\ti40e_aqc_opc_set_arp_proxy_entry    = 0x0104,\n-\ti40e_aqc_opc_set_ns_proxy_entry     = 0x0105,\n+\ti40e_aqc_opc_set_cppm_configuration\t= 0x0103,\n+\ti40e_aqc_opc_set_arp_proxy_entry\t= 0x0104,\n+\ti40e_aqc_opc_set_ns_proxy_entry\t\t= 0x0105,\n \n \t/* LAA */\n-\ti40e_aqc_opc_mng_laa                = 0x0106,   /* AQ obsolete */\n-\ti40e_aqc_opc_mac_address_read       = 0x0107,\n-\ti40e_aqc_opc_mac_address_write      = 0x0108,\n+\ti40e_aqc_opc_mng_laa\t\t= 0x0106,   /* AQ obsolete */\n+\ti40e_aqc_opc_mac_address_read\t= 0x0107,\n+\ti40e_aqc_opc_mac_address_write\t= 0x0108,\n \n \t/* PXE */\n-\ti40e_aqc_opc_clear_pxe_mode         = 0x0110,\n+\ti40e_aqc_opc_clear_pxe_mode\t= 0x0110,\n \n \t/* internal switch commands */\n-\ti40e_aqc_opc_get_switch_config         = 0x0200,\n-\ti40e_aqc_opc_add_statistics            = 0x0201,\n-\ti40e_aqc_opc_remove_statistics         = 0x0202,\n-\ti40e_aqc_opc_set_port_parameters       = 0x0203,\n-\ti40e_aqc_opc_get_switch_resource_alloc = 0x0204,\n-\n-\ti40e_aqc_opc_add_vsi                = 0x0210,\n-\ti40e_aqc_opc_update_vsi_parameters  = 0x0211,\n-\ti40e_aqc_opc_get_vsi_parameters     = 0x0212,\n-\n-\ti40e_aqc_opc_add_pv                = 0x0220,\n-\ti40e_aqc_opc_update_pv_parameters  = 0x0221,\n-\ti40e_aqc_opc_get_pv_parameters     = 0x0222,\n-\n-\ti40e_aqc_opc_add_veb               = 0x0230,\n-\ti40e_aqc_opc_update_veb_parameters = 0x0231,\n-\ti40e_aqc_opc_get_veb_parameters    = 0x0232,\n-\n-\ti40e_aqc_opc_delete_element  = 0x0243,\n-\n-\ti40e_aqc_opc_add_macvlan                  = 0x0250,\n-\ti40e_aqc_opc_remove_macvlan               = 0x0251,\n-\ti40e_aqc_opc_add_vlan                     = 0x0252,\n-\ti40e_aqc_opc_remove_vlan                  = 0x0253,\n-\ti40e_aqc_opc_set_vsi_promiscuous_modes    = 0x0254,\n-\ti40e_aqc_opc_add_tag                      = 0x0255,\n-\ti40e_aqc_opc_remove_tag                   = 0x0256,\n-\ti40e_aqc_opc_add_multicast_etag           = 0x0257,\n-\ti40e_aqc_opc_remove_multicast_etag        = 0x0258,\n-\ti40e_aqc_opc_update_tag                   = 0x0259,\n-\ti40e_aqc_opc_add_control_packet_filter    = 0x025A,\n-\ti40e_aqc_opc_remove_control_packet_filter = 0x025B,\n-\ti40e_aqc_opc_add_cloud_filters            = 0x025C,\n-\ti40e_aqc_opc_remove_cloud_filters         = 0x025D,\n-\n-\ti40e_aqc_opc_add_mirror_rule    = 0x0260,\n-\ti40e_aqc_opc_delete_mirror_rule = 0x0261,\n+\ti40e_aqc_opc_get_switch_config\t\t= 0x0200,\n+\ti40e_aqc_opc_add_statistics\t\t= 0x0201,\n+\ti40e_aqc_opc_remove_statistics\t\t= 0x0202,\n+\ti40e_aqc_opc_set_port_parameters\t= 0x0203,\n+\ti40e_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n+\n+\ti40e_aqc_opc_add_vsi\t\t\t= 0x0210,\n+\ti40e_aqc_opc_update_vsi_parameters\t= 0x0211,\n+\ti40e_aqc_opc_get_vsi_parameters\t\t= 0x0212,\n+\n+\ti40e_aqc_opc_add_pv\t\t\t= 0x0220,\n+\ti40e_aqc_opc_update_pv_parameters\t= 0x0221,\n+\ti40e_aqc_opc_get_pv_parameters\t\t= 0x0222,\n+\n+\ti40e_aqc_opc_add_veb\t\t\t= 0x0230,\n+\ti40e_aqc_opc_update_veb_parameters\t= 0x0231,\n+\ti40e_aqc_opc_get_veb_parameters\t\t= 0x0232,\n+\n+\ti40e_aqc_opc_delete_element\t\t= 0x0243,\n+\n+\ti40e_aqc_opc_add_macvlan\t\t= 0x0250,\n+\ti40e_aqc_opc_remove_macvlan\t\t= 0x0251,\n+\ti40e_aqc_opc_add_vlan\t\t\t= 0x0252,\n+\ti40e_aqc_opc_remove_vlan\t\t= 0x0253,\n+\ti40e_aqc_opc_set_vsi_promiscuous_modes\t= 0x0254,\n+\ti40e_aqc_opc_add_tag\t\t\t= 0x0255,\n+\ti40e_aqc_opc_remove_tag\t\t\t= 0x0256,\n+\ti40e_aqc_opc_add_multicast_etag\t\t= 0x0257,\n+\ti40e_aqc_opc_remove_multicast_etag\t= 0x0258,\n+\ti40e_aqc_opc_update_tag\t\t\t= 0x0259,\n+\ti40e_aqc_opc_add_control_packet_filter\t= 0x025A,\n+\ti40e_aqc_opc_remove_control_packet_filter\t= 0x025B,\n+\ti40e_aqc_opc_add_cloud_filters\t\t= 0x025C,\n+\ti40e_aqc_opc_remove_cloud_filters\t= 0x025D,\n+\n+\ti40e_aqc_opc_add_mirror_rule\t= 0x0260,\n+\ti40e_aqc_opc_delete_mirror_rule\t= 0x0261,\n \n \t/* DCB commands */\n-\ti40e_aqc_opc_dcb_ignore_pfc = 0x0301,\n-\ti40e_aqc_opc_dcb_updated    = 0x0302,\n+\ti40e_aqc_opc_dcb_ignore_pfc\t= 0x0301,\n+\ti40e_aqc_opc_dcb_updated\t= 0x0302,\n \n \t/* TX scheduler */\n-\ti40e_aqc_opc_configure_vsi_bw_limit            = 0x0400,\n-\ti40e_aqc_opc_configure_vsi_ets_sla_bw_limit    = 0x0406,\n-\ti40e_aqc_opc_configure_vsi_tc_bw               = 0x0407,\n-\ti40e_aqc_opc_query_vsi_bw_config               = 0x0408,\n-\ti40e_aqc_opc_query_vsi_ets_sla_config          = 0x040A,\n-\ti40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,\n-\n-\ti40e_aqc_opc_enable_switching_comp_ets             = 0x0413,\n-\ti40e_aqc_opc_modify_switching_comp_ets             = 0x0414,\n-\ti40e_aqc_opc_disable_switching_comp_ets            = 0x0415,\n-\ti40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,\n-\ti40e_aqc_opc_configure_switching_comp_bw_config    = 0x0417,\n-\ti40e_aqc_opc_query_switching_comp_ets_config       = 0x0418,\n-\ti40e_aqc_opc_query_port_ets_config                 = 0x0419,\n-\ti40e_aqc_opc_query_switching_comp_bw_config        = 0x041A,\n-\ti40e_aqc_opc_suspend_port_tx                       = 0x041B,\n-\ti40e_aqc_opc_resume_port_tx                        = 0x041C,\n-\ti40e_aqc_opc_configure_partition_bw                = 0x041D,\n+\ti40e_aqc_opc_configure_vsi_bw_limit\t\t= 0x0400,\n+\ti40e_aqc_opc_configure_vsi_ets_sla_bw_limit\t= 0x0406,\n+\ti40e_aqc_opc_configure_vsi_tc_bw\t\t= 0x0407,\n+\ti40e_aqc_opc_query_vsi_bw_config\t\t= 0x0408,\n+\ti40e_aqc_opc_query_vsi_ets_sla_config\t\t= 0x040A,\n+\ti40e_aqc_opc_configure_switching_comp_bw_limit\t= 0x0410,\n+\n+\ti40e_aqc_opc_enable_switching_comp_ets\t\t\t= 0x0413,\n+\ti40e_aqc_opc_modify_switching_comp_ets\t\t\t= 0x0414,\n+\ti40e_aqc_opc_disable_switching_comp_ets\t\t\t= 0x0415,\n+\ti40e_aqc_opc_configure_switching_comp_ets_bw_limit\t= 0x0416,\n+\ti40e_aqc_opc_configure_switching_comp_bw_config\t\t= 0x0417,\n+\ti40e_aqc_opc_query_switching_comp_ets_config\t\t= 0x0418,\n+\ti40e_aqc_opc_query_port_ets_config\t\t\t= 0x0419,\n+\ti40e_aqc_opc_query_switching_comp_bw_config\t\t= 0x041A,\n+\ti40e_aqc_opc_suspend_port_tx\t\t\t\t= 0x041B,\n+\ti40e_aqc_opc_resume_port_tx\t\t\t\t= 0x041C,\n+\ti40e_aqc_opc_configure_partition_bw\t\t\t= 0x041D,\n \n \t/* hmc */\n-\ti40e_aqc_opc_query_hmc_resource_profile = 0x0500,\n-\ti40e_aqc_opc_set_hmc_resource_profile   = 0x0501,\n+\ti40e_aqc_opc_query_hmc_resource_profile\t= 0x0500,\n+\ti40e_aqc_opc_set_hmc_resource_profile\t= 0x0501,\n \n \t/* phy commands*/\n-\ti40e_aqc_opc_get_phy_abilities   = 0x0600,\n-\ti40e_aqc_opc_set_phy_config      = 0x0601,\n-\ti40e_aqc_opc_set_mac_config      = 0x0603,\n-\ti40e_aqc_opc_set_link_restart_an = 0x0605,\n-\ti40e_aqc_opc_get_link_status     = 0x0607,\n-\ti40e_aqc_opc_set_phy_int_mask    = 0x0613,\n-\ti40e_aqc_opc_get_local_advt_reg  = 0x0614,\n-\ti40e_aqc_opc_set_local_advt_reg  = 0x0615,\n-\ti40e_aqc_opc_get_partner_advt    = 0x0616,\n-\ti40e_aqc_opc_set_lb_modes        = 0x0618,\n-\ti40e_aqc_opc_get_phy_wol_caps    = 0x0621,\n-\ti40e_aqc_opc_set_phy_debug\t = 0x0622,\n-\ti40e_aqc_opc_upload_ext_phy_fm   = 0x0625,\n+\ti40e_aqc_opc_get_phy_abilities\t\t= 0x0600,\n+\ti40e_aqc_opc_set_phy_config\t\t= 0x0601,\n+\ti40e_aqc_opc_set_mac_config\t\t= 0x0603,\n+\ti40e_aqc_opc_set_link_restart_an\t= 0x0605,\n+\ti40e_aqc_opc_get_link_status\t\t= 0x0607,\n+\ti40e_aqc_opc_set_phy_int_mask\t\t= 0x0613,\n+\ti40e_aqc_opc_get_local_advt_reg\t\t= 0x0614,\n+\ti40e_aqc_opc_set_local_advt_reg\t\t= 0x0615,\n+\ti40e_aqc_opc_get_partner_advt\t\t= 0x0616,\n+\ti40e_aqc_opc_set_lb_modes\t\t= 0x0618,\n+\ti40e_aqc_opc_get_phy_wol_caps\t\t= 0x0621,\n+\ti40e_aqc_opc_set_phy_debug\t\t= 0x0622,\n+\ti40e_aqc_opc_upload_ext_phy_fm\t\t= 0x0625,\n \n \t/* NVM commands */\n-\ti40e_aqc_opc_nvm_read         = 0x0701,\n-\ti40e_aqc_opc_nvm_erase        = 0x0702,\n-\ti40e_aqc_opc_nvm_update       = 0x0703,\n-\ti40e_aqc_opc_nvm_config_read  = 0x0704,\n-\ti40e_aqc_opc_nvm_config_write = 0x0705,\n+\ti40e_aqc_opc_nvm_read\t\t\t= 0x0701,\n+\ti40e_aqc_opc_nvm_erase\t\t\t= 0x0702,\n+\ti40e_aqc_opc_nvm_update\t\t\t= 0x0703,\n+\ti40e_aqc_opc_nvm_config_read\t\t= 0x0704,\n+\ti40e_aqc_opc_nvm_config_write\t\t= 0x0705,\n \n \t/* virtualization commands */\n-\ti40e_aqc_opc_send_msg_to_pf   = 0x0801,\n-\ti40e_aqc_opc_send_msg_to_vf   = 0x0802,\n-\ti40e_aqc_opc_send_msg_to_peer = 0x0803,\n+\ti40e_aqc_opc_send_msg_to_pf\t\t= 0x0801,\n+\ti40e_aqc_opc_send_msg_to_vf\t\t= 0x0802,\n+\ti40e_aqc_opc_send_msg_to_peer\t\t= 0x0803,\n \n \t/* alternate structure */\n-\ti40e_aqc_opc_alternate_write          = 0x0900,\n-\ti40e_aqc_opc_alternate_write_indirect = 0x0901,\n-\ti40e_aqc_opc_alternate_read           = 0x0902,\n-\ti40e_aqc_opc_alternate_read_indirect  = 0x0903,\n-\ti40e_aqc_opc_alternate_write_done     = 0x0904,\n-\ti40e_aqc_opc_alternate_set_mode       = 0x0905,\n-\ti40e_aqc_opc_alternate_clear_port     = 0x0906,\n+\ti40e_aqc_opc_alternate_write\t\t= 0x0900,\n+\ti40e_aqc_opc_alternate_write_indirect\t= 0x0901,\n+\ti40e_aqc_opc_alternate_read\t\t= 0x0902,\n+\ti40e_aqc_opc_alternate_read_indirect\t= 0x0903,\n+\ti40e_aqc_opc_alternate_write_done\t= 0x0904,\n+\ti40e_aqc_opc_alternate_set_mode\t\t= 0x0905,\n+\ti40e_aqc_opc_alternate_clear_port\t= 0x0906,\n \n \t/* LLDP commands */\n-\ti40e_aqc_opc_lldp_get_mib    = 0x0A00,\n-\ti40e_aqc_opc_lldp_update_mib = 0x0A01,\n-\ti40e_aqc_opc_lldp_add_tlv    = 0x0A02,\n-\ti40e_aqc_opc_lldp_update_tlv = 0x0A03,\n-\ti40e_aqc_opc_lldp_delete_tlv = 0x0A04,\n-\ti40e_aqc_opc_lldp_stop       = 0x0A05,\n-\ti40e_aqc_opc_lldp_start      = 0x0A06,\n+\ti40e_aqc_opc_lldp_get_mib\t= 0x0A00,\n+\ti40e_aqc_opc_lldp_update_mib\t= 0x0A01,\n+\ti40e_aqc_opc_lldp_add_tlv\t= 0x0A02,\n+\ti40e_aqc_opc_lldp_update_tlv\t= 0x0A03,\n+\ti40e_aqc_opc_lldp_delete_tlv\t= 0x0A04,\n+\ti40e_aqc_opc_lldp_stop\t\t= 0x0A05,\n+\ti40e_aqc_opc_lldp_start\t\t= 0x0A06,\n \n \t/* Tunnel commands */\n-\ti40e_aqc_opc_add_udp_tunnel       = 0x0B00,\n-\ti40e_aqc_opc_del_udp_tunnel       = 0x0B01,\n-\ti40e_aqc_opc_tunnel_key_structure = 0x0B10,\n+\ti40e_aqc_opc_add_udp_tunnel\t= 0x0B00,\n+\ti40e_aqc_opc_del_udp_tunnel\t= 0x0B01,\n+\ti40e_aqc_opc_tunnel_key_structure\t= 0x0B10,\n \n \t/* Async Events */\n-\ti40e_aqc_opc_event_lan_overflow = 0x1001,\n+\ti40e_aqc_opc_event_lan_overflow\t\t= 0x1001,\n \n \t/* OEM commands */\n-\ti40e_aqc_opc_oem_parameter_change     = 0xFE00,\n-\ti40e_aqc_opc_oem_device_status_change = 0xFE01,\n+\ti40e_aqc_opc_oem_parameter_change\t= 0xFE00,\n+\ti40e_aqc_opc_oem_device_status_change\t= 0xFE01,\n \n \t/* debug commands */\n-\ti40e_aqc_opc_debug_get_deviceid     = 0xFF00,\n-\ti40e_aqc_opc_debug_set_mode         = 0xFF01,\n-\ti40e_aqc_opc_debug_read_reg         = 0xFF03,\n-\ti40e_aqc_opc_debug_write_reg        = 0xFF04,\n-\ti40e_aqc_opc_debug_modify_reg       = 0xFF07,\n-\ti40e_aqc_opc_debug_dump_internals   = 0xFF08,\n-\ti40e_aqc_opc_debug_modify_internals = 0xFF09,\n+\ti40e_aqc_opc_debug_get_deviceid\t\t= 0xFF00,\n+\ti40e_aqc_opc_debug_set_mode\t\t= 0xFF01,\n+\ti40e_aqc_opc_debug_read_reg\t\t= 0xFF03,\n+\ti40e_aqc_opc_debug_write_reg\t\t= 0xFF04,\n+\ti40e_aqc_opc_debug_modify_reg\t\t= 0xFF07,\n+\ti40e_aqc_opc_debug_dump_internals\t= 0xFF08,\n+\ti40e_aqc_opc_debug_modify_internals\t= 0xFF09,\n };\n \n /* command structures and indirect data structures */\n@@ -309,7 +309,7 @@ enum i40e_admin_queue_opc {\n /* This macro is used extensively to ensure that command structures are 16\n  * bytes in length as they have to map to the raw array of that size.\n  */\n-#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)\n+#define I40E_CHECK_CMD_LENGTH(X)\tI40E_CHECK_STRUCT_LEN(16, X)\n \n /* internal (0x00XX) commands */\n \n@@ -327,22 +327,22 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);\n \n /* Send driver version (indirect 0x0002) */\n struct i40e_aqc_driver_version {\n-\tu8     driver_major_ver;\n-\tu8     driver_minor_ver;\n-\tu8     driver_build_ver;\n-\tu8     driver_subbuild_ver;\n-\tu8     reserved[4];\n-\t__le32 address_high;\n-\t__le32 address_low;\n+\tu8\tdriver_major_ver;\n+\tu8\tdriver_minor_ver;\n+\tu8\tdriver_build_ver;\n+\tu8\tdriver_subbuild_ver;\n+\tu8\treserved[4];\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);\n \n /* Queue Shutdown (direct 0x0003) */\n struct i40e_aqc_queue_shutdown {\n-\t__le32     driver_unloading;\n-#define I40E_AQ_DRIVER_UNLOADING    0x1\n-\tu8     reserved[12];\n+\t__le32\tdriver_unloading;\n+#define I40E_AQ_DRIVER_UNLOADING\t0x1\n+\tu8\treserved[12];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);\n@@ -358,19 +358,19 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);\n /* Request resource ownership (direct 0x0008)\n  * Release resource ownership (direct 0x0009)\n  */\n-#define I40E_AQ_RESOURCE_NVM               1\n-#define I40E_AQ_RESOURCE_SDP               2\n-#define I40E_AQ_RESOURCE_ACCESS_READ       1\n-#define I40E_AQ_RESOURCE_ACCESS_WRITE      2\n-#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT  3000\n-#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000\n+#define I40E_AQ_RESOURCE_NVM\t\t\t1\n+#define I40E_AQ_RESOURCE_SDP\t\t\t2\n+#define I40E_AQ_RESOURCE_ACCESS_READ\t\t1\n+#define I40E_AQ_RESOURCE_ACCESS_WRITE\t\t2\n+#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT\t3000\n+#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT\t180000\n \n struct i40e_aqc_request_resource {\n-\t__le16 resource_id;\n-\t__le16 access_type;\n-\t__le32 timeout;\n-\t__le32 resource_number;\n-\tu8     reserved[4];\n+\t__le16\tresource_id;\n+\t__le16\taccess_type;\n+\t__le32\ttimeout;\n+\t__le32\tresource_number;\n+\tu8\treserved[4];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);\n@@ -380,7 +380,7 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);\n  */\n struct i40e_aqc_list_capabilites {\n \tu8 command_flags;\n-#define I40E_AQ_LIST_CAP_PF_INDEX_EN     1\n+#define I40E_AQ_LIST_CAP_PF_INDEX_EN\t1\n \tu8 pf_index;\n \tu8 reserved[2];\n \t__le32 count;\n@@ -391,123 +391,123 @@ struct i40e_aqc_list_capabilites {\n I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);\n \n struct i40e_aqc_list_capabilities_element_resp {\n-\t__le16 id;\n-\tu8     major_rev;\n-\tu8     minor_rev;\n-\t__le32 number;\n-\t__le32 logical_id;\n-\t__le32 phys_id;\n-\tu8     reserved[16];\n+\t__le16\tid;\n+\tu8\tmajor_rev;\n+\tu8\tminor_rev;\n+\t__le32\tnumber;\n+\t__le32\tlogical_id;\n+\t__le32\tphys_id;\n+\tu8\treserved[16];\n };\n \n /* list of caps */\n \n-#define I40E_AQ_CAP_ID_SWITCH_MODE      0x0001\n-#define I40E_AQ_CAP_ID_MNG_MODE         0x0002\n-#define I40E_AQ_CAP_ID_NPAR_ACTIVE      0x0003\n-#define I40E_AQ_CAP_ID_OS2BMC_CAP       0x0004\n-#define I40E_AQ_CAP_ID_FUNCTIONS_VALID  0x0005\n-#define I40E_AQ_CAP_ID_ALTERNATE_RAM    0x0006\n-#define I40E_AQ_CAP_ID_SRIOV            0x0012\n-#define I40E_AQ_CAP_ID_VF               0x0013\n-#define I40E_AQ_CAP_ID_VMDQ             0x0014\n-#define I40E_AQ_CAP_ID_8021QBG          0x0015\n-#define I40E_AQ_CAP_ID_8021QBR          0x0016\n-#define I40E_AQ_CAP_ID_VSI              0x0017\n-#define I40E_AQ_CAP_ID_DCB              0x0018\n-#define I40E_AQ_CAP_ID_FCOE             0x0021\n-#define I40E_AQ_CAP_ID_RSS              0x0040\n-#define I40E_AQ_CAP_ID_RXQ              0x0041\n-#define I40E_AQ_CAP_ID_TXQ              0x0042\n-#define I40E_AQ_CAP_ID_MSIX             0x0043\n-#define I40E_AQ_CAP_ID_VF_MSIX          0x0044\n-#define I40E_AQ_CAP_ID_FLOW_DIRECTOR    0x0045\n-#define I40E_AQ_CAP_ID_1588             0x0046\n-#define I40E_AQ_CAP_ID_IWARP            0x0051\n-#define I40E_AQ_CAP_ID_LED              0x0061\n-#define I40E_AQ_CAP_ID_SDP              0x0062\n-#define I40E_AQ_CAP_ID_MDIO             0x0063\n-#define I40E_AQ_CAP_ID_FLEX10           0x00F1\n-#define I40E_AQ_CAP_ID_CEM              0x00F2\n+#define I40E_AQ_CAP_ID_SWITCH_MODE\t0x0001\n+#define I40E_AQ_CAP_ID_MNG_MODE\t\t0x0002\n+#define I40E_AQ_CAP_ID_NPAR_ACTIVE\t0x0003\n+#define I40E_AQ_CAP_ID_OS2BMC_CAP\t0x0004\n+#define I40E_AQ_CAP_ID_FUNCTIONS_VALID\t0x0005\n+#define I40E_AQ_CAP_ID_ALTERNATE_RAM\t0x0006\n+#define I40E_AQ_CAP_ID_SRIOV\t\t0x0012\n+#define I40E_AQ_CAP_ID_VF\t\t0x0013\n+#define I40E_AQ_CAP_ID_VMDQ\t\t0x0014\n+#define I40E_AQ_CAP_ID_8021QBG\t\t0x0015\n+#define I40E_AQ_CAP_ID_8021QBR\t\t0x0016\n+#define I40E_AQ_CAP_ID_VSI\t\t0x0017\n+#define I40E_AQ_CAP_ID_DCB\t\t0x0018\n+#define I40E_AQ_CAP_ID_FCOE\t\t0x0021\n+#define I40E_AQ_CAP_ID_RSS\t\t0x0040\n+#define I40E_AQ_CAP_ID_RXQ\t\t0x0041\n+#define I40E_AQ_CAP_ID_TXQ\t\t0x0042\n+#define I40E_AQ_CAP_ID_MSIX\t\t0x0043\n+#define I40E_AQ_CAP_ID_VF_MSIX\t\t0x0044\n+#define I40E_AQ_CAP_ID_FLOW_DIRECTOR\t0x0045\n+#define I40E_AQ_CAP_ID_1588\t\t0x0046\n+#define I40E_AQ_CAP_ID_IWARP\t\t0x0051\n+#define I40E_AQ_CAP_ID_LED\t\t0x0061\n+#define I40E_AQ_CAP_ID_SDP\t\t0x0062\n+#define I40E_AQ_CAP_ID_MDIO\t\t0x0063\n+#define I40E_AQ_CAP_ID_FLEX10\t\t0x00F1\n+#define I40E_AQ_CAP_ID_CEM\t\t0x00F2\n \n /* Set CPPM Configuration (direct 0x0103) */\n struct i40e_aqc_cppm_configuration {\n-\t__le16 command_flags;\n-#define I40E_AQ_CPPM_EN_LTRC    0x0800\n-#define I40E_AQ_CPPM_EN_DMCTH   0x1000\n-#define I40E_AQ_CPPM_EN_DMCTLX  0x2000\n-#define I40E_AQ_CPPM_EN_HPTC    0x4000\n-#define I40E_AQ_CPPM_EN_DMARC   0x8000\n-\t__le16 ttlx;\n-\t__le32 dmacr;\n-\t__le16 dmcth;\n-\tu8     hptc;\n-\tu8     reserved;\n-\t__le32 pfltrc;\n+\t__le16\tcommand_flags;\n+#define I40E_AQ_CPPM_EN_LTRC\t0x0800\n+#define I40E_AQ_CPPM_EN_DMCTH\t0x1000\n+#define I40E_AQ_CPPM_EN_DMCTLX\t0x2000\n+#define I40E_AQ_CPPM_EN_HPTC\t0x4000\n+#define I40E_AQ_CPPM_EN_DMARC\t0x8000\n+\t__le16\tttlx;\n+\t__le32\tdmacr;\n+\t__le16\tdmcth;\n+\tu8\thptc;\n+\tu8\treserved;\n+\t__le32\tpfltrc;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);\n \n /* Set ARP Proxy command / response (indirect 0x0104) */\n struct i40e_aqc_arp_proxy_data {\n-\t__le16 command_flags;\n-#define I40E_AQ_ARP_INIT_IPV4           0x0008\n-#define I40E_AQ_ARP_UNSUP_CTL           0x0010\n-#define I40E_AQ_ARP_ENA                 0x0020\n-#define I40E_AQ_ARP_ADD_IPV4            0x0040\n-#define I40E_AQ_ARP_DEL_IPV4            0x0080\n-\t__le16 table_id;\n-\t__le32 pfpm_proxyfc;\n-\t__le32 ip_addr;\n-\tu8     mac_addr[6];\n+\t__le16\tcommand_flags;\n+#define I40E_AQ_ARP_INIT_IPV4\t0x0008\n+#define I40E_AQ_ARP_UNSUP_CTL\t0x0010\n+#define I40E_AQ_ARP_ENA\t\t0x0020\n+#define I40E_AQ_ARP_ADD_IPV4\t0x0040\n+#define I40E_AQ_ARP_DEL_IPV4\t0x0080\n+\t__le16\ttable_id;\n+\t__le32\tpfpm_proxyfc;\n+\t__le32\tip_addr;\n+\tu8\tmac_addr[6];\n };\n \n /* Set NS Proxy Table Entry Command (indirect 0x0105) */\n struct i40e_aqc_ns_proxy_data {\n-\t__le16 table_idx_mac_addr_0;\n-\t__le16 table_idx_mac_addr_1;\n-\t__le16 table_idx_ipv6_0;\n-\t__le16 table_idx_ipv6_1;\n-\t__le16 control;\n-#define I40E_AQ_NS_PROXY_ADD_0             0x0100\n-#define I40E_AQ_NS_PROXY_DEL_0             0x0200\n-#define I40E_AQ_NS_PROXY_ADD_1             0x0400\n-#define I40E_AQ_NS_PROXY_DEL_1             0x0800\n-#define I40E_AQ_NS_PROXY_ADD_IPV6_0        0x1000\n-#define I40E_AQ_NS_PROXY_DEL_IPV6_0        0x2000\n-#define I40E_AQ_NS_PROXY_ADD_IPV6_1        0x4000\n-#define I40E_AQ_NS_PROXY_DEL_IPV6_1        0x8000\n-#define I40E_AQ_NS_PROXY_COMMAND_SEQ       0x0001\n-#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL     0x0002\n-#define I40E_AQ_NS_PROXY_INIT_MAC_TBL      0x0004\n-\tu8     mac_addr_0[6];\n-\tu8     mac_addr_1[6];\n-\tu8     local_mac_addr[6];\n-\tu8     ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */\n-\tu8     ipv6_addr_1[16];\n+\t__le16\ttable_idx_mac_addr_0;\n+\t__le16\ttable_idx_mac_addr_1;\n+\t__le16\ttable_idx_ipv6_0;\n+\t__le16\ttable_idx_ipv6_1;\n+\t__le16\tcontrol;\n+#define I40E_AQ_NS_PROXY_ADD_0\t\t0x0100\n+#define I40E_AQ_NS_PROXY_DEL_0\t\t0x0200\n+#define I40E_AQ_NS_PROXY_ADD_1\t\t0x0400\n+#define I40E_AQ_NS_PROXY_DEL_1\t\t0x0800\n+#define I40E_AQ_NS_PROXY_ADD_IPV6_0\t0x1000\n+#define I40E_AQ_NS_PROXY_DEL_IPV6_0\t0x2000\n+#define I40E_AQ_NS_PROXY_ADD_IPV6_1\t0x4000\n+#define I40E_AQ_NS_PROXY_DEL_IPV6_1\t0x8000\n+#define I40E_AQ_NS_PROXY_COMMAND_SEQ\t0x0001\n+#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL\t0x0002\n+#define I40E_AQ_NS_PROXY_INIT_MAC_TBL\t0x0004\n+\tu8\tmac_addr_0[6];\n+\tu8\tmac_addr_1[6];\n+\tu8\tlocal_mac_addr[6];\n+\tu8\tipv6_addr_0[16]; /* Warning! spec specifies BE byte order */\n+\tu8\tipv6_addr_1[16];\n };\n \n /* Manage LAA Command (0x0106) - obsolete */\n struct i40e_aqc_mng_laa {\n \t__le16\tcommand_flags;\n-#define I40E_AQ_LAA_FLAG_WR   0x8000\n-\tu8     reserved[2];\n-\t__le32 sal;\n-\t__le16 sah;\n-\tu8     reserved2[6];\n+#define I40E_AQ_LAA_FLAG_WR\t0x8000\n+\tu8\treserved[2];\n+\t__le32\tsal;\n+\t__le16\tsah;\n+\tu8\treserved2[6];\n };\n \n /* Manage MAC Address Read Command (indirect 0x0107) */\n struct i40e_aqc_mac_address_read {\n \t__le16\tcommand_flags;\n-#define I40E_AQC_LAN_ADDR_VALID   0x10\n-#define I40E_AQC_SAN_ADDR_VALID   0x20\n-#define I40E_AQC_PORT_ADDR_VALID  0x40\n-#define I40E_AQC_WOL_ADDR_VALID   0x80\n-#define I40E_AQC_ADDR_VALID_MASK  0xf0\n-\tu8     reserved[6];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+#define I40E_AQC_LAN_ADDR_VALID\t\t0x10\n+#define I40E_AQC_SAN_ADDR_VALID\t\t0x20\n+#define I40E_AQC_PORT_ADDR_VALID\t0x40\n+#define I40E_AQC_WOL_ADDR_VALID\t\t0x80\n+#define I40E_AQC_ADDR_VALID_MASK\t0xf0\n+\tu8\treserved[6];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);\n@@ -523,14 +523,14 @@ I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);\n \n /* Manage MAC Address Write Command (0x0108) */\n struct i40e_aqc_mac_address_write {\n-\t__le16 command_flags;\n-#define I40E_AQC_WRITE_TYPE_LAA_ONLY    0x0000\n-#define I40E_AQC_WRITE_TYPE_LAA_WOL     0x4000\n-#define I40E_AQC_WRITE_TYPE_PORT        0x8000\n-#define I40E_AQC_WRITE_TYPE_MASK        0xc000\n-\t__le16 mac_sah;\n-\t__le32 mac_sal;\n-\tu8     reserved[8];\n+\t__le16\tcommand_flags;\n+#define I40E_AQC_WRITE_TYPE_LAA_ONLY\t0x0000\n+#define I40E_AQC_WRITE_TYPE_LAA_WOL\t0x4000\n+#define I40E_AQC_WRITE_TYPE_PORT\t0x8000\n+#define I40E_AQC_WRITE_TYPE_MASK\t0xc000\n+\t__le16\tmac_sah;\n+\t__le32\tmac_sal;\n+\tu8\treserved[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);\n@@ -551,10 +551,10 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);\n  * command\n  */\n struct i40e_aqc_switch_seid {\n-\t__le16 seid;\n-\tu8     reserved[6];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\t__le16\tseid;\n+\tu8\treserved[6];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);\n@@ -563,34 +563,34 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);\n  * uses i40e_aqc_switch_seid for the descriptor\n  */\n struct i40e_aqc_get_switch_config_header_resp {\n-\t__le16 num_reported;\n-\t__le16 num_total;\n-\tu8     reserved[12];\n+\t__le16\tnum_reported;\n+\t__le16\tnum_total;\n+\tu8\treserved[12];\n };\n \n struct i40e_aqc_switch_config_element_resp {\n-\tu8     element_type;\n-#define I40E_AQ_SW_ELEM_TYPE_MAC        1\n-#define I40E_AQ_SW_ELEM_TYPE_PF         2\n-#define I40E_AQ_SW_ELEM_TYPE_VF         3\n-#define I40E_AQ_SW_ELEM_TYPE_EMP        4\n-#define I40E_AQ_SW_ELEM_TYPE_BMC        5\n-#define I40E_AQ_SW_ELEM_TYPE_PV         16\n-#define I40E_AQ_SW_ELEM_TYPE_VEB        17\n-#define I40E_AQ_SW_ELEM_TYPE_PA         18\n-#define I40E_AQ_SW_ELEM_TYPE_VSI        19\n-\tu8     revision;\n-#define I40E_AQ_SW_ELEM_REV_1           1\n-\t__le16 seid;\n-\t__le16 uplink_seid;\n-\t__le16 downlink_seid;\n-\tu8     reserved[3];\n-\tu8     connection_type;\n-#define I40E_AQ_CONN_TYPE_REGULAR       0x1\n-#define I40E_AQ_CONN_TYPE_DEFAULT       0x2\n-#define I40E_AQ_CONN_TYPE_CASCADED      0x3\n-\t__le16 scheduler_id;\n-\t__le16 element_info;\n+\tu8\telement_type;\n+#define I40E_AQ_SW_ELEM_TYPE_MAC\t1\n+#define I40E_AQ_SW_ELEM_TYPE_PF\t\t2\n+#define I40E_AQ_SW_ELEM_TYPE_VF\t\t3\n+#define I40E_AQ_SW_ELEM_TYPE_EMP\t4\n+#define I40E_AQ_SW_ELEM_TYPE_BMC\t5\n+#define I40E_AQ_SW_ELEM_TYPE_PV\t\t16\n+#define I40E_AQ_SW_ELEM_TYPE_VEB\t17\n+#define I40E_AQ_SW_ELEM_TYPE_PA\t\t18\n+#define I40E_AQ_SW_ELEM_TYPE_VSI\t19\n+\tu8\trevision;\n+#define I40E_AQ_SW_ELEM_REV_1\t\t1\n+\t__le16\tseid;\n+\t__le16\tuplink_seid;\n+\t__le16\tdownlink_seid;\n+\tu8\treserved[3];\n+\tu8\tconnection_type;\n+#define I40E_AQ_CONN_TYPE_REGULAR\t0x1\n+#define I40E_AQ_CONN_TYPE_DEFAULT\t0x2\n+#define I40E_AQ_CONN_TYPE_CASCADED\t0x3\n+\t__le16\tscheduler_id;\n+\t__le16\telement_info;\n };\n \n /* Get Switch Configuration (indirect 0x0200)\n@@ -598,73 +598,73 @@ struct i40e_aqc_switch_config_element_resp {\n  *    the first in the array is the header, remainder are elements\n  */\n struct i40e_aqc_get_switch_config_resp {\n-\tstruct i40e_aqc_get_switch_config_header_resp header;\n-\tstruct i40e_aqc_switch_config_element_resp    element[1];\n+\tstruct i40e_aqc_get_switch_config_header_resp\theader;\n+\tstruct i40e_aqc_switch_config_element_resp\telement[1];\n };\n \n /* Add Statistics (direct 0x0201)\n  * Remove Statistics (direct 0x0202)\n  */\n struct i40e_aqc_add_remove_statistics {\n-\t__le16 seid;\n-\t__le16 vlan;\n-\t__le16 stat_index;\n-\tu8     reserved[10];\n+\t__le16\tseid;\n+\t__le16\tvlan;\n+\t__le16\tstat_index;\n+\tu8\treserved[10];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);\n \n /* Set Port Parameters command (direct 0x0203) */\n struct i40e_aqc_set_port_parameters {\n-\t__le16 command_flags;\n-#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS   1\n-#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS  2 /* must set! */\n-#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA    4\n-\t__le16 bad_frame_vsi;\n-\t__le16 default_seid;        /* reserved for command */\n-\tu8     reserved[10];\n+\t__le16\tcommand_flags;\n+#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS\t1\n+#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS\t2 /* must set! */\n+#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA\t4\n+\t__le16\tbad_frame_vsi;\n+\t__le16\tdefault_seid;        /* reserved for command */\n+\tu8\treserved[10];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);\n \n /* Get Switch Resource Allocation (indirect 0x0204) */\n struct i40e_aqc_get_switch_resource_alloc {\n-\tu8     num_entries;         /* reserved for command */\n-\tu8     reserved[7];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\tnum_entries;         /* reserved for command */\n+\tu8\treserved[7];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);\n \n /* expect an array of these structs in the response buffer */\n struct i40e_aqc_switch_resource_alloc_element_resp {\n-\tu8     resource_type;\n-#define I40E_AQ_RESOURCE_TYPE_VEB                 0x0\n-#define I40E_AQ_RESOURCE_TYPE_VSI                 0x1\n-#define I40E_AQ_RESOURCE_TYPE_MACADDR             0x2\n-#define I40E_AQ_RESOURCE_TYPE_STAG                0x3\n-#define I40E_AQ_RESOURCE_TYPE_ETAG                0x4\n-#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH      0x5\n-#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH        0x6\n-#define I40E_AQ_RESOURCE_TYPE_VLAN                0x7\n-#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY      0x8\n-#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY     0x9\n-#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL      0xA\n-#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE         0xB\n-#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS          0xC\n-#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS        0xD\n-#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS   0xF\n-#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS          0x10\n-#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS         0x11\n-#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS            0x12\n-#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS        0x13\n-\tu8     reserved1;\n-\t__le16 guaranteed;\n-\t__le16 total;\n-\t__le16 used;\n-\t__le16 total_unalloced;\n-\tu8     reserved2[6];\n+\tu8\tresource_type;\n+#define I40E_AQ_RESOURCE_TYPE_VEB\t\t0x0\n+#define I40E_AQ_RESOURCE_TYPE_VSI\t\t0x1\n+#define I40E_AQ_RESOURCE_TYPE_MACADDR\t\t0x2\n+#define I40E_AQ_RESOURCE_TYPE_STAG\t\t0x3\n+#define I40E_AQ_RESOURCE_TYPE_ETAG\t\t0x4\n+#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH\t0x5\n+#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH\t0x6\n+#define I40E_AQ_RESOURCE_TYPE_VLAN\t\t0x7\n+#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY\t0x8\n+#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY\t0x9\n+#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL\t0xA\n+#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE\t0xB\n+#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS\t0xC\n+#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS\t0xD\n+#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS\t0xF\n+#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS\t0x10\n+#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS\t0x11\n+#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS\t\t0x12\n+#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS\t0x13\n+\tu8\treserved1;\n+\t__le16\tguaranteed;\n+\t__le16\ttotal;\n+\t__le16\tused;\n+\t__le16\ttotal_unalloced;\n+\tu8\treserved2[6];\n };\n \n /* Add VSI (indirect 0x0210)\n@@ -678,24 +678,24 @@ struct i40e_aqc_switch_resource_alloc_element_resp {\n  *     uses the same completion and data structure as Add VSI\n  */\n struct i40e_aqc_add_get_update_vsi {\n-\t__le16 uplink_seid;\n-\tu8     connection_type;\n-#define I40E_AQ_VSI_CONN_TYPE_NORMAL            0x1\n-#define I40E_AQ_VSI_CONN_TYPE_DEFAULT           0x2\n-#define I40E_AQ_VSI_CONN_TYPE_CASCADED          0x3\n-\tu8     reserved1;\n-\tu8     vf_id;\n-\tu8     reserved2;\n-\t__le16 vsi_flags;\n-#define I40E_AQ_VSI_TYPE_SHIFT          0x0\n-#define I40E_AQ_VSI_TYPE_MASK           (0x3 << I40E_AQ_VSI_TYPE_SHIFT)\n-#define I40E_AQ_VSI_TYPE_VF             0x0\n-#define I40E_AQ_VSI_TYPE_VMDQ2          0x1\n-#define I40E_AQ_VSI_TYPE_PF             0x2\n-#define I40E_AQ_VSI_TYPE_EMP_MNG        0x3\n-#define I40E_AQ_VSI_FLAG_CASCADED_PV    0x4\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\t__le16\tuplink_seid;\n+\tu8\tconnection_type;\n+#define I40E_AQ_VSI_CONN_TYPE_NORMAL\t0x1\n+#define I40E_AQ_VSI_CONN_TYPE_DEFAULT\t0x2\n+#define I40E_AQ_VSI_CONN_TYPE_CASCADED\t0x3\n+\tu8\treserved1;\n+\tu8\tvf_id;\n+\tu8\treserved2;\n+\t__le16\tvsi_flags;\n+#define I40E_AQ_VSI_TYPE_SHIFT\t\t0x0\n+#define I40E_AQ_VSI_TYPE_MASK\t\t(0x3 << I40E_AQ_VSI_TYPE_SHIFT)\n+#define I40E_AQ_VSI_TYPE_VF\t\t0x0\n+#define I40E_AQ_VSI_TYPE_VMDQ2\t\t0x1\n+#define I40E_AQ_VSI_TYPE_PF\t\t0x2\n+#define I40E_AQ_VSI_TYPE_EMP_MNG\t0x3\n+#define I40E_AQ_VSI_FLAG_CASCADED_PV\t0x4\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);\n@@ -713,121 +713,121 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);\n \n struct i40e_aqc_vsi_properties_data {\n \t/* first 96 byte are written by SW */\n-\t__le16 valid_sections;\n-#define I40E_AQ_VSI_PROP_SWITCH_VALID       0x0001\n-#define I40E_AQ_VSI_PROP_SECURITY_VALID     0x0002\n-#define I40E_AQ_VSI_PROP_VLAN_VALID         0x0004\n-#define I40E_AQ_VSI_PROP_CAS_PV_VALID       0x0008\n-#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID   0x0010\n-#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID    0x0020\n-#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID    0x0040\n-#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID    0x0080\n-#define I40E_AQ_VSI_PROP_OUTER_UP_VALID     0x0100\n-#define I40E_AQ_VSI_PROP_SCHED_VALID        0x0200\n+\t__le16\tvalid_sections;\n+#define I40E_AQ_VSI_PROP_SWITCH_VALID\t\t0x0001\n+#define I40E_AQ_VSI_PROP_SECURITY_VALID\t\t0x0002\n+#define I40E_AQ_VSI_PROP_VLAN_VALID\t\t0x0004\n+#define I40E_AQ_VSI_PROP_CAS_PV_VALID\t\t0x0008\n+#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID\t0x0010\n+#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID\t0x0020\n+#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID\t0x0040\n+#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID\t0x0080\n+#define I40E_AQ_VSI_PROP_OUTER_UP_VALID\t\t0x0100\n+#define I40E_AQ_VSI_PROP_SCHED_VALID\t\t0x0200\n \t/* switch section */\n-\t__le16 switch_id; /* 12bit id combined with flags below */\n-#define I40E_AQ_VSI_SW_ID_SHIFT             0x0000\n-#define I40E_AQ_VSI_SW_ID_MASK              (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)\n-#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG     0x1000\n-#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB     0x2000\n-#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB     0x4000\n-\tu8     sw_reserved[2];\n+\t__le16\tswitch_id; /* 12bit id combined with flags below */\n+#define I40E_AQ_VSI_SW_ID_SHIFT\t\t0x0000\n+#define I40E_AQ_VSI_SW_ID_MASK\t\t(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)\n+#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG\t0x1000\n+#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB\t0x2000\n+#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB\t0x4000\n+\tu8\tsw_reserved[2];\n \t/* security section */\n-\tu8     sec_flags;\n-#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01\n-#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02\n-#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04\n-\tu8     sec_reserved;\n+\tu8\tsec_flags;\n+#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\t0x01\n+#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK\t0x02\n+#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK\t0x04\n+\tu8\tsec_reserved;\n \t/* VLAN section */\n-\t__le16 pvid; /* VLANS include priority bits */\n-\t__le16 fcoe_pvid;\n-\tu8     port_vlan_flags;\n-#define I40E_AQ_VSI_PVLAN_MODE_SHIFT        0x00\n-#define I40E_AQ_VSI_PVLAN_MODE_MASK         (0x03 << \\\n-\t\t\t\t\t\tI40E_AQ_VSI_PVLAN_MODE_SHIFT)\n-#define I40E_AQ_VSI_PVLAN_MODE_TAGGED       0x01\n-#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED     0x02\n-#define I40E_AQ_VSI_PVLAN_MODE_ALL          0x03\n-#define I40E_AQ_VSI_PVLAN_INSERT_PVID       0x04\n-#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT        0x03\n-#define I40E_AQ_VSI_PVLAN_EMOD_MASK         (0x3 << \\\n-\t\t\t\t\tI40E_AQ_VSI_PVLAN_EMOD_SHIFT)\n-#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH     0x0\n-#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP       0x08\n-#define I40E_AQ_VSI_PVLAN_EMOD_STR          0x10\n-#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING      0x18\n-\tu8     pvlan_reserved[3];\n+\t__le16\tpvid; /* VLANS include priority bits */\n+\t__le16\tfcoe_pvid;\n+\tu8\tport_vlan_flags;\n+#define I40E_AQ_VSI_PVLAN_MODE_SHIFT\t0x00\n+#define I40E_AQ_VSI_PVLAN_MODE_MASK\t(0x03 << \\\n+\t\t\t\t\t I40E_AQ_VSI_PVLAN_MODE_SHIFT)\n+#define I40E_AQ_VSI_PVLAN_MODE_TAGGED\t0x01\n+#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED\t0x02\n+#define I40E_AQ_VSI_PVLAN_MODE_ALL\t0x03\n+#define I40E_AQ_VSI_PVLAN_INSERT_PVID\t0x04\n+#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT\t0x03\n+#define I40E_AQ_VSI_PVLAN_EMOD_MASK\t(0x3 << \\\n+\t\t\t\t\t I40E_AQ_VSI_PVLAN_EMOD_SHIFT)\n+#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH\t0x0\n+#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP\t0x08\n+#define I40E_AQ_VSI_PVLAN_EMOD_STR\t0x10\n+#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING\t0x18\n+\tu8\tpvlan_reserved[3];\n \t/* ingress egress up sections */\n-\t__le32 ingress_table; /* bitmap, 3 bits per up */\n-#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT      0\n-#define I40E_AQ_VSI_UP_TABLE_UP0_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP0_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT      3\n-#define I40E_AQ_VSI_UP_TABLE_UP1_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP1_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT      6\n-#define I40E_AQ_VSI_UP_TABLE_UP2_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP2_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT      9\n-#define I40E_AQ_VSI_UP_TABLE_UP3_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP3_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT      12\n-#define I40E_AQ_VSI_UP_TABLE_UP4_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP4_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT      15\n-#define I40E_AQ_VSI_UP_TABLE_UP5_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP5_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT      18\n-#define I40E_AQ_VSI_UP_TABLE_UP6_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP6_SHIFT)\n-#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT      21\n-#define I40E_AQ_VSI_UP_TABLE_UP7_MASK       (0x7 << \\\n-\t\t\t\t\tI40E_AQ_VSI_UP_TABLE_UP7_SHIFT)\n-\t__le32 egress_table;   /* same defines as for ingress table */\n+\t__le32\tingress_table; /* bitmap, 3 bits per up */\n+#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT\t0\n+#define I40E_AQ_VSI_UP_TABLE_UP0_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT\t3\n+#define I40E_AQ_VSI_UP_TABLE_UP1_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT\t6\n+#define I40E_AQ_VSI_UP_TABLE_UP2_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT\t9\n+#define I40E_AQ_VSI_UP_TABLE_UP3_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT\t12\n+#define I40E_AQ_VSI_UP_TABLE_UP4_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT\t15\n+#define I40E_AQ_VSI_UP_TABLE_UP5_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT\t18\n+#define I40E_AQ_VSI_UP_TABLE_UP6_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)\n+#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT\t21\n+#define I40E_AQ_VSI_UP_TABLE_UP7_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)\n+\t__le32\tegress_table;   /* same defines as for ingress table */\n \t/* cascaded PV section */\n-\t__le16 cas_pv_tag;\n-\tu8     cas_pv_flags;\n-#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT      0x00\n-#define I40E_AQ_VSI_CAS_PV_TAGX_MASK       (0x03 << \\\n-\t\t\t\t\t\tI40E_AQ_VSI_CAS_PV_TAGX_SHIFT)\n-#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE      0x00\n-#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE     0x01\n-#define I40E_AQ_VSI_CAS_PV_TAGX_COPY       0x02\n-#define I40E_AQ_VSI_CAS_PV_INSERT_TAG      0x10\n-#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE      0x20\n-#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40\n-\tu8     cas_pv_reserved;\n+\t__le16\tcas_pv_tag;\n+\tu8\tcas_pv_flags;\n+#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT\t\t0x00\n+#define I40E_AQ_VSI_CAS_PV_TAGX_MASK\t\t(0x03 << \\\n+\t\t\t\t\t\t I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)\n+#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE\t\t0x00\n+#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE\t\t0x01\n+#define I40E_AQ_VSI_CAS_PV_TAGX_COPY\t\t0x02\n+#define I40E_AQ_VSI_CAS_PV_INSERT_TAG\t\t0x10\n+#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE\t\t0x20\n+#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG\t0x40\n+\tu8\tcas_pv_reserved;\n \t/* queue mapping section */\n-\t__le16 mapping_flags;\n-#define I40E_AQ_VSI_QUE_MAP_CONTIG          0x0\n-#define I40E_AQ_VSI_QUE_MAP_NONCONTIG       0x1\n-\t__le16 queue_mapping[16];\n-#define I40E_AQ_VSI_QUEUE_SHIFT             0x0\n-#define I40E_AQ_VSI_QUEUE_MASK              (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)\n-\t__le16 tc_mapping[8];\n-#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT     0\n-#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK      (0x1FF << \\\n-\t\t\t\t\t\tI40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)\n-#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT     9\n-#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK      (0x7 << \\\n-\t\t\t\t\t\tI40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n+\t__le16\tmapping_flags;\n+#define I40E_AQ_VSI_QUE_MAP_CONTIG\t0x0\n+#define I40E_AQ_VSI_QUE_MAP_NONCONTIG\t0x1\n+\t__le16\tqueue_mapping[16];\n+#define I40E_AQ_VSI_QUEUE_SHIFT\t\t0x0\n+#define I40E_AQ_VSI_QUEUE_MASK\t\t(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)\n+\t__le16\ttc_mapping[8];\n+#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT\t0\n+#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK\t(0x1FF << \\\n+\t\t\t\t\t I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)\n+#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT\t9\n+#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK\t(0x7 << \\\n+\t\t\t\t\t I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n \t/* queueing option section */\n-\tu8     queueing_opt_flags;\n-#define I40E_AQ_VSI_QUE_OPT_TCP_ENA         0x10\n-#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA        0x20\n-\tu8     queueing_opt_reserved[3];\n+\tu8\tqueueing_opt_flags;\n+#define I40E_AQ_VSI_QUE_OPT_TCP_ENA\t0x10\n+#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA\t0x20\n+\tu8\tqueueing_opt_reserved[3];\n \t/* scheduler section */\n-\tu8     up_enable_bits;\n-\tu8     sched_reserved;\n+\tu8\tup_enable_bits;\n+\tu8\tsched_reserved;\n \t/* outer up section */\n-\t__le32 outer_up_table; /* same structure and defines as ingress table */\n-\tu8     cmd_reserved[8];\n+\t__le32\touter_up_table; /* same structure and defines as ingress table */\n+\tu8\tcmd_reserved[8];\n \t/* last 32 bytes are written by FW */\n-\t__le16 qs_handle[8];\n+\t__le16\tqs_handle[8];\n #define I40E_AQ_VSI_QS_HANDLE_INVALID\t0xFFFF\n-\t__le16 stat_counter_idx;\n-\t__le16 sched_id;\n-\tu8     resp_reserved[12];\n+\t__le16\tstat_counter_idx;\n+\t__le16\tsched_id;\n+\tu8\tresp_reserved[12];\n };\n \n I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);\n@@ -837,26 +837,26 @@ I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);\n  * (IS_CTRL_PORT only works on add PV)\n  */\n struct i40e_aqc_add_update_pv {\n-\t__le16 command_flags;\n-#define I40E_AQC_PV_FLAG_PV_TYPE                0x1\n-#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN    0x2\n-#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN    0x4\n-#define I40E_AQC_PV_FLAG_IS_CTRL_PORT           0x8\n-\t__le16 uplink_seid;\n-\t__le16 connected_seid;\n-\tu8     reserved[10];\n+\t__le16\tcommand_flags;\n+#define I40E_AQC_PV_FLAG_PV_TYPE\t\t0x1\n+#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN\t0x2\n+#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN\t0x4\n+#define I40E_AQC_PV_FLAG_IS_CTRL_PORT\t\t0x8\n+\t__le16\tuplink_seid;\n+\t__le16\tconnected_seid;\n+\tu8\treserved[10];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);\n \n struct i40e_aqc_add_update_pv_completion {\n \t/* reserved for update; for add also encodes error if rc == ENOSPC */\n-\t__le16 pv_seid;\n-#define I40E_AQC_PV_ERR_FLAG_NO_PV               0x1\n-#define I40E_AQC_PV_ERR_FLAG_NO_SCHED            0x2\n-#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER          0x4\n-#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY            0x8\n-\tu8     reserved[14];\n+\t__le16\tpv_seid;\n+#define I40E_AQC_PV_ERR_FLAG_NO_PV\t0x1\n+#define I40E_AQC_PV_ERR_FLAG_NO_SCHED\t0x2\n+#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER\t0x4\n+#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY\t0x8\n+\tu8\treserved[14];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);\n@@ -866,48 +866,48 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);\n  */\n \n struct i40e_aqc_get_pv_params_completion {\n-\t__le16 seid;\n-\t__le16 default_stag;\n-\t__le16 pv_flags; /* same flags as add_pv */\n-#define I40E_AQC_GET_PV_PV_TYPE            0x1\n-#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG  0x2\n-#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG  0x4\n-\tu8     reserved[8];\n-\t__le16 default_port_seid;\n+\t__le16\tseid;\n+\t__le16\tdefault_stag;\n+\t__le16\tpv_flags; /* same flags as add_pv */\n+#define I40E_AQC_GET_PV_PV_TYPE\t\t\t0x1\n+#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG\t0x2\n+#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG\t0x4\n+\tu8\treserved[8];\n+\t__le16\tdefault_port_seid;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);\n \n /* Add VEB (direct 0x0230) */\n struct i40e_aqc_add_veb {\n-\t__le16 uplink_seid;\n-\t__le16 downlink_seid;\n-\t__le16 veb_flags;\n-#define I40E_AQC_ADD_VEB_FLOATING           0x1\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT    1\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK     (0x3 << \\\n+\t__le16\tuplink_seid;\n+\t__le16\tdownlink_seid;\n+\t__le16\tveb_flags;\n+#define I40E_AQC_ADD_VEB_FLOATING\t\t0x1\n+#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT\t1\n+#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK\t\t(0x3 << \\\n \t\t\t\t\tI40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT  0x2\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA     0x4\n-#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER   0x8\n-\tu8     enable_tcs;\n-\tu8     reserved[9];\n+#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT\t0x2\n+#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA\t\t0x4\n+#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER\t0x8\n+\tu8\tenable_tcs;\n+\tu8\treserved[9];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);\n \n struct i40e_aqc_add_veb_completion {\n-\tu8     reserved[6];\n-\t__le16 switch_seid;\n+\tu8\treserved[6];\n+\t__le16\tswitch_seid;\n \t/* also encodes error if rc == ENOSPC; codes are the same as add_pv */\n-\t__le16 veb_seid;\n-#define I40E_AQC_VEB_ERR_FLAG_NO_VEB              0x1\n-#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED            0x2\n-#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER          0x4\n-#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY            0x8\n-\t__le16 statistic_index;\n-\t__le16 vebs_used;\n-\t__le16 vebs_free;\n+\t__le16\tveb_seid;\n+#define I40E_AQC_VEB_ERR_FLAG_NO_VEB\t\t0x1\n+#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED\t\t0x2\n+#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER\t0x4\n+#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY\t\t0x8\n+\t__le16\tstatistic_index;\n+\t__le16\tvebs_used;\n+\t__le16\tvebs_free;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);\n@@ -916,13 +916,13 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);\n  * uses i40e_aqc_switch_seid for the descriptor\n  */\n struct i40e_aqc_get_veb_parameters_completion {\n-\t__le16 seid;\n-\t__le16 switch_id;\n-\t__le16 veb_flags; /* only the first/last flags from 0x0230 is valid */\n-\t__le16 statistic_index;\n-\t__le16 vebs_used;\n-\t__le16 vebs_free;\n-\tu8     reserved[4];\n+\t__le16\tseid;\n+\t__le16\tswitch_id;\n+\t__le16\tveb_flags; /* only the first/last flags from 0x0230 is valid */\n+\t__le16\tstatistic_index;\n+\t__le16\tvebs_used;\n+\t__le16\tvebs_free;\n+\tu8\treserved[4];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);\n@@ -935,37 +935,37 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);\n \n /* used for the command for most vlan commands */\n struct i40e_aqc_macvlan {\n-\t__le16 num_addresses;\n-\t__le16 seid[3];\n-#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT  0\n-#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK   (0x3FF << \\\n+\t__le16\tnum_addresses;\n+\t__le16\tseid[3];\n+#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT\t0\n+#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK\t(0x3FF << \\\n \t\t\t\t\tI40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n-#define I40E_AQC_MACVLAN_CMD_SEID_VALID      0x8000\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+#define I40E_AQC_MACVLAN_CMD_SEID_VALID\t\t0x8000\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);\n \n /* indirect data for command and response */\n struct i40e_aqc_add_macvlan_element_data {\n-\tu8     mac_addr[6];\n-\t__le16 vlan_tag;\n-\t__le16 flags;\n-#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH     0x0001\n-#define I40E_AQC_MACVLAN_ADD_HASH_MATCH        0x0002\n-#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN       0x0004\n-#define I40E_AQC_MACVLAN_ADD_TO_QUEUE          0x0008\n-\t__le16 queue_number;\n-#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT  0\n-#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK   (0x7FF << \\\n+\tu8\tmac_addr[6];\n+\t__le16\tvlan_tag;\n+\t__le16\tflags;\n+#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH\t0x0001\n+#define I40E_AQC_MACVLAN_ADD_HASH_MATCH\t\t0x0002\n+#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN\t0x0004\n+#define I40E_AQC_MACVLAN_ADD_TO_QUEUE\t\t0x0008\n+\t__le16\tqueue_number;\n+#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT\t0\n+#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK\t\t(0x7FF << \\\n \t\t\t\t\tI40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n \t/* response section */\n-\tu8     match_method;\n-#define I40E_AQC_MM_PERFECT_MATCH             0x01\n-#define I40E_AQC_MM_HASH_MATCH                0x02\n-#define I40E_AQC_MM_ERR_NO_RES                0xFF\n-\tu8     reserved1[3];\n+\tu8\tmatch_method;\n+#define I40E_AQC_MM_PERFECT_MATCH\t0x01\n+#define I40E_AQC_MM_HASH_MATCH\t\t0x02\n+#define I40E_AQC_MM_ERR_NO_RES\t\t0xFF\n+\tu8\treserved1[3];\n };\n \n struct i40e_aqc_add_remove_macvlan_completion {\n@@ -985,19 +985,19 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);\n  */\n \n struct i40e_aqc_remove_macvlan_element_data {\n-\tu8     mac_addr[6];\n-\t__le16 vlan_tag;\n-\tu8     flags;\n-#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH      0x01\n-#define I40E_AQC_MACVLAN_DEL_HASH_MATCH         0x02\n-#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN        0x08\n-#define I40E_AQC_MACVLAN_DEL_ALL_VSIS           0x10\n-\tu8     reserved[3];\n+\tu8\tmac_addr[6];\n+\t__le16\tvlan_tag;\n+\tu8\tflags;\n+#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH\t0x01\n+#define I40E_AQC_MACVLAN_DEL_HASH_MATCH\t\t0x02\n+#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN\t0x08\n+#define I40E_AQC_MACVLAN_DEL_ALL_VSIS\t\t0x10\n+\tu8\treserved[3];\n \t/* reply section */\n-\tu8     error_code;\n-#define I40E_AQC_REMOVE_MACVLAN_SUCCESS         0x0\n-#define I40E_AQC_REMOVE_MACVLAN_FAIL            0xFF\n-\tu8     reply_reserved[3];\n+\tu8\terror_code;\n+#define I40E_AQC_REMOVE_MACVLAN_SUCCESS\t\t0x0\n+#define I40E_AQC_REMOVE_MACVLAN_FAIL\t\t0xFF\n+\tu8\treply_reserved[3];\n };\n \n /* Add VLAN (indirect 0x0252)\n@@ -1005,59 +1005,58 @@ struct i40e_aqc_remove_macvlan_element_data {\n  * use the generic i40e_aqc_macvlan for the command\n  */\n struct i40e_aqc_add_remove_vlan_element_data {\n-\t__le16 vlan_tag;\n-\tu8     vlan_flags;\n+\t__le16\tvlan_tag;\n+\tu8\tvlan_flags;\n /* flags for add VLAN */\n-#define I40E_AQC_ADD_VLAN_LOCAL             0x1\n-#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT       1\n-#define I40E_AQC_ADD_PVLAN_TYPE_MASK        (0x3 << \\\n-\t\t\t\t\t\tI40E_AQC_ADD_PVLAN_TYPE_SHIFT)\n-#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR     0x0\n-#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY     0x2\n-#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY   0x4\n-#define I40E_AQC_VLAN_PTYPE_SHIFT           3\n-#define I40E_AQC_VLAN_PTYPE_MASK            (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)\n-#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI     0x0\n-#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI     0x8\n-#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI   0x10\n-#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI    0x18\n+#define I40E_AQC_ADD_VLAN_LOCAL\t\t\t0x1\n+#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT\t\t1\n+#define I40E_AQC_ADD_PVLAN_TYPE_MASK\t(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)\n+#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR\t\t0x0\n+#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY\t\t0x2\n+#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY\t0x4\n+#define I40E_AQC_VLAN_PTYPE_SHIFT\t\t3\n+#define I40E_AQC_VLAN_PTYPE_MASK\t(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)\n+#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI\t\t0x0\n+#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI\t\t0x8\n+#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI\t0x10\n+#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI\t0x18\n /* flags for remove VLAN */\n-#define I40E_AQC_REMOVE_VLAN_ALL            0x1\n-\tu8     reserved;\n-\tu8     result;\n+#define I40E_AQC_REMOVE_VLAN_ALL\t0x1\n+\tu8\treserved;\n+\tu8\tresult;\n /* flags for add VLAN */\n-#define I40E_AQC_ADD_VLAN_SUCCESS       0x0\n-#define I40E_AQC_ADD_VLAN_FAIL_REQUEST  0xFE\n-#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF\n+#define I40E_AQC_ADD_VLAN_SUCCESS\t0x0\n+#define I40E_AQC_ADD_VLAN_FAIL_REQUEST\t0xFE\n+#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE\t0xFF\n /* flags for remove VLAN */\n-#define I40E_AQC_REMOVE_VLAN_SUCCESS    0x0\n-#define I40E_AQC_REMOVE_VLAN_FAIL       0xFF\n-\tu8     reserved1[3];\n+#define I40E_AQC_REMOVE_VLAN_SUCCESS\t0x0\n+#define I40E_AQC_REMOVE_VLAN_FAIL\t0xFF\n+\tu8\treserved1[3];\n };\n \n struct i40e_aqc_add_remove_vlan_completion {\n-\tu8     reserved[4];\n-\t__le16 vlans_used;\n-\t__le16 vlans_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\treserved[4];\n+\t__le16\tvlans_used;\n+\t__le16\tvlans_free;\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n /* Set VSI Promiscuous Modes (direct 0x0254) */\n struct i40e_aqc_set_vsi_promiscuous_modes {\n-\t__le16 promiscuous_flags;\n-\t__le16 valid_flags;\n+\t__le16\tpromiscuous_flags;\n+\t__le16\tvalid_flags;\n /* flags used for both fields above */\n-#define I40E_AQC_SET_VSI_PROMISC_UNICAST     0x01\n-#define I40E_AQC_SET_VSI_PROMISC_MULTICAST   0x02\n-#define I40E_AQC_SET_VSI_PROMISC_BROADCAST   0x04\n-#define I40E_AQC_SET_VSI_DEFAULT             0x08\n-#define I40E_AQC_SET_VSI_PROMISC_VLAN        0x10\n-\t__le16 seid;\n-#define I40E_AQC_VSI_PROM_CMD_SEID_MASK      0x3FF\n-\t__le16 vlan_tag;\n-#define I40E_AQC_SET_VSI_VLAN_VALID          0x8000\n-\tu8     reserved[8];\n+#define I40E_AQC_SET_VSI_PROMISC_UNICAST\t0x01\n+#define I40E_AQC_SET_VSI_PROMISC_MULTICAST\t0x02\n+#define I40E_AQC_SET_VSI_PROMISC_BROADCAST\t0x04\n+#define I40E_AQC_SET_VSI_DEFAULT\t\t0x08\n+#define I40E_AQC_SET_VSI_PROMISC_VLAN\t\t0x10\n+\t__le16\tseid;\n+#define I40E_AQC_VSI_PROM_CMD_SEID_MASK\t\t0x3FF\n+\t__le16\tvlan_tag;\n+#define I40E_AQC_SET_VSI_VLAN_VALID\t\t0x8000\n+\tu8\treserved[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);\n@@ -1066,23 +1065,23 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);\n  * Uses generic i40e_aqc_add_remove_tag_completion for completion\n  */\n struct i40e_aqc_add_tag {\n-\t__le16 flags;\n-#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE     0x0001\n-\t__le16 seid;\n-#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT  0\n-#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK   (0x3FF << \\\n+\t__le16\tflags;\n+#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE\t\t0x0001\n+\t__le16\tseid;\n+#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT\t0\n+#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n \t\t\t\t\tI40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16 tag;\n-\t__le16 queue_number;\n-\tu8     reserved[8];\n+\t__le16\ttag;\n+\t__le16\tqueue_number;\n+\tu8\treserved[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);\n \n struct i40e_aqc_add_remove_tag_completion {\n-\tu8     reserved[12];\n-\t__le16 tags_used;\n-\t__le16 tags_free;\n+\tu8\treserved[12];\n+\t__le16\ttags_used;\n+\t__le16\ttags_free;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);\n@@ -1091,12 +1090,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);\n  * Uses generic i40e_aqc_add_remove_tag_completion for completion\n  */\n struct i40e_aqc_remove_tag {\n-\t__le16 seid;\n-#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT  0\n-#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \\\n+\t__le16\tseid;\n+#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT\t0\n+#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n \t\t\t\t\tI40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16 tag;\n-\tu8     reserved[12];\n+\t__le16\ttag;\n+\tu8\treserved[12];\n };\n \n /* Add multicast E-Tag (direct 0x0257)\n@@ -1104,22 +1103,22 @@ struct i40e_aqc_remove_tag {\n  * and no external data\n  */\n struct i40e_aqc_add_remove_mcast_etag {\n-\t__le16 pv_seid;\n-\t__le16 etag;\n-\tu8     num_unicast_etags;\n-\tu8     reserved[3];\n-\t__le32 addr_high;          /* address of array of 2-byte s-tags */\n-\t__le32 addr_low;\n+\t__le16\tpv_seid;\n+\t__le16\tetag;\n+\tu8\tnum_unicast_etags;\n+\tu8\treserved[3];\n+\t__le32\taddr_high;          /* address of array of 2-byte s-tags */\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);\n \n struct i40e_aqc_add_remove_mcast_etag_completion {\n-\tu8     reserved[4];\n-\t__le16 mcast_etags_used;\n-\t__le16 mcast_etags_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\treserved[4];\n+\t__le16\tmcast_etags_used;\n+\t__le16\tmcast_etags_free;\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n \n };\n \n@@ -1127,21 +1126,21 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);\n \n /* Update S/E-Tag (direct 0x0259) */\n struct i40e_aqc_update_tag {\n-\t__le16 seid;\n-#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT  0\n-#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \\\n+\t__le16\tseid;\n+#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT\t0\n+#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n \t\t\t\t\tI40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16 old_tag;\n-\t__le16 new_tag;\n-\tu8     reserved[10];\n+\t__le16\told_tag;\n+\t__le16\tnew_tag;\n+\tu8\treserved[10];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);\n \n struct i40e_aqc_update_tag_completion {\n-\tu8     reserved[12];\n-\t__le16 tags_used;\n-\t__le16 tags_free;\n+\tu8\treserved[12];\n+\t__le16\ttags_used;\n+\t__le16\ttags_free;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);\n@@ -1152,30 +1151,30 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);\n  * and the generic direct completion structure\n  */\n struct i40e_aqc_add_remove_control_packet_filter {\n-\tu8     mac[6];\n-\t__le16 etype;\n-\t__le16 flags;\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC    0x0001\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP          0x0002\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE      0x0004\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX            0x0008\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX            0x0000\n-\t__le16 seid;\n-#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT  0\n-#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK   (0x3FF << \\\n+\tu8\tmac[6];\n+\t__le16\tetype;\n+\t__le16\tflags;\n+#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC\t0x0001\n+#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP\t\t0x0002\n+#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE\t0x0004\n+#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX\t\t0x0008\n+#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX\t\t0x0000\n+\t__le16\tseid;\n+#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT\t0\n+#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK\t(0x3FF << \\\n \t\t\t\tI40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)\n-\t__le16 queue;\n-\tu8     reserved[2];\n+\t__le16\tqueue;\n+\tu8\treserved[2];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);\n \n struct i40e_aqc_add_remove_control_packet_filter_completion {\n-\t__le16 mac_etype_used;\n-\t__le16 etype_used;\n-\t__le16 mac_etype_free;\n-\t__le16 etype_free;\n-\tu8     reserved[8];\n+\t__le16\tmac_etype_used;\n+\t__le16\tetype_used;\n+\t__le16\tmac_etype_free;\n+\t__le16\tetype_free;\n+\tu8\treserved[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);\n@@ -1186,23 +1185,23 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);\n  * and the generic indirect completion structure\n  */\n struct i40e_aqc_add_remove_cloud_filters {\n-\tu8     num_filters;\n-\tu8     reserved;\n-\t__le16 seid;\n-#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT  0\n-#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK   (0x3FF << \\\n+\tu8\tnum_filters;\n+\tu8\treserved;\n+\t__le16\tseid;\n+#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT\t0\n+#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK\t(0x3FF << \\\n \t\t\t\t\tI40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)\n-\tu8     reserved2[4];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\treserved2[4];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);\n \n struct i40e_aqc_add_remove_cloud_filters_element_data {\n-\tu8     outer_mac[6];\n-\tu8     inner_mac[6];\n-\t__le16 inner_vlan;\n+\tu8\touter_mac[6];\n+\tu8\tinner_mac[6];\n+\t__le16\tinner_vlan;\n \tunion {\n \t\tstruct {\n \t\t\tu8 reserved[12];\n@@ -1212,49 +1211,49 @@ struct i40e_aqc_add_remove_cloud_filters_element_data {\n \t\t\tu8 data[16];\n \t\t} v6;\n \t} ipaddr;\n-\t__le16 flags;\n-#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT                 0\n-#define I40E_AQC_ADD_CLOUD_FILTER_MASK                  (0x3F << \\\n+\t__le16\tflags;\n+#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT\t\t\t0\n+#define I40E_AQC_ADD_CLOUD_FILTER_MASK\t\t\t(0x3F << \\\n \t\t\t\t\tI40E_AQC_ADD_CLOUD_FILTER_SHIFT)\n /* 0x0000 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_OIP                   0x0001\n+#define I40E_AQC_ADD_CLOUD_FILTER_OIP\t\t\t0x0001\n /* 0x0002 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN            0x0003\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID     0x0004\n+#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN\t\t0x0003\n+#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID\t0x0004\n /* 0x0005 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID           0x0006\n+#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID\t\t0x0006\n /* 0x0007 reserved */\n /* 0x0008 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_OMAC                  0x0009\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC                  0x000A\n-#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC      0x000B\n-#define I40E_AQC_ADD_CLOUD_FILTER_IIP                   0x000C\n-\n-#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE               0x0080\n-#define I40E_AQC_ADD_CLOUD_VNK_SHIFT                    6\n-#define I40E_AQC_ADD_CLOUD_VNK_MASK                     0x00C0\n-#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4                   0\n-#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6                   0x0100\n-\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT               9\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK                0x1E00\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN               0\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC          1\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE                 2\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP                  3\n-\n-\t__le32 tenant_id;\n-\tu8     reserved[4];\n-\t__le16 queue_number;\n-#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT                  0\n-#define I40E_AQC_ADD_CLOUD_QUEUE_MASK                   (0x3F << \\\n-\t\t\t\t\tI40E_AQC_ADD_CLOUD_QUEUE_SHIFT)\n-\tu8     reserved2[14];\n+#define I40E_AQC_ADD_CLOUD_FILTER_OMAC\t\t\t0x0009\n+#define I40E_AQC_ADD_CLOUD_FILTER_IMAC\t\t\t0x000A\n+#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC\t0x000B\n+#define I40E_AQC_ADD_CLOUD_FILTER_IIP\t\t\t0x000C\n+\n+#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE\t\t0x0080\n+#define I40E_AQC_ADD_CLOUD_VNK_SHIFT\t\t\t6\n+#define I40E_AQC_ADD_CLOUD_VNK_MASK\t\t\t0x00C0\n+#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4\t\t\t0\n+#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6\t\t\t0x0100\n+\n+#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT\t\t9\n+#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK\t\t0x1E00\n+#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN\t\t0\n+#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC\t\t1\n+#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE\t\t\t2\n+#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP\t\t\t3\n+\n+\t__le32\ttenant_id;\n+\tu8\treserved[4];\n+\t__le16\tqueue_number;\n+#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT\t\t0\n+#define I40E_AQC_ADD_CLOUD_QUEUE_MASK\t\t(0x3F << \\\n+\t\t\t\t\t\t I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)\n+\tu8\treserved2[14];\n \t/* response section */\n-\tu8     allocation_result;\n-#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS         0x0\n-#define I40E_AQC_ADD_CLOUD_FILTER_FAIL            0xFF\n-\tu8     response_reserved[7];\n+\tu8\tallocation_result;\n+#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS\t0x0\n+#define I40E_AQC_ADD_CLOUD_FILTER_FAIL\t\t0xFF\n+\tu8\tresponse_reserved[7];\n };\n \n struct i40e_aqc_remove_cloud_filters_completion {\n@@ -1276,14 +1275,14 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);\n struct i40e_aqc_add_delete_mirror_rule {\n \t__le16 seid;\n \t__le16 rule_type;\n-#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT            0\n-#define I40E_AQC_MIRROR_RULE_TYPE_MASK             (0x7 << \\\n+#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT\t\t0\n+#define I40E_AQC_MIRROR_RULE_TYPE_MASK\t\t(0x7 << \\\n \t\t\t\t\t\tI40E_AQC_MIRROR_RULE_TYPE_SHIFT)\n-#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS    1\n-#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS     2\n-#define I40E_AQC_MIRROR_RULE_TYPE_VLAN             3\n-#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS      4\n-#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS       5\n+#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS\t1\n+#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS\t2\n+#define I40E_AQC_MIRROR_RULE_TYPE_VLAN\t\t3\n+#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS\t4\n+#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS\t5\n \t__le16 num_entries;\n \t__le16 destination;  /* VSI for add, rule id for delete */\n \t__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */\n@@ -1293,12 +1292,12 @@ struct i40e_aqc_add_delete_mirror_rule {\n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);\n \n struct i40e_aqc_add_delete_mirror_rule_completion {\n-\tu8     reserved[2];\n-\t__le16 rule_id;  /* only used on add */\n-\t__le16 mirror_rules_used;\n-\t__le16 mirror_rules_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\treserved[2];\n+\t__le16\trule_id;  /* only used on add */\n+\t__le16\tmirror_rules_used;\n+\t__le16\tmirror_rules_free;\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);\n@@ -1309,11 +1308,11 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);\n  *    the command and response use the same descriptor structure\n  */\n struct i40e_aqc_pfc_ignore {\n-\tu8     tc_bitmap;\n-\tu8     command_flags; /* unused on response */\n-#define I40E_AQC_PFC_IGNORE_SET    0x80\n-#define I40E_AQC_PFC_IGNORE_CLEAR  0x0\n-\tu8     reserved[14];\n+\tu8\ttc_bitmap;\n+\tu8\tcommand_flags; /* unused on response */\n+#define I40E_AQC_PFC_IGNORE_SET\t\t0x80\n+#define I40E_AQC_PFC_IGNORE_CLEAR\t0x0\n+\tu8\treserved[14];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);\n@@ -1328,10 +1327,10 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);\n  * this generic struct to pass the SEID in param0\n  */\n struct i40e_aqc_tx_sched_ind {\n-\t__le16 vsi_seid;\n-\tu8     reserved[6];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\t__le16\tvsi_seid;\n+\tu8\treserved[6];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);\n@@ -1343,12 +1342,12 @@ struct i40e_aqc_qs_handles_resp {\n \n /* Configure VSI BW limits (direct 0x0400) */\n struct i40e_aqc_configure_vsi_bw_limit {\n-\t__le16 vsi_seid;\n-\tu8     reserved[2];\n-\t__le16 credit;\n-\tu8     reserved1[2];\n-\tu8     max_credit; /* 0-3, limit = 2^max */\n-\tu8     reserved2[7];\n+\t__le16\tvsi_seid;\n+\tu8\treserved[2];\n+\t__le16\tcredit;\n+\tu8\treserved1[2];\n+\tu8\tmax_credit; /* 0-3, limit = 2^max */\n+\tu8\treserved2[7];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);\n@@ -1357,58 +1356,58 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);\n  *    responds with i40e_aqc_qs_handles_resp\n  */\n struct i40e_aqc_configure_vsi_ets_sla_bw_data {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[15];\n-\t__le16 tc_bw_credits[8]; /* FW writesback QS handles here */\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[15];\n+\t__le16\ttc_bw_credits[8]; /* FW writesback QS handles here */\n \n \t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16 tc_bw_max[2];\n-\tu8     reserved1[28];\n+\t__le16\ttc_bw_max[2];\n+\tu8\treserved1[28];\n };\n \n /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)\n  *    responds with i40e_aqc_qs_handles_resp\n  */\n struct i40e_aqc_configure_vsi_tc_bw_data {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[3];\n-\tu8     tc_bw_credits[8];\n-\tu8     reserved1[4];\n-\t__le16 qs_handles[8];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[3];\n+\tu8\ttc_bw_credits[8];\n+\tu8\treserved1[4];\n+\t__le16\tqs_handles[8];\n };\n \n /* Query vsi bw configuration (indirect 0x0408) */\n struct i40e_aqc_query_vsi_bw_config_resp {\n-\tu8     tc_valid_bits;\n-\tu8     tc_suspended_bits;\n-\tu8     reserved[14];\n-\t__le16 qs_handles[8];\n-\tu8     reserved1[4];\n-\t__le16 port_bw_limit;\n-\tu8     reserved2[2];\n-\tu8     max_bw; /* 0-3, limit = 2^max */\n-\tu8     reserved3[23];\n+\tu8\ttc_valid_bits;\n+\tu8\ttc_suspended_bits;\n+\tu8\treserved[14];\n+\t__le16\tqs_handles[8];\n+\tu8\treserved1[4];\n+\t__le16\tport_bw_limit;\n+\tu8\treserved2[2];\n+\tu8\tmax_bw; /* 0-3, limit = 2^max */\n+\tu8\treserved3[23];\n };\n \n /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */\n struct i40e_aqc_query_vsi_ets_sla_config_resp {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[3];\n-\tu8     share_credits[8];\n-\t__le16 credits[8];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[3];\n+\tu8\tshare_credits[8];\n+\t__le16\tcredits[8];\n \n \t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16 tc_bw_max[2];\n+\t__le16\ttc_bw_max[2];\n };\n \n /* Configure Switching Component Bandwidth Limit (direct 0x0410) */\n struct i40e_aqc_configure_switching_comp_bw_limit {\n-\t__le16 seid;\n-\tu8     reserved[2];\n-\t__le16 credit;\n-\tu8     reserved1[2];\n-\tu8     max_bw; /* 0-3, limit = 2^max */\n-\tu8     reserved2[7];\n+\t__le16\tseid;\n+\tu8\treserved[2];\n+\t__le16\tcredit;\n+\tu8\treserved1[2];\n+\tu8\tmax_bw; /* 0-3, limit = 2^max */\n+\tu8\treserved2[7];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);\n@@ -1418,75 +1417,75 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);\n  * Disable Physical Port ETS (indirect 0x0415)\n  */\n struct i40e_aqc_configure_switching_comp_ets_data {\n-\tu8     reserved[4];\n-\tu8     tc_valid_bits;\n-\tu8     seepage;\n-#define I40E_AQ_ETS_SEEPAGE_EN_MASK     0x1\n-\tu8     tc_strict_priority_flags;\n-\tu8     reserved1[17];\n-\tu8     tc_bw_share_credits[8];\n-\tu8     reserved2[96];\n+\tu8\treserved[4];\n+\tu8\ttc_valid_bits;\n+\tu8\tseepage;\n+#define I40E_AQ_ETS_SEEPAGE_EN_MASK\t0x1\n+\tu8\ttc_strict_priority_flags;\n+\tu8\treserved1[17];\n+\tu8\ttc_bw_share_credits[8];\n+\tu8\treserved2[96];\n };\n \n /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */\n struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[15];\n-\t__le16 tc_bw_credit[8];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[15];\n+\t__le16\ttc_bw_credit[8];\n \n \t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16 tc_bw_max[2];\n-\tu8     reserved1[28];\n+\t__le16\ttc_bw_max[2];\n+\tu8\treserved1[28];\n };\n \n /* Configure Switching Component Bandwidth Allocation per Tc\n  * (indirect 0x0417)\n  */\n struct i40e_aqc_configure_switching_comp_bw_config_data {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[2];\n-\tu8     absolute_credits; /* bool */\n-\tu8     tc_bw_share_credits[8];\n-\tu8     reserved1[20];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[2];\n+\tu8\tabsolute_credits; /* bool */\n+\tu8\ttc_bw_share_credits[8];\n+\tu8\treserved1[20];\n };\n \n /* Query Switching Component Configuration (indirect 0x0418) */\n struct i40e_aqc_query_switching_comp_ets_config_resp {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[35];\n-\t__le16 port_bw_limit;\n-\tu8     reserved1[2];\n-\tu8     tc_bw_max; /* 0-3, limit = 2^max */\n-\tu8     reserved2[23];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[35];\n+\t__le16\tport_bw_limit;\n+\tu8\treserved1[2];\n+\tu8\ttc_bw_max; /* 0-3, limit = 2^max */\n+\tu8\treserved2[23];\n };\n \n /* Query PhysicalPort ETS Configuration (indirect 0x0419) */\n struct i40e_aqc_query_port_ets_config_resp {\n-\tu8     reserved[4];\n-\tu8     tc_valid_bits;\n-\tu8     reserved1;\n-\tu8     tc_strict_priority_bits;\n-\tu8     reserved2;\n-\tu8     tc_bw_share_credits[8];\n-\t__le16 tc_bw_limits[8];\n+\tu8\treserved[4];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved1;\n+\tu8\ttc_strict_priority_bits;\n+\tu8\treserved2;\n+\tu8\ttc_bw_share_credits[8];\n+\t__le16\ttc_bw_limits[8];\n \n \t/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */\n-\t__le16 tc_bw_max[2];\n-\tu8     reserved3[32];\n+\t__le16\ttc_bw_max[2];\n+\tu8\treserved3[32];\n };\n \n /* Query Switching Component Bandwidth Allocation per Traffic Type\n  * (indirect 0x041A)\n  */\n struct i40e_aqc_query_switching_comp_bw_config_resp {\n-\tu8     tc_valid_bits;\n-\tu8     reserved[2];\n-\tu8     absolute_credits_enable; /* bool */\n-\tu8     tc_bw_share_credits[8];\n-\t__le16 tc_bw_limits[8];\n+\tu8\ttc_valid_bits;\n+\tu8\treserved[2];\n+\tu8\tabsolute_credits_enable; /* bool */\n+\tu8\ttc_bw_share_credits[8];\n+\t__le16\ttc_bw_limits[8];\n \n \t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16 tc_bw_max[2];\n+\t__le16\ttc_bw_max[2];\n };\n \n /* Suspend/resume port TX traffic\n@@ -1497,37 +1496,37 @@ struct i40e_aqc_query_switching_comp_bw_config_resp {\n  * (indirect 0x041D)\n  */\n struct i40e_aqc_configure_partition_bw_data {\n-\t__le16 pf_valid_bits;\n-\tu8     min_bw[16];      /* guaranteed bandwidth */\n-\tu8     max_bw[16];      /* bandwidth limit */\n+\t__le16\tpf_valid_bits;\n+\tu8\tmin_bw[16];      /* guaranteed bandwidth */\n+\tu8\tmax_bw[16];      /* bandwidth limit */\n };\n \n /* Get and set the active HMC resource profile and status.\n  * (direct 0x0500) and (direct 0x0501)\n  */\n struct i40e_aq_get_set_hmc_resource_profile {\n-\tu8     pm_profile;\n-\tu8     pe_vf_enabled;\n-\tu8     reserved[14];\n+\tu8\tpm_profile;\n+\tu8\tpe_vf_enabled;\n+\tu8\treserved[14];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);\n \n enum i40e_aq_hmc_profile {\n \t/* I40E_HMC_PROFILE_NO_CHANGE    = 0, reserved */\n-\tI40E_HMC_PROFILE_DEFAULT     = 1,\n-\tI40E_HMC_PROFILE_FAVOR_VF    = 2,\n-\tI40E_HMC_PROFILE_EQUAL       = 3,\n+\tI40E_HMC_PROFILE_DEFAULT\t= 1,\n+\tI40E_HMC_PROFILE_FAVOR_VF\t= 2,\n+\tI40E_HMC_PROFILE_EQUAL\t\t= 3,\n };\n \n-#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK       0xF\n-#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK    0x3F\n+#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK\t0xF\n+#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK\t0x3F\n \n /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */\n \n /* set in param0 for get phy abilities to report qualified modules */\n-#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES  0x0001\n-#define I40E_AQ_PHY_REPORT_INITIAL_VALUES     0x0002\n+#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES\t0x0001\n+#define I40E_AQ_PHY_REPORT_INITIAL_VALUES\t0x0002\n \n enum i40e_aq_phy_type {\n \tI40E_PHY_TYPE_SGMII\t\t\t= 0x0,\n@@ -1585,147 +1584,147 @@ struct i40e_aqc_module_desc {\n };\n \n struct i40e_aq_get_phy_abilities_resp {\n-\t__le32 phy_type;       /* bitmap using the above enum for offsets */\n-\tu8     link_speed;     /* bitmap using the above enum bit patterns */\n-\tu8     abilities;\n-#define I40E_AQ_PHY_FLAG_PAUSE_TX         0x01\n-#define I40E_AQ_PHY_FLAG_PAUSE_RX         0x02\n-#define I40E_AQ_PHY_FLAG_LOW_POWER        0x04\n-#define I40E_AQ_PHY_LINK_ENABLED\t\t  0x08\n-#define I40E_AQ_PHY_AN_ENABLED\t\t\t  0x10\n-#define I40E_AQ_PHY_FLAG_MODULE_QUAL      0x20\n-\t__le16 eee_capability;\n-#define I40E_AQ_EEE_100BASE_TX       0x0002\n-#define I40E_AQ_EEE_1000BASE_T       0x0004\n-#define I40E_AQ_EEE_10GBASE_T        0x0008\n-#define I40E_AQ_EEE_1000BASE_KX      0x0010\n-#define I40E_AQ_EEE_10GBASE_KX4      0x0020\n-#define I40E_AQ_EEE_10GBASE_KR       0x0040\n-\t__le32 eeer_val;\n-\tu8     d3_lpan;\n-#define I40E_AQ_SET_PHY_D3_LPAN_ENA  0x01\n-\tu8     reserved[3];\n-\tu8     phy_id[4];\n-\tu8     module_type[3];\n-\tu8     qualified_module_count;\n-#define I40E_AQ_PHY_MAX_QMS          16\n-\tstruct i40e_aqc_module_desc  qualified_module[I40E_AQ_PHY_MAX_QMS];\n+\t__le32\tphy_type;       /* bitmap using the above enum for offsets */\n+\tu8\tlink_speed;     /* bitmap using the above enum bit patterns */\n+\tu8\tabilities;\n+#define I40E_AQ_PHY_FLAG_PAUSE_TX\t0x01\n+#define I40E_AQ_PHY_FLAG_PAUSE_RX\t0x02\n+#define I40E_AQ_PHY_FLAG_LOW_POWER\t0x04\n+#define I40E_AQ_PHY_LINK_ENABLED\t0x08\n+#define I40E_AQ_PHY_AN_ENABLED\t\t0x10\n+#define I40E_AQ_PHY_FLAG_MODULE_QUAL\t0x20\n+\t__le16\teee_capability;\n+#define I40E_AQ_EEE_100BASE_TX\t\t0x0002\n+#define I40E_AQ_EEE_1000BASE_T\t\t0x0004\n+#define I40E_AQ_EEE_10GBASE_T\t\t0x0008\n+#define I40E_AQ_EEE_1000BASE_KX\t\t0x0010\n+#define I40E_AQ_EEE_10GBASE_KX4\t\t0x0020\n+#define I40E_AQ_EEE_10GBASE_KR\t\t0x0040\n+\t__le32\teeer_val;\n+\tu8\td3_lpan;\n+#define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n+\tu8\treserved[3];\n+\tu8\tphy_id[4];\n+\tu8\tmodule_type[3];\n+\tu8\tqualified_module_count;\n+#define I40E_AQ_PHY_MAX_QMS\t\t16\n+\tstruct i40e_aqc_module_desc\tqualified_module[I40E_AQ_PHY_MAX_QMS];\n };\n \n /* Set PHY Config (direct 0x0601) */\n struct i40e_aq_set_phy_config { /* same bits as above in all */\n-\t__le32 phy_type;\n-\tu8     link_speed;\n-\tu8     abilities;\n+\t__le32\tphy_type;\n+\tu8\tlink_speed;\n+\tu8\tabilities;\n /* bits 0-2 use the values from get_phy_abilities_resp */\n #define I40E_AQ_PHY_ENABLE_LINK\t\t0x08\n #define I40E_AQ_PHY_ENABLE_AN\t\t0x10\n #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK\t0x20\n-\t__le16 eee_capability;\n-\t__le32 eeer;\n-\tu8     low_power_ctrl;\n-\tu8     reserved[3];\n+\t__le16\teee_capability;\n+\t__le32\teeer;\n+\tu8\tlow_power_ctrl;\n+\tu8\treserved[3];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n \n /* Set MAC Config command data structure (direct 0x0603) */\n struct i40e_aq_set_mac_config {\n-\t__le16 max_frame_size;\n-\tu8     params;\n-#define I40E_AQ_SET_MAC_CONFIG_CRC_EN           0x04\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK      0x78\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT     3\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE      0x0\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX   0xF\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX   0x9\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX   0x8\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX   0x7\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX   0x6\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX   0x5\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX   0x4\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX   0x3\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX   0x2\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX   0x1\n-\tu8     tx_timer_priority; /* bitmap */\n-\t__le16 tx_timer_value;\n-\t__le16 fc_refresh_threshold;\n-\tu8     reserved[8];\n+\t__le16\tmax_frame_size;\n+\tu8\tparams;\n+#define I40E_AQ_SET_MAC_CONFIG_CRC_EN\t\t0x04\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK\t0x78\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT\t3\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE\t0x0\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX\t0xF\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX\t0x9\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX\t0x8\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX\t0x7\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX\t0x6\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX\t0x5\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX\t0x4\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX\t0x3\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX\t0x2\n+#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX\t0x1\n+\tu8\ttx_timer_priority; /* bitmap */\n+\t__le16\ttx_timer_value;\n+\t__le16\tfc_refresh_threshold;\n+\tu8\treserved[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);\n \n /* Restart Auto-Negotiation (direct 0x605) */\n struct i40e_aqc_set_link_restart_an {\n-\tu8     command;\n-#define I40E_AQ_PHY_RESTART_AN  0x02\n-#define I40E_AQ_PHY_LINK_ENABLE 0x04\n-\tu8     reserved[15];\n+\tu8\tcommand;\n+#define I40E_AQ_PHY_RESTART_AN\t0x02\n+#define I40E_AQ_PHY_LINK_ENABLE\t0x04\n+\tu8\treserved[15];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);\n \n /* Get Link Status cmd & response data structure (direct 0x0607) */\n struct i40e_aqc_get_link_status {\n-\t__le16 command_flags; /* only field set on command */\n-#define I40E_AQ_LSE_MASK             0x3\n-#define I40E_AQ_LSE_NOP              0x0\n-#define I40E_AQ_LSE_DISABLE          0x2\n-#define I40E_AQ_LSE_ENABLE           0x3\n+\t__le16\tcommand_flags; /* only field set on command */\n+#define I40E_AQ_LSE_MASK\t\t0x3\n+#define I40E_AQ_LSE_NOP\t\t\t0x0\n+#define I40E_AQ_LSE_DISABLE\t\t0x2\n+#define I40E_AQ_LSE_ENABLE\t\t0x3\n /* only response uses this flag */\n-#define I40E_AQ_LSE_IS_ENABLED       0x1\n-\tu8     phy_type;    /* i40e_aq_phy_type   */\n-\tu8     link_speed;  /* i40e_aq_link_speed */\n-\tu8     link_info;\n-#define I40E_AQ_LINK_UP              0x01\n-#define I40E_AQ_LINK_FAULT           0x02\n-#define I40E_AQ_LINK_FAULT_TX        0x04\n-#define I40E_AQ_LINK_FAULT_RX        0x08\n-#define I40E_AQ_LINK_FAULT_REMOTE    0x10\n-#define I40E_AQ_MEDIA_AVAILABLE      0x40\n-#define I40E_AQ_SIGNAL_DETECT        0x80\n-\tu8     an_info;\n-#define I40E_AQ_AN_COMPLETED         0x01\n-#define I40E_AQ_LP_AN_ABILITY        0x02\n-#define I40E_AQ_PD_FAULT             0x04\n-#define I40E_AQ_FEC_EN               0x08\n-#define I40E_AQ_PHY_LOW_POWER        0x10\n-#define I40E_AQ_LINK_PAUSE_TX        0x20\n-#define I40E_AQ_LINK_PAUSE_RX        0x40\n-#define I40E_AQ_QUALIFIED_MODULE     0x80\n-\tu8     ext_info;\n-#define I40E_AQ_LINK_PHY_TEMP_ALARM  0x01\n-#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02\n-#define I40E_AQ_LINK_TX_SHIFT        0x02\n-#define I40E_AQ_LINK_TX_MASK         (0x03 << I40E_AQ_LINK_TX_SHIFT)\n-#define I40E_AQ_LINK_TX_ACTIVE       0x00\n-#define I40E_AQ_LINK_TX_DRAINED      0x01\n-#define I40E_AQ_LINK_TX_FLUSHED      0x03\n-#define I40E_AQ_LINK_FORCED_40G      0x10\n-\tu8     loopback;         /* use defines from i40e_aqc_set_lb_mode */\n-\t__le16 max_frame_size;\n-\tu8     config;\n-#define I40E_AQ_CONFIG_CRC_ENA       0x04\n-#define I40E_AQ_CONFIG_PACING_MASK   0x78\n-\tu8     reserved[5];\n+#define I40E_AQ_LSE_IS_ENABLED\t\t0x1\n+\tu8\tphy_type;    /* i40e_aq_phy_type   */\n+\tu8\tlink_speed;  /* i40e_aq_link_speed */\n+\tu8\tlink_info;\n+#define I40E_AQ_LINK_UP\t\t\t0x01\n+#define I40E_AQ_LINK_FAULT\t\t0x02\n+#define I40E_AQ_LINK_FAULT_TX\t\t0x04\n+#define I40E_AQ_LINK_FAULT_RX\t\t0x08\n+#define I40E_AQ_LINK_FAULT_REMOTE\t0x10\n+#define I40E_AQ_MEDIA_AVAILABLE\t\t0x40\n+#define I40E_AQ_SIGNAL_DETECT\t\t0x80\n+\tu8\tan_info;\n+#define I40E_AQ_AN_COMPLETED\t\t0x01\n+#define I40E_AQ_LP_AN_ABILITY\t\t0x02\n+#define I40E_AQ_PD_FAULT\t\t0x04\n+#define I40E_AQ_FEC_EN\t\t\t0x08\n+#define I40E_AQ_PHY_LOW_POWER\t\t0x10\n+#define I40E_AQ_LINK_PAUSE_TX\t\t0x20\n+#define I40E_AQ_LINK_PAUSE_RX\t\t0x40\n+#define I40E_AQ_QUALIFIED_MODULE\t0x80\n+\tu8\text_info;\n+#define I40E_AQ_LINK_PHY_TEMP_ALARM\t0x01\n+#define I40E_AQ_LINK_XCESSIVE_ERRORS\t0x02\n+#define I40E_AQ_LINK_TX_SHIFT\t\t0x02\n+#define I40E_AQ_LINK_TX_MASK\t\t(0x03 << I40E_AQ_LINK_TX_SHIFT)\n+#define I40E_AQ_LINK_TX_ACTIVE\t\t0x00\n+#define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n+#define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n+#define I40E_AQ_LINK_FORCED_40G\t\t0x10\n+\tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n+\t__le16\tmax_frame_size;\n+\tu8\tconfig;\n+#define I40E_AQ_CONFIG_CRC_ENA\t\t0x04\n+#define I40E_AQ_CONFIG_PACING_MASK\t0x78\n+\tu8\treserved[5];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);\n \n /* Set event mask command (direct 0x613) */\n struct i40e_aqc_set_phy_int_mask {\n-\tu8     reserved[8];\n-\t__le16 event_mask;\n-#define I40E_AQ_EVENT_LINK_UPDOWN       0x0002\n-#define I40E_AQ_EVENT_MEDIA_NA          0x0004\n-#define I40E_AQ_EVENT_LINK_FAULT        0x0008\n-#define I40E_AQ_EVENT_PHY_TEMP_ALARM    0x0010\n-#define I40E_AQ_EVENT_EXCESSIVE_ERRORS  0x0020\n-#define I40E_AQ_EVENT_SIGNAL_DETECT     0x0040\n-#define I40E_AQ_EVENT_AN_COMPLETED      0x0080\n-#define I40E_AQ_EVENT_MODULE_QUAL_FAIL  0x0100\n-#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200\n-\tu8     reserved1[6];\n+\tu8\treserved[8];\n+\t__le16\tevent_mask;\n+#define I40E_AQ_EVENT_LINK_UPDOWN\t0x0002\n+#define I40E_AQ_EVENT_MEDIA_NA\t\t0x0004\n+#define I40E_AQ_EVENT_LINK_FAULT\t0x0008\n+#define I40E_AQ_EVENT_PHY_TEMP_ALARM\t0x0010\n+#define I40E_AQ_EVENT_EXCESSIVE_ERRORS\t0x0020\n+#define I40E_AQ_EVENT_SIGNAL_DETECT\t0x0040\n+#define I40E_AQ_EVENT_AN_COMPLETED\t0x0080\n+#define I40E_AQ_EVENT_MODULE_QUAL_FAIL\t0x0100\n+#define I40E_AQ_EVENT_PORT_TX_SUSPENDED\t0x0200\n+\tu8\treserved1[6];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);\n@@ -1735,43 +1734,44 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);\n  * Get Link Partner AN advt register (direct 0x0616)\n  */\n struct i40e_aqc_an_advt_reg {\n-\t__le32 local_an_reg0;\n-\t__le16 local_an_reg1;\n-\tu8     reserved[10];\n+\t__le32\tlocal_an_reg0;\n+\t__le16\tlocal_an_reg1;\n+\tu8\treserved[10];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);\n \n /* Set Loopback mode (0x0618) */\n struct i40e_aqc_set_lb_mode {\n-\t__le16 lb_mode;\n-#define I40E_AQ_LB_PHY_LOCAL   0x01\n-#define I40E_AQ_LB_PHY_REMOTE  0x02\n-#define I40E_AQ_LB_MAC_LOCAL   0x04\n-\tu8     reserved[14];\n+\t__le16\tlb_mode;\n+#define I40E_AQ_LB_PHY_LOCAL\t0x01\n+#define I40E_AQ_LB_PHY_REMOTE\t0x02\n+#define I40E_AQ_LB_MAC_LOCAL\t0x04\n+\tu8\treserved[14];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);\n \n /* Set PHY Debug command (0x0622) */\n struct i40e_aqc_set_phy_debug {\n-\tu8     command_flags;\n+\tu8\tcommand_flags;\n #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL\t0x02\n #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT\t2\n-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK\t(0x03 << I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)\n+#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK\t(0x03 << \\\n+\t\t\t\t\tI40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)\n #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE\t0x00\n #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD\t0x01\n #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT\t0x02\n #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW\t0x10\n-\tu8     reserved[15];\n+\tu8\treserved[15];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);\n \n enum i40e_aq_phy_reg_type {\n-\tI40E_AQC_PHY_REG_INTERNAL         = 0x1,\n-\tI40E_AQC_PHY_REG_EXERNAL_BASET    = 0x2,\n-\tI40E_AQC_PHY_REG_EXERNAL_MODULE   = 0x3\n+\tI40E_AQC_PHY_REG_INTERNAL\t= 0x1,\n+\tI40E_AQC_PHY_REG_EXERNAL_BASET\t= 0x2,\n+\tI40E_AQC_PHY_REG_EXERNAL_MODULE\t= 0x3\n };\n \n /* NVM Read command (indirect 0x0701)\n@@ -1779,40 +1779,40 @@ enum i40e_aq_phy_reg_type {\n  * NVM Update commands (indirect 0x0703)\n  */\n struct i40e_aqc_nvm_update {\n-\tu8     command_flags;\n-#define I40E_AQ_NVM_LAST_CMD    0x01\n-#define I40E_AQ_NVM_FLASH_ONLY  0x80\n-\tu8     module_pointer;\n-\t__le16 length;\n-\t__le32 offset;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\tcommand_flags;\n+#define I40E_AQ_NVM_LAST_CMD\t0x01\n+#define I40E_AQ_NVM_FLASH_ONLY\t0x80\n+\tu8\tmodule_pointer;\n+\t__le16\tlength;\n+\t__le32\toffset;\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);\n \n /* NVM Config Read (indirect 0x0704) */\n struct i40e_aqc_nvm_config_read {\n-\t__le16 cmd_flags;\n+\t__le16\tcmd_flags;\n #define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK\t1\n #define ANVM_READ_SINGLE_FEATURE\t\t0\n #define ANVM_READ_MULTIPLE_FEATURES\t\t1\n-\t__le16 element_count;\n-\t__le16 element_id;\t\t/* Feature/field ID */\n-\tu8     reserved[2];\n-\t__le32 address_high;\n-\t__le32 address_low;\n+\t__le16\telement_count;\n+\t__le16\telement_id; /* Feature/field ID */\n+\tu8\treserved[2];\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);\n \n /* NVM Config Write (indirect 0x0705) */\n struct i40e_aqc_nvm_config_write {\n-\t__le16 cmd_flags;\n-\t__le16 element_count;\n-\tu8     reserved[4];\n-\t__le32 address_high;\n-\t__le32 address_low;\n+\t__le16\tcmd_flags;\n+\t__le16\telement_count;\n+\tu8\treserved[4];\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);\n@@ -1837,10 +1837,10 @@ struct i40e_aqc_nvm_config_data_immediate_field {\n  * Send to Peer PF command (indirect 0x0803)\n  */\n struct i40e_aqc_pf_vf_message {\n-\t__le32 id;\n-\tu8     reserved[4];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\t__le32\tid;\n+\tu8\treserved[4];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);\n@@ -1876,22 +1876,22 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);\n  * uses i40e_aq_desc\n  */\n struct i40e_aqc_alternate_write_done {\n-\t__le16 cmd_flags;\n+\t__le16\tcmd_flags;\n #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK\t1\n #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY\t0\n #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI\t1\n #define I40E_AQ_ALTERNATE_RESET_NEEDED\t\t2\n-\tu8     reserved[14];\n+\tu8\treserved[14];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);\n \n /* Set OEM mode (direct 0x0905) */\n struct i40e_aqc_alternate_set_mode {\n-\t__le32 mode;\n+\t__le32\tmode;\n #define I40E_AQ_ALTERNATE_MODE_NONE\t0\n #define I40E_AQ_ALTERNATE_MODE_OEM\t1\n-\tu8     reserved[12];\n+\tu8\treserved[12];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);\n@@ -1902,33 +1902,33 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);\n \n /* Lan Queue Overflow Event (direct, 0x1001) */\n struct i40e_aqc_lan_overflow {\n-\t__le32 prtdcb_rupto;\n-\t__le32 otx_ctl;\n-\tu8     reserved[8];\n+\t__le32\tprtdcb_rupto;\n+\t__le32\totx_ctl;\n+\tu8\treserved[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);\n \n /* Get LLDP MIB (indirect 0x0A00) */\n struct i40e_aqc_lldp_get_mib {\n-\tu8     type;\n-\tu8     reserved1;\n-#define I40E_AQ_LLDP_MIB_TYPE_MASK                      0x3\n-#define I40E_AQ_LLDP_MIB_LOCAL                          0x0\n-#define I40E_AQ_LLDP_MIB_REMOTE                         0x1\n-#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE               0x2\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK                   0xC\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT                  0x2\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE         0x0\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR               0x1\n-#define I40E_AQ_LLDP_TX_SHIFT              0x4\n-#define I40E_AQ_LLDP_TX_MASK               (0x03 << I40E_AQ_LLDP_TX_SHIFT)\n+\tu8\ttype;\n+\tu8\treserved1;\n+#define I40E_AQ_LLDP_MIB_TYPE_MASK\t\t0x3\n+#define I40E_AQ_LLDP_MIB_LOCAL\t\t\t0x0\n+#define I40E_AQ_LLDP_MIB_REMOTE\t\t\t0x1\n+#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE\t0x2\n+#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK\t\t0xC\n+#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT\t\t0x2\n+#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE\t0x0\n+#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR\t0x1\n+#define I40E_AQ_LLDP_TX_SHIFT\t\t\t0x4\n+#define I40E_AQ_LLDP_TX_MASK\t\t\t(0x03 << I40E_AQ_LLDP_TX_SHIFT)\n /* TX pause flags use I40E_AQ_LINK_TX_* above */\n-\t__le16 local_len;\n-\t__le16 remote_len;\n-\tu8     reserved2[2];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\t__le16\tlocal_len;\n+\t__le16\tremote_len;\n+\tu8\treserved2[2];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);\n@@ -1937,12 +1937,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);\n  * also used for the event (with type in the command field)\n  */\n struct i40e_aqc_lldp_update_mib {\n-\tu8     command;\n-#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE          0x0\n-#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE         0x1\n-\tu8     reserved[7];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\tcommand;\n+#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE\t0x0\n+#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE\t0x1\n+\tu8\treserved[7];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);\n@@ -1951,35 +1951,35 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);\n  * Delete LLDP TLV (indirect 0x0A04)\n  */\n struct i40e_aqc_lldp_add_tlv {\n-\tu8     type; /* only nearest bridge and non-TPMR from 0x0A00 */\n-\tu8     reserved1[1];\n-\t__le16 len;\n-\tu8     reserved2[4];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n+\tu8\treserved1[1];\n+\t__le16\tlen;\n+\tu8\treserved2[4];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);\n \n /* Update LLDP TLV (indirect 0x0A03) */\n struct i40e_aqc_lldp_update_tlv {\n-\tu8     type; /* only nearest bridge and non-TPMR from 0x0A00 */\n-\tu8     reserved;\n-\t__le16 old_len;\n-\t__le16 new_offset;\n-\t__le16 new_len;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n+\tu8\treserved;\n+\t__le16\told_len;\n+\t__le16\tnew_offset;\n+\t__le16\tnew_len;\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);\n \n /* Stop LLDP (direct 0x0A05) */\n struct i40e_aqc_lldp_stop {\n-\tu8     command;\n-#define I40E_AQ_LLDP_AGENT_STOP                 0x0\n-#define I40E_AQ_LLDP_AGENT_SHUTDOWN             0x1\n-\tu8     reserved[15];\n+\tu8\tcommand;\n+#define I40E_AQ_LLDP_AGENT_STOP\t\t0x0\n+#define I40E_AQ_LLDP_AGENT_SHUTDOWN\t0x1\n+\tu8\treserved[15];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);\n@@ -1987,9 +1987,9 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);\n /* Start LLDP (direct 0x0A06) */\n \n struct i40e_aqc_lldp_start {\n-\tu8     command;\n-#define I40E_AQ_LLDP_AGENT_START                0x1\n-\tu8     reserved[15];\n+\tu8\tcommand;\n+#define I40E_AQ_LLDP_AGENT_START\t0x1\n+\tu8\treserved[15];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);\n@@ -2000,13 +2000,13 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);\n \n /* Add Udp Tunnel command and completion (direct 0x0B00) */\n struct i40e_aqc_add_udp_tunnel {\n-\t__le16 udp_port;\n-\tu8     reserved0[3];\n-\tu8     protocol_type;\n+\t__le16\tudp_port;\n+\tu8\treserved0[3];\n+\tu8\tprotocol_type;\n #define I40E_AQC_TUNNEL_TYPE_VXLAN\t0x00\n #define I40E_AQC_TUNNEL_TYPE_NGE\t0x01\n #define I40E_AQC_TUNNEL_TYPE_TEREDO\t0x10\n-\tu8     reserved1[10];\n+\tu8\treserved1[10];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);\n@@ -2015,8 +2015,8 @@ struct i40e_aqc_add_udp_tunnel_completion {\n \t__le16 udp_port;\n \tu8\tfilter_entry_index;\n \tu8\tmultiple_pfs;\n-#define I40E_AQC_SINGLE_PF\t\t\t\t0x0\n-#define I40E_AQC_MULTIPLE_PFS\t\t\t0x1\n+#define I40E_AQC_SINGLE_PF\t\t0x0\n+#define I40E_AQC_MULTIPLE_PFS\t\t0x1\n \tu8\ttotal_filters;\n \tu8\treserved[11];\n };\n@@ -2025,19 +2025,19 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);\n \n /* remove UDP Tunnel command (0x0B01) */\n struct i40e_aqc_remove_udp_tunnel {\n-\tu8     reserved[2];\n-\tu8     index; /* 0 to 15 */\n-\tu8     reserved2[13];\n+\tu8\treserved[2];\n+\tu8\tindex; /* 0 to 15 */\n+\tu8\treserved2[13];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);\n \n struct i40e_aqc_del_udp_tunnel_completion {\n-\t__le16 udp_port;\n-\tu8     index; /* 0 to 15 */\n-\tu8     multiple_pfs;\n-\tu8     total_filters_used;\n-\tu8     reserved1[11];\n+\t__le16\tudp_port;\n+\tu8\tindex; /* 0 to 15 */\n+\tu8\tmultiple_pfs;\n+\tu8\ttotal_filters_used;\n+\tu8\treserved1[11];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);\n@@ -2050,11 +2050,11 @@ struct i40e_aqc_tunnel_key_structure {\n \tu8\tkey1_len;  /* 0 to 15 */\n \tu8\tkey2_len;  /* 0 to 15 */\n \tu8\tflags;\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01\n+#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE\t0x01\n /* response flags */\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS    0x01\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED   0x02\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03\n+#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS\t0x01\n+#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED\t0x02\n+#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN\t0x03\n \tu8\tnetwork_key_index;\n #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN\t\t0x0\n #define I40E_AQC_NETWORK_KEY_INDEX_NGE\t\t\t0x1\n@@ -2067,21 +2067,21 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);\n \n /* OEM mode commands (direct 0xFE0x) */\n struct i40e_aqc_oem_param_change {\n-\t__le32 param_type;\n-#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL   0\n-#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL   1\n-#define I40E_AQ_OEM_PARAM_MAC           2\n-\t__le32 param_value1;\n-\tu8     param_value2[8];\n+\t__le32\tparam_type;\n+#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL\t0\n+#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL\t1\n+#define I40E_AQ_OEM_PARAM_MAC\t\t2\n+\t__le32\tparam_value1;\n+\tu8\tparam_value2[8];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);\n \n struct i40e_aqc_oem_state_change {\n-\t__le32 state;\n-#define I40E_AQ_OEM_STATE_LINK_DOWN  0x0\n-#define I40E_AQ_OEM_STATE_LINK_UP    0x1\n-\tu8     reserved[12];\n+\t__le32\tstate;\n+#define I40E_AQ_OEM_STATE_LINK_DOWN\t0x0\n+#define I40E_AQ_OEM_STATE_LINK_UP\t0x1\n+\tu8\treserved[12];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);\n@@ -2093,18 +2093,18 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);\n /* set test more (0xFF01, internal) */\n \n struct i40e_acq_set_test_mode {\n-\tu8     mode;\n-#define I40E_AQ_TEST_PARTIAL    0\n-#define I40E_AQ_TEST_FULL       1\n-#define I40E_AQ_TEST_NVM        2\n-\tu8     reserved[3];\n-\tu8     command;\n-#define I40E_AQ_TEST_OPEN        0\n-#define I40E_AQ_TEST_CLOSE       1\n-#define I40E_AQ_TEST_INC         2\n-\tu8     reserved2[3];\n-\t__le32 address_high;\n-\t__le32 address_low;\n+\tu8\tmode;\n+#define I40E_AQ_TEST_PARTIAL\t0\n+#define I40E_AQ_TEST_FULL\t1\n+#define I40E_AQ_TEST_NVM\t2\n+\tu8\treserved[3];\n+\tu8\tcommand;\n+#define I40E_AQ_TEST_OPEN\t0\n+#define I40E_AQ_TEST_CLOSE\t1\n+#define I40E_AQ_TEST_INC\t2\n+\tu8\treserved2[3];\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);\n@@ -2157,21 +2157,21 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);\n #define I40E_AQ_CLUSTER_ID_ALTRAM\t11\n \n struct i40e_aqc_debug_dump_internals {\n-\tu8     cluster_id;\n-\tu8     table_id;\n-\t__le16 data_size;\n-\t__le32 idx;\n-\t__le32 address_high;\n-\t__le32 address_low;\n+\tu8\tcluster_id;\n+\tu8\ttable_id;\n+\t__le16\tdata_size;\n+\t__le32\tidx;\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);\n \n struct i40e_aqc_debug_modify_internals {\n-\tu8     cluster_id;\n-\tu8     cluster_specific_params[7];\n-\t__le32 address_high;\n-\t__le32 address_low;\n+\tu8\tcluster_id;\n+\tu8\tcluster_specific_params[7];\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);\n",
    "prefixes": [
        "dpdk-dev",
        "01/15"
    ]
}