Show a patch.

GET /api/patches/312/
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 312,
    "url": "https://patches.dpdk.org/api/patches/312/",
    "web_url": "https://patches.dpdk.org/patch/312/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1409759378-10113-10-git-send-email-bruce.richardson@intel.com>",
    "date": "2014-09-03T15:49:34",
    "name": "[dpdk-dev,09/13] ixgbe: rework vector pmd following mbuf changes",
    "commit_ref": "",
    "pull_url": "",
    "state": "superseded",
    "archived": true,
    "hash": "c1e9c75002b9406a12508f3ae7ddb51b268910d6",
    "submitter": {
        "id": 20,
        "url": "https://patches.dpdk.org/api/people/20/",
        "name": "Bruce Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/patch/312/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/312/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/312/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\r\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Date": "Wed,  3 Sep 2014 16:49:34 +0100",
        "In-Reply-To": "<1409759378-10113-1-git-send-email-bruce.richardson@intel.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<1409759378-10113-1-git-send-email-bruce.richardson@intel.com>",
        "X-Mailer": "git-send-email 1.7.0.7",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "To": "dev@dpdk.org",
        "Received": [
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\r\n\tby dpdk.org (Postfix) with ESMTP id 8799CB39F\r\n\tfor <dev@dpdk.org>; Wed,  3 Sep 2014 17:45:44 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\r\n\tby fmsmga102.fm.intel.com with ESMTP; 03 Sep 2014 08:49:46 -0700",
            "from irvmail001.ir.intel.com ([163.33.26.43])\r\n\tby fmsmga001.fm.intel.com with ESMTP; 03 Sep 2014 08:49:41 -0700",
            "from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com\r\n\t[10.237.217.46])\r\n\tby irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\r\n\ts83Fndme025434; Wed, 3 Sep 2014 16:49:40 +0100",
            "from sivswdev02.ir.intel.com (localhost [127.0.0.1])\r\n\tby sivswdev02.ir.intel.com with ESMTP id s83Fndbb010479;\r\n\tWed, 3 Sep 2014 16:49:39 +0100",
            "(from bricha3@localhost)\r\n\tby sivswdev02.ir.intel.com with  id s83FndjW010475;\r\n\tWed, 3 Sep 2014 16:49:39 +0100"
        ],
        "From": "Bruce Richardson <bruce.richardson@intel.com>",
        "Precedence": "list",
        "X-ExtLoop1": "1",
        "Message-Id": "<1409759378-10113-10-git-send-email-bruce.richardson@intel.com>",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH 09/13] ixgbe: rework vector pmd following mbuf\r\n\tchanges",
        "X-List-Received-Date": "Wed, 03 Sep 2014 15:45:45 -0000",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\r\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Return-Path": "<bricha3@ecsmtp.ir.intel.com>",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,458,1406617200\"; d=\"scan'208\";a=\"585697558\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "X-Mailman-Version": "2.1.15"
    },
    "content": "The vector PMD expects fields to be in a specific order so that it can\ndo vector operations on multiple fields at a time. Following mbuf\nrework, adjust driver to take account of the new layout and re-enable it\nin the config.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n config/common_linuxapp                |   2 +-\n lib/librte_pmd_ixgbe/ixgbe_rxtx.c     |   2 +-\n lib/librte_pmd_ixgbe/ixgbe_rxtx.h     |   4 +-\n lib/librte_pmd_ixgbe/ixgbe_rxtx_vec.c | 136 +++++++++++++---------------------\n 4 files changed, 54 insertions(+), 90 deletions(-)",
    "diff": "diff --git a/config/common_linuxapp b/config/common_linuxapp\r\nindex b140af7..5bee910 100644\r\n--- a/config/common_linuxapp\r\n+++ b/config/common_linuxapp\r\n@@ -191,7 +191,7 @@ CONFIG_RTE_LIBRTE_IXGBE_DEBUG_DRIVER=n\r\n CONFIG_RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC=n\r\n CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y\r\n CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n\r\n-CONFIG_RTE_IXGBE_INC_VECTOR=n\r\n+CONFIG_RTE_IXGBE_INC_VECTOR=y\r\n CONFIG_RTE_IXGBE_RX_OLFLAGS_ENABLE=y\r\n \r\n #\r\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c\r\nindex c7f1642..f48c62a 100644\r\n--- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c\r\n+++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c\r\n@@ -2167,7 +2167,7 @@ ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,\r\n \t\tif (!ixgbe_rx_vec_condition_check(dev)) {\r\n \t\t\tPMD_INIT_LOG(INFO, \"Vector rx enabled, please make \"\r\n \t\t\t\t     \"sure RX burst size no less than 32.\\n\");\r\n-\t\t\tixgbe_rxq_vec_setup(rxq, socket_id);\r\n+\t\t\tixgbe_rxq_vec_setup(rxq);\r\n \t\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_vec;\r\n \t\t}\r\n #endif\r\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.h b/lib/librte_pmd_ixgbe/ixgbe_rxtx.h\r\nindex 70dbcb0..5e98b21 100644\r\n--- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.h\r\n+++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.h\r\n@@ -115,6 +115,7 @@ struct igb_rx_queue {\r\n \tstruct igb_rx_entry *sw_ring; /**< address of RX software ring. */\r\n \tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\r\n \tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\r\n+\tuint64_t            mbuf_initializer; /**< value to init mbufs */\r\n \tuint16_t            nb_rx_desc; /**< number of RX descriptors. */\r\n \tuint16_t            rx_tail;  /**< current value of RDT register. */\r\n \tuint16_t            nb_rx_hold; /**< number of held free RX desc. */\r\n@@ -126,7 +127,6 @@ struct igb_rx_queue {\r\n #ifdef RTE_IXGBE_INC_VECTOR\r\n \tuint16_t            rxrearm_nb; /**< the idx we start the re-arming from */\r\n \tuint16_t            rxrearm_start;  /**< number of remaining to be re-armed */\r\n-\t__m128i             misc_info;  /**< cache XMM combine port_id/crc/nb_segs */\r\n #endif\r\n \tuint16_t            rx_free_thresh; /**< max free RX desc to hold. */\r\n \tuint16_t            queue_id; /**< RX queue index. */\r\n@@ -260,7 +260,7 @@ struct ixgbe_txq_ops {\r\n uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\r\n uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\r\n int ixgbe_txq_vec_setup(struct igb_tx_queue *txq, unsigned int socket_id);\r\n-int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq, unsigned int socket_id);\r\n+int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq);\r\n int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev);\r\n #endif\r\n \r\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx_vec.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx_vec.c\r\nindex bafb215..3332a92 100644\r\n--- a/lib/librte_pmd_ixgbe/ixgbe_rxtx_vec.c\r\n+++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx_vec.c\r\n@@ -47,15 +47,11 @@\r\n static inline void\r\n ixgbe_rxq_rearm(struct igb_rx_queue *rxq)\r\n {\r\n-\tstatic const struct rte_mbuf mb_def = {\r\n-\t\t.nb_segs = 1,\r\n-\t};\r\n \tint i;\r\n \tuint16_t rx_id;\r\n \tvolatile union ixgbe_adv_rx_desc *rxdp;\r\n \tstruct igb_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];\r\n \tstruct rte_mbuf *mb0, *mb1;\r\n-\t__m128i def_low;\r\n \t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\r\n \t\t\tRTE_PKTMBUF_HEADROOM);\r\n \r\n@@ -66,8 +62,6 @@ ixgbe_rxq_rearm(struct igb_rx_queue *rxq)\r\n \r\n \trxdp = rxq->rx_ring + rxq->rxrearm_start;\r\n \r\n-\tdef_low = _mm_load_si128((__m128i *)&(mb_def.next));\r\n-\r\n \t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\r\n \tfor (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {\r\n \t\t__m128i dma_addr0, dma_addr1;\r\n@@ -76,33 +70,25 @@ ixgbe_rxq_rearm(struct igb_rx_queue *rxq)\r\n \t\tmb0 = rxep[0].mbuf;\r\n \t\tmb1 = rxep[1].mbuf;\r\n \r\n+\t\t/* flush mbuf with pkt template */\r\n+\t\tmb0->rearm_data[0] = rxq->mbuf_initializer;\r\n+\t\tmb1->rearm_data[0] = rxq->mbuf_initializer;\r\n+\r\n \t\t/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */\r\n \t\tvaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));\r\n \t\tvaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));\r\n \r\n-\t\t/* calc va/pa of pkt data point */\r\n-\t\tvaddr0 = _mm_add_epi64(vaddr0, hdr_room);\r\n-\t\tvaddr1 = _mm_add_epi64(vaddr1, hdr_room);\r\n-\r\n \t\t/* convert pa to dma_addr hdr/data */\r\n \t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\r\n \t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\r\n \r\n-\t\t/* fill va into t0 def pkt template */\r\n-\t\tvaddr0 = _mm_unpacklo_epi64(def_low, vaddr0);\r\n-\t\tvaddr1 = _mm_unpacklo_epi64(def_low, vaddr1);\r\n+\t\t/* add headroom to pa values */\r\n+\t\tdma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\r\n+\t\tdma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\r\n \r\n \t\t/* flush desc with pa dma_addr */\r\n \t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\r\n \t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\r\n-\r\n-\t\t/* flush mbuf with pkt template */\r\n-\t\t_mm_store_si128((__m128i *)&mb0->next, vaddr0);\r\n-\t\t_mm_store_si128((__m128i *)&mb1->next, vaddr1);\r\n-\r\n-\t\t/* update refcnt per pkt */\r\n-\t\trte_mbuf_refcnt_set(mb0, 1);\r\n-\t\trte_mbuf_refcnt_set(mb1, 1);\r\n \t}\r\n \r\n \trxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;\r\n@@ -189,7 +175,13 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n \tint pos;\r\n \tuint64_t var;\r\n \t__m128i shuf_msk;\r\n-\t__m128i in_port;\r\n+\t__m128i crc_adjust = _mm_set_epi16(\r\n+\t\t\t\t0, 0, 0, 0, /* ignore non-length fields */\r\n+\t\t\t\t0,          /* ignore high-16bits of pkt_len */\r\n+\t\t\t\t-rxq->crc_len, /* sub crc on pkt_len */\r\n+\t\t\t\t-rxq->crc_len, /* sub crc on data_len */\r\n+\t\t\t\t0            /* ignore pkt_type field */\r\n+\t\t\t);\r\n \t__m128i dd_check;\r\n \r\n \tif (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))\r\n@@ -222,8 +214,8 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n \t\t15, 14,      /* octet 14~15, low 16 bits vlan_macip */\r\n \t\t0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */\r\n \t\t13, 12,      /* octet 12~13, low 16 bits pkt_len */\r\n-\t\t0xFF, 0xFF,  /* skip nb_segs and in_port, zero out */\r\n-\t\t13, 12       /* octet 12~13, 16 bits data_len */\r\n+\t\t13, 12,      /* octet 12~13, 16 bits data_len */\r\n+\t\t0xFF, 0xFF   /* skip pkt_type field */\r\n \t\t);\r\n \r\n \r\n@@ -231,9 +223,6 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n \t * the next 'n' mbufs into the cache */\r\n \tsw_ring = &rxq->sw_ring[rxq->rx_tail];\r\n \r\n-\t/* in_port, nb_seg = 1, crc_len */\r\n-\tin_port = rxq->misc_info;\r\n-\r\n \t/*\r\n \t * A. load 4 packet in one loop\r\n \t * B. copy 4 mbuf point from swring to rx_pkts\r\n@@ -285,8 +274,8 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n \t\tdesc_to_olflags_v(descs, &rx_pkts[pos]);\r\n \r\n \t\t/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */\r\n-\t\tpkt_mb4 = _mm_add_epi16(pkt_mb4, in_port);\r\n-\t\tpkt_mb3 = _mm_add_epi16(pkt_mb3, in_port);\r\n+\t\tpkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);\r\n+\t\tpkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);\r\n \r\n \t\t/* D.1 pkt 1,2 convert format from desc to pktmbuf */\r\n \t\tpkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);\r\n@@ -297,23 +286,23 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n \t\tstaterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);\r\n \r\n \t\t/* D.3 copy final 3,4 data to rx_pkts */\r\n-\t\t_mm_storeu_si128((__m128i *)&(rx_pkts[pos+3]->data_len),\r\n+\t\t_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,\r\n \t\t\t\tpkt_mb4);\r\n-\t\t_mm_storeu_si128((__m128i *)&(rx_pkts[pos+2]->data_len),\r\n+\t\t_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,\r\n \t\t\t\tpkt_mb3);\r\n \r\n \t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\r\n-\t\tpkt_mb2 = _mm_add_epi16(pkt_mb2, in_port);\r\n-\t\tpkt_mb1 = _mm_add_epi16(pkt_mb1, in_port);\r\n+\t\tpkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);\r\n+\t\tpkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);\r\n \r\n \t\t/* C.3 calc avaialbe number of desc */\r\n \t\tstaterr = _mm_and_si128(staterr, dd_check);\r\n \t\tstaterr = _mm_packs_epi32(staterr, zero);\r\n \r\n \t\t/* D.3 copy final 1,2 data to rx_pkts */\r\n-\t\t_mm_storeu_si128((__m128i *)&(rx_pkts[pos+1]->data_len),\r\n+\t\t_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,\r\n \t\t\t\tpkt_mb2);\r\n-\t\t_mm_storeu_si128((__m128i *)&(rx_pkts[pos]->data_len),\r\n+\t\t_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,\r\n \t\t\t\tpkt_mb1);\r\n \r\n \t\t/* C.4 calc avaialbe number of desc */\r\n@@ -330,46 +319,19 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n \r\n \treturn nb_pkts_recd;\r\n }\r\n-\r\n static inline void\r\n vtx1(volatile union ixgbe_adv_tx_desc *txdp,\r\n-\t\tstruct rte_mbuf *pkt, __m128i flags)\r\n+\t\tstruct rte_mbuf *pkt, uint64_t flags)\r\n {\r\n-\t__m128i t0, t1, offset, ols, ba, ctl;\r\n-\r\n-\t/* load buf_addr/buf_physaddr in t0 */\r\n-\tt0 = _mm_loadu_si128((__m128i *)&(pkt->buf_addr));\r\n-\t/* load data, ... pkt_len in t1 */\r\n-\tt1 = _mm_loadu_si128((__m128i *)&(pkt->data));\r\n-\r\n-\t/* calc offset = (data - buf_adr) */\r\n-\toffset = _mm_sub_epi64(t1, t0);\r\n-\r\n-\t/* cmd_type_len: pkt_len |= DCMD_DTYP_FLAGS */\r\n-\tctl = _mm_or_si128(t1, flags);\r\n-\r\n-\t/* reorder as buf_physaddr/buf_addr */\r\n-\toffset = _mm_shuffle_epi32(offset, 0x4E);\r\n-\r\n-\t/* olinfo_stats: pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT */\r\n-\tols = _mm_slli_epi32(t1, IXGBE_ADVTXD_PAYLEN_SHIFT);\r\n-\r\n-\t/* buffer_addr = buf_physaddr + offset */\r\n-\tba = _mm_add_epi64(t0, offset);\r\n-\r\n-\t/* format cmd_type_len/olinfo_status */\r\n-\tctl = _mm_unpackhi_epi32(ctl, ols);\r\n-\r\n-\t/* format buf_physaddr/cmd_type_len */\r\n-\tba = _mm_unpackhi_epi64(ba, ctl);\r\n-\r\n-\t/* write desc */\r\n-\t_mm_store_si128((__m128i *)&txdp->read, ba);\r\n+\t__m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |\r\n+\t\t\tflags | pkt->data_len,\r\n+\t\t\tpkt->buf_physaddr + pkt->data_off);\r\n+\t_mm_store_si128((__m128i *)&txdp->read, descriptor);\r\n }\r\n \r\n static inline void\r\n vtx(volatile union ixgbe_adv_tx_desc *txdp,\r\n-\t\tstruct rte_mbuf **pkt, uint16_t nb_pkts,  __m128i flags)\r\n+\t\tstruct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)\r\n {\r\n \tint i;\r\n \tfor (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)\r\n@@ -456,9 +418,8 @@ ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\r\n \tstruct igb_tx_entry_v *txep;\r\n \tstruct igb_tx_entry_seq *txsp;\r\n \tuint16_t n, nb_commit, tx_id;\r\n-\t__m128i flags = _mm_set_epi32(DCMD_DTYP_FLAGS, 0, 0, 0);\r\n-\t__m128i rs = _mm_set_epi32(IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS,\r\n-\t\t\t0, 0, 0);\r\n+\tuint64_t flags = DCMD_DTYP_FLAGS;\r\n+\tuint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;\r\n \tint i;\r\n \r\n \tif (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))\r\n@@ -610,6 +571,23 @@ static struct ixgbe_txq_ops vec_txq_ops = {\r\n \t.reset = ixgbe_reset_tx_queue,\r\n };\r\n \r\n+int\r\n+ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq)\r\n+{\r\n+\tstatic struct rte_mbuf mb_def = {\r\n+\t\t.nb_segs = 1,\r\n+\t\t.data_off = RTE_PKTMBUF_HEADROOM,\r\n+#ifdef RTE_MBUF_REFCNT\r\n+\t\t.refcnt = 1,\r\n+#endif\r\n+\t};\r\n+\r\n+\tmb_def.buf_len = rxq->mb_pool->elt_size - sizeof(struct rte_mbuf);\r\n+\tmb_def.port = rxq->port_id;\r\n+\trxq->mbuf_initializer = *((uint64_t *)&mb_def.rearm_data);\r\n+\treturn 0;\r\n+}\r\n+\r\n int ixgbe_txq_vec_setup(struct igb_tx_queue *txq,\r\n \t\t\tunsigned int socket_id)\r\n {\r\n@@ -637,21 +615,6 @@ int ixgbe_txq_vec_setup(struct igb_tx_queue *txq,\r\n \treturn 0;\r\n }\r\n \r\n-int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq,\r\n-\t\t\t__rte_unused unsigned int socket_id)\r\n-{\r\n-\trxq->misc_info =\r\n-\t\t_mm_set_epi16(\r\n-\t\t\t0, 0, 0, 0, 0,\r\n-\t\t\t(uint16_t)-rxq->crc_len, /* sub crc on pkt_len */\r\n-\t\t\t(uint16_t)(rxq->port_id << 8 | 1),\r\n-\t\t\t/* 8b port_id and 8b nb_seg*/\r\n-\t\t\t(uint16_t)-rxq->crc_len  /* sub crc on data_len */\r\n-\t\t\t);\r\n-\r\n-\treturn 0;\r\n-}\r\n-\r\n int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev)\r\n {\r\n #ifndef RTE_LIBRTE_IEEE1588\r\n@@ -683,3 +646,4 @@ int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev)\r\n \treturn -1;\r\n #endif\r\n }\r\n+\r\n",
    "prefixes": [
        "dpdk-dev",
        "09/13"
    ]
}