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GET /api/patches/29482/?format=api
{ "id": 29482, "url": "https://patches.dpdk.org/api/patches/29482/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1506955841-19683-3-git-send-email-rasland@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1506955841-19683-3-git-send-email-rasland@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1506955841-19683-3-git-send-email-rasland@mellanox.com", "date": "2017-10-02T14:50:41", "name": "[dpdk-dev,3/3] net/mlx5: add Rx HW timestamp", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b3afb60e1cbb70c696abe2709e67e5872f9a88d9", "submitter": { "id": 513, "url": "https://patches.dpdk.org/api/people/513/?format=api", "name": "Raslan Darawsheh", "email": "rasland@mellanox.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1506955841-19683-3-git-send-email-rasland@mellanox.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/29482/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/29482/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E50BF1B255;\n\tMon, 2 Oct 2017 16:50:59 +0200 (CEST)", "from EUR01-HE1-obe.outbound.protection.outlook.com\n\t(mail-he1eur01on0065.outbound.protection.outlook.com [104.47.0.65])\n\tby dpdk.org (Postfix) with ESMTP id CF80F1B24F\n\tfor <dev@dpdk.org>; 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SFP:1101; SCL:1; SRVR:AM2PR05MB1217; H:mellanox.com; FPR:;\n\tSPF:None; \n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: mellanox.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Oct 2017 14:50:54.8851\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "a652971c-7d2e-4d9b-a6a4-d149256f461b", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM2PR05MB1217", "Subject": "[dpdk-dev] [PATCH 3/3] net/mlx5: add Rx HW timestamp", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Expose Rx HW timestamp to packet mbufs.\n\nSigned-off-by :Raslan Darawsheh <rasland@mellanox.com>\nAcked-by: Yongseok Koh <yskoh@mellanox.com>\n---\n drivers/net/mlx5/mlx5_ethdev.c | 3 ++-\n drivers/net/mlx5/mlx5_rxq.c | 6 +++++-\n drivers/net/mlx5/mlx5_rxtx.c | 5 +++++\n drivers/net/mlx5/mlx5_rxtx.h | 3 ++-\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 13 ++++++++++++-\n 5 files changed, 26 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex d8bcef4..892c2cc 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -686,7 +686,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n \t\t DEV_RX_OFFLOAD_TCP_CKSUM) :\n \t\t 0) |\n-\t\t(priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0);\n+\t\t(priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) |\n+\t\tDEV_RX_OFFLOAD_TIMESTAMP;\n \tif (!priv->mps)\n \t\tinfo->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;\n \tif (priv->hw_csum)\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 9bb6a29..e48e240 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -609,7 +609,7 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)\n \tattr.cq.mlx5 = (struct mlx5dv_cq_init_attr){\n \t\t.comp_mask = 0,\n \t};\n-\tif (priv->cqe_comp) {\n+\tif (priv->cqe_comp && !rxq_data->hw_timestamp) {\n \t\tattr.cq.ibv.comp_mask |= IBV_CQ_INIT_ATTR_MASK_FLAGS;\n \t\tattr.cq.mlx5.comp_mask |=\n \t\t\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;\n@@ -620,6 +620,8 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)\n \t\t */\n \t\tif (rxq_check_vec_support(rxq_data) < 0)\n \t\t\tcqe_n *= 2;\n+\t} else if (priv->cqe_comp && rxq_data->hw_timestamp) {\n+\t\tDEBUG(\"Rx CQE compression is disabled for HW timestamp\");\n \t}\n \ttmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,\n \t\t\t\t\t\t &attr.cq.mlx5));\n@@ -936,6 +938,8 @@ mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,\n \tif (priv->hw_csum_l2tun)\n \t\ttmpl->rxq.csum_l2tun =\n \t\t\t!!dev->data->dev_conf.rxmode.hw_ip_checksum;\n+\ttmpl->rxq.hw_timestamp =\n+\t\t\t!!dev->data->dev_conf.rxmode.hw_timestamp;\n \t/* Configure VLAN stripping. */\n \ttmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&\n \t\t\t !!dev->data->dev_conf.rxmode.hw_vlan_strip);\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 275cd6a..961967b 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -1887,6 +1887,11 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t\tpkt->vlan_tci =\n \t\t\t\t\trte_be_to_cpu_16(cqe->vlan_info);\n \t\t\t}\n+\t\t\tif (rxq->hw_timestamp) {\n+\t\t\t\tpkt->timestamp =\n+\t\t\t\t\trte_be_to_cpu_64(cqe->timestamp);\n+\t\t\t\tpkt->ol_flags |= PKT_RX_TIMESTAMP;\n+\t\t\t}\n \t\t\tif (rxq->crc_present)\n \t\t\t\tlen -= ETHER_CRC_LEN;\n \t\t\tPKT_LEN(pkt) = len;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 8470a55..c207a8b 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -106,6 +106,7 @@ struct rxq_zip {\n struct mlx5_rxq_data {\n \tunsigned int csum:1; /* Enable checksum offloading. */\n \tunsigned int csum_l2tun:1; /* Same for L2 tunnels. */\n+\tunsigned int hw_timestamp:1; /* Enable HW timestamp. */\n \tunsigned int vlan_strip:1; /* Enable VLAN stripping. */\n \tunsigned int crc_present:1; /* CRC must be subtracted. */\n \tunsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */\n@@ -115,7 +116,7 @@ struct mlx5_rxq_data {\n \tunsigned int rss_hash:1; /* RSS hash result is enabled. */\n \tunsigned int mark:1; /* Marked flow available on the queue. */\n \tunsigned int pending_err:1; /* CQE error needs to be handled. */\n-\tunsigned int :7; /* Remaining bits. */\n+\tunsigned int :6; /* Remaining bits. */\n \tvolatile uint32_t *rq_db;\n \tvolatile uint32_t *cq_db;\n \tuint16_t rq_ci;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex c2142d7..e9819b7 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -545,7 +545,8 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],\n {\n \t__m128i pinfo0, pinfo1;\n \t__m128i pinfo, ptype;\n-\t__m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);\n+\t__m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |\n+\t\t\t\t\t rxq->hw_timestamp * PKT_RX_TIMESTAMP);\n \t__m128i cv_flags;\n \tconst __m128i zero = _mm_setzero_si128();\n \tconst __m128i ptype_mask =\n@@ -938,6 +939,16 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\trxq->pending_err |= !!_mm_cvtsi128_si64(opcode);\n \t\t/* D.5 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);\n+\t\tif (rxq->hw_timestamp) {\n+\t\t\tpkts[pos]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos].timestamp);\n+\t\t\tpkts[pos + 1]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos + p1].timestamp);\n+\t\t\tpkts[pos + 2]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos + p2].timestamp);\n+\t\t\tpkts[pos + 3]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos + p3].timestamp);\n+\t\t}\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t\t/* Add up received bytes count. */\n \t\tbyte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);\n", "prefixes": [ "dpdk-dev", "3/3" ] }