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GET /api/patches/29474/?format=api
{ "id": 29474, "url": "https://patches.dpdk.org/api/patches/29474/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20171002111738.79520-1-sergio.gonzalez.monroy@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20171002111738.79520-1-sergio.gonzalez.monroy@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20171002111738.79520-1-sergio.gonzalez.monroy@intel.com", "date": "2017-10-02T11:17:38", "name": "[dpdk-dev,v3] eal/x86: implement x86 specific tsc hz", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "45f6433ce43790ac746eafb4a9868ed3f1133e6a", "submitter": { "id": 73, "url": "https://patches.dpdk.org/api/people/73/?format=api", "name": "Sergio Gonzalez Monroy", "email": "sergio.gonzalez.monroy@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20171002111738.79520-1-sergio.gonzalez.monroy@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/29474/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/29474/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 289731B209;\n\tMon, 2 Oct 2017 13:17:43 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 88E8B1B1CE\n\tfor <dev@dpdk.org>; Mon, 2 Oct 2017 13:17:41 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Oct 2017 04:17:40 -0700", "from silpixa00397517.ir.intel.com (HELO\n\tsilpixa00397517.ger.corp.intel.com) ([10.237.222.54])\n\tby orsmga001.jf.intel.com with ESMTP; 02 Oct 2017 04:17:39 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,469,1500966000\"; d=\"scan'208\";\n\ta=\"1177729175\"", "From": "Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>", "To": "dev@dpdk.org", "Cc": "harry.van.haaren@intel.com,\n\tbruce.richardson@intel.com", "Date": "Mon, 2 Oct 2017 12:17:38 +0100", "Message-Id": "<20171002111738.79520-1-sergio.gonzalez.monroy@intel.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20171002100930.78602-1-sergio.gonzalez.monroy@intel.com>", "References": "<20171002100930.78602-1-sergio.gonzalez.monroy@intel.com>", "Subject": "[dpdk-dev] [PATCH v3] eal/x86: implement x86 specific tsc hz", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "First, try to use CPUID Time Stamp Counter and Nominal Core Crystal\nClock Information Leaf to determine the tsc hz on platforms that\nsupports it (does not require privileged user).\n\nIf the CPUID leaf is not available, then try to determine the tsc hz by\nreading the MSR 0xCE (requires privileged user).\n\nDefault to the tsc hz estimation if both methods fail.\n\nSigned-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>\nAcked-by: Harry van Haaren <harry.van.haaren@intel.com>\nTested-by: Bruce Richardson <bruce.richardson@intel.com>\n---\nDEPENDS on:\nhttp://dpdk.org/dev/patchwork/patch/29086/\n\nv3:\n - acked-by and tested-by tags\n\nv2:\n - fix misspelled word in commit message\n - address comment for more clear code\n\n lib/librte_eal/common/arch/x86/rte_cycles.c | 142 +++++++++++++++++++++\n .../common/include/arch/x86/rte_cycles.h | 7 +-\n lib/librte_eal/linuxapp/eal/Makefile | 1 +\n 3 files changed, 145 insertions(+), 5 deletions(-)\n create mode 100644 lib/librte_eal/common/arch/x86/rte_cycles.c", "diff": "diff --git a/lib/librte_eal/common/arch/x86/rte_cycles.c b/lib/librte_eal/common/arch/x86/rte_cycles.c\nnew file mode 100644\nindex 0000000..7cf6093\n--- /dev/null\n+++ b/lib/librte_eal/common/arch/x86/rte_cycles.c\n@@ -0,0 +1,142 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <fcntl.h>\n+#include <unistd.h>\n+#include <cpuid.h>\n+#include <rte_cycles.h>\n+\n+static unsigned int\n+rte_cpu_get_model(uint32_t fam_mod_step)\n+{\n+\tuint32_t family, model, ext_model;\n+\n+\tfamily = (fam_mod_step >> 8) & 0xf;\n+\tmodel = (fam_mod_step >> 4) & 0xf;\n+\n+\tif (family == 6 || family == 15) {\n+\t\text_model = (fam_mod_step >> 16) & 0xf;\n+\t\tmodel += (ext_model << 4);\n+\t}\n+\n+\treturn model;\n+}\n+\n+static int32_t\n+rdmsr(int msr, uint64_t *val)\n+{\n+\tint fd;\n+\tint ret;\n+\n+\tfd = open(\"/dev/cpu/0/msr\", O_RDONLY);\n+\tif (fd < 0)\n+\t\treturn fd;\n+\n+\tret = pread(fd, val, sizeof(uint64_t), msr);\n+\n+\tclose(fd);\n+\n+\treturn ret;\n+}\n+\n+static uint32_t\n+check_model_wsm_nhm(uint8_t model)\n+{\n+\tswitch (model) {\n+\t/* Westmere */\n+\tcase 0x25:\n+\tcase 0x2C:\n+\tcase 0x2F:\n+\t/* Nehalem */\n+\tcase 0x1E:\n+\tcase 0x1F:\n+\tcase 0x1A:\n+\tcase 0x2E:\n+\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static uint32_t\n+check_model_gdm_dnv(uint8_t model)\n+{\n+\tswitch (model) {\n+\t/* Goldmont */\n+\tcase 0x5C:\n+\t/* Denverton */\n+\tcase 0x5F:\n+\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+uint64_t\n+rte_rdtsc_arch_hz(void)\n+{\n+\tuint64_t tsc_hz = 0;\n+\tuint32_t a, b, c, d, maxleaf;\n+\tuint8_t mult, model;\n+\tint32_t ret;\n+\n+\t/*\n+\t * Time Stamp Counter and Nominal Core Crystal Clock\n+\t * Information Leaf\n+\t */\n+\tmaxleaf = __get_cpuid_max(0, NULL);\n+\n+\tif (maxleaf >= 0x15) {\n+\t\t__cpuid(0x15, a, b, c, d);\n+\n+\t\t/* EBX : TSC/Crystal ratio, ECX : Crystal Hz */\n+\t\tif (b && c)\n+\t\t\treturn c * (b / a);\n+\t}\n+\n+\t__cpuid(0x1, a, b, c, d);\n+\tmodel = rte_cpu_get_model(a);\n+\n+\tif (check_model_wsm_nhm(model))\n+\t\tmult = 133;\n+\telse if ((c & bit_AVX) || check_model_gdm_dnv(model))\n+\t\tmult = 100;\n+\telse\n+\t\treturn 0;\n+\n+\tret = rdmsr(0xCE, &tsc_hz);\n+\tif (ret < 0)\n+\t\treturn 0;\n+\n+\treturn ((tsc_hz >> 8) & 0xff) * mult * 1E6;\n+}\ndiff --git a/lib/librte_eal/common/include/arch/x86/rte_cycles.h b/lib/librte_eal/common/include/arch/x86/rte_cycles.h\nindex e2661e2..0db89dc 100644\n--- a/lib/librte_eal/common/include/arch/x86/rte_cycles.h\n+++ b/lib/librte_eal/common/include/arch/x86/rte_cycles.h\n@@ -84,11 +84,8 @@ rte_rdtsc(void)\n * The number of rdtsc cycles in one second. Return zero if the architecture\n * support is not available.\n */\n-static inline uint64_t\n-rte_rdtsc_arch_hz(void)\n-{\n-\treturn 0;\n-}\n+uint64_t\n+rte_rdtsc_arch_hz(void);\n \n static inline uint64_t\n rte_rdtsc_precise(void)\ndiff --git a/lib/librte_eal/linuxapp/eal/Makefile b/lib/librte_eal/linuxapp/eal/Makefile\nindex 90bca4d..9d44828 100644\n--- a/lib/librte_eal/linuxapp/eal/Makefile\n+++ b/lib/librte_eal/linuxapp/eal/Makefile\n@@ -104,6 +104,7 @@ SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += rte_service.c\n # from arch dir\n SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += rte_cpuflags.c\n SRCS-$(CONFIG_RTE_ARCH_X86) += rte_spinlock.c\n+SRCS-$(CONFIG_RTE_ARCH_X86) += rte_cycles.c\n \n CFLAGS_eal_common_cpuflags.o := $(CPUFLAGS_LIST)\n \n", "prefixes": [ "dpdk-dev", "v3" ] }