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GET /api/patches/29440/?format=api
{ "id": 29440, "url": "https://patches.dpdk.org/api/patches/29440/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1506700252-34949-3-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1506700252-34949-3-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1506700252-34949-3-git-send-email-beilei.xing@intel.com", "date": "2017-09-29T15:50:46", "name": "[dpdk-dev,v7,2/8] net/i40e: update ptype and pctype info", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f6e6c9ee17b8c49bb7ac3af371dd83a835d5cb1f", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1506700252-34949-3-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/29440/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/29440/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 78C021B1A2;\n\tFri, 29 Sep 2017 17:51:56 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 3B5B51B19F\n\tfor <dev@dpdk.org>; Fri, 29 Sep 2017 17:51:41 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Sep 2017 08:51:41 -0700", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby orsmga001.jf.intel.com with ESMTP; 29 Sep 2017 08:51:40 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,453,1500966000\"; d=\"scan'208\";\n\ta=\"1177050452\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "jingjing.wu@intel.com", "Cc": "andrey.chilikin@intel.com,\n\tdev@dpdk.org", "Date": "Fri, 29 Sep 2017 23:50:46 +0800", "Message-Id": "<1506700252-34949-3-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1506700252-34949-1-git-send-email-beilei.xing@intel.com>", "References": "<1506662342-18966-1-git-send-email-beilei.xing@intel.com>\n\t<1506700252-34949-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v7 2/8] net/i40e: update ptype and pctype info", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update new packet type and new pctype info when downloading\nprofile.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 312 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/i40e/i40e_ethdev.h | 24 ++++\n drivers/net/i40e/rte_pmd_i40e.c | 6 +-\n 3 files changed, 341 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex acdf0de..1da18e4 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -65,6 +65,7 @@\n #include \"i40e_rxtx.h\"\n #include \"i40e_pf.h\"\n #include \"i40e_regs.h\"\n+#include \"rte_pmd_i40e.h\"\n \n #define ETH_I40E_FLOATING_VEB_ARG\t\"enable_floating_veb\"\n #define ETH_I40E_FLOATING_VEB_LIST_ARG\t\"floating_veb_list\"\n@@ -1042,6 +1043,21 @@ i40e_init_fdir_filter_list(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+static void\n+i40e_init_customized_info(struct i40e_pf *pf)\n+{\n+\tint i;\n+\n+\t/* Initialize customized pctype */\n+\tfor (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {\n+\t\tpf->customized_pctype[i].index = i;\n+\t\tpf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;\n+\t\tpf->customized_pctype[i].valid = false;\n+\t}\n+\n+\tpf->gtp_support = false;\n+}\n+\n static int\n eth_i40e_dev_init(struct rte_eth_dev *dev)\n {\n@@ -1307,6 +1323,9 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t/* initialize Traffic Manager configuration */\n \ti40e_tm_conf_init(dev);\n \n+\t/* Initialize customized information */\n+\ti40e_init_customized_info(pf);\n+\n \tret = i40e_init_ethtype_filter_list(dev);\n \tif (ret < 0)\n \t\tgoto err_init_ethtype_filter_list;\n@@ -10913,6 +10932,299 @@ is_i40e_supported(struct rte_eth_dev *dev)\n \treturn is_device_supported(dev, &rte_i40e_pmd);\n }\n \n+struct i40e_customized_pctype*\n+i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {\n+\t\tif (pf->customized_pctype[i].index == index)\n+\t\t\treturn &pf->customized_pctype[i];\n+\t}\n+\treturn NULL;\n+}\n+\n+static int\n+i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,\n+\t\t\t uint32_t pkg_size, uint32_t proto_num,\n+\t\t\t struct rte_pmd_i40e_proto_info *proto)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tuint32_t pctype_num;\n+\tstruct rte_pmd_i40e_ptype_info *pctype;\n+\tuint32_t buff_size;\n+\tstruct i40e_customized_pctype *new_pctype = NULL;\n+\tuint8_t proto_id;\n+\tuint8_t pctype_value;\n+\tchar name[64];\n+\tuint32_t i, j, n;\n+\tint ret;\n+\n+\tret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,\n+\t\t\t\t(uint8_t *)&pctype_num, sizeof(pctype_num),\n+\t\t\t\tRTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get pctype number\");\n+\t\treturn -1;\n+\t}\n+\tif (!pctype_num) {\n+\t\tPMD_DRV_LOG(INFO, \"No new pctype added\");\n+\t\treturn -1;\n+\t}\n+\n+\tbuff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);\n+\tpctype = rte_zmalloc(\"new_pctype\", buff_size, 0);\n+\tif (!pctype) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory\");\n+\t\treturn -1;\n+\t}\n+\t/* get information about new pctype list */\n+\tret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,\n+\t\t\t\t\t(uint8_t *)pctype, buff_size,\n+\t\t\t\t\tRTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get pctype list\");\n+\t\trte_free(pctype);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Update customized pctype. */\n+\tfor (i = 0; i < pctype_num; i++) {\n+\t\tpctype_value = pctype[i].ptype_id;\n+\t\tmemset(name, 0, sizeof(name));\n+\t\tfor (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {\n+\t\t\tproto_id = pctype[i].protocols[j];\n+\t\t\tif (proto_id == RTE_PMD_I40E_PROTO_UNUSED)\n+\t\t\t\tcontinue;\n+\t\t\tfor (n = 0; n < proto_num; n++) {\n+\t\t\t\tif (proto[n].proto_id != proto_id)\n+\t\t\t\t\tcontinue;\n+\t\t\t\tstrcat(name, proto[n].name);\n+\t\t\t\tstrcat(name, \"_\");\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tname[strlen(name) - 1] = '\\0';\n+\t\tif (!strcmp(name, \"GTPC\"))\n+\t\t\tnew_pctype =\n+\t\t\t\ti40e_find_customized_pctype(pf,\n+\t\t\t\t\t\t I40E_CUSTOMIZED_GTPC);\n+\t\telse if (!strcmp(name, \"GTPU_IPV4\"))\n+\t\t\tnew_pctype =\n+\t\t\t\ti40e_find_customized_pctype(pf,\n+\t\t\t\t\t\t I40E_CUSTOMIZED_GTPU_IPV4);\n+\t\telse if (!strcmp(name, \"GTPU_IPV6\"))\n+\t\t\tnew_pctype =\n+\t\t\t\ti40e_find_customized_pctype(pf,\n+\t\t\t\t\t\t I40E_CUSTOMIZED_GTPU_IPV6);\n+\t\telse if (!strcmp(name, \"GTPU\"))\n+\t\t\tnew_pctype =\n+\t\t\t\ti40e_find_customized_pctype(pf,\n+\t\t\t\t\t\t I40E_CUSTOMIZED_GTPU);\n+\t\tif (new_pctype) {\n+\t\t\tnew_pctype->pctype = pctype_value;\n+\t\t\tnew_pctype->valid = true;\n+\t\t}\n+\t}\n+\n+\trte_free(pctype);\n+\treturn 0;\n+}\n+\n+static int\n+i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,\n+\t\t\t uint32_t pkg_size, uint32_t proto_num,\n+\t\t\t struct rte_pmd_i40e_proto_info *proto)\n+{\n+\tstruct rte_pmd_i40e_ptype_mapping *ptype_mapping;\n+\tuint8_t port_id = dev->data->port_id;\n+\tuint32_t ptype_num;\n+\tstruct rte_pmd_i40e_ptype_info *ptype;\n+\tuint32_t buff_size;\n+\tuint8_t proto_id;\n+\tchar name[16];\n+\tuint32_t i, j, n;\n+\tbool inner_ip;\n+\tint ret;\n+\n+\t/* get information about new ptype num */\n+\tret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,\n+\t\t\t\t(uint8_t *)&ptype_num, sizeof(ptype_num),\n+\t\t\t\tRTE_PMD_I40E_PKG_INFO_PTYPE_NUM);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get ptype number\");\n+\t\treturn ret;\n+\t}\n+\tif (!ptype_num) {\n+\t\tPMD_DRV_LOG(INFO, \"No new ptype added\");\n+\t\treturn -1;\n+\t}\n+\n+\tbuff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);\n+\tptype = rte_zmalloc(\"new_ptype\", buff_size, 0);\n+\tif (!ptype) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* get information about new ptype list */\n+\tret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,\n+\t\t\t\t\t(uint8_t *)ptype, buff_size,\n+\t\t\t\t\tRTE_PMD_I40E_PKG_INFO_PTYPE_LIST);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get ptype list\");\n+\t\trte_free(ptype);\n+\t\treturn ret;\n+\t}\n+\n+\tbuff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);\n+\tptype_mapping = rte_zmalloc(\"ptype_mapping\", buff_size, 0);\n+\tif (!ptype_mapping) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory\");\n+\t\trte_free(ptype);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Update ptype mapping table. */\n+\tfor (i = 0; i < ptype_num; i++) {\n+\t\tptype_mapping[i].hw_ptype = ptype[i].ptype_id;\n+\t\tptype_mapping[i].sw_ptype = 0;\n+\t\tinner_ip = false;\n+\t\tfor (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {\n+\t\t\tproto_id = ptype[i].protocols[j];\n+\t\t\tif (proto_id == RTE_PMD_I40E_PROTO_UNUSED)\n+\t\t\t\tcontinue;\n+\t\t\tfor (n = 0; n < proto_num; n++) {\n+\t\t\t\tif (proto[n].proto_id != proto_id)\n+\t\t\t\t\tcontinue;\n+\t\t\t\tmemset(name, 0, sizeof(name));\n+\t\t\t\tstrcpy(name, proto[n].name);\n+\t\t\t\tif (!strncmp(name, \"IPV4\", 4) && !inner_ip) {\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_L3_IPV4_EXT_UNKNOWN;\n+\t\t\t\t\tinner_ip = true;\n+\t\t\t\t} else if (!strncmp(name, \"IPV4\", 4) &&\n+\t\t\t\t\t inner_ip) {\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;\n+\t\t\t\t} else if (!strncmp(name, \"IPV6\", 4) &&\n+\t\t\t\t\t !inner_ip) {\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_L3_IPV6_EXT_UNKNOWN;\n+\t\t\t\t\tinner_ip = true;\n+\t\t\t\t} else if (!strncmp(name, \"IPV6\", 4) &&\n+\t\t\t\t\t inner_ip) {\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;\n+\t\t\t\t} else if (!strncmp(name, \"IPV4FRAG\", 8)) {\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_INNER_L4_FRAG;\n+\t\t\t\t} else if (!strncmp(name, \"IPV6FRAG\", 8)) {\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_INNER_L4_FRAG;\n+\t\t\t\t} else if (!strncmp(name, \"GTPC\", 4))\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_TUNNEL_GTPC;\n+\t\t\t\telse if (!strncmp(name, \"GTPU\", 4))\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_TUNNEL_GTPU;\n+\t\t\t\telse if (!strncmp(name, \"UDP\", 3))\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_INNER_L4_UDP;\n+\t\t\t\telse if (!strncmp(name, \"TCP\", 3))\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_INNER_L4_TCP;\n+\t\t\t\telse if (!strncmp(name, \"SCTP\", 4))\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_INNER_L4_SCTP;\n+\t\t\t\telse if (!strncmp(name, \"ICMP\", 4) ||\n+\t\t\t\t\t !strncmp(name, \"ICMPV6\", 6))\n+\t\t\t\t\tptype_mapping[i].sw_ptype |=\n+\t\t\t\t\t\tRTE_PTYPE_INNER_L4_ICMP;\n+\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,\n+\t\t\t\t\t\tptype_num, 0);\n+\tif (ret)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to update mapping table.\");\n+\n+\trte_free(ptype_mapping);\n+\trte_free(ptype);\n+\treturn ret;\n+}\n+\n+void\n+i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,\n+\t\t\t uint32_t pkg_size)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tuint32_t proto_num;\n+\tstruct rte_pmd_i40e_proto_info *proto;\n+\tuint32_t buff_size;\n+\tuint32_t i;\n+\tint ret;\n+\n+\t/* get information about protocol number */\n+\tret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,\n+\t\t\t\t (uint8_t *)&proto_num, sizeof(proto_num),\n+\t\t\t\t RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get protocol number\");\n+\t\treturn;\n+\t}\n+\tif (!proto_num) {\n+\t\tPMD_DRV_LOG(INFO, \"No new protocol added\");\n+\t\treturn;\n+\t}\n+\n+\tbuff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);\n+\tproto = rte_zmalloc(\"new_proto\", buff_size, 0);\n+\tif (!proto) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory\");\n+\t\treturn;\n+\t}\n+\n+\t/* get information about protocol list */\n+\tret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,\n+\t\t\t\t\t(uint8_t *)proto, buff_size,\n+\t\t\t\t\tRTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get protocol list\");\n+\t\trte_free(proto);\n+\t\treturn;\n+\t}\n+\n+\t/* Check if GTP is supported. */\n+\tfor (i = 0; i < proto_num; i++) {\n+\t\tif (!strncmp(proto[i].name, \"GTP\", 3)) {\n+\t\t\tpf->gtp_support = true;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Update customized pctype info */\n+\tret = i40e_update_customized_pctype(dev, pkg, pkg_size,\n+\t\t\t\t\t proto_num, proto);\n+\tif (ret)\n+\t\tPMD_DRV_LOG(INFO, \"No pctype is updated.\");\n+\n+\t/* Update customized ptype info */\n+\tret = i40e_update_customized_ptype(dev, pkg, pkg_size,\n+\t\t\t\t\t proto_num, proto);\n+\tif (ret)\n+\t\tPMD_DRV_LOG(INFO, \"No ptype is updated.\");\n+\n+\trte_free(proto);\n+}\n+\n /* Create a QinQ cloud filter\n *\n * The Fortville NIC has limited resources for tunnel filters,\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex ad80f0f..73fb5c3 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -722,6 +722,21 @@ struct i40e_tm_conf {\n \tbool committed;\n };\n \n+enum i40e_new_pctype {\n+\tI40E_CUSTOMIZED_GTPC = 0,\n+\tI40E_CUSTOMIZED_GTPU_IPV4,\n+\tI40E_CUSTOMIZED_GTPU_IPV6,\n+\tI40E_CUSTOMIZED_GTPU,\n+\tI40E_CUSTOMIZED_MAX,\n+};\n+\n+#define I40E_FILTER_PCTYPE_INVALID 0\n+struct i40e_customized_pctype {\n+\tenum i40e_new_pctype index; /* Indicate which customized pctype */\n+\tuint8_t pctype; /* New pctype value */\n+\tbool valid; /* Check if it's valid */\n+};\n+\n /*\n * Structure to store private data specific for PF instance.\n */\n@@ -786,6 +801,11 @@ struct i40e_pf {\n \tbool mpls_replace_flag; /* 1 - MPLS filter replace is done */\n \tbool qinq_replace_flag; /* QINQ filter replace is done */\n \tstruct i40e_tm_conf tm_conf;\n+\n+\t/* Dynamic Device Personalization */\n+\tbool gtp_support; /* 1 - support GTP-C and GTP-U */\n+\t/* customer customized pctype */\n+\tstruct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];\n };\n \n enum pending_msg {\n@@ -1003,6 +1023,10 @@ void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);\n int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);\n void i40e_tm_conf_init(struct rte_eth_dev *dev);\n void i40e_tm_conf_uninit(struct rte_eth_dev *dev);\n+struct i40e_customized_pctype*\n+i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);\n+void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,\n+\t\t\t\t uint32_t pkg_size);\n \n #define I40E_DEV_TO_PCI(eth_dev) \\\n \tRTE_DEV_TO_PCI((eth_dev)->device)\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c\nindex f57e59b..5aa9c69 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.c\n+++ b/drivers/net/i40e/rte_pmd_i40e.c\n@@ -1608,6 +1608,8 @@ rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,\n \t\treturn -EINVAL;\n \t}\n \n+\ti40e_update_customized_info(dev, buff, size);\n+\n \t/* Find metadata segment */\n \tmetadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,\n \t\t\t\t\t\t\tpkg_hdr);\n@@ -2109,7 +2111,9 @@ static int check_invalid_pkt_type(uint32_t pkt_type)\n \t tnl != RTE_PTYPE_TUNNEL_VXLAN &&\n \t tnl != RTE_PTYPE_TUNNEL_NVGRE &&\n \t tnl != RTE_PTYPE_TUNNEL_GENEVE &&\n-\t tnl != RTE_PTYPE_TUNNEL_GRENAT)\n+\t tnl != RTE_PTYPE_TUNNEL_GRENAT &&\n+\t tnl != RTE_PTYPE_TUNNEL_GTPC &&\n+\t tnl != RTE_PTYPE_TUNNEL_GTPU)\n \t\treturn -1;\n \n \tif (il2 &&\n", "prefixes": [ "dpdk-dev", "v7", "2/8" ] }