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GET /api/patches/28612/?format=api
{ "id": 28612, "url": "https://patches.dpdk.org/api/patches/28612/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com", "date": "2017-09-12T09:31:18", "name": "[dpdk-dev,v2,3/3] crypto/qat: enable TX tail writes coalescing", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d8b4e01f984eb2230c75bd439167b425aed59562", "submitter": { "id": 4, "url": "https://patches.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 22, "url": "https://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/28612/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/28612/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E15571AF03;\n\tTue, 12 Sep 2017 11:31:28 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 76B6F56A1\n\tfor <dev@dpdk.org>; Tue, 12 Sep 2017 11:31:23 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t12 Sep 2017 02:31:21 -0700", "from irvmail001.ir.intel.com ([163.33.26.43])\n\tby fmsmga006.fm.intel.com with ESMTP; 12 Sep 2017 02:31:19 -0700", "from sivswdev01.ir.intel.com (sivswdev01.ir.intel.com\n\t[10.237.217.45])\n\tby irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\n\tv8C9VJpU004579; Tue, 12 Sep 2017 10:31:19 +0100", "from sivswdev01.ir.intel.com (localhost [127.0.0.1])\n\tby sivswdev01.ir.intel.com with ESMTP id v8C9VJQc030070;\n\tTue, 12 Sep 2017 10:31:19 +0100", "(from aburakov@localhost)\n\tby sivswdev01.ir.intel.com with LOCAL id v8C9VIJT030066;\n\tTue, 12 Sep 2017 10:31:18 +0100" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.42,382,1500966000\"; d=\"scan'208\";a=\"150841056\"", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "fiona.trahe@intel.com, john.griffin@intel.com, deepak.k.jain@intel.com, \n\tpablo.de.lara.guarch@intel.com", "Date": "Tue, 12 Sep 2017 10:31:18 +0100", "Message-Id": "<8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": [ "<7ebf9384e20ea6fde085044c505e19719d041d25.1503651900.git.anatoly.burakov@intel.com>", "<cover.1505142402.git.anatoly.burakov@intel.com>" ], "References": [ "<7ebf9384e20ea6fde085044c505e19719d041d25.1503651900.git.anatoly.burakov@intel.com>", "<cover.1505142402.git.anatoly.burakov@intel.com>" ], "Subject": "[dpdk-dev] [PATCH v2 3/3] crypto/qat: enable TX tail writes\n\tcoalescing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Don't write CSR tail until we processed enough TX descriptors.\n\nTo avoid crypto operations sitting in the TX ring indefinitely,\nthe \"force write\" threshold is used:\n - on TX, no tail write coalescing will occur if number of inflights\n is below force write threshold\n - on RX, check if we have a number of crypto ops enqueued that is\n below force write threshold that are not yet submitted to\n processing.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\nv2: fixed commit message\n\n doc/guides/rel_notes/release_17_11.rst | 1 +\n drivers/crypto/qat/qat_crypto.c | 41 ++++++++++++++++++++++++----------\n drivers/crypto/qat/qat_crypto.h | 7 ++++++\n 3 files changed, 37 insertions(+), 12 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_17_11.rst b/doc/guides/rel_notes/release_17_11.rst\nindex 0b77095..f0d3960 100644\n--- a/doc/guides/rel_notes/release_17_11.rst\n+++ b/doc/guides/rel_notes/release_17_11.rst\n@@ -47,6 +47,7 @@ New Features\n \n * Removed atomics from the internal queue pair structure.\n * Coalesce writes to HEAD CSR on response processing.\n+ * Coalesce writes to TAIL CSR on request processing.\n \n \n Resolved Issues\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c\nindex 1656e0f..a2b202f 100644\n--- a/drivers/crypto/qat/qat_crypto.c\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -921,6 +921,14 @@ qat_bpicipher_postprocess(struct qat_session *ctx,\n \treturn sym_op->cipher.data.length - last_block_len;\n }\n \n+static inline void\n+txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {\n+\tWRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,\n+\t\t\tq->hw_queue_number, q->tail);\n+\tq->nb_pending_requests = 0;\n+\tq->csr_tail = q->tail;\n+}\n+\n uint16_t\n qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n@@ -973,10 +981,13 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tcur_op++;\n \t}\n kick_tail:\n-\tWRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,\n-\t\t\tqueue->hw_queue_number, tail);\n \tqueue->tail = tail;\n \ttmp_qp->stats.enqueued_count += nb_ops_sent;\n+\tqueue->nb_pending_requests += nb_ops_sent;\n+\tif (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||\n+\t\t\tqueue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {\n+\t\ttxq_write_tail(tmp_qp, queue);\n+\t}\n \treturn nb_ops_sent;\n }\n \n@@ -1011,17 +1022,18 @@ uint16_t\n qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n {\n-\tstruct qat_queue *queue;\n+\tstruct qat_queue *rx_queue, *tx_queue;\n \tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n \tuint32_t msg_counter = 0;\n \tstruct rte_crypto_op *rx_op;\n \tstruct icp_qat_fw_comn_resp *resp_msg;\n \tuint32_t head;\n \n-\tqueue = &(tmp_qp->rx_q);\n-\thead = queue->head;\n+\trx_queue = &(tmp_qp->rx_q);\n+\ttx_queue = &(tmp_qp->tx_q);\n+\thead = rx_queue->head;\n \tresp_msg = (struct icp_qat_fw_comn_resp *)\n-\t\t\t((uint8_t *)queue->base_addr + head);\n+\t\t\t((uint8_t *)rx_queue->base_addr + head);\n \n \twhile (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&\n \t\t\tmsg_counter != nb_ops) {\n@@ -1048,21 +1060,26 @@ qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n \t\t}\n \n-\t\thead = adf_modulo(head + queue->msg_size, queue->modulo);\n+\t\thead = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);\n \t\tresp_msg = (struct icp_qat_fw_comn_resp *)\n-\t\t\t\t((uint8_t *)queue->base_addr + head);\n+\t\t\t\t((uint8_t *)rx_queue->base_addr + head);\n \t\t*ops = rx_op;\n \t\tops++;\n \t\tmsg_counter++;\n \t}\n \tif (msg_counter > 0) {\n-\t\tqueue->head = head;\n+\t\trx_queue->head = head;\n \t\ttmp_qp->stats.dequeued_count += msg_counter;\n-\t\tqueue->nb_processed_responses += msg_counter;\n+\t\trx_queue->nb_processed_responses += msg_counter;\n \t\ttmp_qp->inflights16 -= msg_counter;\n \n-\t\tif (queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)\n-\t\t\trxq_free_desc(tmp_qp, queue);\n+\t\tif (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)\n+\t\t\trxq_free_desc(tmp_qp, rx_queue);\n+\t}\n+\t/* also check if tail needs to be advanced */\n+\tif (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&\n+\t\t\ttx_queue->tail != tx_queue->csr_tail) {\n+\t\ttxq_write_tail(tmp_qp, tx_queue);\n \t}\n \treturn msg_counter;\n }\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex d78957c..0ebb083 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -52,6 +52,10 @@\n \n #define QAT_CSR_HEAD_WRITE_THRESH 32U\n /* number of requests to accumulate before writing head CSR */\n+#define QAT_CSR_TAIL_WRITE_THRESH 32U\n+/* number of requests to accumulate before writing tail CSR */\n+#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U\n+/* number of inflights below which no tail write coalescing should occur */\n \n struct qat_session;\n \n@@ -77,8 +81,11 @@ struct qat_queue {\n \tuint8_t\t\thw_queue_number;\n \t/* HW queue aka ring offset on bundle */\n \tuint32_t\tcsr_head;\t\t/* last written head value */\n+\tuint32_t\tcsr_tail;\t\t/* last written tail value */\n \tuint16_t\tnb_processed_responses;\n \t/* number of responses processed since last CSR head write */\n+\tuint16_t\tnb_pending_requests;\n+\t/* number of requests pending since last CSR tail write */\n };\n \n struct qat_qp {\n", "prefixes": [ "dpdk-dev", "v2", "3/3" ] }