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GET /api/patches/28113/?format=api
{ "id": 28113, "url": "https://patches.dpdk.org/api/patches/28113/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20170831063719.19273-4-santosh.shukla@caviumnetworks.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20170831063719.19273-4-santosh.shukla@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20170831063719.19273-4-santosh.shukla@caviumnetworks.com", "date": "2017-08-31T06:37:12", "name": "[dpdk-dev,v2,03/10] mempool/octeontx: probe fpavf pcie devices", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3f63b92b988cb21be550677a426322cc5ddddaeb", "submitter": { "id": 480, "url": "https://patches.dpdk.org/api/people/480/?format=api", "name": "Santosh Shukla", "email": "santosh.shukla@caviumnetworks.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20170831063719.19273-4-santosh.shukla@caviumnetworks.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/28113/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/28113/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id A2190330D;\n\tThu, 31 Aug 2017 08:38:08 +0200 (CEST)", "from NAM01-BN3-obe.outbound.protection.outlook.com\n\t(mail-bn3nam01on0069.outbound.protection.outlook.com [104.47.33.69])\n\tby dpdk.org (Postfix) with ESMTP id 2EAB83251\n\tfor <dev@dpdk.org>; Thu, 31 Aug 2017 08:38:06 +0200 (CEST)", "from localhost.localdomain (111.93.218.67) by\n\tMWHPR07MB3104.namprd07.prod.outlook.com (10.172.95.10) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.13.10; Thu, 31 Aug 2017 06:38:01 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=qYfnw6t+Hbp4XRMKHIPOPWbXFJb2Z58GOMiUVmtKtHs=;\n\tb=NYMYp/Qccyugpi08eouxsqv8frqIG6xukGgzRJdUuQSyccpEVlS+6lhsPbnVYlcwN/h7ij5GSIIDIxw+Fl7bt9RV3mjo3/RCQtXkBFtYMXMXzkezDembcEUXO07T0hK07k1ZHIDeNuvaC+tmo23d43faEsu4nTxaPmA/Iv7UfaM=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Santosh.Shukla@cavium.com; ", "From": "Santosh Shukla <santosh.shukla@caviumnetworks.com>", "To": "dev@dpdk.org,\n\tolivier.matz@6wind.com", "Cc": "jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,\n\tthomas@monjalon.net, hemant.agrawal@nxp.com,\n\tSantosh Shukla <santosh.shukla@caviumnetworks.com>", "Date": "Thu, 31 Aug 2017 12:07:12 +0530", "Message-Id": "<20170831063719.19273-4-santosh.shukla@caviumnetworks.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170831063719.19273-1-santosh.shukla@caviumnetworks.com>", "References": "<20170824132903.32057-1-santosh.shukla@caviumnetworks.com>\n\t<20170831063719.19273-1-santosh.shukla@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[111.93.218.67]", "X-ClientProxiedBy": "PN1PR01CA0089.INDPRD01.PROD.OUTLOOK.COM (10.174.144.157)\n\tTo MWHPR07MB3104.namprd07.prod.outlook.com (10.172.95.10)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "f17c33b9-c64d-4f22-6cb0-08d4f03ad55a", "X-Microsoft-Antispam": "UriScan:; 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(10201501046)(100000703101)(100105400095)(93006095)(3002001)(6041248)(20161123564025)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123560025)(20161123562025)(20161123558100)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:MWHPR07MB3104; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:MWHPR07MB3104; ", "X-Forefront-PRVS": "04163EF38A", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(6009001)(6069001)(199003)(189002)(66066001)(6486002)(33646002)(50226002)(47776003)(6506006)(68736007)(36756003)(50986999)(101416001)(4326008)(76176999)(189998001)(25786009)(50466002)(48376002)(7736002)(5003940100001)(6512007)(105586002)(8656003)(478600001)(6666003)(2906002)(110136004)(107886003)(305945005)(53936002)(8676002)(42186005)(5009440100003)(72206003)(42882006)(2950100002)(1076002)(97736004)(81166006)(81156014)(8936002)(3846002)(6116002)(5660300001)(106356001);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR07MB3104; H:localhost.localdomain;\n\tFPR:; \n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Aug 2017 06:38:01.8074\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR07MB3104", "Subject": "[dpdk-dev] [PATCH v2 03/10] mempool/octeontx: probe fpavf pcie\n\tdevices", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "A mempool device is set of PCIe vfs.\nOn Octeontx HW, each mempool devices are enumerated as\nseparate SRIOV VF PCIe device.\n\nIn order to expose as a mempool device:\nOn PCIe probe, the driver stores the information associated with the\nPCIe device and later upon application pool request\n(e.g. rte_mempool_create_empty), Infrastructure creates a pool device\nwith earlier probed PCIe VF devices.\n\nSigned-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>\nSigned-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\n---\n drivers/mempool/octeontx/octeontx_fpavf.c | 151 ++++++++++++++++++++++++++++++\n drivers/mempool/octeontx/octeontx_fpavf.h | 39 ++++++++\n 2 files changed, 190 insertions(+)", "diff": "diff --git a/drivers/mempool/octeontx/octeontx_fpavf.c b/drivers/mempool/octeontx/octeontx_fpavf.c\nindex 9bb7759c0..0b4a9357f 100644\n--- a/drivers/mempool/octeontx/octeontx_fpavf.c\n+++ b/drivers/mempool/octeontx/octeontx_fpavf.c\n@@ -29,3 +29,154 @@\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n+\n+#include <stdlib.h>\n+#include <string.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <unistd.h>\n+#include <fcntl.h>\n+#include <errno.h>\n+#include <sys/mman.h>\n+\n+#include <rte_atomic.h>\n+#include <rte_eal.h>\n+#include <rte_pci.h>\n+#include <rte_errno.h>\n+#include <rte_memory.h>\n+#include <rte_malloc.h>\n+#include <rte_spinlock.h>\n+\n+#include \"octeontx_fpavf.h\"\n+\n+struct fpavf_res {\n+\tvoid\t\t*pool_stack_base;\n+\tvoid\t\t*bar0;\n+\tuint64_t\tstack_ln_ptr;\n+\tuint16_t\tdomain_id;\n+\tuint16_t\tvf_id;\t/* gpool_id */\n+\tuint16_t\tsz128;\t/* Block size in cache lines */\n+\tbool\t\tis_inuse;\n+};\n+\n+struct octeontx_fpadev {\n+\trte_spinlock_t lock;\n+\tuint8_t\ttotal_gpool_cnt;\n+\tstruct fpavf_res pool[FPA_VF_MAX];\n+};\n+\n+static struct octeontx_fpadev fpadev;\n+\n+static void\n+octeontx_fpavf_setup(void)\n+{\n+\tuint8_t i;\n+\tstatic bool init_once;\n+\n+\tif (!init_once) {\n+\t\trte_spinlock_init(&fpadev.lock);\n+\t\tfpadev.total_gpool_cnt = 0;\n+\n+\t\tfor (i = 0; i < FPA_VF_MAX; i++) {\n+\n+\t\t\tfpadev.pool[i].domain_id = ~0;\n+\t\t\tfpadev.pool[i].stack_ln_ptr = 0;\n+\t\t\tfpadev.pool[i].sz128 = 0;\n+\t\t\tfpadev.pool[i].bar0 = NULL;\n+\t\t\tfpadev.pool[i].pool_stack_base = NULL;\n+\t\t\tfpadev.pool[i].is_inuse = false;\n+\t\t}\n+\t\tinit_once = 1;\n+\t}\n+}\n+\n+static int\n+octeontx_fpavf_identify(void *bar0)\n+{\n+\tuint64_t val;\n+\tuint16_t domain_id;\n+\tuint16_t vf_id;\n+\tuint64_t stack_ln_ptr;\n+\n+\tval = fpavf_read64((void *)((uintptr_t)bar0 +\n+\t\t\t\tFPA_VF_VHAURA_CNT_THRESHOLD(0)));\n+\n+\tdomain_id = (val >> 8) & 0xffff;\n+\tvf_id = (val >> 24) & 0xffff;\n+\n+\tstack_ln_ptr = fpavf_read64((void *)((uintptr_t)bar0 +\n+\t\t\t\t\tFPA_VF_VHPOOL_THRESHOLD(0)));\n+\tif (vf_id >= FPA_VF_MAX) {\n+\t\tfpavf_log_err(\"vf_id(%d) greater than max vf (32)\\n\", vf_id);\n+\t\treturn -1;\n+\t}\n+\n+\tif (fpadev.pool[vf_id].is_inuse) {\n+\t\tfpavf_log_err(\"vf_id %d is_inuse\\n\", vf_id);\n+\t\treturn -1;\n+\t}\n+\n+\tfpadev.pool[vf_id].domain_id = domain_id;\n+\tfpadev.pool[vf_id].vf_id = vf_id;\n+\tfpadev.pool[vf_id].bar0 = bar0;\n+\tfpadev.pool[vf_id].stack_ln_ptr = stack_ln_ptr;\n+\n+\t/* SUCCESS */\n+\treturn vf_id;\n+}\n+\n+/* FPAVF pcie device aka mempool probe */\n+static int\n+fpavf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tuint8_t *idreg;\n+\tint res;\n+\tstruct fpavf_res *fpa;\n+\n+\tRTE_SET_USED(pci_drv);\n+\tRTE_SET_USED(fpa);\n+\n+\t/* For secondary processes, the primary has done all the work */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (pci_dev->mem_resource[0].addr == NULL) {\n+\t\tfpavf_log_err(\"Empty bars %p \", pci_dev->mem_resource[0].addr);\n+\t\treturn -ENODEV;\n+\t}\n+\tidreg = pci_dev->mem_resource[0].addr;\n+\n+\tocteontx_fpavf_setup();\n+\n+\tres = octeontx_fpavf_identify(idreg);\n+\tif (res < 0)\n+\t\treturn -1;\n+\n+\tfpa = &fpadev.pool[res];\n+\tfpadev.total_gpool_cnt++;\n+\trte_wmb();\n+\n+\tfpavf_log_dbg(\"total_fpavfs %d bar0 %p domain %d vf %d stk_ln_ptr 0x%x\",\n+\t\t fpadev.total_gpool_cnt, fpa->bar0, fpa->domain_id,\n+\t\t fpa->vf_id, (unsigned int)fpa->stack_ln_ptr);\n+\n+\treturn 0;\n+}\n+\n+static const struct rte_pci_id pci_fpavf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t\tPCI_DEVICE_ID_OCTEONTX_FPA_VF)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct rte_pci_driver pci_fpavf = {\n+\t.id_table = pci_fpavf_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,\n+\t.probe = fpavf_probe,\n+};\n+\n+RTE_PMD_REGISTER_PCI(octeontx_fpavf, pci_fpavf);\ndiff --git a/drivers/mempool/octeontx/octeontx_fpavf.h b/drivers/mempool/octeontx/octeontx_fpavf.h\nindex 1c703725c..c43b1a7d2 100644\n--- a/drivers/mempool/octeontx/octeontx_fpavf.h\n+++ b/drivers/mempool/octeontx/octeontx_fpavf.h\n@@ -34,6 +34,7 @@\n #define\t__OCTEONTX_FPAVF_H__\n \n #include <rte_debug.h>\n+#include <rte_io.h>\n \n #ifdef RTE_LIBRTE_OCTEONTX_MEMPOOL_DEBUG\n #define fpavf_log_info(fmt, args...) \\\n@@ -87,4 +88,42 @@\n #define\tFPA_VF0_APERTURE_SHIFT\t\t22\n #define FPA_AURA_SET_SIZE\t\t16\n \n+\n+/*\n+ * In Cavium OcteonTX SoC, all accesses to the device registers are\n+ * implictly strongly ordered. So, The relaxed version of IO operation is\n+ * safe to use with out any IO memory barriers.\n+ */\n+#define fpavf_read64 rte_read64_relaxed\n+#define fpavf_write64 rte_write64_relaxed\n+\n+/* ARM64 specific functions */\n+#if defined(RTE_ARCH_ARM64)\n+#define fpavf_load_pair(val0, val1, addr) ({\t\t\\\n+\t\t\tasm volatile(\t\t\t\\\n+\t\t\t\"ldp %x[x0], %x[x1], [%x[p1]]\"\t\\\n+\t\t\t:[x0]\"=r\"(val0), [x1]\"=r\"(val1) \\\n+\t\t\t:[p1]\"r\"(addr)\t\t\t\\\n+\t\t\t); })\n+\n+#define fpavf_store_pair(val0, val1, addr) ({\t\t\\\n+\t\t\tasm volatile(\t\t\t\\\n+\t\t\t\"stp %x[x0], %x[x1], [%x[p1]]\"\t\\\n+\t\t\t::[x0]\"r\"(val0), [x1]\"r\"(val1), [p1]\"r\"(addr) \\\n+\t\t\t); })\n+#else /* Un optimized functions for building on non arm64 arch */\n+\n+#define fpavf_load_pair(val0, val1, addr)\t\t\\\n+do {\t\t\t\t\t\t\t\\\n+\tval0 = rte_read64(addr);\t\t\t\\\n+\tval1 = rte_read64(((uint8_t *)addr) + 8);\t\\\n+} while (0)\n+\n+#define fpavf_store_pair(val0, val1, addr)\t\t\\\n+do {\t\t\t\t\t\t\t\\\n+\trte_write64(val0, addr);\t\t\t\\\n+\trte_write64(val1, (((uint8_t *)addr) + 8));\t\\\n+} while (0)\n+#endif\n+\n #endif\t/* __OCTEONTX_FPAVF_H__ */\n", "prefixes": [ "dpdk-dev", "v2", "03/10" ] }