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GET /api/patches/28075/?format=api
{ "id": 28075, "url": "https://patches.dpdk.org/api/patches/28075/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/22e16781b4231bc202a377f95e51cdeb999598bf.1504076528.git.shahafs@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<22e16781b4231bc202a377f95e51cdeb999598bf.1504076528.git.shahafs@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/22e16781b4231bc202a377f95e51cdeb999598bf.1504076528.git.shahafs@mellanox.com", "date": "2017-08-30T07:07:08", "name": "[dpdk-dev,v2,2/2] net/mlx5: enforce Tx num of segments limitation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "759a92534368a26bc705cf87eafae59256572b48", "submitter": { "id": 634, "url": "https://patches.dpdk.org/api/people/634/?format=api", "name": "Shahaf Shuler", "email": "shahafs@mellanox.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/22e16781b4231bc202a377f95e51cdeb999598bf.1504076528.git.shahafs@mellanox.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/28075/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/28075/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 872C22C2E;\n\tWed, 30 Aug 2017 09:07:25 +0200 (CEST)", "from EUR02-VE1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr20052.outbound.protection.outlook.com [40.107.2.52])\n\tby dpdk.org (Postfix) with ESMTP id 28E0011D4;\n\tWed, 30 Aug 2017 09:07:22 +0200 (CEST)", "from mellanox.com (82.166.227.17) by\n\tAM4PR05MB3138.eurprd05.prod.outlook.com (2603:10a6:205:3::15) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1385.9;\n\tWed, 30 Aug 2017 07:07:19 +0000" ], "DKIM-Signature": "v=1; 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SFP:1101; SCL:1; SRVR:AM4PR05MB3138; H:mellanox.com; FPR:;\n\tSPF:None; \n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: mellanox.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Aug 2017 07:07:19.8521\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM4PR05MB3138", "Subject": "[dpdk-dev] [PATCH v2 2/2] net/mlx5: enforce Tx num of segments\n\tlimitation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Mellanox NICs has a limitation on the number of mbuf segments a multi\nsegment mbuf can have. The max number depends on the Tx offloads requested.\n\nThe current code not enforce such limitation, which might cause\nmalformed work requests to be written to the device.\n\nThis commit adds verification for the number of mbuf segments posted\nto the device. In case of overflow the packet will not be sent.\nDebug prints were added to help application identify the cause for such\ncase.\n\nIn addition update the nic documentation with the limitation.\nConsidering device limitation is 63 data segments in a work request, the\nmaximum number of segment in mbuf was calculated taking TSO as the worst\ncase:\n\nmax_nb_segs = 63 - (control_segment + ethernet segment +\n\t\t TSO headers inline + inline segment +\n\t\t extra inline to align to cacheline)\n\nCc: stable@dpdk.org\n\nSigned-off-by: Shahaf Shuler <shahafs@mellanox.com>\n---\nThis patch should be applied only after the series:\nhttp://dpdk.org/dev/patchwork/patch/27367/\n\non v2:\n - remove parenthesis around MLX5_MAX_DS.\n - add limitation to nic guide.\n - update commit message.\n - fix typo.\n---\n doc/guides/nics/mlx5.rst | 2 ++\n drivers/net/mlx5/mlx5_defs.h | 3 ++-\n drivers/net/mlx5/mlx5_prm.h | 3 +++\n drivers/net/mlx5/mlx5_rxtx.c | 30 +++++++++++++++++++++++++++---\n drivers/net/mlx5/mlx5_rxtx_vec_sse.c | 8 ++++++++\n drivers/net/mlx5/mlx5_txq.c | 27 +++++++++++++++++++++++++++\n 6 files changed, 69 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex f4cb18bca..d8244de97 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -124,6 +124,8 @@ Limitations\n \n Will match any ipv4 packet (VLAN included).\n \n+- A multi segment mbuf must have less than 50 segments. That means mbuf->nb_segs < 50.\n+\n Configuration\n -------------\n \ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex a76bc6f65..3de0e5d81 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -100,7 +100,8 @@\n \n /*\n * Maximum size of burst for vectorized Tx. This is related to the maximum size\n- * of Enhaned MPW (eMPW) WQE as vectorized Tx is supported with eMPW.\n+ * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW.\n+ * Careful when changing, large value can cause wqe DS to overlap.\n */\n #define MLX5_VPMD_TX_MAX_BURST 32U\n \ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 608072f7e..bc2b72333 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -154,6 +154,9 @@\n /* Default mark value used when none is provided. */\n #define MLX5_FLOW_MARK_DEFAULT 0xffffff\n \n+/* Maximum number of DS in WQE. */\n+#define MLX5_MAX_DS 63\n+\n /* Subset of struct mlx5_wqe_eth_seg. */\n struct mlx5_wqe_eth_seg_small {\n \tuint32_t rsvd0;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex fe9e7eac0..d7aa382f9 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -657,6 +657,15 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\telse\n \t\t\tj += sg;\n next_pkt:\n+\t\tif (ds > MLX5_MAX_DS) {\n+#ifndef NDEBUG\n+\t\t\tWARN(\"Cannot send packet %p with %d segments \"\n+\t\t\t \"wqe.ds = %d, wqe.inline_sz = %d\",\n+\t\t\t (void *)pkts, (*pkts)->nb_segs, ds,\n+\t\t\t pkt_inline_sz);\n+#endif\n+\t\t\tbreak;\n+\t\t}\n \t\t++elts_head;\n \t\t++pkts;\n \t\t++i;\n@@ -843,8 +852,13 @@ mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\tif (max_elts < segs_n)\n \t\t\tbreak;\n \t\t/* Do not bother with large packets MPW cannot handle. */\n-\t\tif (segs_n > MLX5_MPW_DSEG_MAX)\n+\t\tif (segs_n > MLX5_MPW_DSEG_MAX) {\n+#ifndef NDEBUG\n+\t\t\tWARN(\"Cannot send packet %p with %d segments\",\n+\t\t\t (void *)buf, segs_n);\n+#endif\n \t\t\tbreak;\n+\t\t}\n \t\tmax_elts -= segs_n;\n \t\t--pkts_n;\n \t\t/* Should we enable HW CKSUM offload */\n@@ -1064,8 +1078,13 @@ mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,\n \t\tif (max_elts < segs_n)\n \t\t\tbreak;\n \t\t/* Do not bother with large packets MPW cannot handle. */\n-\t\tif (segs_n > MLX5_MPW_DSEG_MAX)\n+\t\tif (segs_n > MLX5_MPW_DSEG_MAX) {\n+#ifndef NDEBUG\n+\t\t\tWARN(\"Cannot send packet %p with %d segments\",\n+\t\t\t (void *)buf, segs_n);\n+#endif\n \t\t\tbreak;\n+\t\t}\n \t\tmax_elts -= segs_n;\n \t\t--pkts_n;\n \t\t/*\n@@ -1353,8 +1372,13 @@ mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\tif (max_elts - j < segs_n)\n \t\t\tbreak;\n \t\t/* Do not bother with large packets MPW cannot handle. */\n-\t\tif (segs_n > MLX5_MPW_DSEG_MAX)\n+\t\tif (segs_n > MLX5_MPW_DSEG_MAX) {\n+#ifndef NDEBUG\n+\t\t\tWARN(\"Cannot send packet %p with %d segments\",\n+\t\t\t (void *)buf, segs_n);\n+#endif\n \t\t\tbreak;\n+\t\t}\n \t\t/* Should we enable HW CKSUM offload. */\n \t\tif (buf->ol_flags &\n \t\t (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.c b/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\nindex f89762ff8..9d6f6df32 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\n@@ -248,6 +248,13 @@ txq_scatter_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\tif (segs_n == 1 ||\n \t\t max_elts < segs_n || max_wqe < 2)\n \t\t\tbreak;\n+\t\tif (segs_n > MLX5_MPW_DSEG_MAX) {\n+#ifndef NDEBUG\n+\t\t\tWARN(\"Cannot send packet %p with %d segments\",\n+\t\t\t (void *)buf, segs_n);\n+#endif\n+\t\t\tbreak;\n+\t\t}\n \t\twqe = &((volatile struct mlx5_wqe64 *)\n \t\t\t txq->wqes)[wqe_ci & wq_mask].hdr;\n \t\tif (buf->ol_flags &\n@@ -365,6 +372,7 @@ txq_burst_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,\n \tmax_elts = (elts_n - (elts_head - txq->elts_tail));\n \tmax_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);\n \tpkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);\n+\tassert(pkts_n <= MLX5_MAX_DS - nb_dword_in_hdr);\n \tif (unlikely(!pkts_n))\n \t\treturn 0;\n \telts = &(*txq->elts)[elts_head & elts_m];\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 4b0b532b1..091b1a93d 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -288,6 +288,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\t.comp_mask = IBV_EXP_QP_INIT_ATTR_PD,\n \t};\n \tif (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {\n+\t\tunsigned int ds_cnt;\n+\n \t\ttmpl.txq.max_inline =\n \t\t\t((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /\n \t\t\t RTE_CACHE_LINE_SIZE);\n@@ -320,6 +322,31 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\t\tattr.init.cap.max_inline_data =\n \t\t\t\ttmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;\n \t\t}\n+\t\t/*\n+\t\t * Check if the inline size is too large in a way which\n+\t\t * can make the wqe DS to overflow.\n+\t\t * Considering in calculation:\n+\t\t *\tWQE CTRL (1 DS)\n+\t\t *\tWQE ETH (1 DS)\n+\t\t *\tinline part (N DS)\n+\t\t */\n+\t\tds_cnt = 2 +\n+\t\t\t(attr.init.cap.max_inline_data / MLX5_WQE_DWORD_SIZE);\n+\t\tif (ds_cnt > MLX5_MAX_DS) {\n+\t\t\tunsigned int max_inline = (MLX5_MAX_DS - 2) *\n+\t\t\t\t\t\t MLX5_WQE_DWORD_SIZE;\n+\n+\t\t\t/* Ceil down*/\n+\t\t\tmax_inline = max_inline - (max_inline %\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\t\tWARN(\"txq inline is too large (%d) setting it to \"\n+\t\t\t \"the maximum possible: %d\\n\",\n+\t\t\t priv->txq_inline, max_inline);\n+\t\t\ttmpl.txq.max_inline = max_inline / RTE_CACHE_LINE_SIZE;\n+\t\t\tattr.init.cap.max_inline_data = max_inline;\n+\t\t\tif (priv->mps == MLX5_MPW_ENHANCED)\n+\t\t\t\ttmpl.txq.inline_max_packet_sz = max_inline;\n+\t\t}\n \t}\n \tif (priv->tso) {\n \t\tattr.init.max_tso_header =\n", "prefixes": [ "dpdk-dev", "v2", "2/2" ] }