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GET /api/patches/28040/?format=api
{ "id": 28040, "url": "https://patches.dpdk.org/api/patches/28040/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20170829014654.36240-1-wei.zhao1@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20170829014654.36240-1-wei.zhao1@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20170829014654.36240-1-wei.zhao1@intel.com", "date": "2017-08-29T01:46:54", "name": "[dpdk-dev,1/2] net/i40e: queue region set and flush", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3f599b0ce32648e95ba384c8eafad2cd677b5cfb", "submitter": { "id": 495, "url": "https://patches.dpdk.org/api/people/495/?format=api", "name": "Zhao1, Wei", "email": "wei.zhao1@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20170829014654.36240-1-wei.zhao1@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/28040/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/28040/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1D559101B;\n\tTue, 29 Aug 2017 03:52:54 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 1C4E11F5\n\tfor <dev@dpdk.org>; Tue, 29 Aug 2017 03:52:51 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Aug 2017 18:52:51 -0700", "from dpdk2.bj.intel.com ([172.16.182.198])\n\tby fmsmga002.fm.intel.com with ESMTP; 28 Aug 2017 18:52:50 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.41,443,1498546800\"; d=\"scan'208\";\n\ta=\"1211732285\"", "From": "Wei Zhao <wei.zhao1@intel.com>", "To": "dev@dpdk.org", "Cc": "root <root@dpdk2.bj.intel.com>,\n\tWei Zhao <wei.zhao1@intel.com>", "Date": "Tue, 29 Aug 2017 09:46:54 +0800", "Message-Id": "<20170829014654.36240-1-wei.zhao1@intel.com>", "X-Mailer": "git-send-email 2.9.3", "Subject": "[dpdk-dev] [PATCH 1/2] net/i40e: queue region set and flush", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: root <root@dpdk2.bj.intel.com>\n\nThis feature enable queue regions configuration for RSS in PF/VF,\nso that different traffic classes or different packet\nclassification types can be separated to different queues in\ndifferent queue regions.This patch can set queue region range,\nit include queue number in a region and the index of first queue.\nThis patch enable mapping between different priorities (UP) and\ndifferent traffic classes.It also enable mapping between a region\nindex and a sepcific flowtype(PCTYPE).It also provide the solution\nof flush all configuration about queue region the above described.\n\nSigned-off-by: Wei Zhao <wei.zhao1@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.h | 6 +\n drivers/net/i40e/rte_pmd_i40e.c | 287 ++++++++++++++++++++++++++++++\n drivers/net/i40e/rte_pmd_i40e.h | 39 ++++\n drivers/net/i40e/rte_pmd_i40e_version.map | 7 +\n 4 files changed, 339 insertions(+)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 48abc05..1d6e9b2 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -260,6 +260,12 @@ enum i40e_flxpld_layer_idx {\n #define I40E_QOS_BW_WEIGHT_MIN 1\n /* The max bandwidth weight is 127. */\n #define I40E_QOS_BW_WEIGHT_MAX 127\n+/* The max queue region index is 7. */\n+#define I40E_TCREGION_MAX_INDEX 7\n+/* The max queue region userpriority is 7. */\n+#define I40E_REGION_USERPRIORITY_MAX_INDEX 7\n+/* The max pctype index is 63. */\n+#define I40E_REGION_PCTYPE_MAX_INDEX 63\n \n /**\n * The overhead from MTU to max frame size.\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c\nindex 950a0d6..5d1e1d4 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.c\n+++ b/drivers/net/i40e/rte_pmd_i40e.c\n@@ -2117,3 +2117,290 @@ int rte_pmd_i40e_ptype_mapping_replace(uint8_t port,\n \n \treturn 0;\n }\n+\n+static int\n+i40e_set_queue_region(struct i40e_hw *hw, struct i40e_pf *pf,\n+\t\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tuint32_t TCREGION, TC_OFFSET, TC_SIZE;\n+\tuint16_t TC_SIZE_TB[7] = {1, 2, 4, 8, 16, 32, 64};\n+\tuint16_t i, index;\n+\tuint16_t main_vsi_seid = pf->main_vsi_seid;\n+\tstruct i40e_vsi *main_vsi = pf->main_vsi;\n+\tuint32_t ret = -EINVAL;\n+\n+\tindex = conf_ptr->region_id >> 1;\n+\tfor (i = 0; i < I40E_TCREGION_MAX_INDEX; i++)\n+\t\tif (conf_ptr->queue_num == TC_SIZE_TB[i])\n+\t\t\tbreak;\n+\n+\tif (i == I40E_TCREGION_MAX_INDEX) {\n+\t\tprintf(\"The region sizes should be any of the following \"\n+\t\t\"values: 1, 2, 4, 8, 16, 32, 64 as long as the \"\n+\t\t\"total number of queues do not exceed the VSI allocation\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->region_id >= I40E_TCREGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif ((conf_ptr->queue_startIndex + conf_ptr->queue_num)\n+\t\t\t\t\t> main_vsi->nb_qps) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue index exceeds the VSI range\");\n+\t\treturn ret;\n+\t}\n+\n+\tTCREGION = i40e_read_rx_ctl(hw,\n+\t\t\t\tI40E_VSIQF_TCREGION(index, main_vsi_seid));\n+\tif ((conf_ptr->region_id & 1) == 0) {\n+\t\tTC_OFFSET = (conf_ptr->queue_startIndex <<\n+\t\t\t\t\tI40E_VSIQF_TCREGION_TC_OFFSET_SHIFT) &\n+\t\t\t\t\tI40E_VSIQF_TCREGION_TC_OFFSET_MASK;\n+\t\tTC_SIZE = i << I40E_VSIQF_TCREGION_TC_SIZE_SHIFT;\n+\t} else {\n+\t\tTC_OFFSET = (conf_ptr->queue_startIndex <<\n+\t\t\t\t\tI40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT) &\n+\t\t\t\t\tI40E_VSIQF_TCREGION_TC_OFFSET2_MASK;\n+\t\tTC_SIZE = i << I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT;\n+\t}\n+\tTCREGION |= TC_OFFSET;\n+\tTCREGION |= TC_SIZE;\n+\ti40e_write_rx_ctl(hw, I40E_VSIQF_TCREGION(index, main_vsi_seid),\n+\t\t\t\t\t\tTCREGION);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_region_flowtype_pf(struct i40e_hw *hw,\n+\t\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tuint32_t PFQF_HREGION;\n+\tuint32_t ret = -EINVAL;\n+\tuint16_t index;\n+\n+\tif (conf_ptr->region_id > I40E_PFQF_HREGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->flowtype >= I40E_FILTER_PCTYPE_MAX) {\n+\t\tPMD_INIT_LOG(ERR, \"the flowtype or PCTYPE max index is 63\");\n+\t\treturn ret;\n+\t}\n+\n+\tindex = conf_ptr->flowtype >> 3;\n+\tPFQF_HREGION = i40e_read_rx_ctl(hw, I40E_PFQF_HREGION(index));\n+\n+\tif ((conf_ptr->flowtype & 0x7) == 0) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_0_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 1) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_1_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 2) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_2_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 3) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_3_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 4) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_4_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 5) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_5_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 6) {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_6_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT;\n+\t} else {\n+\t\tPFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_7_SHIFT;\n+\t\tPFQF_HREGION |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT;\n+\t}\n+\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HREGION(index), PFQF_HREGION);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_region_flowtype_vf(struct i40e_hw *hw,\n+\t\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tuint32_t VFQF_HREGION;\n+\tuint32_t ret = -EINVAL;\n+\tuint16_t index;\n+\n+\tif (conf_ptr->region_id > I40E_VFQF_HREGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->flowtype > I40E_REGION_PCTYPE_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the flowtype or PCTYPE max index is 63\");\n+\t\treturn ret;\n+\t}\n+\n+\tindex = conf_ptr->flowtype >> 3;\n+\tVFQF_HREGION = i40e_read_rx_ctl(hw, I40E_VFQF_HREGION(index));\n+\n+\tif ((conf_ptr->flowtype & 0x7) == 0) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_0_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 1) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_1_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 2) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_2_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 3) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_3_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 4) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_4_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 5) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_5_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT;\n+\t} else if ((conf_ptr->flowtype & 0x7) == 6) {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_6_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT;\n+\t} else {\n+\t\tVFQF_HREGION |= conf_ptr->region_id <<\n+\t\t\t\tI40E_VFQF_HREGION_REGION_7_SHIFT;\n+\t\tVFQF_HREGION |= 1 << I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT;\n+\t}\n+\n+\ti40e_write_rx_ctl(hw, I40E_VFQF_HREGION(index), VFQF_HREGION);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_up_tc(struct i40e_hw *hw,\n+\t\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tuint32_t PRTDCB_RUP2TC;\n+\tuint32_t ret = -EINVAL;\n+\n+\tif (conf_ptr->UserPriority > I40E_REGION_USERPRIORITY_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->TrafficClasses >= I40E_TCREGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the TrafficClasses max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tPRTDCB_RUP2TC = I40E_READ_REG(hw, I40E_PRTDCB_RUP2TC);\n+\tif (conf_ptr->UserPriority == 0)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP0TC_SHIFT;\n+\telse if (conf_ptr->UserPriority == 1)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP1TC_SHIFT;\n+\telse if (conf_ptr->UserPriority == 2)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP2TC_SHIFT;\n+\telse if (conf_ptr->UserPriority == 3)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP3TC_SHIFT;\n+\telse if (conf_ptr->UserPriority == 4)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP4TC_SHIFT;\n+\telse if (conf_ptr->UserPriority == 5)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP5TC_SHIFT;\n+\telse if (conf_ptr->UserPriority == 6)\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP6TC_SHIFT;\n+\telse\n+\t\tPRTDCB_RUP2TC |= conf_ptr->TrafficClasses <<\n+\t\t\t\tI40E_PRTDCB_RUP2TC_UP7TC_SHIFT;\n+\n+\tI40E_WRITE_REG(hw, I40E_PRTDCB_RUP2TC, PRTDCB_RUP2TC);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_flush_region_all_conf(struct i40e_hw *hw, struct i40e_pf *pf)\n+{\n+\tuint32_t SET_ZERO = 0;\n+\tuint16_t i;\n+\tuint16_t main_vsi_seid = pf->main_vsi_seid;\n+\n+\tI40E_WRITE_REG(hw, I40E_PRTDCB_RUP2TC, SET_ZERO);\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\ti40e_write_rx_ctl(hw, I40E_VSIQF_TCREGION(i, main_vsi_seid),\n+\t\t\t\t\t\tSET_ZERO);\n+\n+\tfor (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)\n+\t\ti40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), SET_ZERO);\n+\n+\tfor (i = 0; i < I40E_VFQF_HREGION_MAX_INDEX; i++)\n+\t\ti40e_write_rx_ctl(hw, I40E_VFQF_HREGION(i), SET_ZERO);\n+\n+\treturn 0;\n+}\n+\n+int rte_pmd_i40e_queue_region_conf(uint8_t port,\n+\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tstruct rte_eth_dev *dev = &rte_eth_devices[port];\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tenum rte_pmd_i40e_queue_region_op op_type = conf_ptr->op;\n+\tuint32_t ret;\n+\n+\tif (!is_i40e_supported(dev))\n+\t\treturn -ENOTSUP;\n+\n+\tswitch (op_type) {\n+\tcase RTE_PMD_I40E_QUEUE_REGION_SET:\n+\t\tret = i40e_set_queue_region(hw, pf, conf_ptr);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_REGION_FLOWTYPE_PF_SET:\n+\t\tret = i40e_set_region_flowtype_pf(hw, conf_ptr);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_REGION_FLOWTYPE_VF_SET:\n+\t\tret = i40e_set_region_flowtype_vf(hw, conf_ptr);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_UP_TC_SET:\n+\t\tret = i40e_set_up_tc(hw, conf_ptr);\n+\t\tbreak;\n+\n+\tcase RTE_PMD_I40E_REGION_ALL_FLUSH:\n+\t\tret = i40e_flush_region_all_conf(hw, pf);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tPMD_DRV_LOG(WARNING, \"op type (%d) not supported\",\n+\t\t\t op_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn ret;\n+}\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.h b/drivers/net/i40e/rte_pmd_i40e.h\nindex 356fa89..e85997a 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.h\n+++ b/drivers/net/i40e/rte_pmd_i40e.h\n@@ -91,6 +91,19 @@ enum rte_pmd_i40e_package_info {\n \tRTE_PMD_I40E_PKG_INFO_MAX = 0xFFFFFFFF\n };\n \n+/**\n+ * Option types of queue region.\n+ */\n+enum rte_pmd_i40e_queue_region_op {\n+\tRTE_PMD_I40E_REGION_UNDEFINED = 0,\n+\tRTE_PMD_I40E_QUEUE_REGION_SET, /**< add queue region set*/\n+\tRTE_PMD_I40E_REGION_FLOWTYPE_PF_SET, /**< add pf region pctype set */\n+\tRTE_PMD_I40E_REGION_FLOWTYPE_VF_SET, /**< add vf region pctype set */\n+\tRTE_PMD_I40E_UP_TC_SET, /**< add queue region pctype set */\n+\tRTE_PMD_I40E_REGION_ALL_FLUSH, /**< flush all configuration */\n+\tRTE_PMD_I40E_QUEUE_REGION_OP_MAX\n+};\n+\n #define RTE_PMD_I40E_DDP_NAME_SIZE 32\n \n /**\n@@ -146,6 +159,19 @@ struct rte_pmd_i40e_ptype_mapping {\n };\n \n /**\n+ * Queue region information get from CLI.\n+ */\n+struct rte_i40e_rss_region_conf {\n+\tuint8_t region_id;\n+\tuint8_t flowtype;\n+\tuint8_t queue_startIndex;\n+\tuint8_t queue_num;\n+\tuint8_t UserPriority;\n+\tuint8_t TrafficClasses;\n+\tenum rte_pmd_i40e_queue_region_op op;\n+};\n+\n+/**\n * Notify VF when PF link status changes.\n *\n * @param port\n@@ -637,4 +663,17 @@ int rte_pmd_i40e_ptype_mapping_replace(uint8_t port,\n \t\t\t\t uint8_t mask,\n \t\t\t\t uint32_t pkt_type);\n \n+/**\n+ * Get RSS queue region info from CLI and do configuration for\n+ * that port as the command otion type\n+ *\n+ * @param port\n+ * pointer to port identifier of the device\n+ * @param conf_ptr\n+ * pointer to the struct that contain all the\n+ * region configuration parameters\n+ */\n+int rte_pmd_i40e_queue_region_conf(uint8_t port,\n+\t\tstruct rte_i40e_rss_region_conf *conf_ptr);\n+\n #endif /* _PMD_I40E_H_ */\ndiff --git a/drivers/net/i40e/rte_pmd_i40e_version.map b/drivers/net/i40e/rte_pmd_i40e_version.map\nindex 20cc980..77ac385 100644\n--- a/drivers/net/i40e/rte_pmd_i40e_version.map\n+++ b/drivers/net/i40e/rte_pmd_i40e_version.map\n@@ -45,3 +45,10 @@ DPDK_17.08 {\n \trte_pmd_i40e_get_ddp_info;\n \n } DPDK_17.05;\n+\n+DPDK_17.11 {\n+\tglobal:\n+\n+\trte_pmd_i40e_queue_region_conf;\n+\n+} DPDK_17.08;\n", "prefixes": [ "dpdk-dev", "1/2" ] }