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GET /api/patches/27958/?format=api
{ "id": 27958, "url": "https://patches.dpdk.org/api/patches/27958/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1503658183-4078-4-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1503658183-4078-4-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1503658183-4078-4-git-send-email-hemant.agrawal@nxp.com", "date": "2017-08-25T10:49:19", "name": "[dpdk-dev,03/27] bus/fslmc: add qbman API to do enqueue with multiple frames", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "889a2d7690041a421237f98ff2c963de9929a8b4", "submitter": { "id": 477, "url": "https://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1503658183-4078-4-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/27958/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/27958/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D1CB890F5;\n\tFri, 25 Aug 2017 12:50:11 +0200 (CEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0062.outbound.protection.outlook.com\n\t[104.47.37.62]) by dpdk.org (Postfix) with ESMTP id CB2337D9F\n\tfor <dev@dpdk.org>; Fri, 25 Aug 2017 12:50:09 +0200 (CEST)", "from CY1PR03CA0007.namprd03.prod.outlook.com (2603:10b6:600::17) by\n\tBL2PR03MB547.namprd03.prod.outlook.com (2a01:111:e400:c23::20) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1385.9;\n\tFri, 25 Aug 2017 10:50:07 +0000", "from BL2FFO11FD033.protection.gbl (2a01:111:f400:7c09::189) by\n\tCY1PR03CA0007.outlook.office365.com (2603:10b6:600::17) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1385.9 via Frontend Transport; Fri, 25 Aug 2017 10:50:07 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11FD033.mail.protection.outlook.com (10.173.161.129) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.1341.15 via Frontend Transport; Fri, 25 Aug 2017 10:50:06 +0000", "from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net\n\t[10.232.134.28])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv7PAnw67032070; Fri, 25 Aug 2017 03:50:05 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <shreyansh.jain@nxp.com>", "Date": "Fri, 25 Aug 2017 16:19:19 +0530", "Message-ID": "<1503658183-4078-4-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503658183-4078-1-git-send-email-hemant.agrawal@nxp.com>", "References": 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"5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL2PR03MB547", "Subject": "[dpdk-dev] [PATCH 03/27] bus/fslmc: add qbman API to do enqueue\n\twith multiple frames", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Haiying Wang <Haiying.Wang@nxp.com>\n\nClean it up and update the prototype.\n\nSigned-off-by: Haiying Wang <Haiying.Wang@nxp.com>\nSigned-off-by: Hemant Agrawal <Hemant.Agrawal@nxp.com>\n---\n drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h | 32 ++--\n drivers/bus/fslmc/qbman/qbman_portal.c | 200 +++++++--------------\n drivers/bus/fslmc/rte_bus_fslmc_version.map | 3 +-\n drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 2 +-\n drivers/event/dpaa2/dpaa2_eventdev.c | 2 +-\n drivers/net/dpaa2/dpaa2_rxtx.c | 2 +-\n 6 files changed, 83 insertions(+), 158 deletions(-)", "diff": "diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\nindex 23c3d13..fe1cc94 100644\n--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n@@ -914,19 +914,33 @@ void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,\n int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,\n \t\t const struct qbman_fd *fd);\n /**\n- * qbman_swp_enqueue_multiple_eqdesc() - Enqueue multiple frames with separte\n- * enqueue descriptors.\n+ * qbman_swp_enqueue_multiple() - Enqueue multiple frames with same\n+\t\t\t\t eq descriptor\n * @s: the software portal used for enqueue.\n- * @d: the enqueue descriptors\n+ * @d: the enqueue descriptor.\n * @fd: the frame descriptor to be enqueued.\n * @num_frames: the number of the frames to be enqueued.\n *\n * Return the number of enqueued frames, -EBUSY if the EQCR is not ready.\n */\n-int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,\n+int qbman_swp_enqueue_multiple(struct qbman_swp *s,\n \t\t\t const struct qbman_eq_desc *d,\n \t\t\t const struct qbman_fd *fd,\n \t\t\t int num_frames);\n+/**\n+ * qbman_swp_enqueue_multiple_desc() - Enqueue multiple frames with\n+ *\t\t\t\t individual eq descriptor.\n+ * @s: the software portal used for enqueue.\n+ * @d: the enqueue descriptor.\n+ * @fd: the frame descriptor to be enqueued.\n+ * @num_frames: the number of the frames to be enqueued.\n+ *\n+ * Return the number of enqueued frames, -EBUSY if the EQCR is not ready.\n+ */\n+int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,\n+\t\t\t\t const struct qbman_eq_desc *d,\n+\t\t\t\t const struct qbman_fd *fd,\n+\t\t\t\t int num_frames);\n \n /* TODO:\n * qbman_swp_enqueue_thresh() - Set threshold for EQRI interrupt.\n@@ -1119,16 +1133,6 @@ int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid);\n */\n int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,\n \t\t\t\t uint64_t ctx);\n-int qbman_swp_fill_ring(struct qbman_swp *s,\n-\t\t\tconst struct qbman_eq_desc *d,\n-\t\t const struct qbman_fd *fd,\n-\t\t uint8_t burst_index);\n-int qbman_swp_flush_ring(struct qbman_swp *s);\n-void qbman_sync(void);\n-int qbman_swp_send_multiple(struct qbman_swp *s,\n-\t\t\t const struct qbman_eq_desc *d,\n-\t\t\t const struct qbman_fd *fd,\n-\t\t\t int frames_to_send);\n \n int qbman_check_command_complete(struct qbman_swp *s,\n \t\t\t\t const struct qbman_result *dq);\ndiff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c\nindex 97df703..f212829 100644\n--- a/drivers/bus/fslmc/qbman/qbman_portal.c\n+++ b/drivers/bus/fslmc/qbman/qbman_portal.c\n@@ -525,15 +525,26 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s,\n \treturn 0;\n }\n \n-int qbman_swp_fill_ring(struct qbman_swp *s,\n-\t\t\tconst struct qbman_eq_desc *d,\n-\t\t\tconst struct qbman_fd *fd,\n-\t\t\t__attribute__((unused)) uint8_t burst_index)\n+int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,\n+\t\t const struct qbman_fd *fd)\n+{\n+\tif (s->sys.eqcr_mode == qman_eqcr_vb_array)\n+\t\treturn qbman_swp_enqueue_array_mode(s, d, fd);\n+\telse /* Use ring mode by default */\n+\t\treturn qbman_swp_enqueue_ring_mode(s, d, fd);\n+}\n+\n+int qbman_swp_enqueue_multiple(struct qbman_swp *s,\n+\t\t\t const struct qbman_eq_desc *d,\n+\t\t\t const struct qbman_fd *fd,\n+\t\t\t int num_frames)\n {\n \tuint32_t *p;\n \tconst uint32_t *cl = qb_cl(d);\n-\tuint32_t eqcr_ci;\n+\tuint32_t eqcr_ci, eqcr_pi;\n \tuint8_t diff;\n+\tint i, num_enqueued = 0;\n+\tuint64_t addr_cena;\n \n \tif (!s->eqcr.available) {\n \t\teqcr_ci = s->eqcr.ci;\n@@ -543,62 +554,58 @@ int qbman_swp_fill_ring(struct qbman_swp *s,\n \t\t\t\t eqcr_ci, s->eqcr.ci);\n \t\ts->eqcr.available += diff;\n \t\tif (!diff)\n-\t\t\treturn -EBUSY;\n+\t\t\treturn 0;\n \t}\n-\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n-\t\tQBMAN_CENA_SWP_EQCR((s->eqcr.pi/* +burst_index */) & 7));\n-\tmemcpy(&p[1], &cl[1], 7 * 4);\n-\tmemcpy(&p[8], fd, sizeof(struct qbman_fd));\n-\n-\t/* lwsync(); */\n-\tp[0] = cl[0] | s->eqcr.pi_vb;\n-\n-\ts->eqcr.pi++;\n-\ts->eqcr.pi &= 0xF;\n-\ts->eqcr.available--;\n-\tif (!(s->eqcr.pi & 7))\n-\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n-\n-\treturn 0;\n-}\n \n-int qbman_swp_flush_ring(struct qbman_swp *s)\n-{\n-\tvoid *ptr = s->sys.addr_cena;\n+\teqcr_pi = s->eqcr.pi;\n+\tnum_enqueued = (s->eqcr.available < num_frames) ?\n+\t\t\ts->eqcr.available : num_frames;\n+\ts->eqcr.available -= num_enqueued;\n+\t/* Fill in the EQCR ring */\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tmemcpy(&p[1], &cl[1], 28);\n+\t\tmemcpy(&p[8], &fd[i], sizeof(*fd));\n+\t\teqcr_pi++;\n+\t\teqcr_pi &= 0xF;\n+\t}\n \n-\tdcbf((uint64_t)ptr);\n-\tdcbf((uint64_t)ptr + 0x40);\n-\tdcbf((uint64_t)ptr + 0x80);\n-\tdcbf((uint64_t)ptr + 0xc0);\n-\tdcbf((uint64_t)ptr + 0x100);\n-\tdcbf((uint64_t)ptr + 0x140);\n-\tdcbf((uint64_t)ptr + 0x180);\n-\tdcbf((uint64_t)ptr + 0x1c0);\n+\tlwsync();\n \n-\treturn 0;\n-}\n+\t/* Set the verb byte, have to substitute in the valid-bit */\n+\teqcr_pi = s->eqcr.pi;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n+\t\teqcr_pi++;\n+\t\teqcr_pi &= 0xF;\n+\t\tif (!(eqcr_pi & 7))\n+\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n+\t}\n \n-void qbman_sync(void)\n-{\n-\tlwsync();\n-}\n+\t/* Flush all the cacheline without load/store in between */\n+\teqcr_pi = s->eqcr.pi;\n+\taddr_cena = (uint64_t)s->sys.addr_cena;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tdcbf((uint64_t *)(addr_cena +\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));\n+\t\teqcr_pi++;\n+\t\teqcr_pi &= 0xF;\n+\t}\n+\ts->eqcr.pi = eqcr_pi;\n \n-int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,\n-\t\t const struct qbman_fd *fd)\n-{\n-\tif (s->sys.eqcr_mode == qman_eqcr_vb_array)\n-\t\treturn qbman_swp_enqueue_array_mode(s, d, fd);\n-\telse /* Use ring mode by default */\n-\t\treturn qbman_swp_enqueue_ring_mode(s, d, fd);\n+\treturn num_enqueued;\n }\n \n-int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,\n-\t\t\t const struct qbman_eq_desc *d,\n-\t\t\t const struct qbman_fd *fd,\n-\t\t\t int num_frames)\n+int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,\n+\t\t\t\t const struct qbman_eq_desc *d,\n+\t\t\t\t const struct qbman_fd *fd,\n+\t\t\t\t int num_frames)\n {\n \tuint32_t *p;\n-\tconst uint32_t *cl = qb_cl(d);\n+\tconst uint32_t *cl;\n \tuint32_t eqcr_ci, eqcr_pi;\n \tuint8_t diff;\n \tint i, num_enqueued = 0;\n@@ -623,29 +630,26 @@ int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,\n \tfor (i = 0; i < num_enqueued; i++) {\n \t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n \t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tcl = qb_cl(&d[i]);\n \t\tmemcpy(&p[1], &cl[1], 28);\n \t\tmemcpy(&p[8], &fd[i], sizeof(*fd));\n \t\teqcr_pi++;\n \t\teqcr_pi &= 0xF;\n-\t\t/*Pointing to the next enqueue descriptor*/\n-\t\tcl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t));\n \t}\n \n \tlwsync();\n \n \t/* Set the verb byte, have to substitute in the valid-bit */\n \teqcr_pi = s->eqcr.pi;\n-\tcl = qb_cl(d);\n \tfor (i = 0; i < num_enqueued; i++) {\n \t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n \t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tcl = qb_cl(&d[i]);\n \t\tp[0] = cl[0] | s->eqcr.pi_vb;\n \t\teqcr_pi++;\n \t\teqcr_pi &= 0xF;\n \t\tif (!(eqcr_pi & 7))\n \t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n-\t\t/*Pointing to the next enqueue descriptor*/\n-\t\tcl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t));\n \t}\n \n \t/* Flush all the cacheline without load/store in between */\n@@ -1493,87 +1497,3 @@ struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx)\n \tdq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx));\n \treturn dq;\n }\n-\n-int qbman_swp_send_multiple(struct qbman_swp *s,\n-\t\t\t const struct qbman_eq_desc *d,\n-\t\t\t const struct qbman_fd *fd,\n-\t\t\t int frames_to_send)\n-{\n-\tuint32_t *p;\n-\tconst uint32_t *cl = qb_cl(d);\n-\tuint32_t eqcr_ci;\n-\tuint8_t diff;\n-\tint sent = 0;\n-\tint i;\n-\tint initial_pi = s->eqcr.pi;\n-\tuint64_t start_pointer;\n-\n-\tif (!s->eqcr.available) {\n-\t\teqcr_ci = s->eqcr.ci;\n-\t\ts->eqcr.ci = qbman_cena_read_reg(&s->sys,\n-\t\t\t\t QBMAN_CENA_SWP_EQCR_CI) & 0xF;\n-\t\tdiff = qm_cyc_diff(QBMAN_EQCR_SIZE,\n-\t\t\t\t eqcr_ci, s->eqcr.ci);\n-\t\tif (!diff)\n-\t\t\tgoto done;\n-\t\ts->eqcr.available += diff;\n-\t}\n-\n-\t/* we are trying to send frames_to_send,\n-\t * if we have enough space in the ring\n-\t */\n-\twhile (s->eqcr.available && frames_to_send--) {\n-\t\tp = qbman_cena_write_start_wo_shadow_fast(&s->sys,\n-\t\t\t\t\tQBMAN_CENA_SWP_EQCR((initial_pi) & 7));\n-\t\t/* Write command (except of first byte) and FD */\n-\t\tmemcpy(&p[1], &cl[1], 7 * 4);\n-\t\tmemcpy(&p[8], &fd[sent], sizeof(struct qbman_fd));\n-\n-\t\tinitial_pi++;\n-\t\tinitial_pi &= 0xF;\n-\t\ts->eqcr.available--;\n-\t\tsent++;\n-\t}\n-\n-done:\n-\tinitial_pi = s->eqcr.pi;\n-\tlwsync();\n-\n-\t/* in order for flushes to complete faster:\n-\t * we use a following trick: we record all lines in 32 bit word\n-\t */\n-\n-\tinitial_pi = s->eqcr.pi;\n-\tfor (i = 0; i < sent; i++) {\n-\t\tp = qbman_cena_write_start_wo_shadow_fast(&s->sys,\n-\t\t\t\t\tQBMAN_CENA_SWP_EQCR((initial_pi) & 7));\n-\n-\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n-\t\tinitial_pi++;\n-\t\tinitial_pi &= 0xF;\n-\n-\t\tif (!(initial_pi & 7))\n-\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n-\t}\n-\n-\tinitial_pi = s->eqcr.pi;\n-\n-\t/* We need to flush all the lines but without\n-\t * load/store operations between them.\n-\t * We assign start_pointer before we start loop so that\n-\t * in loop we do not read it from memory\n-\t */\n-\tstart_pointer = (uint64_t)s->sys.addr_cena;\n-\tfor (i = 0; i < sent; i++) {\n-\t\tp = (uint32_t *)(start_pointer\n-\t\t\t\t + QBMAN_CENA_SWP_EQCR(initial_pi & 7));\n-\t\tdcbf((uint64_t)p);\n-\t\tinitial_pi++;\n-\t\tinitial_pi &= 0xF;\n-\t}\n-\n-\t/* Update producer index for the next call */\n-\ts->eqcr.pi = initial_pi;\n-\n-\treturn sent;\n-}\ndiff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map\nindex 6ac256d..13fb46a 100644\n--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map\n+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map\n@@ -69,7 +69,8 @@ DPDK_17.08 {\n \tqbman_result_SCN_state_in_mem;\n \tqbman_swp_dqrr_consume;\n \tqbman_swp_dqrr_next;\n-\tqbman_swp_enqueue_multiple_eqdesc;\n+\tqbman_swp_enqueue_multiple;\n+\tqbman_swp_enqueue_multiple_desc;\n \tqbman_swp_interrupt_clear_status;\n \tqbman_swp_push_set;\n \trte_dpaa2_alloc_dpci_dev;\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\nindex bae0a96..8052d36 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n@@ -671,7 +671,7 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \t\t}\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n-\t\t\tloop += qbman_swp_send_multiple(swp, &eqdesc,\n+\t\t\tloop += qbman_swp_enqueue_multiple(swp, &eqdesc,\n \t\t\t\t\t\t\t&fd_arr[loop],\n \t\t\t\t\t\t\tframes_to_send - loop);\n \t\t}\ndiff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c\nindex cf2d274..81286a8 100644\n--- a/drivers/event/dpaa2/dpaa2_eventdev.c\n+++ b/drivers/event/dpaa2/dpaa2_eventdev.c\n@@ -144,7 +144,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],\n \t\t}\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n-\t\t\tloop += qbman_swp_enqueue_multiple_eqdesc(swp,\n+\t\t\tloop += qbman_swp_enqueue_multiple_desc(swp,\n \t\t\t\t\t&eqdesc[loop], &fd_arr[loop],\n \t\t\t\t\tframes_to_send - loop);\n \t\t}\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nindex 3c057a3..4342c73 100644\n--- a/drivers/net/dpaa2/dpaa2_rxtx.c\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -622,7 +622,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n \t\t}\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n-\t\t\tloop += qbman_swp_send_multiple(swp, &eqdesc,\n+\t\t\tloop += qbman_swp_enqueue_multiple(swp, &eqdesc,\n \t\t\t\t\t&fd_arr[loop], frames_to_send - loop);\n \t\t}\n \n", "prefixes": [ "dpdk-dev", "03/27" ] }