Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/26395/?format=api
{ "id": 26395, "url": "https://patches.dpdk.org/api/patches/26395/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1499179471-19145-15-git-send-email-shreyansh.jain@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1499179471-19145-15-git-send-email-shreyansh.jain@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1499179471-19145-15-git-send-email-shreyansh.jain@nxp.com", "date": "2017-07-04T14:44:05", "name": "[dpdk-dev,v2,14/40] bus/dpaa: add BMan hardware interfaces", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "20222ea484188b16cf54c7d63e62fcbe0786a449", "submitter": { "id": 497, "url": "https://patches.dpdk.org/api/people/497/?format=api", "name": "Shreyansh Jain", "email": "shreyansh.jain@nxp.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1499179471-19145-15-git-send-email-shreyansh.jain@nxp.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/26395/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/26395/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5ABD47D0B;\n\tTue, 4 Jul 2017 16:36:06 +0200 (CEST)", "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0062.outbound.protection.outlook.com [104.47.42.62])\n\tby dpdk.org (Postfix) with ESMTP id EA9645A3E\n\tfor <dev@dpdk.org>; Tue, 4 Jul 2017 16:35:59 +0200 (CEST)", "from MWHPR03CA0037.namprd03.prod.outlook.com (10.174.173.154) by\n\tCY1PR0301MB0603.namprd03.prod.outlook.com (10.160.142.22) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1220.11; Tue, 4 Jul 2017 14:35:57 +0000", "from BL2FFO11FD040.protection.gbl (2a01:111:f400:7c09::122) by\n\tMWHPR03CA0037.outlook.office365.com (2603:10b6:301:3b::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1199.15\n\tvia Frontend Transport; Tue, 4 Jul 2017 14:35:57 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBL2FFO11FD040.mail.protection.outlook.com (10.173.161.136) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.1199.9 via Frontend Transport; Tue, 4 Jul 2017 14:35:56 +0000", "from Tophie.ap.freescale.net ([10.232.14.39])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv64EZM6w016426; Tue, 4 Jul 2017 07:35:54 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "Shreyansh Jain <shreyansh.jain@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <hemant.agrawal@nxp.com>", "Date": "Tue, 4 Jul 2017 20:14:05 +0530", "Message-ID": "<1499179471-19145-15-git-send-email-shreyansh.jain@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1499179471-19145-1-git-send-email-shreyansh.jain@nxp.com>", "References": "<1497591668-3320-1-git-send-email-shreyansh.jain@nxp.com>\n\t<1499179471-19145-1-git-send-email-shreyansh.jain@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131436525568766567;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603031)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:CY1PR0301MB0603; ", "X-MS-TrafficTypeDiagnostic": "CY1PR0301MB0603:", "X-Microsoft-Antispam-PRVS": "<CY1PR0301MB06033C33F88365B9778746E590D70@CY1PR0301MB0603.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(236129657087228)(185117386973197)(48057245064654)(148574349560750)(275809806118684)(167848164394848)(158140799945019)(247924648384137);", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(5005006)(13016025)(13018025)(8121501046)(3002001)(100000703101)(100105400095)(10201501046)(93006095)(93001095)(6055026)(6096035)(20161123561025)(20161123565025)(20161123559100)(20161123556025)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123563025)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY1PR0301MB0603; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR0301MB0603; ", "X-Forefront-PRVS": "0358535363", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Jul 2017 14:35:56.6270\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0301MB0603", "Subject": "[dpdk-dev] [PATCH v2 14/40] bus/dpaa: add BMan hardware interfaces", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>\nSigned-off-by: Roy Pledge <roy.pledge@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\nSigned-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>\n---\n drivers/bus/dpaa/Makefile | 1 +\n drivers/bus/dpaa/base/qbman/bman.c | 394 +++++++++++++++++++++\n drivers/bus/dpaa/base/qbman/bman.h | 550 ++++++++++++++++++++++++++++++\n drivers/bus/dpaa/base/qbman/bman_driver.c | 12 +\n drivers/bus/dpaa/base/qbman/dpaa_alloc.c | 16 +\n 5 files changed, 973 insertions(+)\n create mode 100644 drivers/bus/dpaa/base/qbman/bman.c\n create mode 100644 drivers/bus/dpaa/base/qbman/bman.h", "diff": "diff --git a/drivers/bus/dpaa/Makefile b/drivers/bus/dpaa/Makefile\nindex 24dfa13..6d0c5ee 100644\n--- a/drivers/bus/dpaa/Makefile\n+++ b/drivers/bus/dpaa/Makefile\n@@ -71,6 +71,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += \\\n \tbase/fman/of.c \\\n \tbase/fman/netcfg_layer.c \\\n \tbase/qbman/process.c \\\n+\tbase/qbman/bman.c \\\n \tbase/qbman/bman_driver.c \\\n \tbase/qbman/qman.c \\\n \tbase/qbman/qman_driver.c \\\ndiff --git a/drivers/bus/dpaa/base/qbman/bman.c b/drivers/bus/dpaa/base/qbman/bman.c\nnew file mode 100644\nindex 0000000..a0bea62\n--- /dev/null\n+++ b/drivers/bus/dpaa/base/qbman/bman.c\n@@ -0,0 +1,394 @@\n+/*-\n+ * This file is provided under a dual BSD/GPLv2 license. When using or\n+ * redistributing this file, you may do so under either license.\n+ *\n+ * BSD LICENSE\n+ *\n+ * Copyright 2008-2016 Freescale Semiconductor Inc.\n+ * Copyright 2017 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ * GPL LICENSE SUMMARY\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include \"bman.h\"\n+#include <rte_branch_prediction.h>\n+\n+/* Compilation constants */\n+#define RCR_THRESH\t2\t/* reread h/w CI when running out of space */\n+#define IRQNAME\t\t\"BMan portal %d\"\n+#define MAX_IRQNAME\t16\t/* big enough for \"BMan portal %d\" */\n+\n+struct bman_portal {\n+\tstruct bm_portal p;\n+\t/* 2-element array. pools[0] is mask, pools[1] is snapshot. */\n+\tstruct bman_depletion *pools;\n+\tint thresh_set;\n+\tunsigned long irq_sources;\n+\tu32 slowpoll;\t/* only used when interrupts are off */\n+\t/* When the cpu-affine portal is activated, this is non-NULL */\n+\tconst struct bm_portal_config *config;\n+\tchar irqname[MAX_IRQNAME];\n+};\n+\n+static cpumask_t affine_mask;\n+static DEFINE_SPINLOCK(affine_mask_lock);\n+static DEFINE_PER_CPU(struct bman_portal, bman_affine_portal);\n+\n+static inline struct bman_portal *get_affine_portal(void)\n+{\n+\treturn &get_cpu_var(bman_affine_portal);\n+}\n+\n+/*\n+ * This object type refers to a pool, it isn't *the* pool. There may be\n+ * more than one such object per BMan buffer pool, eg. if different users of\n+ * the pool are operating via different portals.\n+ */\n+struct bman_pool {\n+\tstruct bman_pool_params params;\n+\t/* Used for hash-table admin when using depletion notifications. */\n+\tstruct bman_portal *portal;\n+\tstruct bman_pool *next;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tatomic_t in_use;\n+#endif\n+};\n+\n+static inline\n+struct bman_portal *bman_create_portal(struct bman_portal *portal,\n+\t\t\t\t const struct bm_portal_config *c)\n+{\n+\tstruct bm_portal *p;\n+\tconst struct bman_depletion *pools = &c->mask;\n+\tint ret;\n+\tu8 bpid = 0;\n+\n+\tp = &portal->p;\n+\t/*\n+\t * prep the low-level portal struct with the mapped addresses from the\n+\t * config, everything that follows depends on it and \"config\" is more\n+\t * for (de)reference...\n+\t */\n+\tp->addr.ce = c->addr_virt[DPAA_PORTAL_CE];\n+\tp->addr.ci = c->addr_virt[DPAA_PORTAL_CI];\n+\tif (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {\n+\t\tpr_err(\"Bman RCR initialisation failed\\n\");\n+\t\treturn NULL;\n+\t}\n+\tif (bm_mc_init(p)) {\n+\t\tpr_err(\"Bman MC initialisation failed\\n\");\n+\t\tgoto fail_mc;\n+\t}\n+\tportal->pools = kmalloc(2 * sizeof(*pools), GFP_KERNEL);\n+\tif (!portal->pools)\n+\t\tgoto fail_pools;\n+\tportal->pools[0] = *pools;\n+\tbman_depletion_init(portal->pools + 1);\n+\twhile (bpid < bman_pool_max) {\n+\t\t/*\n+\t\t * Default to all BPIDs disabled, we enable as required at\n+\t\t * run-time.\n+\t\t */\n+\t\tbm_isr_bscn_mask(p, bpid, 0);\n+\t\tbpid++;\n+\t}\n+\tportal->slowpoll = 0;\n+\t/* Write-to-clear any stale interrupt status bits */\n+\tbm_isr_disable_write(p, 0xffffffff);\n+\tportal->irq_sources = 0;\n+\tbm_isr_enable_write(p, portal->irq_sources);\n+\tbm_isr_status_clear(p, 0xffffffff);\n+\tsnprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);\n+\tif (request_irq(c->irq, NULL, 0, portal->irqname,\n+\t\t\tportal)) {\n+\t\tpr_err(\"request_irq() failed\\n\");\n+\t\tgoto fail_irq;\n+\t}\n+\n+\t/* Need RCR to be empty before continuing */\n+\tret = bm_rcr_get_fill(p);\n+\tif (ret) {\n+\t\tpr_err(\"Bman RCR unclean\\n\");\n+\t\tgoto fail_rcr_empty;\n+\t}\n+\t/* Success */\n+\tportal->config = c;\n+\n+\tbm_isr_disable_write(p, 0);\n+\tbm_isr_uninhibit(p);\n+\treturn portal;\n+fail_rcr_empty:\n+\tfree_irq(c->irq, portal);\n+fail_irq:\n+\tkfree(portal->pools);\n+fail_pools:\n+\tbm_mc_finish(p);\n+fail_mc:\n+\tbm_rcr_finish(p);\n+\treturn NULL;\n+}\n+\n+struct bman_portal *\n+bman_create_affine_portal(const struct bm_portal_config *c)\n+{\n+\tstruct bman_portal *portal = get_affine_portal();\n+\n+\t/*This function is called from the context which is already affine to\n+\t *CPU or in other words this in non-migratable to other CPUs.\n+\t */\n+\tportal = bman_create_portal(portal, c);\n+\tif (portal) {\n+\t\tspin_lock(&affine_mask_lock);\n+\t\tCPU_SET(c->cpu, &affine_mask);\n+\t\tspin_unlock(&affine_mask_lock);\n+\t}\n+\treturn portal;\n+}\n+\n+static inline\n+void bman_destroy_portal(struct bman_portal *bm)\n+{\n+\tconst struct bm_portal_config *pcfg;\n+\n+\tpcfg = bm->config;\n+\tbm_rcr_cce_update(&bm->p);\n+\tbm_rcr_cce_update(&bm->p);\n+\n+\tfree_irq(pcfg->irq, bm);\n+\n+\tkfree(bm->pools);\n+\tbm_mc_finish(&bm->p);\n+\tbm_rcr_finish(&bm->p);\n+\tbm->config = NULL;\n+}\n+\n+const struct\n+bm_portal_config *bman_destroy_affine_portal(void)\n+{\n+\tstruct bman_portal *bm = get_affine_portal();\n+\tconst struct bm_portal_config *pcfg;\n+\n+\tpcfg = bm->config;\n+\tbman_destroy_portal(bm);\n+\tspin_lock(&affine_mask_lock);\n+\tCPU_CLR(pcfg->cpu, &affine_mask);\n+\tspin_unlock(&affine_mask_lock);\n+\treturn pcfg;\n+}\n+\n+int\n+bman_get_portal_index(void)\n+{\n+\tstruct bman_portal *p = get_affine_portal();\n+\treturn p->config->index;\n+}\n+\n+static const u32 zero_thresholds[4] = {0, 0, 0, 0};\n+\n+struct bman_pool *bman_new_pool(const struct bman_pool_params *params)\n+{\n+\tstruct bman_pool *pool = NULL;\n+\tu32 bpid;\n+\n+\tif (params->flags & BMAN_POOL_FLAG_DYNAMIC_BPID) {\n+\t\tint ret = bman_alloc_bpid(&bpid);\n+\n+\t\tif (ret)\n+\t\t\treturn NULL;\n+\t} else {\n+\t\tif (params->bpid >= bman_pool_max)\n+\t\t\treturn NULL;\n+\t\tbpid = params->bpid;\n+\t}\n+\tif (params->flags & BMAN_POOL_FLAG_THRESH) {\n+\t\tint ret = bm_pool_set(bpid, params->thresholds);\n+\n+\t\tif (ret)\n+\t\t\tgoto err;\n+\t}\n+\n+\tpool = kmalloc(sizeof(*pool), GFP_KERNEL);\n+\tif (!pool)\n+\t\tgoto err;\n+\tpool->params = *params;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tatomic_set(&pool->in_use, 1);\n+#endif\n+\tif (params->flags & BMAN_POOL_FLAG_DYNAMIC_BPID)\n+\t\tpool->params.bpid = bpid;\n+\n+\treturn pool;\n+err:\n+\tif (params->flags & BMAN_POOL_FLAG_THRESH)\n+\t\tbm_pool_set(bpid, zero_thresholds);\n+\n+\tif (params->flags & BMAN_POOL_FLAG_DYNAMIC_BPID)\n+\t\tbman_release_bpid(bpid);\n+\tkfree(pool);\n+\n+\treturn NULL;\n+}\n+\n+void bman_free_pool(struct bman_pool *pool)\n+{\n+\tif (pool->params.flags & BMAN_POOL_FLAG_THRESH)\n+\t\tbm_pool_set(pool->params.bpid, zero_thresholds);\n+\tif (pool->params.flags & BMAN_POOL_FLAG_DYNAMIC_BPID)\n+\t\tbman_release_bpid(pool->params.bpid);\n+\tkfree(pool);\n+}\n+\n+const struct bman_pool_params *bman_get_params(const struct bman_pool *pool)\n+{\n+\treturn &pool->params;\n+}\n+\n+static void update_rcr_ci(struct bman_portal *p, int avail)\n+{\n+\tif (avail)\n+\t\tbm_rcr_cce_prefetch(&p->p);\n+\telse\n+\t\tbm_rcr_cce_update(&p->p);\n+}\n+\n+#define BMAN_BUF_MASK 0x0000fffffffffffful\n+int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num,\n+\t\t u32 flags __maybe_unused)\n+{\n+\tstruct bman_portal *p;\n+\tstruct bm_rcr_entry *r;\n+\tu32 i = num - 1;\n+\tu8 avail;\n+\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tif (!num || (num > 8))\n+\t\treturn -EINVAL;\n+\tif (pool->params.flags & BMAN_POOL_FLAG_NO_RELEASE)\n+\t\treturn -EINVAL;\n+#endif\n+\n+\tp = get_affine_portal();\n+\tavail = bm_rcr_get_avail(&p->p);\n+\tif (avail < 2)\n+\t\tupdate_rcr_ci(p, avail);\n+\tr = bm_rcr_start(&p->p);\n+\tif (unlikely(!r))\n+\t\treturn -EBUSY;\n+\n+\t/*\n+\t * we can copy all but the first entry, as this can trigger badness\n+\t * with the valid-bit\n+\t */\n+\tr->bufs[0].opaque =\n+\t\tcpu_to_be64(((u64)pool->params.bpid << 48) |\n+\t\t\t (bufs[0].opaque & BMAN_BUF_MASK));\n+\tif (i) {\n+\t\tfor (i = 1; i < num; i++)\n+\t\t\tr->bufs[i].opaque =\n+\t\t\t\tcpu_to_be64(bufs[i].opaque & BMAN_BUF_MASK);\n+\t}\n+\n+\tbm_rcr_pvb_commit(&p->p, BM_RCR_VERB_CMD_BPID_SINGLE |\n+\t\t\t (num & BM_RCR_VERB_BUFCOUNT_MASK));\n+\n+\treturn 0;\n+}\n+\n+int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num,\n+\t\t u32 flags __maybe_unused)\n+{\n+\tstruct bman_portal *p = get_affine_portal();\n+\tstruct bm_mc_command *mcc;\n+\tstruct bm_mc_result *mcr;\n+\tint ret, i;\n+\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tif (!num || (num > 8))\n+\t\treturn -EINVAL;\n+\tif (pool->params.flags & BMAN_POOL_FLAG_ONLY_RELEASE)\n+\t\treturn -EINVAL;\n+#endif\n+\n+\tmcc = bm_mc_start(&p->p);\n+\tmcc->acquire.bpid = pool->params.bpid;\n+\tbm_mc_commit(&p->p, BM_MCC_VERB_CMD_ACQUIRE |\n+\t\t\t(num & BM_MCC_VERB_ACQUIRE_BUFCOUNT));\n+\twhile (!(mcr = bm_mc_result(&p->p)))\n+\t\tcpu_relax();\n+\tret = mcr->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT;\n+\tif (bufs) {\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\tbufs[i].opaque =\n+\t\t\t\tbe64_to_cpu(mcr->acquire.bufs[i].opaque);\n+\t}\n+\tif (ret != num)\n+\t\tret = -ENOMEM;\n+\treturn ret;\n+}\n+\n+int bman_query_pools(struct bm_pool_state *state)\n+{\n+\tstruct bman_portal *p = get_affine_portal();\n+\tstruct bm_mc_result *mcr;\n+\n+\tbm_mc_start(&p->p);\n+\tbm_mc_commit(&p->p, BM_MCC_VERB_CMD_QUERY);\n+\twhile (!(mcr = bm_mc_result(&p->p)))\n+\t\tcpu_relax();\n+\tDPAA_ASSERT((mcr->verb & BM_MCR_VERB_CMD_MASK) ==\n+\t\t BM_MCR_VERB_CMD_QUERY);\n+\t*state = mcr->query;\n+\tstate->as.state.state[0] = be32_to_cpu(state->as.state.state[0]);\n+\tstate->as.state.state[1] = be32_to_cpu(state->as.state.state[1]);\n+\tstate->ds.state.state[0] = be32_to_cpu(state->ds.state.state[0]);\n+\tstate->ds.state.state[1] = be32_to_cpu(state->ds.state.state[1]);\n+\treturn 0;\n+}\n+\n+u32 bman_query_free_buffers(struct bman_pool *pool)\n+{\n+\treturn bm_pool_free_buffers(pool->params.bpid);\n+}\n+\n+int bman_update_pool_thresholds(struct bman_pool *pool, const u32 *thresholds)\n+{\n+\tu32 bpid;\n+\n+\tbpid = bman_get_params(pool)->bpid;\n+\n+\treturn bm_pool_set(bpid, thresholds);\n+}\n+\n+int bman_shutdown_pool(u32 bpid)\n+{\n+\tstruct bman_portal *p = get_affine_portal();\n+\treturn bm_shutdown_pool(&p->p, bpid);\n+}\ndiff --git a/drivers/bus/dpaa/base/qbman/bman.h b/drivers/bus/dpaa/base/qbman/bman.h\nnew file mode 100644\nindex 0000000..2af30e9\n--- /dev/null\n+++ b/drivers/bus/dpaa/base/qbman/bman.h\n@@ -0,0 +1,550 @@\n+/*-\n+ * This file is provided under a dual BSD/GPLv2 license. When using or\n+ * redistributing this file, you may do so under either license.\n+ *\n+ * BSD LICENSE\n+ *\n+ * Copyright 2010-2016 Freescale Semiconductor Inc.\n+ * Copyright 2017 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ * GPL LICENSE SUMMARY\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __BMAN_H\n+#define __BMAN_H\n+\n+#include \"bman_priv.h\"\n+\n+/* Cache-inhibited register offsets */\n+#define BM_REG_RCR_PI_CINH\t0x3000\n+#define BM_REG_RCR_CI_CINH\t0x3100\n+#define BM_REG_RCR_ITR\t\t0x3200\n+#define BM_REG_CFG\t\t0x3300\n+#define BM_REG_SCN(n)\t\t(0x3400 + ((n) << 6))\n+#define BM_REG_ISR\t\t0x3e00\n+#define BM_REG_IIR 0x3ec0\n+\n+/* Cache-enabled register offsets */\n+#define BM_CL_CR\t\t0x0000\n+#define BM_CL_RR0\t\t0x0100\n+#define BM_CL_RR1\t\t0x0140\n+#define BM_CL_RCR\t\t0x1000\n+#define BM_CL_RCR_PI_CENA\t0x3000\n+#define BM_CL_RCR_CI_CENA\t0x3100\n+\n+/* BTW, the drivers (and h/w programming model) already obtain the required\n+ * synchronisation for portal accesses via lwsync(), hwsync(), and\n+ * data-dependencies. Use of barrier()s or other order-preserving primitives\n+ * simply degrade performance. Hence the use of the __raw_*() interfaces, which\n+ * simply ensure that the compiler treats the portal registers as volatile (ie.\n+ * non-coherent).\n+ */\n+\n+/* Cache-inhibited register access. */\n+#define __bm_in(bm, o)\t\tbe32_to_cpu(__raw_readl((bm)->ci + (o)))\n+#define __bm_out(bm, o, val) __raw_writel(cpu_to_be32(val), \\\n+\t\t\t\t\t (bm)->ci + (o))\n+#define bm_in(reg)\t\t__bm_in(&portal->addr, BM_REG_##reg)\n+#define bm_out(reg, val)\t__bm_out(&portal->addr, BM_REG_##reg, val)\n+\n+/* Cache-enabled (index) register access */\n+#define __bm_cl_touch_ro(bm, o) dcbt_ro((bm)->ce + (o))\n+#define __bm_cl_touch_rw(bm, o) dcbt_rw((bm)->ce + (o))\n+#define __bm_cl_in(bm, o)\tbe32_to_cpu(__raw_readl((bm)->ce + (o)))\n+#define __bm_cl_out(bm, o, val) \\\n+\tdo { \\\n+\t\tu32 *__tmpclout = (bm)->ce + (o); \\\n+\t\t__raw_writel(cpu_to_be32(val), __tmpclout); \\\n+\t\tdcbf(__tmpclout); \\\n+\t} while (0)\n+#define __bm_cl_invalidate(bm, o) dccivac((bm)->ce + (o))\n+#define bm_cl_touch_ro(reg) __bm_cl_touch_ro(&portal->addr, BM_CL_##reg##_CENA)\n+#define bm_cl_touch_rw(reg) __bm_cl_touch_rw(&portal->addr, BM_CL_##reg##_CENA)\n+#define bm_cl_in(reg)\t __bm_cl_in(&portal->addr, BM_CL_##reg##_CENA)\n+#define bm_cl_out(reg, val) __bm_cl_out(&portal->addr, BM_CL_##reg##_CENA, val)\n+#define bm_cl_invalidate(reg)\\\n+\t__bm_cl_invalidate(&portal->addr, BM_CL_##reg##_CENA)\n+\n+/* Cyclic helper for rings. FIXME: once we are able to do fine-grain perf\n+ * analysis, look at using the \"extra\" bit in the ring index registers to avoid\n+ * cyclic issues.\n+ */\n+static inline u8 bm_cyc_diff(u8 ringsize, u8 first, u8 last)\n+{\n+\t/* 'first' is included, 'last' is excluded */\n+\tif (first <= last)\n+\t\treturn last - first;\n+\treturn ringsize + last - first;\n+}\n+\n+/* Portal modes.\n+ * Enum types;\n+ * pmode == production mode\n+ * cmode == consumption mode,\n+ * Enum values use 3 letter codes. First letter matches the portal mode,\n+ * remaining two letters indicate;\n+ * ci == cache-inhibited portal register\n+ * ce == cache-enabled portal register\n+ * vb == in-band valid-bit (cache-enabled)\n+ */\n+enum bm_rcr_pmode {\t\t/* matches BCSP_CFG::RPM */\n+\tbm_rcr_pci = 0,\t\t/* PI index, cache-inhibited */\n+\tbm_rcr_pce = 1,\t\t/* PI index, cache-enabled */\n+\tbm_rcr_pvb = 2\t\t/* valid-bit */\n+};\n+\n+enum bm_rcr_cmode {\t\t/* s/w-only */\n+\tbm_rcr_cci,\t\t/* CI index, cache-inhibited */\n+\tbm_rcr_cce\t\t/* CI index, cache-enabled */\n+};\n+\n+/* --- Portal structures --- */\n+\n+#define BM_RCR_SIZE\t\t8\n+\n+struct bm_rcr {\n+\tstruct bm_rcr_entry *ring, *cursor;\n+\tu8 ci, available, ithresh, vbit;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tu32 busy;\n+\tenum bm_rcr_pmode pmode;\n+\tenum bm_rcr_cmode cmode;\n+#endif\n+};\n+\n+struct bm_mc {\n+\tstruct bm_mc_command *cr;\n+\tstruct bm_mc_result *rr;\n+\tu8 rridx, vbit;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tenum {\n+\t\t/* Can only be _mc_start()ed */\n+\t\tmc_idle,\n+\t\t/* Can only be _mc_commit()ed or _mc_abort()ed */\n+\t\tmc_user,\n+\t\t/* Can only be _mc_retry()ed */\n+\t\tmc_hw\n+\t} state;\n+#endif\n+};\n+\n+struct bm_addr {\n+\tvoid __iomem *ce;\t/* cache-enabled */\n+\tvoid __iomem *ci;\t/* cache-inhibited */\n+};\n+\n+struct bm_portal {\n+\tstruct bm_addr addr;\n+\tstruct bm_rcr rcr;\n+\tstruct bm_mc mc;\n+\tstruct bm_portal_config config;\n+} ____cacheline_aligned;\n+\n+/* Bit-wise logic to wrap a ring pointer by clearing the \"carry bit\" */\n+#define RCR_CARRYCLEAR(p) \\\n+\t(void *)((unsigned long)(p) & (~(unsigned long)(BM_RCR_SIZE << 6)))\n+\n+/* Bit-wise logic to convert a ring pointer to a ring index */\n+static inline u8 RCR_PTR2IDX(struct bm_rcr_entry *e)\n+{\n+\treturn ((uintptr_t)e >> 6) & (BM_RCR_SIZE - 1);\n+}\n+\n+/* Increment the 'cursor' ring pointer, taking 'vbit' into account */\n+static inline void RCR_INC(struct bm_rcr *rcr)\n+{\n+\t/* NB: this is odd-looking, but experiments show that it generates\n+\t * fast code with essentially no branching overheads. We increment to\n+\t * the next RCR pointer and handle overflow and 'vbit'.\n+\t */\n+\tstruct bm_rcr_entry *partial = rcr->cursor + 1;\n+\n+\trcr->cursor = RCR_CARRYCLEAR(partial);\n+\tif (partial != rcr->cursor)\n+\t\trcr->vbit ^= BM_RCR_VERB_VBIT;\n+}\n+\n+static inline int bm_rcr_init(struct bm_portal *portal, enum bm_rcr_pmode pmode,\n+\t\t\t __maybe_unused enum bm_rcr_cmode cmode)\n+{\n+\t/* This use of 'register', as well as all other occurrences, is because\n+\t * it has been observed to generate much faster code with gcc than is\n+\t * otherwise the case.\n+\t */\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\tu32 cfg;\n+\tu8 pi;\n+\n+\trcr->ring = portal->addr.ce + BM_CL_RCR;\n+\trcr->ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1);\n+\n+\tpi = bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1);\n+\trcr->cursor = rcr->ring + pi;\n+\trcr->vbit = (bm_in(RCR_PI_CINH) & BM_RCR_SIZE) ? BM_RCR_VERB_VBIT : 0;\n+\trcr->available = BM_RCR_SIZE - 1\n+\t\t- bm_cyc_diff(BM_RCR_SIZE, rcr->ci, pi);\n+\trcr->ithresh = bm_in(RCR_ITR);\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\trcr->busy = 0;\n+\trcr->pmode = pmode;\n+\trcr->cmode = cmode;\n+#endif\n+\tcfg = (bm_in(CFG) & 0xffffffe0) | (pmode & 0x3); /* BCSP_CFG::RPM */\n+\tbm_out(CFG, cfg);\n+\treturn 0;\n+}\n+\n+static inline void bm_rcr_finish(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\tu8 pi = bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1);\n+\tu8 ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1);\n+\n+\tDPAA_ASSERT(!rcr->busy);\n+\tif (pi != RCR_PTR2IDX(rcr->cursor))\n+\t\tpr_crit(\"loosing uncommitted RCR entries\\n\");\n+\tif (ci != rcr->ci)\n+\t\tpr_crit(\"missing existing RCR completions\\n\");\n+\tif (rcr->ci != RCR_PTR2IDX(rcr->cursor))\n+\t\tpr_crit(\"RCR destroyed unquiesced\\n\");\n+}\n+\n+static inline struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(!rcr->busy);\n+\tif (!rcr->available)\n+\t\treturn NULL;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\trcr->busy = 1;\n+#endif\n+\tdcbz_64(rcr->cursor);\n+\treturn rcr->cursor;\n+}\n+\n+static inline void bm_rcr_abort(struct bm_portal *portal)\n+{\n+\t__maybe_unused register struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(rcr->busy);\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\trcr->busy = 0;\n+#endif\n+}\n+\n+static inline struct bm_rcr_entry *bm_rcr_pend_and_next(\n+\t\t\t\t\tstruct bm_portal *portal, u8 myverb)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(rcr->busy);\n+\tDPAA_ASSERT(rcr->pmode != bm_rcr_pvb);\n+\tif (rcr->available == 1)\n+\t\treturn NULL;\n+\trcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit;\n+\tdcbf_64(rcr->cursor);\n+\tRCR_INC(rcr);\n+\trcr->available--;\n+\tdcbz_64(rcr->cursor);\n+\treturn rcr->cursor;\n+}\n+\n+static inline void bm_rcr_pci_commit(struct bm_portal *portal, u8 myverb)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(rcr->busy);\n+\tDPAA_ASSERT(rcr->pmode == bm_rcr_pci);\n+\trcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit;\n+\tRCR_INC(rcr);\n+\trcr->available--;\n+\thwsync();\n+\tbm_out(RCR_PI_CINH, RCR_PTR2IDX(rcr->cursor));\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\trcr->busy = 0;\n+#endif\n+}\n+\n+static inline void bm_rcr_pce_prefetch(struct bm_portal *portal)\n+{\n+\t__maybe_unused register struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(rcr->pmode == bm_rcr_pce);\n+\tbm_cl_invalidate(RCR_PI);\n+\tbm_cl_touch_rw(RCR_PI);\n+}\n+\n+static inline void bm_rcr_pce_commit(struct bm_portal *portal, u8 myverb)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(rcr->busy);\n+\tDPAA_ASSERT(rcr->pmode == bm_rcr_pce);\n+\trcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit;\n+\tRCR_INC(rcr);\n+\trcr->available--;\n+\tlwsync();\n+\tbm_cl_out(RCR_PI, RCR_PTR2IDX(rcr->cursor));\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\trcr->busy = 0;\n+#endif\n+}\n+\n+static inline void bm_rcr_pvb_commit(struct bm_portal *portal, u8 myverb)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\tstruct bm_rcr_entry *rcursor;\n+\n+\tDPAA_ASSERT(rcr->busy);\n+\tDPAA_ASSERT(rcr->pmode == bm_rcr_pvb);\n+\tlwsync();\n+\trcursor = rcr->cursor;\n+\trcursor->__dont_write_directly__verb = myverb | rcr->vbit;\n+\tdcbf_64(rcursor);\n+\tRCR_INC(rcr);\n+\trcr->available--;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\trcr->busy = 0;\n+#endif\n+}\n+\n+static inline u8 bm_rcr_cci_update(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\tu8 diff, old_ci = rcr->ci;\n+\n+\tDPAA_ASSERT(rcr->cmode == bm_rcr_cci);\n+\trcr->ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1);\n+\tdiff = bm_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);\n+\trcr->available += diff;\n+\treturn diff;\n+}\n+\n+static inline void bm_rcr_cce_prefetch(struct bm_portal *portal)\n+{\n+\t__maybe_unused register struct bm_rcr *rcr = &portal->rcr;\n+\n+\tDPAA_ASSERT(rcr->cmode == bm_rcr_cce);\n+\tbm_cl_touch_ro(RCR_CI);\n+}\n+\n+static inline u8 bm_rcr_cce_update(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\tu8 diff, old_ci = rcr->ci;\n+\n+\tDPAA_ASSERT(rcr->cmode == bm_rcr_cce);\n+\trcr->ci = bm_cl_in(RCR_CI) & (BM_RCR_SIZE - 1);\n+\tbm_cl_invalidate(RCR_CI);\n+\tdiff = bm_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);\n+\trcr->available += diff;\n+\treturn diff;\n+}\n+\n+static inline u8 bm_rcr_get_ithresh(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\treturn rcr->ithresh;\n+}\n+\n+static inline void bm_rcr_set_ithresh(struct bm_portal *portal, u8 ithresh)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\trcr->ithresh = ithresh;\n+\tbm_out(RCR_ITR, ithresh);\n+}\n+\n+static inline u8 bm_rcr_get_avail(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\treturn rcr->available;\n+}\n+\n+static inline u8 bm_rcr_get_fill(struct bm_portal *portal)\n+{\n+\tregister struct bm_rcr *rcr = &portal->rcr;\n+\n+\treturn BM_RCR_SIZE - 1 - rcr->available;\n+}\n+\n+/* --- Management command API --- */\n+\n+static inline int bm_mc_init(struct bm_portal *portal)\n+{\n+\tregister struct bm_mc *mc = &portal->mc;\n+\n+\tmc->cr = portal->addr.ce + BM_CL_CR;\n+\tmc->rr = portal->addr.ce + BM_CL_RR0;\n+\tmc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) &\n+\t\t\tBM_MCC_VERB_VBIT) ? 0 : 1;\n+\tmc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tmc->state = mc_idle;\n+#endif\n+\treturn 0;\n+}\n+\n+static inline void bm_mc_finish(struct bm_portal *portal)\n+{\n+\t__maybe_unused register struct bm_mc *mc = &portal->mc;\n+\n+\tDPAA_ASSERT(mc->state == mc_idle);\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tif (mc->state != mc_idle)\n+\t\tpr_crit(\"Losing incomplete MC command\\n\");\n+#endif\n+}\n+\n+static inline struct bm_mc_command *bm_mc_start(struct bm_portal *portal)\n+{\n+\tregister struct bm_mc *mc = &portal->mc;\n+\n+\tDPAA_ASSERT(mc->state == mc_idle);\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tmc->state = mc_user;\n+#endif\n+\tdcbz_64(mc->cr);\n+\treturn mc->cr;\n+}\n+\n+static inline void bm_mc_abort(struct bm_portal *portal)\n+{\n+\t__maybe_unused register struct bm_mc *mc = &portal->mc;\n+\n+\tDPAA_ASSERT(mc->state == mc_user);\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tmc->state = mc_idle;\n+#endif\n+}\n+\n+static inline void bm_mc_commit(struct bm_portal *portal, u8 myverb)\n+{\n+\tregister struct bm_mc *mc = &portal->mc;\n+\tstruct bm_mc_result *rr = mc->rr + mc->rridx;\n+\n+\tDPAA_ASSERT(mc->state == mc_user);\n+\tlwsync();\n+\tmc->cr->__dont_write_directly__verb = myverb | mc->vbit;\n+\tdcbf(mc->cr);\n+\tdcbit_ro(rr);\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tmc->state = mc_hw;\n+#endif\n+}\n+\n+static inline struct bm_mc_result *bm_mc_result(struct bm_portal *portal)\n+{\n+\tregister struct bm_mc *mc = &portal->mc;\n+\tstruct bm_mc_result *rr = mc->rr + mc->rridx;\n+\n+\tDPAA_ASSERT(mc->state == mc_hw);\n+\t/* The inactive response register's verb byte always returns zero until\n+\t * its command is submitted and completed. This includes the valid-bit,\n+\t * in case you were wondering.\n+\t */\n+\tif (!__raw_readb(&rr->verb)) {\n+\t\tdcbit_ro(rr);\n+\t\treturn NULL;\n+\t}\n+\tmc->rridx ^= 1;\n+\tmc->vbit ^= BM_MCC_VERB_VBIT;\n+#ifdef RTE_LIBRTE_DPAA_CHECKING\n+\tmc->state = mc_idle;\n+#endif\n+\treturn rr;\n+}\n+\n+#define SCN_REG(bpid) BM_REG_SCN((bpid) / 32)\n+#define SCN_BIT(bpid) (0x80000000 >> (bpid & 31))\n+static inline void bm_isr_bscn_mask(struct bm_portal *portal, u8 bpid,\n+\t\t\t\t int enable)\n+{\n+\tu32 val;\n+\n+\tDPAA_ASSERT(bpid < bman_pool_max);\n+\t/* REG_SCN for bpid=0..31, REG_SCN+4 for bpid=32..63 */\n+\tval = __bm_in(&portal->addr, SCN_REG(bpid));\n+\tif (enable)\n+\t\tval |= SCN_BIT(bpid);\n+\telse\n+\t\tval &= ~SCN_BIT(bpid);\n+\t__bm_out(&portal->addr, SCN_REG(bpid), val);\n+}\n+\n+static inline u32 __bm_isr_read(struct bm_portal *portal, enum bm_isr_reg n)\n+{\n+#if defined(RTE_ARCH_ARM64)\n+\treturn __bm_in(&portal->addr, BM_REG_ISR + (n << 6));\n+#else\n+\treturn __bm_in(&portal->addr, BM_REG_ISR + (n << 2));\n+#endif\n+}\n+\n+static inline void __bm_isr_write(struct bm_portal *portal, enum bm_isr_reg n,\n+\t\t\t\t u32 val)\n+{\n+#if defined(RTE_ARCH_ARM64)\n+\t__bm_out(&portal->addr, BM_REG_ISR + (n << 6), val);\n+#else\n+\t__bm_out(&portal->addr, BM_REG_ISR + (n << 2), val);\n+#endif\n+}\n+\n+/* Buffer Pool Cleanup */\n+static inline int bm_shutdown_pool(struct bm_portal *p, u32 bpid)\n+{\n+\tstruct bm_mc_command *bm_cmd;\n+\tstruct bm_mc_result *bm_res;\n+\n+\tint aq_count = 0;\n+\tbool stop = false;\n+\n+\twhile (!stop) {\n+\t\t/* Acquire buffers until empty */\n+\t\tbm_cmd = bm_mc_start(p);\n+\t\tbm_cmd->acquire.bpid = bpid;\n+\t\tbm_mc_commit(p, BM_MCC_VERB_CMD_ACQUIRE | 1);\n+\t\twhile (!(bm_res = bm_mc_result(p)))\n+\t\t\tcpu_relax();\n+\t\tif (!(bm_res->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT)) {\n+\t\t\t/* Pool is empty */\n+\t\t\tstop = true;\n+\t\t} else\n+\t\t\t++aq_count;\n+\t};\n+\treturn 0;\n+}\n+\n+#endif /* __BMAN_H */\ndiff --git a/drivers/bus/dpaa/base/qbman/bman_driver.c b/drivers/bus/dpaa/base/qbman/bman_driver.c\nindex fb3c50e..28f2cf2 100644\n--- a/drivers/bus/dpaa/base/qbman/bman_driver.c\n+++ b/drivers/bus/dpaa/base/qbman/bman_driver.c\n@@ -65,6 +65,7 @@ static __thread struct dpaa_ioctl_portal_map map = {\n static int fsl_bman_portal_init(uint32_t idx, int is_shared)\n {\n \tcpu_set_t cpuset;\n+\tstruct bman_portal *portal;\n \tint loop, ret;\n \tstruct dpaa_ioctl_irq_map irq_map;\n \n@@ -111,6 +112,14 @@ static int fsl_bman_portal_init(uint32_t idx, int is_shared)\n \t/* Use the IRQ FD as a unique IRQ number */\n \tpcfg.irq = fd;\n \n+\tportal = bman_create_affine_portal(&pcfg);\n+\tif (!portal) {\n+\t\tpr_err(\"Bman portal initialisation failed (%d)\",\n+\t\t pcfg.cpu);\n+\t\tprocess_portal_unmap(&map.addr);\n+\t\treturn -EBUSY;\n+\t}\n+\n \t/* Set the IRQ number */\n \tirq_map.type = dpaa_portal_bman;\n \tirq_map.portal_cinh = map.addr.cinh;\n@@ -120,10 +129,13 @@ static int fsl_bman_portal_init(uint32_t idx, int is_shared)\n \n static int fsl_bman_portal_finish(void)\n {\n+\t__maybe_unused const struct bm_portal_config *cfg;\n \tint ret;\n \n \tprocess_portal_irq_unmap(fd);\n \n+\tcfg = bman_destroy_affine_portal();\n+\tBUG_ON(cfg != &pcfg);\n \tret = process_portal_unmap(&map.addr);\n \tif (ret)\n \t\terror(0, ret, \"process_portal_unmap()\");\ndiff --git a/drivers/bus/dpaa/base/qbman/dpaa_alloc.c b/drivers/bus/dpaa/base/qbman/dpaa_alloc.c\nindex 690576a..35dba7f 100644\n--- a/drivers/bus/dpaa/base/qbman/dpaa_alloc.c\n+++ b/drivers/bus/dpaa/base/qbman/dpaa_alloc.c\n@@ -41,6 +41,22 @@\n #include \"dpaa_sys.h\"\n #include <process.h>\n #include <fsl_qman.h>\n+#include <fsl_bman.h>\n+\n+int bman_alloc_bpid_range(u32 *result, u32 count, u32 align, int partial)\n+{\n+\treturn process_alloc(dpaa_id_bpid, result, count, align, partial);\n+}\n+\n+void bman_release_bpid_range(u32 bpid, u32 count)\n+{\n+\tprocess_release(dpaa_id_bpid, bpid, count);\n+}\n+\n+int bman_reserve_bpid_range(u32 bpid, u32 count)\n+{\n+\treturn process_reserve(dpaa_id_bpid, bpid, count);\n+}\n \n int qman_alloc_fqid_range(u32 *result, u32 count, u32 align, int partial)\n {\n", "prefixes": [ "dpdk-dev", "v2", "14/40" ] }