Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2393/?format=api
{ "id": 2393, "url": "https://patches.dpdk.org/api/patches/2393/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1421747640-20978-3-git-send-email-danny.zhou@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1421747640-20978-3-git-send-email-danny.zhou@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1421747640-20978-3-git-send-email-danny.zhou@intel.com", "date": "2015-01-20T09:53:57", "name": "[dpdk-dev,RFC,2/5] ixgbe: enable rx queue interrupts", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b5fe75ea829f50c7ee445623d14a285facce8ae9", "submitter": { "id": 29, "url": "https://patches.dpdk.org/api/people/29/?format=api", "name": "Zhou, Danny", "email": "danny.zhou@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1421747640-20978-3-git-send-email-danny.zhou@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/2393/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/2393/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 19F6D5AA2;\n\tTue, 20 Jan 2015 10:54:29 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 178F75A9D\n\tfor <dev@dpdk.org>; Tue, 20 Jan 2015 10:54:23 +0100 (CET)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga102.jf.intel.com with ESMTP; 20 Jan 2015 01:51:19 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga003.jf.intel.com with ESMTP; 20 Jan 2015 01:47:38 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t0K9sBdn000480;\n\tTue, 20 Jan 2015 17:54:11 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t0K9s8UI021028; Tue, 20 Jan 2015 17:54:10 +0800", "(from dyzhou@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t0K9s8vY021024; \n\tTue, 20 Jan 2015 17:54:08 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.09,433,1418112000\"; d=\"scan'208\";a=\"514752784\"", "From": "Danny Zhou <danny.zhou@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 20 Jan 2015 17:53:57 +0800", "Message-Id": "<1421747640-20978-3-git-send-email-danny.zhou@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1421747640-20978-1-git-send-email-danny.zhou@intel.com>", "References": "<1421747640-20978-1-git-send-email-danny.zhou@intel.com>", "Subject": "[dpdk-dev] [RFC PATCH 2/5] ixgbe: enable rx queue interrupts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Danny Zhou <danny.zhou@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe_ethdev.c | 203 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 203 insertions(+)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe_ethdev.c b/lib/librte_pmd_ixgbe/ixgbe_ethdev.c\nindex 3fc3738..1d694c5 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe_ethdev.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe_ethdev.c\n@@ -173,6 +173,7 @@ static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n \t\t\tuint16_t reta_size);\n static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);\n static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);\n+static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);\n static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);\n static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);\n static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,\n@@ -217,6 +218,11 @@ static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,\n static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,\n \t\tuint8_t\trule_id);\n \n+static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);\n+static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);\n+static void ixgbe_set_ivar(struct ixgbe_hw *hw, s8 direction, u8 queue, u8 msix_vector);\n+static void ixgbe_configure_msix(struct ixgbe_hw *hw);\n+\n static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,\n \t\tuint16_t queue_idx, uint16_t tx_rate);\n static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n@@ -332,6 +338,8 @@ static struct eth_dev_ops ixgbe_eth_dev_ops = {\n \t.tx_queue_start\t = ixgbe_dev_tx_queue_start,\n \t.tx_queue_stop = ixgbe_dev_tx_queue_stop,\n \t.rx_queue_setup = ixgbe_dev_rx_queue_setup,\n+\t.rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,\n+\t.rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,\n \t.rx_queue_release = ixgbe_dev_rx_queue_release,\n \t.rx_queue_count = ixgbe_dev_rx_queue_count,\n \t.rx_descriptor_done = ixgbe_dev_rx_descriptor_done,\n@@ -1481,6 +1489,9 @@ ixgbe_dev_start(struct rte_eth_dev *dev)\n \t/* configure PF module if SRIOV enabled */\n \tixgbe_pf_host_configure(dev);\n \n+\t/* confiugre msix for sleep until rx interrupt */\n+\tixgbe_configure_msix(hw);\n+\n \t/* initialize transmission unit */\n \tixgbe_dev_tx_init(dev);\n \n@@ -1550,6 +1561,10 @@ skip_link_setup:\n \tif (dev->data->dev_conf.intr_conf.lsc != 0)\n \t\tixgbe_dev_lsc_interrupt_setup(dev);\n \n+\t/* check if rxq interrupt is enabled */\n+\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n+\t\tixgbe_dev_rxq_interrupt_setup(dev);\n+\n \t/* resume enabled intr since hw reset */\n \tixgbe_enable_intr(dev);\n \n@@ -2212,6 +2227,28 @@ ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+/**\n+ * It clears the interrupt causes and enables the interrupt.\n+ * It will be called once only during nic initialized.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static int\n+ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)\n+{\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n+\n+\tintr->mask |= IXGBE_EICR_RTX_QUEUE;\n+\n+\treturn 0;\n+}\n+\n /*\n * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.\n *\n@@ -3502,6 +3539,172 @@ ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)\n \treturn 0;\n }\n \n+static int\n+ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tu32 mask;\n+\tstruct ixgbe_hw *hw =\n+\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n+\n+\tif (queue_id < 16) {\n+\t\tixgbe_disable_intr(hw);\n+\t\tintr->mask |= (1 << queue_id);\n+\t\tixgbe_enable_intr(dev);\n+\t} else if (queue_id < 32) {\n+\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));\n+\t\tmask &= (1 << queue_id);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);\n+\t} else if (queue_id < 64) {\n+\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));\n+\t\tmask &= (1 << (queue_id - 32));\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tu32 mask;\n+\tstruct ixgbe_hw *hw =\n+\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n+\n+\tif (queue_id < 16) {\n+\t\tixgbe_disable_intr(hw);\n+\t\tintr->mask &= ~(1 << queue_id);\n+\t\tixgbe_enable_intr(dev);\n+\t} else if (queue_id < 32) {\n+\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));\n+\t\tmask &= ~(1 << queue_id);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);\n+\t} else if (queue_id < 64) {\n+\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));\n+\t\tmask &= ~(1 << (queue_id - 32));\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors\n+ * @hw: pointer to ixgbe_hw struct\n+ * @direction: 0 for Rx, 1 for Tx, -1 for other causes\n+ * @queue: queue to map the corresponding interrupt to\n+ * @msix_vector: the vector to map to the corresponding queue\n+ */\n+static void\n+ixgbe_set_ivar(struct ixgbe_hw *hw, s8 direction,\n+\t\t\t u8 queue, u8 msix_vector)\n+{\n+\tu32 ivar, index;\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_82598EB:\n+\t\tmsix_vector |= IXGBE_IVAR_ALLOC_VAL;\n+\t\tif (direction == -1)\n+\t\t\tdirection = 0;\n+\t\tindex = (((direction * 64) + queue) >> 2) & 0x1F;\n+\t\tivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));\n+\t\tivar &= ~(0xFF << (8 * (queue & 0x3)));\n+\t\tivar |= (msix_vector << (8 * (queue & 0x3)));\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);\n+\t\tbreak;\n+\tcase ixgbe_mac_82599EB:\n+\tcase ixgbe_mac_X540:\n+\t\tif (direction == -1) {\n+\t\t\t/* other causes */\n+\t\t\tmsix_vector |= IXGBE_IVAR_ALLOC_VAL;\n+\t\t\tindex = ((queue & 1) * 8);\n+\t\t\tivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);\n+\t\t\tivar &= ~(0xFF << index);\n+\t\t\tivar |= (msix_vector << index);\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);\n+\t\t\tbreak;\n+\t\t} else {\n+\t\t\t/* tx or rx causes */\n+\t\t\tmsix_vector |= IXGBE_IVAR_ALLOC_VAL;\n+\t\t\tindex = ((16 * (queue & 1)) + (8 * direction));\n+\t\t\tivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));\n+\t\t\tivar &= ~(0xFF << index);\n+\t\t\tivar |= (msix_vector << index);\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);\n+\t\t\tbreak;\n+\t\t}\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * ixgbe_configure_msix - Configure MSI-X hardware\n+ * @hw: board private structure\n+ * ixgbe_configure_msix sets up the hardware to properly generate MSI-X\n+ * interrupts.\n+ */\n+static void\n+ixgbe_configure_msix(struct ixgbe_hw *hw)\n+{\n+\tint queue_id;\n+\tu32 mask;\n+\tu32 gpie;\n+\n+\t/* set GPIE for in MSI-x mode */\n+\tgpie = IXGBE_READ_REG(hw, IXGBE_GPIE);\n+\tgpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |\n+\t\t IXGBE_GPIE_OCD;\n+\tgpie |= IXGBE_GPIE_EIAME;\n+\t/*\n+\t * use EIAM to auto-mask when MSI-X interrupt is asserted\n+\t * this saves a register write for every interrupt\n+\t */\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_82598EB:\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);\n+\t\tbreak;\n+\tcase ixgbe_mac_82599EB:\n+\tcase ixgbe_mac_X540:\n+\tdefault:\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);\n+\t\tbreak;\n+\t}\n+\tIXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);\n+\n+\t/*\n+\t* Populate the IVAR table and set the ITR values to the\n+\t* corresponding register.\n+\t*/\n+\tfor (queue_id = 0; queue_id < VFIO_MAX_QUEUE_ID; queue_id++)\n+\t\tixgbe_set_ivar(hw, 0, queue_id, queue_id);\n+\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_82598EB:\n+\t\tixgbe_set_ivar(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,\n+\t\t\t VFIO_MAX_QUEUE_ID);\n+\t\tbreak;\n+\tcase ixgbe_mac_82599EB:\n+\tcase ixgbe_mac_X540:\n+\t\tixgbe_set_ivar(hw, -1, 1, 32);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\tIXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id), 1950);\n+\n+\t/* set up to autoclear timer, and the vectors */\n+\tmask = IXGBE_EIMS_ENABLE_MASK;\n+\tmask &= ~(IXGBE_EIMS_OTHER |\n+\t\t IXGBE_EIMS_MAILBOX |\n+\t\t IXGBE_EIMS_LSC);\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);\n+}\n+\n static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,\n \tuint16_t queue_idx, uint16_t tx_rate)\n {\n", "prefixes": [ "dpdk-dev", "RFC", "2/5" ] }