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GET /api/patches/2199/?format=api
https://patches.dpdk.org/api/patches/2199/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1420527230-17037-10-git-send-email-zlu@ezchip.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1420527230-17037-10-git-send-email-zlu@ezchip.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1420527230-17037-10-git-send-email-zlu@ezchip.com", "date": "2015-01-06T06:53:47", "name": "[dpdk-dev,v2,09/12] eal/tile: add CPU flags operations for TileGx", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "cc862b5f40dc9e03e6b647fbcdf539909f437ab0", "submitter": { "id": 130, "url": "https://patches.dpdk.org/api/people/130/?format=api", "name": "Zhigang Lu", "email": "zlu@ezchip.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1420527230-17037-10-git-send-email-zlu@ezchip.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/2199/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/2199/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 4ECC45A40;\n\tTue, 6 Jan 2015 08:02:17 +0100 (CET)", "from emea01-am1-obe.outbound.protection.outlook.com\n\t(mail-am1on0061.outbound.protection.outlook.com [157.56.112.61])\n\tby dpdk.org (Postfix) with ESMTP id 358AE58DD\n\tfor <dev@dpdk.org>; Tue, 6 Jan 2015 08:02:16 +0100 (CET)", "from DB4PR02CA0037.eurprd02.prod.outlook.com (10.242.174.165) by\n\tAM3PR02MB004.eurprd02.prod.outlook.com (10.242.242.26) with Microsoft\n\tSMTP Server (TLS) id 15.1.49.12; Tue, 6 Jan 2015 07:02:06 +0000", "from DB3FFO11FD046.protection.gbl (2a01:111:f400:7e04::180) by\n\tDB4PR02CA0037.outlook.office365.com (2a01:111:e400:983b::37) with\n\tMicrosoft SMTP Server (TLS) id 15.1.49.12 via Frontend Transport;\n\tTue, 6 Jan 2015 07:02:06 +0000", "from bjgfarm-2.internal.tilera.com (124.207.145.166) by\n\tDB3FFO11FD046.mail.protection.outlook.com (10.47.217.77) with\n\tMicrosoft SMTP Server (TLS) id 15.1.49.13 via Frontend Transport;\n\tTue, 6 Jan 2015 07:02:03 +0000", "(from zlu@localhost)\n\tby bjgfarm-2.internal.tilera.com (8.14.4/8.14.4/Submit) id\n\tt0671eGS017218; Tue, 6 Jan 2015 15:01:40 +0800" ], "From": "Zhigang Lu <zlu@ezchip.com>", "To": "<dev@dpdk.org>", "Date": "Tue, 6 Jan 2015 14:53:47 +0800", "Message-ID": "<1420527230-17037-10-git-send-email-zlu@ezchip.com>", "X-Mailer": "git-send-email 2.1.2", "In-Reply-To": "<1420527230-17037-1-git-send-email-zlu@ezchip.com>", "References": "<1420527230-17037-1-git-send-email-zlu@ezchip.com>", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of ezchip.com does not\n\tdesignate 124.207.145.166 as permitted sender)\n\treceiver=protection.outlook.com; client-ip=124.207.145.166;\n\thelo=bjgfarm-2.internal.tilera.com;", "Authentication-Results": "spf=fail (sender IP is 124.207.145.166)\n\tsmtp.mailfrom=zlu@ezchip.com; ", "X-Forefront-Antispam-Report": "CIP:124.207.145.166; CTRY:CN; IPV:NLI; EFV:NLI; \n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(339900001)(189002)(199003)(97736003)(19580405001)(21056001)(120916001)(229853001)(19580395003)(6806004)(99396003)(36756003)(107046002)(2351001)(62966003)(68736005)(2950100001)(31966008)(106466001)(42186005)(77156002)(105606002)(50466002)(50226001)(4396001)(46102003)(48376002)(110136001)(89996001)(33646002)(84676001)(50986999)(92566001)(104016003)(86362001)(76176999)(64706001)(87936001)(20776003)(47776003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR02MB004;\n\tH:bjgfarm-2.internal.tilera.com; \n\tFPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en;", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-DmarcAction": "None", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:(3005003);SRVR:AM3PR02MB004;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0; PCL:0; RULEID:(601004);\n\tSRVR:AM3PR02MB004; ", "BCL:0;PCL:0;RULEID:;SRVR:AM3PR02MB004;" ], "X-Forefront-PRVS": "0448A97BF2", "X-OriginatorOrg": "ezchip.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Jan 2015 07:02:03.3373\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "0fc16e0a-3cd3-4092-8b2f-0a42cff122c3", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3;\n\tIp=[124.207.145.166]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM3PR02MB004", "Subject": "[dpdk-dev] [PATCH v2 09/12] eal/tile: add CPU flags operations for\n\tTileGx", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds empty functions for CPU flags operations to support DPDK,\nsince tile processor doesn't have CPU flag hardware registers.\n\nSigned-off-by: Zhigang Lu <zlu@ezchip.com>\nSigned-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>\n---\n .../common/include/arch/tile/rte_cpuflags.h | 78 ++++++++++++++++++++++\n 1 file changed, 78 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_cpuflags.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..872e38c\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\n@@ -0,0 +1,78 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2014 Tilera Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Tilera Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_CPUFLAGS_TILE_H_\n+#define _RTE_CPUFLAGS_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdint.h>\n+\n+#include <rte_common.h>\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_SSE4_1 = 0, /**< SSE4_1 */\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS,\t/**< This should always be the last! */\n+};\n+\n+static const struct feature_entry cpu_feature_table[] = {\n+\tFEAT_DEF(SSE4_1, 0x00000000, 0, 0, 0)\n+};\n+\n+static inline void\n+rte_cpu_get_features(__rte_unused uint32_t leaf,\n+\t\t __rte_unused uint32_t subleaf,\n+\t\t __rte_unused cpuid_registers_t out)\n+{\n+}\n+\n+static inline int\n+rte_cpu_get_flag_enabled(__rte_unused enum rte_cpu_flag_t feature)\n+{\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\t/* Flag does not match anything in the feature tables */\n+\t\treturn -ENOENT;\n+\n+\treturn 0;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_TILE_H_ */\n", "prefixes": [ "dpdk-dev", "v2", "09/12" ] }{ "id": 2199, "url": "