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GET /api/patches/2197/?format=api
{ "id": 2197, "url": "https://patches.dpdk.org/api/patches/2197/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1420527230-17037-8-git-send-email-zlu@ezchip.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1420527230-17037-8-git-send-email-zlu@ezchip.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1420527230-17037-8-git-send-email-zlu@ezchip.com", "date": "2015-01-06T06:53:45", "name": "[dpdk-dev,v2,07/12] eal: split vector operations to architecture specific", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d978ff64d0bf09218f59a63f89ab2c71ccff9444", "submitter": { "id": 130, "url": "https://patches.dpdk.org/api/people/130/?format=api", "name": "Zhigang Lu", "email": "zlu@ezchip.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1420527230-17037-8-git-send-email-zlu@ezchip.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/2197/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/2197/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5C0375A40;\n\tTue, 6 Jan 2015 08:01:01 +0100 (CET)", "from emea01-db3-obe.outbound.protection.outlook.com\n\t(mail-db3on0087.outbound.protection.outlook.com [157.55.234.87])\n\tby dpdk.org (Postfix) with ESMTP id 5D04F58DD\n\tfor <dev@dpdk.org>; Tue, 6 Jan 2015 08:00:59 +0100 (CET)", "from DB4PR02CA0016.eurprd02.prod.outlook.com (10.242.174.144) by\n\tAM2PR02MB0580.eurprd02.prod.outlook.com (25.160.56.26) with Microsoft\n\tSMTP Server (TLS) id 15.1.49.12; Tue, 6 Jan 2015 07:00:56 +0000", "from DB3FFO11FD022.protection.gbl (2a01:111:f400:7e04::160) by\n\tDB4PR02CA0016.outlook.office365.com (2a01:111:e400:983b::16) with\n\tMicrosoft SMTP Server (TLS) id 15.1.49.12 via Frontend Transport;\n\tTue, 6 Jan 2015 07:00:56 +0000", "from bjgfarm-2.internal.tilera.com (124.207.145.166) by\n\tDB3FFO11FD022.mail.protection.outlook.com (10.47.217.53) with\n\tMicrosoft SMTP Server (TLS) id 15.1.49.13 via Frontend Transport;\n\tTue, 6 Jan 2015 07:00:50 +0000", "(from zlu@localhost)\n\tby bjgfarm-2.internal.tilera.com (8.14.4/8.14.4/Submit) id\n\tt0670GXS017182; Tue, 6 Jan 2015 15:00:16 +0800" ], "From": "Zhigang Lu <zlu@ezchip.com>", "To": "<dev@dpdk.org>", "Date": "Tue, 6 Jan 2015 14:53:45 +0800", "Message-ID": "<1420527230-17037-8-git-send-email-zlu@ezchip.com>", "X-Mailer": "git-send-email 2.1.2", "In-Reply-To": "<1420527230-17037-1-git-send-email-zlu@ezchip.com>", "References": "<1420527230-17037-1-git-send-email-zlu@ezchip.com>", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of ezchip.com does not\n\tdesignate 124.207.145.166 as permitted sender)\n\treceiver=protection.outlook.com; client-ip=124.207.145.166;\n\thelo=bjgfarm-2.internal.tilera.com;", "Authentication-Results": "spf=fail (sender IP is 124.207.145.166)\n\tsmtp.mailfrom=zlu@ezchip.com; ", "X-Forefront-Antispam-Report": "CIP:124.207.145.166; CTRY:CN; IPV:NLI; EFV:NLI; \n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(339900001)(199003)(189002)(33646002)(92566001)(36756003)(89996001)(86362001)(87936001)(50226001)(104016003)(110136001)(106466001)(97736003)(31966008)(2351001)(107046002)(229853001)(105606002)(19580405001)(99396003)(21056001)(76176999)(46102003)(50986999)(50466002)(48376002)(84676001)(120916001)(42186005)(2950100001)(19580395003)(4396001)(47776003)(6806004)(20776003)(64706001)(77156002)(62966003)(68736005);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM2PR02MB0580;\n\tH:bjgfarm-2.internal.tilera.com; \n\tFPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en;", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-DmarcAction": "None", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:(3005003);SRVR:AM2PR02MB0580;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0; PCL:0; RULEID:(601004);\n\tSRVR:AM2PR02MB0580; ", "BCL:0; PCL:0; RULEID:;\n\tSRVR:AM2PR02MB0580; " ], "X-Forefront-PRVS": "0448A97BF2", "X-OriginatorOrg": "ezchip.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Jan 2015 07:00:50.9675\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "0fc16e0a-3cd3-4092-8b2f-0a42cff122c3", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3;\n\tIp=[124.207.145.166]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM2PR02MB0580", "Subject": "[dpdk-dev] [PATCH v2 07/12] eal: split vector operations to\n\tarchitecture specific", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch splits vector operations from DPDK and push them\nto architecture specific arch directories, so that other processor\narchitecture can implement its own vector functions to support DPDK.\n\nSigned-off-by: Zhigang Lu <zlu@ezchip.com>\nSigned-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>\n---\n lib/librte_eal/common/Makefile | 3 +-\n .../common/include/arch/ppc_64/rte_common_vect.h | 73 +++++++++++++++++\n .../common/include/arch/x86/rte_common_vect.h | 81 +++++++++++++++++++\n .../common/include/generic/rte_common_vect.h | 51 ++++++++++++\n lib/librte_eal/common/include/rte_common_vect.h | 93 ----------------------\n 5 files changed, 206 insertions(+), 95 deletions(-)\n create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_common_vect.h\n create mode 100644 lib/librte_eal/common/include/arch/x86/rte_common_vect.h\n create mode 100644 lib/librte_eal/common/include/generic/rte_common_vect.h\n delete mode 100644 lib/librte_eal/common/include/rte_common_vect.h", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex 52c1a5f..02cac22 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -39,7 +39,6 @@ INC += rte_rwlock.h rte_tailq.h rte_interrupts.h rte_alarm.h\n INC += rte_string_fns.h rte_version.h rte_tailq_elem.h\n INC += rte_eal_memconfig.h rte_malloc_heap.h\n INC += rte_hexdump.h rte_devargs.h rte_dev.h\n-INC += rte_common_vect.h\n INC += rte_pci_dev_feature_defs.h rte_pci_dev_features.h\n \n ifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y)\n@@ -47,7 +46,7 @@ INC += rte_warnings.h\n endif\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n-GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h\n+GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_common_vect.h\n # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk\n ARCH_DIR ?= $(RTE_ARCH)\n ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))\ndiff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_common_vect.h b/lib/librte_eal/common/include/arch/ppc_64/rte_common_vect.h\nnew file mode 100644\nindex 0000000..485b7eb\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_common_vect.h\n@@ -0,0 +1,73 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_COMMON_VECT_PPC_64_H_\n+#define _RTE_COMMON_VECT_PPC_64_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE SSE/AVX related header.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_common_vect.h\"\n+\n+#if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))\n+\n+#ifdef __SSE__\n+#include <xmmintrin.h>\n+#endif\n+\n+#ifdef __SSE2__\n+#include <emmintrin.h>\n+#endif\n+\n+#if defined(__SSE4_2__) || defined(__SSE4_1__)\n+#include <smmintrin.h>\n+#endif\n+\n+#else\n+\n+#include <x86intrin.h>\n+\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_COMMON__VECT_PPC_64_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/x86/rte_common_vect.h b/lib/librte_eal/common/include/arch/x86/rte_common_vect.h\nnew file mode 100644\nindex 0000000..5ffe3fb\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/x86/rte_common_vect.h\n@@ -0,0 +1,81 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_COMMON_VECT_X86_H_\n+#define _RTE_COMMON_VECT_X86_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE SSE/AVX related header.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_common_vect.h\"\n+\n+#if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))\n+\n+#ifdef __SSE__\n+#include <xmmintrin.h>\n+#endif\n+\n+#ifdef __SSE2__\n+#include <emmintrin.h>\n+#endif\n+\n+#if defined(__SSE4_2__) || defined(__SSE4_1__)\n+#include <smmintrin.h>\n+#endif\n+\n+#else\n+\n+#include <x86intrin.h>\n+\n+#endif\n+\n+#ifdef RTE_ARCH_I686\n+#define _mm_cvtsi128_si64(a) ({ \\\n+\trte_xmm_t m; \\\n+\tm.m = (a); \\\n+\t(m.u64[0]); \\\n+})\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_COMMON__VECT_X86_H_ */\ndiff --git a/lib/librte_eal/common/include/generic/rte_common_vect.h b/lib/librte_eal/common/include/generic/rte_common_vect.h\nnew file mode 100644\nindex 0000000..3e32682\n--- /dev/null\n+++ b/lib/librte_eal/common/include/generic/rte_common_vect.h\n@@ -0,0 +1,51 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_COMMON_VECT_H_\n+#define _RTE_COMMON_VECT_H_\n+\n+typedef __m128i xmm_t;\n+\n+#define\tXMM_SIZE\t(sizeof(xmm_t))\n+#define\tXMM_MASK\t(XMM_SIZE - 1)\n+\n+typedef union rte_xmm {\n+\txmm_t m;\n+\tuint8_t u8[XMM_SIZE / sizeof(uint8_t)];\n+\tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n+\tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n+\tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n+\tdouble pd[XMM_SIZE / sizeof(double)];\n+} rte_xmm_t;\n+\n+#endif /* _RTE_COMMON__VECT_H_ */\ndiff --git a/lib/librte_eal/common/include/rte_common_vect.h b/lib/librte_eal/common/include/rte_common_vect.h\ndeleted file mode 100644\nindex 95bf4b1..0000000\n--- a/lib/librte_eal/common/include/rte_common_vect.h\n+++ /dev/null\n@@ -1,93 +0,0 @@\n-/*-\n- * BSD LICENSE\n- *\n- * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n- * All rights reserved.\n- *\n- * Redistribution and use in source and binary forms, with or without\n- * modification, are permitted provided that the following conditions\n- * are met:\n- *\n- * * Redistributions of source code must retain the above copyright\n- * notice, this list of conditions and the following disclaimer.\n- * * Redistributions in binary form must reproduce the above copyright\n- * notice, this list of conditions and the following disclaimer in\n- * the documentation and/or other materials provided with the\n- * distribution.\n- * * Neither the name of Intel Corporation nor the names of its\n- * contributors may be used to endorse or promote products derived\n- * from this software without specific prior written permission.\n- *\n- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- */\n-\n-#ifndef _RTE_COMMON_VECT_H_\n-#define _RTE_COMMON_VECT_H_\n-\n-/**\n- * @file\n- *\n- * RTE SSE/AVX related header.\n- */\n-\n-#if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))\n-\n-#ifdef __SSE__\n-#include <xmmintrin.h>\n-#endif\n-\n-#ifdef __SSE2__\n-#include <emmintrin.h>\n-#endif\n-\n-#if defined(__SSE4_2__) || defined(__SSE4_1__)\n-#include <smmintrin.h>\n-#endif\n-\n-#else\n-\n-#include <x86intrin.h>\n-\n-#endif\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-typedef __m128i xmm_t;\n-\n-#define\tXMM_SIZE\t(sizeof(xmm_t))\n-#define\tXMM_MASK\t(XMM_SIZE - 1)\n-\n-typedef union rte_xmm {\n-\txmm_t m;\n-\tuint8_t u8[XMM_SIZE / sizeof(uint8_t)];\n-\tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n-\tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n-\tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n-\tdouble pd[XMM_SIZE / sizeof(double)];\n-} rte_xmm_t;\n-\n-#ifdef RTE_ARCH_I686\n-#define _mm_cvtsi128_si64(a) ({ \\\n-\trte_xmm_t m; \\\n-\tm.m = (a); \\\n-\t(m.u64[0]); \\\n-})\n-#endif\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_COMMON__VECT_H_ */\n", "prefixes": [ "dpdk-dev", "v2", "07/12" ] }