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GET /api/patches/194/?format=api
{ "id": 194, "url": "https://patches.dpdk.org/api/patches/194/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1408695969-9774-5-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1408695969-9774-5-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1408695969-9774-5-git-send-email-helin.zhang@intel.com", "date": "2014-08-22T08:26:08", "name": "[dpdk-dev,4/5] i40e: rework of updating/querying redirection table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0510000e67dd9877957630682374cd00c9fb846e", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1408695969-9774-5-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/194/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/194/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<hzhan75@shecgisg004.sh.intel.com>", "Received": [ "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 8AFBAB378\n\tfor <dev@dpdk.org>; Fri, 22 Aug 2014 10:22:45 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga102.fm.intel.com with ESMTP; 22 Aug 2014 01:26:25 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 22 Aug 2014 01:26:25 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s7M8QNUP017807;\n\tFri, 22 Aug 2014 16:26:23 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s7M8QJIm009912; Fri, 22 Aug 2014 16:26:21 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7M8QJIh009908; \n\tFri, 22 Aug 2014 16:26:19 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,378,1406617200\"; d=\"scan'208\";a=\"588419818\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 22 Aug 2014 16:26:08 +0800", "Message-Id": "<1408695969-9774-5-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>", "References": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 4/5] i40e: rework of updating/querying\n\tredirection table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "X-List-Received-Date": "Fri, 22 Aug 2014 08:22:46 -0000" }, "content": "i40e can support 128 or 512 entries of redirection\ntable entries, according to the firmware configuration.\nIn addition, as ethdev has been changed to support\nmultiple sizes of redirection table, the functions of\nupdating/querying redirection table need to be reworked.\nGetting the redirection table size is supported in ops\nof 'dev_infos_get'.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Jijiang Liu <jijiang.liu@intel.com>\nReviewed-by: Cunming Liang <cunming.liang@intel.com>\nReviewed-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 88 ++++++++++++++++++++++++------------\n lib/librte_pmd_i40e/i40e_ethdev.h | 1 +\n lib/librte_pmd_i40e/i40e_ethdev_vf.c | 1 +\n 3 files changed, 62 insertions(+), 28 deletions(-)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 9ed31b5..7289f1a 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -158,9 +158,11 @@ static void i40e_macaddr_add(struct rte_eth_dev *dev,\n \t\t\t uint32_t pool);\n static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);\n static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_rss_reta *reta_conf);\n+\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\t uint16_t reta_size);\n static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_rss_reta *reta_conf);\n+\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\t uint16_t reta_size);\n \n static int i40e_get_cap(struct i40e_hw *hw);\n static int i40e_pf_parameter_init(struct rte_eth_dev *dev);\n@@ -1231,6 +1233,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n \t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n \t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n+\tdev_info->reta_size = pf->hash_lut_size;\n }\n \n static int\n@@ -1431,32 +1434,40 @@ i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)\n \n static int\n i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_rss_reta *reta_conf)\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n {\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t lut, l;\n-\tuint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;\n-\n-\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < max)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n-\t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t\t\t(i - max)) & 0xF);\n+\tuint16_t i, j, lut_size = pf->hash_lut_size;\n+\tuint16_t idx, shift;\n+\tuint8_t mask;\n+\n+\tif (reta_size != lut_size ||\n+\t\treta_size > ETH_RSS_RETA_SIZE_512) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\t\t\"(%d)\\n\", reta_size, lut_size);\n+\t\treturn -EINVAL;\n+\t}\n \n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf);\n \t\tif (!mask)\n \t\t\tcontinue;\n-\n-\t\tif (mask == 0xF)\n+\t\tif (mask == 0xf)\n \t\t\tl = 0;\n \t\telse\n \t\t\tl = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));\n-\n \t\tfor (j = 0, lut = 0; j < 4; j++) {\n \t\t\tif (mask & (0x1 << j))\n-\t\t\t\tlut |= reta_conf->reta[i + j] << (8 * j);\n+\t\t\t\tlut |= reta_conf[idx].reta[shift + j] <<\n+\t\t\t\t\t\t\t(CHAR_BIT * j);\n \t\t\telse\n-\t\t\t\tlut |= l & (0xFF << (8 * j));\n+\t\t\t\tlut |= l & (0xff << (CHAR_BIT * j));\n \t\t}\n \t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n \t}\n@@ -1466,27 +1477,36 @@ i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n \n static int\n i40e_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_eth_rss_reta *reta_conf)\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size)\n {\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t lut;\n-\tuint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;\n-\n-\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < max)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n-\t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t\t\t(i - max)) & 0xF);\n+\tuint16_t i, j, lut_size = pf->hash_lut_size;\n+\tuint16_t idx, shift;\n+\tuint8_t mask;\n+\n+\tif (reta_size != lut_size ||\n+\t\treta_size > ETH_RSS_RETA_SIZE_512) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\t\t\"(%d)\\n\", reta_size, lut_size);\n+\t\treturn -EINVAL;\n+\t}\n \n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf);\n \t\tif (!mask)\n \t\t\tcontinue;\n \n \t\tlut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));\n \t\tfor (j = 0; j < 4; j++) {\n \t\t\tif (mask & (0x1 << j))\n-\t\t\t\treta_conf->reta[i + j] =\n-\t\t\t\t\t(uint8_t)((lut >> (8 * j)) & 0xFF);\n+\t\t\t\treta_conf[idx].reta[shift] = ((lut >>\n+\t\t\t\t\t(CHAR_BIT * j)) & 0xff);\n \t\t}\n \t}\n \n@@ -2761,7 +2781,19 @@ i40e_pf_setup(struct i40e_pf *pf)\n \n \t/* Configure filter control */\n \tmemset(&settings, 0, sizeof(settings));\n-\tsettings.hash_lut_size = I40E_HASH_LUT_SIZE_128;\n+\tif (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)\n+\t\tsettings.hash_lut_size = I40E_HASH_LUT_SIZE_128;\n+\telse if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)\n+\t\tsettings.hash_lut_size = I40E_HASH_LUT_SIZE_512;\n+\telse {\n+\t\tPMD_DRV_LOG(ERR, \"Hash lookup table size (%u) not supported\\n\",\n+\t\t\t\t\t\thw->func_caps.rss_table_size);\n+\t\treturn I40E_ERR_PARAM;\n+\t}\n+\tPMD_DRV_LOG(INFO, \"Hardware capability of hash lookup table \"\n+\t\t\t\"size: %u\\n\", hw->func_caps.rss_table_size);\n+\tpf->hash_lut_size = hw->func_caps.rss_table_size;\n+\n \t/* Enable ethtype and macvlan filters */\n \tsettings.enable_ethtype = TRUE;\n \tsettings.enable_macvlan = TRUE;\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex 64deef2..a1a2e75 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -216,6 +216,7 @@ struct i40e_pf {\n \tuint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */\n \tuint16_t vf_nb_qps; /* The number of queue pairs of VF */\n \tuint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */\n+\tuint16_t hash_lut_size; /* The size of hash lookup table */\n };\n \n enum pending_msg {\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev_vf.c b/lib/librte_pmd_i40e/i40e_ethdev_vf.c\nindex 2726bfb..4d89f35 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev_vf.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev_vf.c\n@@ -1426,6 +1426,7 @@ i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \tdev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;\n \tdev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;\n \tdev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;\n+\tdev_info->reta_size = ETH_RSS_RETA_SIZE_64;\n }\n \n static void\n", "prefixes": [ "dpdk-dev", "4/5" ] }