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GET /api/patches/192/?format=api
{ "id": 192, "url": "https://patches.dpdk.org/api/patches/192/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1408695969-9774-3-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1408695969-9774-3-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1408695969-9774-3-git-send-email-helin.zhang@intel.com", "date": "2014-08-22T08:26:06", "name": "[dpdk-dev,2/5] e1000: rework of updating/querying redirection table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "30e29639f38f0a9a7b812e90e39b69bab824d489", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1408695969-9774-3-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/192/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/192/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<hzhan75@shecgisg004.sh.intel.com>", "Received": [ "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 6FD13B36D\n\tfor <dev@dpdk.org>; Fri, 22 Aug 2014 10:22:42 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga102.fm.intel.com with ESMTP; 22 Aug 2014 01:26:21 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 22 Aug 2014 01:26:20 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s7M8QIUi017800;\n\tFri, 22 Aug 2014 16:26:18 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s7M8QFZq009898; Fri, 22 Aug 2014 16:26:17 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7M8QFl9009894; \n\tFri, 22 Aug 2014 16:26:15 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,378,1406617200\"; d=\"scan'208\";a=\"588419806\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 22 Aug 2014 16:26:06 +0800", "Message-Id": "<1408695969-9774-3-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>", "References": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/5] e1000: rework of updating/querying\n\tredirection table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "X-List-Received-Date": "Fri, 22 Aug 2014 08:22:43 -0000" }, "content": "As ethdev has been changed to support multiple sizes\nof redirection table, the functions of updating/querying\nredirection table need to be reworked. In addition,\ngetting the redirection table size is supported in ops\nof 'dev_infos_get'.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Jijiang Liu <jijiang.liu@intel.com>\nReviewed-by: Cunming Liang <cunming.liang@intel.com>\nReviewed-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_e1000/igb_ethdev.c | 184 ++++++++++++++++++++++++++------------\n 1 file changed, 127 insertions(+), 57 deletions(-)", "diff": "diff --git a/lib/librte_pmd_e1000/igb_ethdev.c b/lib/librte_pmd_e1000/igb_ethdev.c\nindex 3187d92..47438ad 100644\n--- a/lib/librte_pmd_e1000/igb_ethdev.c\n+++ b/lib/librte_pmd_e1000/igb_ethdev.c\n@@ -71,6 +71,8 @@ static void eth_igb_stats_get(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_stats *rte_stats);\n static void eth_igb_stats_reset(struct rte_eth_dev *dev);\n static void eth_igb_infos_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_dev_info *dev_info);\n+static void eth_igbvf_infos_get(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_dev_info *dev_info);\n static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_fc_conf *fc_conf);\n@@ -124,10 +126,11 @@ static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,\n static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);\n static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);\n static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t struct rte_eth_rss_reta *reta_conf);\n+\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\t uint16_t reta_size);\n static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,\n-\t\tstruct rte_eth_rss_reta *reta_conf);\n-\n+\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\t uint16_t reta_size);\n static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,\n \t\t\tstruct rte_syn_filter *filter, uint16_t rx_queue);\n static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);\n@@ -270,7 +273,7 @@ static struct eth_dev_ops igbvf_eth_dev_ops = {\n \t.stats_get = eth_igbvf_stats_get,\n \t.stats_reset = eth_igbvf_stats_reset,\n \t.vlan_filter_set = igbvf_vlan_filter_set,\n-\t.dev_infos_get = eth_igb_infos_get,\n+\t.dev_infos_get = eth_igbvf_infos_get,\n \t.rx_queue_setup = eth_igb_rx_queue_setup,\n \t.rx_queue_release = eth_igb_rx_queue_release,\n \t.tx_queue_setup = eth_igb_tx_queue_setup,\n@@ -1257,8 +1260,7 @@ eth_igbvf_stats_reset(struct rte_eth_dev *dev)\n }\n \n static void\n-eth_igb_infos_get(struct rte_eth_dev *dev,\n-\t\t struct rte_eth_dev_info *dev_info)\n+eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n {\n \tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n@@ -1331,6 +1333,72 @@ eth_igb_infos_get(struct rte_eth_dev *dev,\n \t\tdev_info->max_tx_queues = 0;\n \t\tdev_info->max_vmdq_pools = 0;\n \t}\n+\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n+}\n+\n+static void\n+eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tdev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */\n+\tdev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */\n+\tdev_info->max_mac_addrs = hw->mac.rar_entry_count;\n+\tdev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |\n+\t\t\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n+\tdev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |\n+\t\t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n+\tswitch (hw->mac.type) {\n+\tcase e1000_82575:\n+\t\tdev_info->max_rx_queues = 4;\n+\t\tdev_info->max_tx_queues = 4;\n+\t\tdev_info->max_vmdq_pools = 0;\n+\t\tbreak;\n+\tcase e1000_82576:\n+\t\tdev_info->max_rx_queues = 16;\n+\t\tdev_info->max_tx_queues = 16;\n+\t\tdev_info->max_vmdq_pools = ETH_8_POOLS;\n+\t\tbreak;\n+\tcase e1000_82580:\n+\t\tdev_info->max_rx_queues = 8;\n+\t\tdev_info->max_tx_queues = 8;\n+\t\tdev_info->max_vmdq_pools = ETH_8_POOLS;\n+\t\tbreak;\n+\tcase e1000_i350:\n+\t\tdev_info->max_rx_queues = 8;\n+\t\tdev_info->max_tx_queues = 8;\n+\t\tdev_info->max_vmdq_pools = ETH_8_POOLS;\n+\t\tbreak;\n+\tcase e1000_i354:\n+\t\tdev_info->max_rx_queues = 8;\n+\t\tdev_info->max_tx_queues = 8;\n+\t\tbreak;\n+\tcase e1000_i210:\n+\t\tdev_info->max_rx_queues = 4;\n+\t\tdev_info->max_tx_queues = 4;\n+\t\tdev_info->max_vmdq_pools = 0;\n+\t\tbreak;\n+\tcase e1000_vfadapt:\n+\t\tdev_info->max_rx_queues = 2;\n+\t\tdev_info->max_tx_queues = 2;\n+\t\tdev_info->max_vmdq_pools = 0;\n+\t\tbreak;\n+\tcase e1000_vfadapt_i350:\n+\t\tdev_info->max_rx_queues = 1;\n+\t\tdev_info->max_tx_queues = 1;\n+\t\tdev_info->max_vmdq_pools = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Should not happen */\n+\t\tdev_info->max_rx_queues = 0;\n+\t\tdev_info->max_tx_queues = 0;\n+\t\tdev_info->max_vmdq_pools = 0;\n+\t}\n }\n \n /* return 0 means link status changed, -1 means not changed */\n@@ -2011,7 +2079,7 @@ igbvf_stop_adapter(struct rte_eth_dev *dev)\n \tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tmemset(&dev_info, 0, sizeof(dev_info));\n-\teth_igb_infos_get(dev, &dev_info);\n+\teth_igbvf_infos_get(dev, &dev_info);\n \n \t/* Clear interrupt mask to stop from interrupts being generated */\n \tigbvf_intr_disable(hw);\n@@ -2224,38 +2292,39 @@ igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n \n static int\n eth_igb_rss_reta_update(struct rte_eth_dev *dev,\n- struct rte_eth_rss_reta *reta_conf)\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size)\n {\n-\tuint8_t i,j,mask;\n-\tuint32_t reta;\n-\tstruct e1000_hw *hw =\n-\t\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint8_t i, j, mask;\n+\tuint32_t reta, r;\n+\tuint16_t idx, shift;\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\t/*\n-\t * Update Redirection Table RETA[n],n=0...31,The redirection table has\n-\t * 128-entries in 32 registers\n-\t */\n-\tfor(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < ETH_RSS_RETA_NUM_ENTRIES/2)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n+\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\tif (mask == 0xf)\n+\t\t\tr = 0;\n \t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t(i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);\n-\t\tif (mask != 0) {\n-\t\t\treta = 0;\n-\t\t\t/* If all 4 entries were set,don't need read RETA register */\n-\t\t\tif (mask != 0xF)\n-\t\t\t\treta = E1000_READ_REG(hw,E1000_RETA(i >> 2));\n-\n-\t\t\tfor (j = 0; j < 4; j++) {\n-\t\t\t\tif (mask & (0x1 << j)) {\n-\t\t\t\t\tif (mask != 0xF)\n-\t\t\t\t\t\treta &= ~(0xFF << 8 * j);\n-\t\t\t\t\treta |= reta_conf->reta[i + j] << 8 * j;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tE1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);\n+\t\t\tr = E1000_READ_REG(hw, E1000_RETA(i >> 2));\n+\t\tfor (j = 0, reta = 0; j < 4; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n+\t\t\t\t\t\t\t(CHAR_BIT * j);\n+\t\t\telse\n+\t\t\t\treta |= r & (0xff << (CHAR_BIT * j));\n \t\t}\n+\t\tE1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);\n \t}\n \n \treturn 0;\n@@ -2263,31 +2332,32 @@ eth_igb_rss_reta_update(struct rte_eth_dev *dev,\n \n static int\n eth_igb_rss_reta_query(struct rte_eth_dev *dev,\n- struct rte_eth_rss_reta *reta_conf)\n+\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t uint16_t reta_size)\n {\n-\tuint8_t i,j,mask;\n+\tuint8_t i, j, mask;\n \tuint32_t reta;\n-\tstruct e1000_hw *hw =\n-\t\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t idx, shift;\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\t/*\n-\t * Read Redirection Table RETA[n],n=0...31,The redirection table has\n-\t * 128-entries in 32 registers\n-\t */\n-\tfor(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < ETH_RSS_RETA_NUM_ENTRIES/2)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n-\t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t(i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);\n-\n-\t\tif (mask != 0) {\n-\t\t\treta = E1000_READ_REG(hw,E1000_RETA(i >> 2));\n-\t\t\tfor (j = 0; j < 4; j++) {\n-\t\t\t\tif (mask & (0x1 << j))\n-\t\t\t\t\treta_conf->reta[i + j] =\n-\t\t\t\t\t\t(uint8_t)((reta >> 8 * j) & 0xFF);\n-\t\t\t}\n+\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\treta = E1000_READ_REG(hw, E1000_RETA(i >> 2));\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta_conf[idx].reta[shift + j] =\n+\t\t\t\t\t((reta >> (CHAR_BIT * j)) & 0xff);\n \t\t}\n \t}\n \n", "prefixes": [ "dpdk-dev", "2/5" ] }