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GET /api/patches/17605/?format=api
{ "id": 17605, "url": "https://patches.dpdk.org/api/patches/17605/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1480833100-48545-15-git-send-email-wei.dai@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1480833100-48545-15-git-send-email-wei.dai@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1480833100-48545-15-git-send-email-wei.dai@intel.com", "date": "2016-12-04T06:31:26", "name": "[dpdk-dev,15/29] net/ixgbe/base: support FW commands to control some PHYs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "097f7baeb1013c298313e2b9e1ae24cce3de3c3d", "submitter": { "id": 490, "url": "https://patches.dpdk.org/api/people/490/?format=api", "name": "Wei Dai", "email": "wei.dai@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1480833100-48545-15-git-send-email-wei.dai@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/17605/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/17605/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5C3A2FA82;\n\tSun, 4 Dec 2016 07:36:54 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id CF2E25678\n\tfor <dev@dpdk.org>; Sun, 4 Dec 2016 07:35:43 +0100 (CET)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga101.fm.intel.com with ESMTP; 03 Dec 2016 22:35:42 -0800", "from dpdk4.bj.intel.com ([172.16.182.178])\n\tby orsmga003.jf.intel.com with ESMTP; 03 Dec 2016 22:35:41 -0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.33,740,1477983600\"; d=\"scan'208\";a=\"908483928\"", "From": "Wei Dai <wei.dai@intel.com>", "To": "helin.zhang@intel.com,\n\tkonstantin.ananyev@intel.com", "Cc": "dev@dpdk.org,\n\tWei Dai <wei.dai@intel.com>", "Date": "Sun, 4 Dec 2016 14:31:26 +0800", "Message-Id": "<1480833100-48545-15-git-send-email-wei.dai@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1480833100-48545-1-git-send-email-wei.dai@intel.com>", "References": "<1480833100-48545-1-git-send-email-wei.dai@intel.com>", "Subject": "[dpdk-dev] [PATCH 15/29] net/ixgbe/base: support FW commands to\n\tcontrol some PHYs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Implement support for new firmware commands to be used to access\nand control some PHYs.\n\nSigned-off-by: Wei Dai <wei.dai@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_common.h | 4 +-\n drivers/net/ixgbe/base/ixgbe_osdep.h | 3 +-\n drivers/net/ixgbe/base/ixgbe_type.h | 70 ++++++++++-\n drivers/net/ixgbe/base/ixgbe_x550.c | 230 +++++++++++++++++++++++++++++++++-\n 4 files changed, 300 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_common.h b/drivers/net/ixgbe/base/ixgbe_common.h\nindex 93e80ea..903f34d 100644\n--- a/drivers/net/ixgbe/base/ixgbe_common.h\n+++ b/drivers/net/ixgbe/base/ixgbe_common.h\n@@ -161,7 +161,9 @@ u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);\n s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,\n \t\t\t\t u32 length, u32 timeout, bool return_data);\n s32 ixgbe_hic_unlocked(struct ixgbe_hw *, u32 *buffer, u32 length, u32 timeout);\n-\n+s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *);\n+s32 ixgbe_fw_phy_activity(struct ixgbe_hw *, u16 activity,\n+\t\t\t u32 (*data)[FW_PHY_ACT_DATA_COUNT]);\n void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);\n \n extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);\ndiff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h\nindex 77f0af5..b0977b6 100644\n--- a/drivers/net/ixgbe/base/ixgbe_osdep.h\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h\n@@ -95,8 +95,9 @@ enum {\n #define STATIC static\n #define IXGBE_NTOHL(_i)\trte_be_to_cpu_32(_i)\n #define IXGBE_NTOHS(_i)\trte_be_to_cpu_16(_i)\n+#define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i)\n #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)\n-#define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)\n+#define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)\n #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)\n #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)\n #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex adc5fb3..c7100b0 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -3063,6 +3063,59 @@ enum ixgbe_fdir_pballoc_type {\n #define FW_INT_PHY_REQ_LEN\t\t10\n #define FW_INT_PHY_REQ_READ\t\t0\n #define FW_INT_PHY_REQ_WRITE\t\t1\n+#define FW_PHY_ACT_REQ_CMD\t\t5\n+#define FW_PHY_ACT_DATA_COUNT\t\t4\n+#define FW_PHY_ACT_REQ_LEN\t\t(4 + 4 * FW_PHY_ACT_DATA_COUNT)\n+#define FW_PHY_ACT_INIT_PHY\t\t1\n+#define FW_PHY_ACT_SETUP_LINK\t\t2\n+#define FW_PHY_ACT_LINK_SPEED_10\t(1u << 0)\n+#define FW_PHY_ACT_LINK_SPEED_100\t(1u << 1)\n+#define FW_PHY_ACT_LINK_SPEED_1G\t(1u << 2)\n+#define FW_PHY_ACT_LINK_SPEED_2_5G\t(1u << 3)\n+#define FW_PHY_ACT_LINK_SPEED_5G\t(1u << 4)\n+#define FW_PHY_ACT_LINK_SPEED_10G\t(1u << 5)\n+#define FW_PHY_ACT_LINK_SPEED_20G\t(1u << 6)\n+#define FW_PHY_ACT_LINK_SPEED_25G\t(1u << 7)\n+#define FW_PHY_ACT_LINK_SPEED_40G\t(1u << 8)\n+#define FW_PHY_ACT_LINK_SPEED_50G\t(1u << 9)\n+#define FW_PHY_ACT_LINK_SPEED_100G\t(1u << 10)\n+#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16\n+#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \\\n+\t\t\t\t\t FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)\n+#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u\n+#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX\t1u\n+#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX\t2u\n+#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u\n+#define FW_PHY_ACT_SETUP_LINK_LP\t(1u << 18)\n+#define FW_PHY_ACT_SETUP_LINK_HP\t(1u << 19)\n+#define FW_PHY_ACT_SETUP_LINK_EEE\t(1u << 20)\n+#define FW_PHY_ACT_SETUP_LINK_AN\t(1u << 22)\n+#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN\t(1u << 0)\n+#define FW_PHY_ACT_GET_LINK_INFO\t3\n+#define FW_PHY_ACT_GET_LINK_INFO_EEE\t(1u << 19)\n+#define FW_PHY_ACT_GET_LINK_INFO_FC_TX\t(1u << 20)\n+#define FW_PHY_ACT_GET_LINK_INFO_FC_RX\t(1u << 21)\n+#define FW_PHY_ACT_GET_LINK_INFO_POWER\t(1u << 22)\n+#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE\t(1u << 24)\n+#define FW_PHY_ACT_GET_LINK_INFO_TEMP\t(1u << 25)\n+#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX\t(1u << 28)\n+#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX\t(1u << 29)\n+#define FW_PHY_ACT_FORCE_LINK_DOWN\t4\n+#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF\t(1u << 0)\n+#define FW_PHY_ACT_PHY_SW_RESET\t\t5\n+#define FW_PHY_ACT_PHY_HW_RESET\t\t6\n+#define FW_PHY_ACT_GET_PHY_INFO\t\t7\n+#define FW_PHY_ACT_UD_2\t\t\t0x1002\n+#define FW_PHY_ACT_UD_2_10G_KR_EEE\t(1u << 6)\n+#define FW_PHY_ACT_UD_2_10G_KX4_EEE\t(1u << 5)\n+#define FW_PHY_ACT_UD_2_1G_KX_EEE\t(1u << 4)\n+#define FW_PHY_ACT_UD_2_10G_T_EEE\t(1u << 3)\n+#define FW_PHY_ACT_UD_2_1G_T_EEE\t(1u << 2)\n+#define FW_PHY_ACT_UD_2_100M_TX_EEE\t(1u << 1)\n+#define FW_PHY_ACT_RETRIES\t\t50\n+#define FW_PHY_INFO_SPEED_MASK\t\t0xFFFu\n+#define FW_PHY_INFO_ID_HI_MASK\t\t0xFFFF0000u\n+#define FW_PHY_INFO_ID_LO_MASK\t\t0x0000FFFFu\n \n /* Host Interface Command Structures */\n \n@@ -3170,6 +3223,19 @@ struct ixgbe_hic_internal_phy_resp {\n \t__be32 read_data;\n };\n \n+struct ixgbe_hic_phy_activity_req {\n+\tstruct ixgbe_hic_hdr hdr;\n+\tu8 port_number;\n+\tu8 pad;\n+\t__le16 activity_id;\n+\t__be32 data[FW_PHY_ACT_DATA_COUNT];\n+};\n+\n+struct ixgbe_hic_phy_activity_resp {\n+\tstruct ixgbe_hic_hdr hdr;\n+\t__be32 data[FW_PHY_ACT_DATA_COUNT];\n+};\n+\n #ifdef C99\n #pragma pack(pop)\n #else\n@@ -4046,8 +4112,8 @@ struct ixgbe_phy_info {\n \tbool reset_disable;\n \tixgbe_autoneg_advertised autoneg_advertised;\n \tixgbe_link_speed speeds_supported;\n-\tenum ixgbe_ms_type ms_type;\n-\tenum ixgbe_ms_type original_ms_type;\n+\tixgbe_link_speed eee_speeds_supported;\n+\tixgbe_link_speed eee_speeds_advertised;\n \tenum ixgbe_smart_speed smart_speed;\n \tbool smart_speed_active;\n \tbool multispeed_fiber;\ndiff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c\nindex 97fbf88..0a041b7 100644\n--- a/drivers/net/ixgbe/base/ixgbe_x550.c\n+++ b/drivers/net/ixgbe/base/ixgbe_x550.c\n@@ -467,6 +467,133 @@ STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)\n \treturn IXGBE_SUCCESS;\n }\n \n+/**\n+ * ixgbe_fw_phy_activity - Perform an activity on a PHY\n+ * @hw: pointer to hardware structure\n+ * @activity: activity to perform\n+ * @data: Pointer to 4 32-bit words of data\n+ */\n+s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,\n+\t\t\t u32 (*data)[FW_PHY_ACT_DATA_COUNT])\n+{\n+\tunion {\n+\t\tstruct ixgbe_hic_phy_activity_req cmd;\n+\t\tstruct ixgbe_hic_phy_activity_resp rsp;\n+\t} hic;\n+\tu16 retries = FW_PHY_ACT_RETRIES;\n+\ts32 rc;\n+\tu16 i;\n+\n+\tdo {\n+\t\tmemset(&hic, 0, sizeof(hic));\n+\t\thic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;\n+\t\thic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;\n+\t\thic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\t\thic.cmd.port_number = hw->bus.lan_id;\n+\t\thic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);\n+\t\tfor (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)\n+\t\t\thic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);\n+\n+\t\trc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,\n+\t\t\t\t\t\t sizeof(hic.cmd),\n+\t\t\t\t\t\t IXGBE_HI_COMMAND_TIMEOUT,\n+\t\t\t\t\t\t true);\n+\t\tif (rc != IXGBE_SUCCESS)\n+\t\t\treturn rc;\n+\t\tif (hic.rsp.hdr.cmd_or_resp.ret_status ==\n+\t\t FW_CEM_RESP_STATUS_SUCCESS) {\n+\t\t\tfor (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)\n+\t\t\t\t(*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);\n+\t\t\treturn IXGBE_SUCCESS;\n+\t\t}\n+\t\tusec_delay(20);\n+\t\t--retries;\n+\t} while (retries > 0);\n+\n+\treturn IXGBE_ERR_HOST_INTERFACE_COMMAND;\n+}\n+\n+static const struct {\n+\tu16 fw_speed;\n+\tixgbe_link_speed phy_speed;\n+} ixgbe_fw_map[] = {\n+\t{ FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },\n+\t{ FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },\n+\t{ FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },\n+\t{ FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },\n+\t{ FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },\n+\t{ FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },\n+};\n+\n+/**\n+ * ixgbe_get_phy_id_fw - Get the phy ID via firmware command\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns error code\n+ */\n+static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)\n+{\n+\tu32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };\n+\tu16 phy_speeds;\n+\tu16 phy_id_lo;\n+\ts32 rc;\n+\tu16 i;\n+\n+\trc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\thw->phy.speeds_supported = 0;\n+\tphy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;\n+\tfor (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {\n+\t\tif (phy_speeds & ixgbe_fw_map[i].fw_speed)\n+\t\t\thw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;\n+\t}\n+\tif (!hw->phy.autoneg_advertised)\n+\t\thw->phy.autoneg_advertised = hw->phy.speeds_supported;\n+\n+\thw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;\n+\tphy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;\n+\thw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;\n+\thw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;\n+\tif (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)\n+\t\treturn IXGBE_ERR_PHY_ADDR_INVALID;\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_identify_phy_fw - Get PHY type based on firmware command\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns error code\n+ */\n+static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)\n+{\n+\tif (hw->bus.lan_id)\n+\t\thw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;\n+\telse\n+\t\thw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;\n+\n+\thw->phy.type = ixgbe_phy_m88;\n+\thw->phy.ops.read_reg = NULL;\n+\thw->phy.ops.write_reg = NULL;\n+\treturn ixgbe_get_phy_id_fw(hw);\n+}\n+\n+/**\n+ * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns error code\n+ */\n+s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)\n+{\n+\tu32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };\n+\n+\tsetup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;\n+\treturn ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);\n+}\n+\n STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,\n \t\t\t\t u32 device_type, u16 *phy_data)\n {\n@@ -605,7 +732,18 @@ s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)\n \n \t/* PHY */\n \tphy->ops.init = ixgbe_init_phy_ops_X550em;\n-\tphy->ops.identify = ixgbe_identify_phy_x550em;\n+\tswitch (hw->device_id) {\n+\tcase IXGBE_DEV_ID_X550EM_A_1G_T:\n+\tcase IXGBE_DEV_ID_X550EM_A_1G_T_L:\n+\t\tmac->ops.setup_fc = NULL;\n+\t\tphy->ops.identify = ixgbe_identify_phy_fw;\n+\t\tphy->ops.set_phy_power = NULL;\n+\t\tphy->ops.get_firmware_version = NULL;\n+\t\tbreak;\n+\tdefault:\n+\t\tphy->ops.identify = ixgbe_identify_phy_x550em;\n+\t}\n+\n \tif (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)\n \t\tphy->ops.set_phy_power = NULL;\n \n@@ -624,6 +762,92 @@ s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)\n }\n \n /**\n+ * ixgbe_setup_fw_link - Setup firmware-controlled PHYs\n+ * @hw: pointer to hardware structure\n+ */\n+static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)\n+{\n+\tu32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };\n+\ts32 rc;\n+\tu16 i;\n+\n+\tif (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))\n+\t\treturn 0;\n+\n+\tif (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {\n+\t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,\n+\t\t\t \"ixgbe_fc_rx_pause not valid in strict IEEE mode\\n\");\n+\t\treturn IXGBE_ERR_INVALID_LINK_SETTINGS;\n+\t}\n+\n+\tswitch (hw->fc.requested_mode) {\n+\tcase ixgbe_fc_full:\n+\t\tsetup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<\n+\t\t\t FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;\n+\t\tbreak;\n+\tcase ixgbe_fc_rx_pause:\n+\t\tsetup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<\n+\t\t\t FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;\n+\t\tbreak;\n+\tcase ixgbe_fc_tx_pause:\n+\t\tsetup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<\n+\t\t\t FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {\n+\t\tif (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)\n+\t\t\tsetup[0] |= ixgbe_fw_map[i].fw_speed;\n+\t}\n+\tsetup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;\n+\n+\tif (hw->phy.eee_speeds_advertised)\n+\t\tsetup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;\n+\n+\trc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);\n+\tif (rc)\n+\t\treturn rc;\n+\tif (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)\n+\t\treturn IXGBE_ERR_OVERTEMP;\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs\n+ * @hw: pointer to hardware structure\n+ *\n+ * Called at init time to set up flow control.\n+ */\n+static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)\n+{\n+\tif (hw->fc.requested_mode == ixgbe_fc_default)\n+\t\thw->fc.requested_mode = ixgbe_fc_full;\n+\n+\treturn ixgbe_setup_fw_link(hw);\n+}\n+\n+/**\n+ * ixgbe_setup_eee_fw - Enable/disable EEE support\n+ * @hw: pointer to the HW structure\n+ * @enable_eee: boolean flag to enable EEE\n+ *\n+ * Enable/disable EEE based on enable_eee flag.\n+ * This function controls EEE for firmware-based PHY implementations.\n+ */\n+static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)\n+{\n+\tif (!!hw->phy.eee_speeds_advertised == enable_eee)\n+\t\treturn IXGBE_SUCCESS;\n+\tif (enable_eee)\n+\t\thw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;\n+\telse\n+\t\thw->phy.eee_speeds_advertised = 0;\n+\treturn hw->phy.ops.setup_link(hw);\n+}\n+\n+/**\n * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n@@ -667,13 +891,13 @@ s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)\n \tif ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||\n \t\t(hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {\n \t\tmac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;\n-\t\tmac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;\n+\t\tmac->ops.setup_fc = ixgbe_fc_autoneg_fw;\n \t}\n \n \tswitch (hw->device_id) {\n \tcase IXGBE_DEV_ID_X550EM_A_KR:\n \tcase IXGBE_DEV_ID_X550EM_A_KR_L:\n-\t\tmac->ops.setup_eee = ixgbe_setup_eee_X550;\n+\t\tmac->ops.setup_eee = ixgbe_setup_eee_fw;\n \t\tbreak;\n \tdefault:\n \t\tmac->ops.setup_eee = NULL;\n", "prefixes": [ "dpdk-dev", "15/29" ] }