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{
    "id": 17335,
    "url": "https://patches.dpdk.org/api/patches/17335/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-6-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1480436367-20749-6-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1480436367-20749-6-git-send-email-arybchenko@solarflare.com",
    "date": "2016-11-29T16:18:37",
    "name": "[dpdk-dev,v2,05/55] net/sfc: import libefx MCDI definition",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "1a4ee5e03f51693abef0ed2c5499d345e8f5893a",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-6-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/17335/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/17335/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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        ],
        "X-MXL-Hash": [
            "583daaef1ccef37d-d93080cdac89f0eeebba70ff4f6d79311437d236",
            "583daaeb1367faa9-9d8c0d4012b8a856dbd8ef1534c5198abaea572a"
        ],
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>",
        "Date": "Tue, 29 Nov 2016 16:18:37 +0000",
        "Message-ID": "<1480436367-20749-6-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>\n\t<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-AnalysisOut": [
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            "[Bzeizutn5_OT:22]"
        ],
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        "X-MAIL-FROM": "<arybchenko@solarflare.com>",
        "X-SOURCE-IP": "[12.187.104.26]",
        "X-Mailman-Approved-At": "Tue, 29 Nov 2016 21:25:51 +0100",
        "Subject": "[dpdk-dev] [PATCH v2 05/55] net/sfc: import libefx MCDI definition",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
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    },
    "content": "The header defines data interface between host CPU and NIC\nmanagement CPU.\n\nThe header is automatially generated from firmware sources.\n\nMCDI is used on NIC control path (configuration,\nevent/transmit/receive queues setup and teardown etc), but\nnot used on data path.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/efx_regs_mcdi.h | 15690 +++++++++++++++++++++++++++++++++\n 1 file changed, 15690 insertions(+)\n create mode 100644 drivers/net/sfc/base/efx_regs_mcdi.h",
    "diff": "diff --git a/drivers/net/sfc/base/efx_regs_mcdi.h b/drivers/net/sfc/base/efx_regs_mcdi.h\nnew file mode 100644\nindex 0000000..66896fb\n--- /dev/null\n+++ b/drivers/net/sfc/base/efx_regs_mcdi.h\n@@ -0,0 +1,15690 @@\n+/*-\n+ * Copyright 2008-2013 Solarflare Communications Inc.  All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND\n+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n+ * SUCH DAMAGE.\n+ */\n+\n+/*! \\cidoxg_firmware_mc_cmd */\n+\n+#ifndef _SIENA_MC_DRIVER_PCOL_H\n+#define\t_SIENA_MC_DRIVER_PCOL_H\n+\n+\n+/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */\n+/* Power-on reset state */\n+#define MC_FW_STATE_POR (1)\n+/* If this is set in MC_RESET_STATE_REG then it should be\n+ * possible to jump into IMEM without loading code from flash. */\n+#define MC_FW_WARM_BOOT_OK (2)\n+/* The MC main image has started to boot. */\n+#define MC_FW_STATE_BOOTING (4)\n+/* The Scheduler has started. */\n+#define MC_FW_STATE_SCHED (8)\n+/* If this is set in MC_RESET_STATE_REG then it should be\n+ * possible to jump into IMEM without loading code from flash.\n+ * Unlike a warm boot, assume DMEM has been reloaded, so that\n+ * the MC persistent data must be reinitialised. */\n+#define MC_FW_TEPID_BOOT_OK (16)\n+/* We have entered the main firmware via recovery mode.  This\n+ * means that MC persistent data must be reinitialised, but that\n+ * we shouldn't touch PCIe config. */\n+#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)\n+/* BIST state has been initialized */\n+#define MC_FW_BIST_INIT_OK (128)\n+\n+/* Siena MC shared memmory offsets */\n+/* The 'doorbell' addresses are hard-wired to alert the MC when written */\n+#define\tMC_SMEM_P0_DOORBELL_OFST\t0x000\n+#define\tMC_SMEM_P1_DOORBELL_OFST\t0x004\n+/* The rest of these are firmware-defined */\n+#define\tMC_SMEM_P0_PDU_OFST\t\t0x008\n+#define\tMC_SMEM_P1_PDU_OFST\t\t0x108\n+#define\tMC_SMEM_PDU_LEN\t\t\t0x100\n+#define\tMC_SMEM_P0_PTP_TIME_OFST\t0x7f0\n+#define\tMC_SMEM_P0_STATUS_OFST\t\t0x7f8\n+#define\tMC_SMEM_P1_STATUS_OFST\t\t0x7fc\n+\n+/* Values to be written to the per-port status dword in shared\n+ * memory on reboot and assert */\n+#define MC_STATUS_DWORD_REBOOT (0xb007b007)\n+#define MC_STATUS_DWORD_ASSERT (0xdeaddead)\n+\n+/* Check whether an mcfw version (in host order) belongs to a bootloader */\n+#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)\n+\n+/* The current version of the MCDI protocol.\n+ *\n+ * Note that the ROM burnt into the card only talks V0, so at the very\n+ * least every driver must support version 0 and MCDI_PCOL_VERSION\n+ */\n+#ifdef WITH_MCDI_V2\n+#define MCDI_PCOL_VERSION 2\n+#else\n+#define MCDI_PCOL_VERSION 1\n+#endif\n+\n+/* Unused commands: 0x23, 0x27, 0x30, 0x31 */\n+\n+/* MCDI version 1\n+ *\n+ * Each MCDI request starts with an MCDI_HEADER, which is a 32bit\n+ * structure, filled in by the client.\n+ *\n+ *       0       7  8     16    20     22  23  24    31\n+ *      | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |\n+ *               |                      |   |\n+ *               |                      |   \\--- Response\n+ *               |                      \\------- Error\n+ *               \\------------------------------ Resync (always set)\n+ *\n+ * The client writes it's request into MC shared memory, and rings the\n+ * doorbell. Each request is completed by either by the MC writting\n+ * back into shared memory, or by writting out an event.\n+ *\n+ * All MCDI commands support completion by shared memory response. Each\n+ * request may also contain additional data (accounted for by HEADER.LEN),\n+ * and some response's may also contain additional data (again, accounted\n+ * for by HEADER.LEN).\n+ *\n+ * Some MCDI commands support completion by event, in which any associated\n+ * response data is included in the event.\n+ *\n+ * The protocol requires one response to be delivered for every request, a\n+ * request should not be sent unless the response for the previous request\n+ * has been received (either by polling shared memory, or by receiving\n+ * an event).\n+ */\n+\n+/** Request/Response structure */\n+#define MCDI_HEADER_OFST 0\n+#define MCDI_HEADER_CODE_LBN 0\n+#define MCDI_HEADER_CODE_WIDTH 7\n+#define MCDI_HEADER_RESYNC_LBN 7\n+#define MCDI_HEADER_RESYNC_WIDTH 1\n+#define MCDI_HEADER_DATALEN_LBN 8\n+#define MCDI_HEADER_DATALEN_WIDTH 8\n+#define MCDI_HEADER_SEQ_LBN 16\n+#define MCDI_HEADER_SEQ_WIDTH 4\n+#define MCDI_HEADER_RSVD_LBN 20\n+#define MCDI_HEADER_RSVD_WIDTH 1\n+#define MCDI_HEADER_NOT_EPOCH_LBN 21\n+#define MCDI_HEADER_NOT_EPOCH_WIDTH 1\n+#define MCDI_HEADER_ERROR_LBN 22\n+#define MCDI_HEADER_ERROR_WIDTH 1\n+#define MCDI_HEADER_RESPONSE_LBN 23\n+#define MCDI_HEADER_RESPONSE_WIDTH 1\n+#define MCDI_HEADER_XFLAGS_LBN 24\n+#define MCDI_HEADER_XFLAGS_WIDTH 8\n+/* Request response using event */\n+#define MCDI_HEADER_XFLAGS_EVREQ 0x01\n+/* Request (and signal) early doorbell return */\n+#define MCDI_HEADER_XFLAGS_DBRET 0x02\n+\n+/* Maximum number of payload bytes */\n+#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc\n+#define MCDI_CTL_SDU_LEN_MAX_V2 0x400\n+\n+#ifdef WITH_MCDI_V2\n+#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2\n+#else\n+#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1\n+#endif\n+\n+\n+/* The MC can generate events for two reasons:\n+ *   - To advance a shared memory request if XFLAGS_EVREQ was set\n+ *   - As a notification (link state, i2c event), controlled\n+ *     via MC_CMD_LOG_CTRL\n+ *\n+ * Both events share a common structure:\n+ *\n+ *  0      32     33      36    44     52     60\n+ * | Data | Cont | Level | Src | Code | Rsvd |\n+ *           |\n+ *           \\ There is another event pending in this notification\n+ *\n+ * If Code==CMDDONE, then the fields are further interpreted as:\n+ *\n+ *   - LEVEL==INFO    Command succeeded\n+ *   - LEVEL==ERR     Command failed\n+ *\n+ *    0     8         16      24     32\n+ *   | Seq | Datalen | Errno | Rsvd |\n+ *\n+ *   These fields are taken directly out of the standard MCDI header, i.e.,\n+ *   LEVEL==ERR, Datalen == 0 => Reboot\n+ *\n+ * Events can be squirted out of the UART (using LOG_CTRL) without a\n+ * MCDI header.  An event can be distinguished from a MCDI response by\n+ * examining the first byte which is 0xc0.  This corresponds to the\n+ * non-existent MCDI command MC_CMD_DEBUG_LOG.\n+ *\n+ *      0         7        8\n+ *     | command | Resync |     = 0xc0\n+ *\n+ * Since the event is written in big-endian byte order, this works\n+ * providing bits 56-63 of the event are 0xc0.\n+ *\n+ *      56     60  63\n+ *     | Rsvd | Code |    = 0xc0\n+ *\n+ * Which means for convenience the event code is 0xc for all MC\n+ * generated events.\n+ */\n+#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc\n+\n+\n+/* Operation not permitted. */\n+#define MC_CMD_ERR_EPERM 1\n+/* Non-existent command target */\n+#define MC_CMD_ERR_ENOENT 2\n+/* assert() has killed the MC */\n+#define MC_CMD_ERR_EINTR 4\n+/* I/O failure */\n+#define MC_CMD_ERR_EIO 5\n+/* Already exists */\n+#define MC_CMD_ERR_EEXIST 6\n+/* Try again */\n+#define MC_CMD_ERR_EAGAIN 11\n+/* Out of memory */\n+#define MC_CMD_ERR_ENOMEM 12\n+/* Caller does not hold required locks */\n+#define MC_CMD_ERR_EACCES 13\n+/* Resource is currently unavailable (e.g. lock contention) */\n+#define MC_CMD_ERR_EBUSY 16\n+/* No such device */\n+#define MC_CMD_ERR_ENODEV 19\n+/* Invalid argument to target */\n+#define MC_CMD_ERR_EINVAL 22\n+/* Broken pipe */\n+#define MC_CMD_ERR_EPIPE 32\n+/* Read-only */\n+#define MC_CMD_ERR_EROFS 30\n+/* Out of range */\n+#define MC_CMD_ERR_ERANGE 34\n+/* Non-recursive resource is already acquired */\n+#define MC_CMD_ERR_EDEADLK 35\n+/* Operation not implemented */\n+#define MC_CMD_ERR_ENOSYS 38\n+/* Operation timed out */\n+#define MC_CMD_ERR_ETIME 62\n+/* Link has been severed */\n+#define MC_CMD_ERR_ENOLINK 67\n+/* Protocol error */\n+#define MC_CMD_ERR_EPROTO 71\n+/* Operation not supported */\n+#define MC_CMD_ERR_ENOTSUP 95\n+/* Address not available */\n+#define MC_CMD_ERR_EADDRNOTAVAIL 99\n+/* Not connected */\n+#define MC_CMD_ERR_ENOTCONN 107\n+/* Operation already in progress */\n+#define MC_CMD_ERR_EALREADY 114\n+\n+/* Resource allocation failed. */\n+#define MC_CMD_ERR_ALLOC_FAIL  0x1000\n+/* V-adaptor not found. */\n+#define MC_CMD_ERR_NO_VADAPTOR 0x1001\n+/* EVB port not found. */\n+#define MC_CMD_ERR_NO_EVB_PORT 0x1002\n+/* V-switch not found. */\n+#define MC_CMD_ERR_NO_VSWITCH  0x1003\n+/* Too many VLAN tags. */\n+#define MC_CMD_ERR_VLAN_LIMIT  0x1004\n+/* Bad PCI function number. */\n+#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005\n+/* Invalid VLAN mode. */\n+#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006\n+/* Invalid v-switch type. */\n+#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007\n+/* Invalid v-port type. */\n+#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008\n+/* MAC address exists. */\n+#define MC_CMD_ERR_MAC_EXIST 0x1009\n+/* Slave core not present */\n+#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a\n+/* The datapath is disabled. */\n+#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b\n+/* The requesting client is not a function */\n+#define MC_CMD_ERR_CLIENT_NOT_FN  0x100c\n+/* The requested operation might require the\n+   command to be passed between MCs, and the\n+   transport doesn't support that.  Should\n+   only ever been seen over the UART. */\n+#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d\n+/* VLAN tag(s) exists */\n+#define MC_CMD_ERR_VLAN_EXIST 0x100e\n+/* No MAC address assigned to an EVB port */\n+#define MC_CMD_ERR_NO_MAC_ADDR 0x100f\n+/* Notifies the driver that the request has been relayed\n+ * to an admin function for authorization. The driver should\n+ * wait for a PROXY_RESPONSE event and then resend its request.\n+ * This error code is followed by a 32-bit handle that\n+ * helps matching it with the respective PROXY_RESPONSE event. */\n+#define MC_CMD_ERR_PROXY_PENDING 0x1010\n+#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4\n+/* The request cannot be passed for authorization because\n+ * another request from the same function is currently being\n+ * authorized. The drvier should try again later. */\n+#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011\n+/* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function\n+ * that has enabled proxying or BLOCK_INDEX points to a function that\n+ * doesn't await an authorization. */\n+#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012\n+/* This code is currently only used internally in FW. Its meaning is that\n+ * an operation failed due to lack of SR-IOV privilege.\n+ * Normally it is translated to EPERM by send_cmd_err(),\n+ * but it may also be used to trigger some special mechanism\n+ * for handling such case, e.g. to relay the failed request\n+ * to a designated admin function for authorization. */\n+#define MC_CMD_ERR_NO_PRIVILEGE 0x1013\n+/* Workaround 26807 could not be turned on/off because some functions\n+ * have already installed filters. See the comment at\n+ * MC_CMD_WORKAROUND_BUG26807. */\n+#define MC_CMD_ERR_FILTERS_PRESENT 0x1014\n+/* The clock whose frequency you've attempted to set set\n+ * doesn't exist on this NIC */\n+#define MC_CMD_ERR_NO_CLOCK 0x1015\n+/* Returned by MC_CMD_TESTASSERT if the action that should\n+ * have caused an assertion failed to do so.  */\n+#define MC_CMD_ERR_UNREACHABLE 0x1016\n+/* This command needs to be processed in the background but there were no\n+ * resources to do so. Send it again after a command has completed. */\n+#define MC_CMD_ERR_QUEUE_FULL 0x1017\n+\n+#define MC_CMD_ERR_CODE_OFST 0\n+\n+/* We define 8 \"escape\" commands to allow\n+   for command number space extension */\n+\n+#define MC_CMD_CMD_SPACE_ESCAPE_0\t      0x78\n+#define MC_CMD_CMD_SPACE_ESCAPE_1\t      0x79\n+#define MC_CMD_CMD_SPACE_ESCAPE_2\t      0x7A\n+#define MC_CMD_CMD_SPACE_ESCAPE_3\t      0x7B\n+#define MC_CMD_CMD_SPACE_ESCAPE_4\t      0x7C\n+#define MC_CMD_CMD_SPACE_ESCAPE_5\t      0x7D\n+#define MC_CMD_CMD_SPACE_ESCAPE_6\t      0x7E\n+#define MC_CMD_CMD_SPACE_ESCAPE_7\t      0x7F\n+\n+/* Vectors in the boot ROM */\n+/* Point to the copycode entry point. */\n+#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)\n+#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)\n+#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)\n+/* Points to the recovery mode entry point. */\n+#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)\n+#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)\n+#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)\n+\n+/* The command set exported by the boot ROM (MCDI v0) */\n+#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {\t\t\\\n+\t(1 << MC_CMD_READ32)\t|\t\t\t\\\n+\t(1 << MC_CMD_WRITE32)\t|\t\t\t\\\n+\t(1 << MC_CMD_COPYCODE)\t|\t\t\t\\\n+\t(1 << MC_CMD_GET_VERSION),\t\t\t\\\n+\t0, 0, 0 }\n+\n+#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x)\t\t\\\n+\t(MC_CMD_SENSOR_ENTRY_OFST + (_x))\n+\n+#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n)\t\t\\\n+\t(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +\t\t\\\n+\t MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST +\t\t\\\n+\t (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)\n+\n+#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n)\t\t\\\n+\t(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +\t\t\\\n+\t MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST +\t\\\n+\t (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)\n+\n+#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n)\t\t\\\n+\t(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +\t\t\\\n+\t MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST +\t\t\\\n+\t (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)\n+\n+/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default\n+ * stack ID (which must be in the range 1-255) along with an EVB port ID.\n+ */\n+#define EVB_STACK_ID(n)  (((n) & 0xff) << 16)\n+\n+\n+#ifdef WITH_MCDI_V2\n+\n+/* Version 2 adds an optional argument to error returns: the errno value\n+ * may be followed by the (0-based) number of the first argument that\n+ * could not be processed.\n+ */\n+#define MC_CMD_ERR_ARG_OFST 4\n+\n+/* No space */\n+#define MC_CMD_ERR_ENOSPC 28\n+\n+#endif\n+\n+/* MCDI_EVENT structuredef */\n+#define\tMCDI_EVENT_LEN 8\n+#define\tMCDI_EVENT_CONT_LBN 32\n+#define\tMCDI_EVENT_CONT_WIDTH 1\n+#define\tMCDI_EVENT_LEVEL_LBN 33\n+#define\tMCDI_EVENT_LEVEL_WIDTH 3\n+/* enum: Info. */\n+#define\tMCDI_EVENT_LEVEL_INFO  0x0\n+/* enum: Warning. */\n+#define\tMCDI_EVENT_LEVEL_WARN 0x1\n+/* enum: Error. */\n+#define\tMCDI_EVENT_LEVEL_ERR 0x2\n+/* enum: Fatal. */\n+#define\tMCDI_EVENT_LEVEL_FATAL 0x3\n+#define\tMCDI_EVENT_DATA_OFST 0\n+#define\tMCDI_EVENT_CMDDONE_SEQ_LBN 0\n+#define\tMCDI_EVENT_CMDDONE_SEQ_WIDTH 8\n+#define\tMCDI_EVENT_CMDDONE_DATALEN_LBN 8\n+#define\tMCDI_EVENT_CMDDONE_DATALEN_WIDTH 8\n+#define\tMCDI_EVENT_CMDDONE_ERRNO_LBN 16\n+#define\tMCDI_EVENT_CMDDONE_ERRNO_WIDTH 8\n+#define\tMCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0\n+#define\tMCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_LBN 16\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4\n+/* enum: 100Mbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_100M  0x1\n+/* enum: 1Gbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_1G  0x2\n+/* enum: 10Gbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_10G  0x3\n+/* enum: 40Gbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_40G  0x4\n+#define\tMCDI_EVENT_LINKCHANGE_FCNTL_LBN 20\n+#define\tMCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4\n+#define\tMCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24\n+#define\tMCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8\n+#define\tMCDI_EVENT_SENSOREVT_MONITOR_LBN 0\n+#define\tMCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8\n+#define\tMCDI_EVENT_SENSOREVT_STATE_LBN 8\n+#define\tMCDI_EVENT_SENSOREVT_STATE_WIDTH 8\n+#define\tMCDI_EVENT_SENSOREVT_VALUE_LBN 16\n+#define\tMCDI_EVENT_SENSOREVT_VALUE_WIDTH 16\n+#define\tMCDI_EVENT_FWALERT_DATA_LBN 8\n+#define\tMCDI_EVENT_FWALERT_DATA_WIDTH 24\n+#define\tMCDI_EVENT_FWALERT_REASON_LBN 0\n+#define\tMCDI_EVENT_FWALERT_REASON_WIDTH 8\n+/* enum: SRAM Access. */\n+#define\tMCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1\n+#define\tMCDI_EVENT_FLR_VF_LBN 0\n+#define\tMCDI_EVENT_FLR_VF_WIDTH 8\n+#define\tMCDI_EVENT_TX_ERR_TXQ_LBN 0\n+#define\tMCDI_EVENT_TX_ERR_TXQ_WIDTH 12\n+#define\tMCDI_EVENT_TX_ERR_TYPE_LBN 12\n+#define\tMCDI_EVENT_TX_ERR_TYPE_WIDTH 4\n+/* enum: Descriptor loader reported failure */\n+#define\tMCDI_EVENT_TX_ERR_DL_FAIL 0x1\n+/* enum: Descriptor ring empty and no EOP seen for packet */\n+#define\tMCDI_EVENT_TX_ERR_NO_EOP 0x2\n+/* enum: Overlength packet */\n+#define\tMCDI_EVENT_TX_ERR_2BIG 0x3\n+/* enum: Malformed option descriptor */\n+#define\tMCDI_EVENT_TX_BAD_OPTDESC 0x5\n+/* enum: Option descriptor part way through a packet */\n+#define\tMCDI_EVENT_TX_OPT_IN_PKT 0x8\n+/* enum: DMA or PIO data access error */\n+#define\tMCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9\n+#define\tMCDI_EVENT_TX_ERR_INFO_LBN 16\n+#define\tMCDI_EVENT_TX_ERR_INFO_WIDTH 16\n+#define\tMCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12\n+#define\tMCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1\n+#define\tMCDI_EVENT_TX_FLUSH_TXQ_LBN 0\n+#define\tMCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12\n+#define\tMCDI_EVENT_PTP_ERR_TYPE_LBN 0\n+#define\tMCDI_EVENT_PTP_ERR_TYPE_WIDTH 8\n+/* enum: PLL lost lock */\n+#define\tMCDI_EVENT_PTP_ERR_PLL_LOST 0x1\n+/* enum: Filter overflow (PDMA) */\n+#define\tMCDI_EVENT_PTP_ERR_FILTER 0x2\n+/* enum: FIFO overflow (FPGA) */\n+#define\tMCDI_EVENT_PTP_ERR_FIFO 0x3\n+/* enum: Merge queue overflow */\n+#define\tMCDI_EVENT_PTP_ERR_QUEUE 0x4\n+#define\tMCDI_EVENT_AOE_ERR_TYPE_LBN 0\n+#define\tMCDI_EVENT_AOE_ERR_TYPE_WIDTH 8\n+/* enum: AOE failed to load - no valid image? */\n+#define\tMCDI_EVENT_AOE_NO_LOAD 0x1\n+/* enum: AOE FC reported an exception */\n+#define\tMCDI_EVENT_AOE_FC_ASSERT 0x2\n+/* enum: AOE FC watchdogged */\n+#define\tMCDI_EVENT_AOE_FC_WATCHDOG 0x3\n+/* enum: AOE FC failed to start */\n+#define\tMCDI_EVENT_AOE_FC_NO_START 0x4\n+/* enum: Generic AOE fault - likely to have been reported via other means too\n+ * but intended for use by aoex driver.\n+ */\n+#define\tMCDI_EVENT_AOE_FAULT 0x5\n+/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */\n+#define\tMCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6\n+/* enum: AOE loaded successfully */\n+#define\tMCDI_EVENT_AOE_LOAD 0x7\n+/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */\n+#define\tMCDI_EVENT_AOE_DMA 0x8\n+/* enum: AOE byteblaster connected/disconnected (Connection status in\n+ * AOE_ERR_DATA)\n+ */\n+#define\tMCDI_EVENT_AOE_BYTEBLASTER 0x9\n+/* enum: DDR ECC status update */\n+#define\tMCDI_EVENT_AOE_DDR_ECC_STATUS 0xa\n+/* enum: PTP status update */\n+#define\tMCDI_EVENT_AOE_PTP_STATUS 0xb\n+/* enum: FPGA header incorrect */\n+#define\tMCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc\n+/* enum: FPGA Powered Off due to error in powering up FPGA */\n+#define\tMCDI_EVENT_AOE_FPGA_POWER_OFF 0xd\n+/* enum: AOE FPGA load failed due to MC to MUM communication failure */\n+#define\tMCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe\n+/* enum: Notify that invalid flash type detected */\n+#define\tMCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf\n+/* enum: Notify that the attempt to run FPGA Controller firmware timedout */\n+#define\tMCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10\n+#define\tMCDI_EVENT_AOE_ERR_DATA_LBN 8\n+#define\tMCDI_EVENT_AOE_ERR_DATA_WIDTH 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8\n+/* enum: Reading from NV failed */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0\n+/* enum: Invalid Magic Number if FPGA header */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1\n+/* enum: Invalid Silicon type detected in header */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2\n+/* enum: Unsupported VRatio */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3\n+/* enum: Unsupported DDR Type */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4\n+/* enum: DDR Voltage out of supported range */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5\n+/* enum: Unsupported DDR speed */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6\n+/* enum: Unsupported DDR size */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7\n+/* enum: Unsupported DDR rank */\n+#define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8\n+/* enum: Primary boot flash */\n+#define\tMCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0\n+/* enum: Secondary boot flash */\n+#define\tMCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8\n+#define\tMCDI_EVENT_RX_ERR_RXQ_LBN 0\n+#define\tMCDI_EVENT_RX_ERR_RXQ_WIDTH 12\n+#define\tMCDI_EVENT_RX_ERR_TYPE_LBN 12\n+#define\tMCDI_EVENT_RX_ERR_TYPE_WIDTH 4\n+#define\tMCDI_EVENT_RX_ERR_INFO_LBN 16\n+#define\tMCDI_EVENT_RX_ERR_INFO_WIDTH 16\n+#define\tMCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12\n+#define\tMCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1\n+#define\tMCDI_EVENT_RX_FLUSH_RXQ_LBN 0\n+#define\tMCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12\n+#define\tMCDI_EVENT_MC_REBOOT_COUNT_LBN 0\n+#define\tMCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16\n+#define\tMCDI_EVENT_MUM_ERR_TYPE_LBN 0\n+#define\tMCDI_EVENT_MUM_ERR_TYPE_WIDTH 8\n+/* enum: MUM failed to load - no valid image? */\n+#define\tMCDI_EVENT_MUM_NO_LOAD 0x1\n+/* enum: MUM f/w reported an exception */\n+#define\tMCDI_EVENT_MUM_ASSERT 0x2\n+/* enum: MUM not kicking watchdog */\n+#define\tMCDI_EVENT_MUM_WATCHDOG 0x3\n+#define\tMCDI_EVENT_MUM_ERR_DATA_LBN 8\n+#define\tMCDI_EVENT_MUM_ERR_DATA_WIDTH 8\n+#define\tMCDI_EVENT_DATA_LBN 0\n+#define\tMCDI_EVENT_DATA_WIDTH 32\n+#define\tMCDI_EVENT_SRC_LBN 36\n+#define\tMCDI_EVENT_SRC_WIDTH 8\n+#define\tMCDI_EVENT_EV_CODE_LBN 60\n+#define\tMCDI_EVENT_EV_CODE_WIDTH 4\n+#define\tMCDI_EVENT_CODE_LBN 44\n+#define\tMCDI_EVENT_CODE_WIDTH 8\n+/* enum: Event generated by host software */\n+#define\tMCDI_EVENT_SW_EVENT 0x0\n+/* enum: Bad assert. */\n+#define\tMCDI_EVENT_CODE_BADSSERT 0x1\n+/* enum: PM Notice. */\n+#define\tMCDI_EVENT_CODE_PMNOTICE 0x2\n+/* enum: Command done. */\n+#define\tMCDI_EVENT_CODE_CMDDONE 0x3\n+/* enum: Link change. */\n+#define\tMCDI_EVENT_CODE_LINKCHANGE 0x4\n+/* enum: Sensor Event. */\n+#define\tMCDI_EVENT_CODE_SENSOREVT 0x5\n+/* enum: Schedule error. */\n+#define\tMCDI_EVENT_CODE_SCHEDERR 0x6\n+/* enum: Reboot. */\n+#define\tMCDI_EVENT_CODE_REBOOT 0x7\n+/* enum: Mac stats DMA. */\n+#define\tMCDI_EVENT_CODE_MAC_STATS_DMA 0x8\n+/* enum: Firmware alert. */\n+#define\tMCDI_EVENT_CODE_FWALERT 0x9\n+/* enum: Function level reset. */\n+#define\tMCDI_EVENT_CODE_FLR 0xa\n+/* enum: Transmit error */\n+#define\tMCDI_EVENT_CODE_TX_ERR 0xb\n+/* enum: Tx flush has completed */\n+#define\tMCDI_EVENT_CODE_TX_FLUSH  0xc\n+/* enum: PTP packet received timestamp */\n+#define\tMCDI_EVENT_CODE_PTP_RX  0xd\n+/* enum: PTP NIC failure */\n+#define\tMCDI_EVENT_CODE_PTP_FAULT  0xe\n+/* enum: PTP PPS event */\n+#define\tMCDI_EVENT_CODE_PTP_PPS  0xf\n+/* enum: Rx flush has completed */\n+#define\tMCDI_EVENT_CODE_RX_FLUSH  0x10\n+/* enum: Receive error */\n+#define\tMCDI_EVENT_CODE_RX_ERR 0x11\n+/* enum: AOE fault */\n+#define\tMCDI_EVENT_CODE_AOE  0x12\n+/* enum: Network port calibration failed (VCAL). */\n+#define\tMCDI_EVENT_CODE_VCAL_FAIL  0x13\n+/* enum: HW PPS event */\n+#define\tMCDI_EVENT_CODE_HW_PPS  0x14\n+/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and\n+ * a different format)\n+ */\n+#define\tMCDI_EVENT_CODE_MC_REBOOT 0x15\n+/* enum: the MC has detected a parity error */\n+#define\tMCDI_EVENT_CODE_PAR_ERR 0x16\n+/* enum: the MC has detected a correctable error */\n+#define\tMCDI_EVENT_CODE_ECC_CORR_ERR 0x17\n+/* enum: the MC has detected an uncorrectable error */\n+#define\tMCDI_EVENT_CODE_ECC_FATAL_ERR 0x18\n+/* enum: The MC has entered offline BIST mode */\n+#define\tMCDI_EVENT_CODE_MC_BIST 0x19\n+/* enum: PTP tick event providing current NIC time */\n+#define\tMCDI_EVENT_CODE_PTP_TIME 0x1a\n+/* enum: MUM fault */\n+#define\tMCDI_EVENT_CODE_MUM 0x1b\n+/* enum: notify the designated PF of a new authorization request */\n+#define\tMCDI_EVENT_CODE_PROXY_REQUEST 0x1c\n+/* enum: notify a function that awaits an authorization that its request has\n+ * been processed and it may now resend the command\n+ */\n+#define\tMCDI_EVENT_CODE_PROXY_RESPONSE 0x1d\n+/* enum: Artificial event generated by host and posted via MC for test\n+ * purposes.\n+ */\n+#define\tMCDI_EVENT_CODE_TESTGEN  0xfa\n+#define\tMCDI_EVENT_CMDDONE_DATA_OFST 0\n+#define\tMCDI_EVENT_CMDDONE_DATA_LBN 0\n+#define\tMCDI_EVENT_CMDDONE_DATA_WIDTH 32\n+#define\tMCDI_EVENT_LINKCHANGE_DATA_OFST 0\n+#define\tMCDI_EVENT_LINKCHANGE_DATA_LBN 0\n+#define\tMCDI_EVENT_LINKCHANGE_DATA_WIDTH 32\n+#define\tMCDI_EVENT_SENSOREVT_DATA_OFST 0\n+#define\tMCDI_EVENT_SENSOREVT_DATA_LBN 0\n+#define\tMCDI_EVENT_SENSOREVT_DATA_WIDTH 32\n+#define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0\n+#define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0\n+#define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32\n+#define\tMCDI_EVENT_TX_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_TX_ERR_DATA_LBN 0\n+#define\tMCDI_EVENT_TX_ERR_DATA_WIDTH 32\n+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of\n+ * timestamp\n+ */\n+#define\tMCDI_EVENT_PTP_SECONDS_OFST 0\n+#define\tMCDI_EVENT_PTP_SECONDS_LBN 0\n+#define\tMCDI_EVENT_PTP_SECONDS_WIDTH 32\n+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of\n+ * timestamp\n+ */\n+#define\tMCDI_EVENT_PTP_MAJOR_OFST 0\n+#define\tMCDI_EVENT_PTP_MAJOR_LBN 0\n+#define\tMCDI_EVENT_PTP_MAJOR_WIDTH 32\n+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field\n+ * of timestamp\n+ */\n+#define\tMCDI_EVENT_PTP_NANOSECONDS_OFST 0\n+#define\tMCDI_EVENT_PTP_NANOSECONDS_LBN 0\n+#define\tMCDI_EVENT_PTP_NANOSECONDS_WIDTH 32\n+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of\n+ * timestamp\n+ */\n+#define\tMCDI_EVENT_PTP_MINOR_OFST 0\n+#define\tMCDI_EVENT_PTP_MINOR_LBN 0\n+#define\tMCDI_EVENT_PTP_MINOR_WIDTH 32\n+/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet\n+ */\n+#define\tMCDI_EVENT_PTP_UUID_OFST 0\n+#define\tMCDI_EVENT_PTP_UUID_LBN 0\n+#define\tMCDI_EVENT_PTP_UUID_WIDTH 32\n+#define\tMCDI_EVENT_RX_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_RX_ERR_DATA_LBN 0\n+#define\tMCDI_EVENT_RX_ERR_DATA_WIDTH 32\n+#define\tMCDI_EVENT_PAR_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_PAR_ERR_DATA_LBN 0\n+#define\tMCDI_EVENT_PAR_ERR_DATA_WIDTH 32\n+#define\tMCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0\n+#define\tMCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32\n+#define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0\n+#define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32\n+/* For CODE_PTP_TIME events, the major value of the PTP clock */\n+#define\tMCDI_EVENT_PTP_TIME_MAJOR_OFST 0\n+#define\tMCDI_EVENT_PTP_TIME_MAJOR_LBN 0\n+#define\tMCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32\n+/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8\n+/* For CODE_PTP_TIME events where report sync status is enabled, indicates\n+ * whether the NIC clock has ever been set\n+ */\n+#define\tMCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36\n+#define\tMCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1\n+/* For CODE_PTP_TIME events where report sync status is enabled, indicates\n+ * whether the NIC and System clocks are in sync\n+ */\n+#define\tMCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37\n+#define\tMCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1\n+/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of\n+ * the minor value of the PTP clock\n+ */\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6\n+#define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0\n+#define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0\n+#define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32\n+#define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0\n+#define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0\n+#define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32\n+/* Zero means that the request has been completed or authorized, and the driver\n+ * should resend it. A non-zero value means that the authorization has been\n+ * denied, and gives the reason. Typically it will be EPERM.\n+ */\n+#define\tMCDI_EVENT_PROXY_RESPONSE_RC_LBN 36\n+#define\tMCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8\n+\n+/* FCDI_EVENT structuredef */\n+#define\tFCDI_EVENT_LEN 8\n+#define\tFCDI_EVENT_CONT_LBN 32\n+#define\tFCDI_EVENT_CONT_WIDTH 1\n+#define\tFCDI_EVENT_LEVEL_LBN 33\n+#define\tFCDI_EVENT_LEVEL_WIDTH 3\n+/* enum: Info. */\n+#define\tFCDI_EVENT_LEVEL_INFO  0x0\n+/* enum: Warning. */\n+#define\tFCDI_EVENT_LEVEL_WARN 0x1\n+/* enum: Error. */\n+#define\tFCDI_EVENT_LEVEL_ERR 0x2\n+/* enum: Fatal. */\n+#define\tFCDI_EVENT_LEVEL_FATAL 0x3\n+#define\tFCDI_EVENT_DATA_OFST 0\n+#define\tFCDI_EVENT_LINK_STATE_STATUS_LBN 0\n+#define\tFCDI_EVENT_LINK_STATE_STATUS_WIDTH 1\n+#define\tFCDI_EVENT_LINK_DOWN 0x0 /* enum */\n+#define\tFCDI_EVENT_LINK_UP 0x1 /* enum */\n+#define\tFCDI_EVENT_DATA_LBN 0\n+#define\tFCDI_EVENT_DATA_WIDTH 32\n+#define\tFCDI_EVENT_SRC_LBN 36\n+#define\tFCDI_EVENT_SRC_WIDTH 8\n+#define\tFCDI_EVENT_EV_CODE_LBN 60\n+#define\tFCDI_EVENT_EV_CODE_WIDTH 4\n+#define\tFCDI_EVENT_CODE_LBN 44\n+#define\tFCDI_EVENT_CODE_WIDTH 8\n+/* enum: The FC was rebooted. */\n+#define\tFCDI_EVENT_CODE_REBOOT 0x1\n+/* enum: Bad assert. */\n+#define\tFCDI_EVENT_CODE_ASSERT 0x2\n+/* enum: DDR3 test result. */\n+#define\tFCDI_EVENT_CODE_DDR_TEST_RESULT 0x3\n+/* enum: Link status. */\n+#define\tFCDI_EVENT_CODE_LINK_STATE 0x4\n+/* enum: A timed read is ready to be serviced. */\n+#define\tFCDI_EVENT_CODE_TIMED_READ 0x5\n+/* enum: One or more PPS IN events */\n+#define\tFCDI_EVENT_CODE_PPS_IN 0x6\n+/* enum: Tick event from PTP clock */\n+#define\tFCDI_EVENT_CODE_PTP_TICK 0x7\n+/* enum: ECC error counters */\n+#define\tFCDI_EVENT_CODE_DDR_ECC_STATUS 0x8\n+/* enum: Current status of PTP */\n+#define\tFCDI_EVENT_CODE_PTP_STATUS 0x9\n+/* enum: Port id config to map MC-FC port idx */\n+#define\tFCDI_EVENT_CODE_PORT_CONFIG 0xa\n+/* enum: Boot result or error code */\n+#define\tFCDI_EVENT_CODE_BOOT_RESULT 0xb\n+#define\tFCDI_EVENT_REBOOT_SRC_LBN 36\n+#define\tFCDI_EVENT_REBOOT_SRC_WIDTH 8\n+#define\tFCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */\n+#define\tFCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */\n+#define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0\n+#define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0\n+#define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32\n+#define\tFCDI_EVENT_ASSERT_TYPE_LBN 36\n+#define\tFCDI_EVENT_ASSERT_TYPE_WIDTH 8\n+#define\tFCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36\n+#define\tFCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8\n+#define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0\n+#define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0\n+#define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32\n+#define\tFCDI_EVENT_LINK_STATE_DATA_OFST 0\n+#define\tFCDI_EVENT_LINK_STATE_DATA_LBN 0\n+#define\tFCDI_EVENT_LINK_STATE_DATA_WIDTH 32\n+#define\tFCDI_EVENT_PTP_STATE_OFST 0\n+#define\tFCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */\n+#define\tFCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */\n+#define\tFCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */\n+#define\tFCDI_EVENT_PTP_STATE_LBN 0\n+#define\tFCDI_EVENT_PTP_STATE_WIDTH 32\n+#define\tFCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36\n+#define\tFCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8\n+#define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0\n+#define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0\n+#define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32\n+/* Index of MC port being referred to */\n+#define\tFCDI_EVENT_PORT_CONFIG_SRC_LBN 36\n+#define\tFCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8\n+/* FC Port index that matches the MC port index in SRC */\n+#define\tFCDI_EVENT_PORT_CONFIG_DATA_OFST 0\n+#define\tFCDI_EVENT_PORT_CONFIG_DATA_LBN 0\n+#define\tFCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32\n+#define\tFCDI_EVENT_BOOT_RESULT_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */\n+#define\tFCDI_EVENT_BOOT_RESULT_LBN 0\n+#define\tFCDI_EVENT_BOOT_RESULT_WIDTH 32\n+\n+/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events\n+ * to the MC. Note that this structure | is overlayed over a normal FCDI event\n+ * such that bits 32-63 containing | event code, level, source etc remain the\n+ * same. In this case the data | field of the header is defined to be the\n+ * number of timestamps\n+ */\n+#define\tFCDI_EXTENDED_EVENT_PPS_LENMIN 16\n+#define\tFCDI_EXTENDED_EVENT_PPS_LENMAX 248\n+#define\tFCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))\n+/* Number of timestamps following */\n+#define\tFCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0\n+#define\tFCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0\n+#define\tFCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32\n+/* Seconds field of a timestamp record */\n+#define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8\n+#define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64\n+#define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32\n+/* Nanoseconds field of a timestamp record */\n+#define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12\n+#define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96\n+#define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32\n+/* Timestamp records comprising the event */\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64\n+\n+/* MUM_EVENT structuredef */\n+#define\tMUM_EVENT_LEN 8\n+#define\tMUM_EVENT_CONT_LBN 32\n+#define\tMUM_EVENT_CONT_WIDTH 1\n+#define\tMUM_EVENT_LEVEL_LBN 33\n+#define\tMUM_EVENT_LEVEL_WIDTH 3\n+/* enum: Info. */\n+#define\tMUM_EVENT_LEVEL_INFO  0x0\n+/* enum: Warning. */\n+#define\tMUM_EVENT_LEVEL_WARN 0x1\n+/* enum: Error. */\n+#define\tMUM_EVENT_LEVEL_ERR 0x2\n+/* enum: Fatal. */\n+#define\tMUM_EVENT_LEVEL_FATAL 0x3\n+#define\tMUM_EVENT_DATA_OFST 0\n+#define\tMUM_EVENT_SENSOR_ID_LBN 0\n+#define\tMUM_EVENT_SENSOR_ID_WIDTH 8\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */\n+#define\tMUM_EVENT_SENSOR_STATE_LBN 8\n+#define\tMUM_EVENT_SENSOR_STATE_WIDTH 8\n+#define\tMUM_EVENT_PORT_PHY_READY_LBN 0\n+#define\tMUM_EVENT_PORT_PHY_READY_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_LINK_UP_LBN 1\n+#define\tMUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_TX_LOL_LBN 2\n+#define\tMUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_RX_LOL_LBN 3\n+#define\tMUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_TX_LOS_LBN 4\n+#define\tMUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_RX_LOS_LBN 5\n+#define\tMUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_TX_FAULT_LBN 6\n+#define\tMUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1\n+#define\tMUM_EVENT_DATA_LBN 0\n+#define\tMUM_EVENT_DATA_WIDTH 32\n+#define\tMUM_EVENT_SRC_LBN 36\n+#define\tMUM_EVENT_SRC_WIDTH 8\n+#define\tMUM_EVENT_EV_CODE_LBN 60\n+#define\tMUM_EVENT_EV_CODE_WIDTH 4\n+#define\tMUM_EVENT_CODE_LBN 44\n+#define\tMUM_EVENT_CODE_WIDTH 8\n+/* enum: The MUM was rebooted. */\n+#define\tMUM_EVENT_CODE_REBOOT 0x1\n+/* enum: Bad assert. */\n+#define\tMUM_EVENT_CODE_ASSERT 0x2\n+/* enum: Sensor failure. */\n+#define\tMUM_EVENT_CODE_SENSOR 0x3\n+/* enum: Link fault has been asserted, or has cleared. */\n+#define\tMUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4\n+#define\tMUM_EVENT_SENSOR_DATA_OFST 0\n+#define\tMUM_EVENT_SENSOR_DATA_LBN 0\n+#define\tMUM_EVENT_SENSOR_DATA_WIDTH 32\n+#define\tMUM_EVENT_PORT_PHY_FLAGS_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_FLAGS_LBN 0\n+#define\tMUM_EVENT_PORT_PHY_FLAGS_WIDTH 32\n+#define\tMUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0\n+#define\tMUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32\n+#define\tMUM_EVENT_PORT_PHY_CAPS_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_CAPS_LBN 0\n+#define\tMUM_EVENT_PORT_PHY_CAPS_WIDTH 32\n+#define\tMUM_EVENT_PORT_PHY_TECH_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_TECH_LBN 0\n+#define\tMUM_EVENT_PORT_PHY_TECH_WIDTH 32\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */\n+#define\tMUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40\n+#define\tMUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4\n+\n+\n+/***********************************/\n+/* MC_CMD_READ32\n+ * Read multiple 32byte words from MC memory.\n+ */\n+#define\tMC_CMD_READ32 0x1\n+#undef\tMC_CMD_0x1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_READ32_IN msgrequest */\n+#define\tMC_CMD_READ32_IN_LEN 8\n+#define\tMC_CMD_READ32_IN_ADDR_OFST 0\n+#define\tMC_CMD_READ32_IN_NUMWORDS_OFST 4\n+\n+/* MC_CMD_READ32_OUT msgresponse */\n+#define\tMC_CMD_READ32_OUT_LENMIN 4\n+#define\tMC_CMD_READ32_OUT_LENMAX 252\n+#define\tMC_CMD_READ32_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_READ32_OUT_BUFFER_OFST 0\n+#define\tMC_CMD_READ32_OUT_BUFFER_LEN 4\n+#define\tMC_CMD_READ32_OUT_BUFFER_MINNUM 1\n+#define\tMC_CMD_READ32_OUT_BUFFER_MAXNUM 63\n+\n+\n+/***********************************/\n+/* MC_CMD_WRITE32\n+ * Write multiple 32byte words to MC memory.\n+ */\n+#define\tMC_CMD_WRITE32 0x2\n+#undef\tMC_CMD_0x2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_WRITE32_IN msgrequest */\n+#define\tMC_CMD_WRITE32_IN_LENMIN 8\n+#define\tMC_CMD_WRITE32_IN_LENMAX 252\n+#define\tMC_CMD_WRITE32_IN_LEN(num) (4+4*(num))\n+#define\tMC_CMD_WRITE32_IN_ADDR_OFST 0\n+#define\tMC_CMD_WRITE32_IN_BUFFER_OFST 4\n+#define\tMC_CMD_WRITE32_IN_BUFFER_LEN 4\n+#define\tMC_CMD_WRITE32_IN_BUFFER_MINNUM 1\n+#define\tMC_CMD_WRITE32_IN_BUFFER_MAXNUM 62\n+\n+/* MC_CMD_WRITE32_OUT msgresponse */\n+#define\tMC_CMD_WRITE32_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_COPYCODE\n+ * Copy MC code between two locations and jump.\n+ */\n+#define\tMC_CMD_COPYCODE 0x3\n+#undef\tMC_CMD_0x3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_COPYCODE_IN msgrequest */\n+#define\tMC_CMD_COPYCODE_IN_LEN 16\n+/* Source address\n+ *\n+ * The main image should be entered via a copy of a single word from and to a\n+ * magic address, which controls various aspects of the boot. The magic address\n+ * is a bitfield, with each bit as documented below.\n+ */\n+#define\tMC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0\n+/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */\n+#define\tMC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000\n+/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and\n+ * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)\n+ */\n+#define\tMC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0\n+/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,\n+ * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see\n+ * below)\n+ */\n+#define\tMC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1\n+/* Destination address */\n+#define\tMC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4\n+#define\tMC_CMD_COPYCODE_IN_NUMWORDS_OFST 8\n+/* Address of where to jump after copy. */\n+#define\tMC_CMD_COPYCODE_IN_JUMP_OFST 12\n+/* enum: Control should return to the caller rather than jumping */\n+#define\tMC_CMD_COPYCODE_JUMP_NONE 0x1\n+\n+/* MC_CMD_COPYCODE_OUT msgresponse */\n+#define\tMC_CMD_COPYCODE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_FUNC\n+ * Select function for function-specific commands.\n+ */\n+#define\tMC_CMD_SET_FUNC 0x4\n+#undef\tMC_CMD_0x4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_FUNC_IN msgrequest */\n+#define\tMC_CMD_SET_FUNC_IN_LEN 4\n+/* Set function */\n+#define\tMC_CMD_SET_FUNC_IN_FUNC_OFST 0\n+\n+/* MC_CMD_SET_FUNC_OUT msgresponse */\n+#define\tMC_CMD_SET_FUNC_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_BOOT_STATUS\n+ * Get the instruction address from which the MC booted.\n+ */\n+#define\tMC_CMD_GET_BOOT_STATUS 0x5\n+#undef\tMC_CMD_0x5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */\n+#define\tMC_CMD_GET_BOOT_STATUS_IN_LEN 0\n+\n+/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_LEN 8\n+/* ?? */\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0\n+/* enum: indicates that the MC wasn't flash booted */\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL  0xdeadbeef\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_ASSERTS\n+ * Get (and optionally clear) the current assertion status. Only\n+ * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other\n+ * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS\n+ */\n+#define\tMC_CMD_GET_ASSERTS 0x6\n+#undef\tMC_CMD_0x6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_ASSERTS_IN msgrequest */\n+#define\tMC_CMD_GET_ASSERTS_IN_LEN 4\n+/* Set to clear assertion */\n+#define\tMC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0\n+\n+/* MC_CMD_GET_ASSERTS_OUT msgresponse */\n+#define\tMC_CMD_GET_ASSERTS_OUT_LEN 140\n+/* Assertion status flag. */\n+#define\tMC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0\n+/* enum: No assertions have failed. */\n+#define\tMC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1\n+/* enum: A system-level assertion has failed. */\n+#define\tMC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2\n+/* enum: A thread-level assertion has failed. */\n+#define\tMC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3\n+/* enum: The system was reset by the watchdog. */\n+#define\tMC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4\n+/* enum: An illegal address trap stopped the system (huntington and later) */\n+#define\tMC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5\n+/* Failing PC value */\n+#define\tMC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4\n+/* Saved GP regs */\n+#define\tMC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8\n+#define\tMC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4\n+#define\tMC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31\n+/* enum: A magic value hinting that the value in this register at the time of\n+ * the failure has likely been lost.\n+ */\n+#define\tMC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057\n+/* Failing thread address */\n+#define\tMC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132\n+#define\tMC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136\n+\n+\n+/***********************************/\n+/* MC_CMD_LOG_CTRL\n+ * Configure the output stream for log events such as link state changes,\n+ * sensor notifications and MCDI completions\n+ */\n+#define\tMC_CMD_LOG_CTRL 0x7\n+#undef\tMC_CMD_0x7_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LOG_CTRL_IN msgrequest */\n+#define\tMC_CMD_LOG_CTRL_IN_LEN 8\n+/* Log destination */\n+#define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0\n+/* enum: UART. */\n+#define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1\n+/* enum: Event queue. */\n+#define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2\n+/* Legacy argument. Must be zero. */\n+#define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4\n+\n+/* MC_CMD_LOG_CTRL_OUT msgresponse */\n+#define\tMC_CMD_LOG_CTRL_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_VERSION\n+ * Get version information about the MC firmware.\n+ */\n+#define\tMC_CMD_GET_VERSION 0x8\n+#undef\tMC_CMD_0x8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_VERSION_IN msgrequest */\n+#define\tMC_CMD_GET_VERSION_IN_LEN 0\n+\n+/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */\n+#define\tMC_CMD_GET_VERSION_EXT_IN_LEN 4\n+/* placeholder, set to 0 */\n+#define\tMC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0\n+\n+/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */\n+#define\tMC_CMD_GET_VERSION_V0_OUT_LEN 4\n+#define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0\n+/* enum: Reserved version number to indicate \"any\" version. */\n+#define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff\n+/* enum: Bootrom version value for Siena. */\n+#define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000\n+/* enum: Bootrom version value for Huntington. */\n+#define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001\n+\n+/* MC_CMD_GET_VERSION_OUT msgresponse */\n+#define\tMC_CMD_GET_VERSION_OUT_LEN 32\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n+#define\tMC_CMD_GET_VERSION_OUT_PCOL_OFST 4\n+/* 128bit mask of functions supported by the current firmware */\n+#define\tMC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8\n+#define\tMC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_OFST 24\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_LEN 8\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28\n+\n+/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_LEN 48\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4\n+/* 128bit mask of functions supported by the current firmware */\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28\n+/* extra info */\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16\n+\n+\n+/***********************************/\n+/* MC_CMD_FC\n+ * Perform an FC operation\n+ */\n+#define\tMC_CMD_FC 0x9\n+\n+/* MC_CMD_FC_IN msgrequest */\n+#define\tMC_CMD_FC_IN_LEN 4\n+#define\tMC_CMD_FC_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_FC_IN_OP_LBN 0\n+#define\tMC_CMD_FC_IN_OP_WIDTH 8\n+/* enum: NULL MCDI command to FC. */\n+#define\tMC_CMD_FC_OP_NULL 0x1\n+/* enum: Unused opcode */\n+#define\tMC_CMD_FC_OP_UNUSED 0x2\n+/* enum: MAC driver commands */\n+#define\tMC_CMD_FC_OP_MAC 0x3\n+/* enum: Read FC memory */\n+#define\tMC_CMD_FC_OP_READ32 0x4\n+/* enum: Write to FC memory */\n+#define\tMC_CMD_FC_OP_WRITE32 0x5\n+/* enum: Read FC memory */\n+#define\tMC_CMD_FC_OP_TRC_READ 0x6\n+/* enum: Write to FC memory */\n+#define\tMC_CMD_FC_OP_TRC_WRITE 0x7\n+/* enum: FC firmware Version */\n+#define\tMC_CMD_FC_OP_GET_VERSION 0x8\n+/* enum: Read FC memory */\n+#define\tMC_CMD_FC_OP_TRC_RX_READ 0x9\n+/* enum: Write to FC memory */\n+#define\tMC_CMD_FC_OP_TRC_RX_WRITE 0xa\n+/* enum: SFP parameters */\n+#define\tMC_CMD_FC_OP_SFP 0xb\n+/* enum: DDR3 test */\n+#define\tMC_CMD_FC_OP_DDR_TEST 0xc\n+/* enum: Get Crash context from FC */\n+#define\tMC_CMD_FC_OP_GET_ASSERT 0xd\n+/* enum: Get FPGA Build registers */\n+#define\tMC_CMD_FC_OP_FPGA_BUILD 0xe\n+/* enum: Read map support commands */\n+#define\tMC_CMD_FC_OP_READ_MAP 0xf\n+/* enum: FC Capabilities */\n+#define\tMC_CMD_FC_OP_CAPABILITIES 0x10\n+/* enum: FC Global flags */\n+#define\tMC_CMD_FC_OP_GLOBAL_FLAGS 0x11\n+/* enum: FC IO using relative addressing modes */\n+#define\tMC_CMD_FC_OP_IO_REL 0x12\n+/* enum: FPGA link information */\n+#define\tMC_CMD_FC_OP_UHLINK 0x13\n+/* enum: Configure loopbacks and link on FPGA ports */\n+#define\tMC_CMD_FC_OP_SET_LINK 0x14\n+/* enum: Licensing operations relating to AOE */\n+#define\tMC_CMD_FC_OP_LICENSE 0x15\n+/* enum: Startup information to the FC */\n+#define\tMC_CMD_FC_OP_STARTUP 0x16\n+/* enum: Configure a DMA read */\n+#define\tMC_CMD_FC_OP_DMA 0x17\n+/* enum: Configure a timed read */\n+#define\tMC_CMD_FC_OP_TIMED_READ 0x18\n+/* enum: Control UART logging */\n+#define\tMC_CMD_FC_OP_LOG 0x19\n+/* enum: Get the value of a given clock_id */\n+#define\tMC_CMD_FC_OP_CLOCK 0x1a\n+/* enum: DDR3/QDR3 parameters */\n+#define\tMC_CMD_FC_OP_DDR 0x1b\n+/* enum: PTP and timestamp control */\n+#define\tMC_CMD_FC_OP_TIMESTAMP 0x1c\n+/* enum: Commands for SPI Flash interface */\n+#define\tMC_CMD_FC_OP_SPI 0x1d\n+/* enum: Commands for diagnostic components */\n+#define\tMC_CMD_FC_OP_DIAG 0x1e\n+/* enum: External AOE port. */\n+#define\tMC_CMD_FC_IN_PORT_EXT_OFST 0x0\n+/* enum: Internal AOE port. */\n+#define\tMC_CMD_FC_IN_PORT_INT_OFST 0x40\n+\n+/* MC_CMD_FC_IN_NULL msgrequest */\n+#define\tMC_CMD_FC_IN_NULL_LEN 4\n+#define\tMC_CMD_FC_IN_CMD_OFST 0\n+\n+/* MC_CMD_FC_IN_PHY msgrequest */\n+#define\tMC_CMD_FC_IN_PHY_LEN 5\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* FC PHY driver operation code */\n+#define\tMC_CMD_FC_IN_PHY_OP_OFST 4\n+#define\tMC_CMD_FC_IN_PHY_OP_LEN 1\n+/* enum: PHY init handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_INIT 0x1\n+/* enum: PHY reconfigure handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2\n+/* enum: PHY reboot handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_REBOOT 0x3\n+/* enum: PHY get_supported_cap handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4\n+/* enum: PHY get_config handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5\n+/* enum: PHY get_media_info handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6\n+/* enum: PHY set_led handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_SET_LED 0x7\n+/* enum: PHY lasi_interrupt handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8\n+/* enum: PHY check_link handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9\n+/* enum: PHY fill_stats handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa\n+/* enum: PHY bpx_link_state_changed handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb\n+/* enum: PHY get_state handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_STATE 0xc\n+/* enum: PHY start_bist handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_START_BIST 0xd\n+/* enum: PHY poll_bist handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe\n+/* enum: PHY nvram_test handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf\n+/* enum: PHY relinquish handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10\n+/* enum: PHY read connection from FC - may be not required */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11\n+/* enum: PHY read flags from FC - may be not required */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12\n+\n+/* MC_CMD_FC_IN_PHY_INIT msgrequest */\n+#define\tMC_CMD_FC_IN_PHY_INIT_LEN 4\n+#define\tMC_CMD_FC_IN_PHY_CMD_OFST 0\n+\n+/* MC_CMD_FC_IN_MAC msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_MAC_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_MAC_OP_LBN 0\n+#define\tMC_CMD_FC_IN_MAC_OP_WIDTH 8\n+/* enum: MAC reconfigure handler */\n+#define\tMC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1\n+/* enum: MAC Set command - same as MC_CMD_SET_MAC */\n+#define\tMC_CMD_FC_OP_MAC_OP_SET_LINK 0x2\n+/* enum: MAC statistics */\n+#define\tMC_CMD_FC_OP_MAC_OP_GET_STATS 0x3\n+/* enum: MAC RX statistics */\n+#define\tMC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6\n+/* enum: MAC TX statistics */\n+#define\tMC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7\n+/* enum: MAC Read status */\n+#define\tMC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8\n+#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8\n+#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8\n+/* enum: External FPGA port. */\n+#define\tMC_CMD_FC_PORT_EXT 0x0\n+/* enum: Internal Siena-facing FPGA ports. */\n+#define\tMC_CMD_FC_PORT_INT 0x1\n+#define\tMC_CMD_FC_IN_MAC_PORT_IDX_LBN 16\n+#define\tMC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8\n+#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24\n+#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8\n+/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n+ * irrelevant. Port number is derived from pci_fn; passed in FC header.\n+ */\n+#define\tMC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0\n+/* enum: Override default port number. Port number determined by fields\n+ * PORT_TYPE and PORT_IDX.\n+ */\n+#define\tMC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1\n+\n+/* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_LEN 32\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/* MTU size */\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8\n+/* Drain Tx FIFO */\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28\n+\n+/* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_READ_STATUS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/* MC Statistics index */\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1\n+/* Number of statistics to read */\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16\n+#define\tMC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */\n+#define\tMC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */\n+\n+/* MC_CMD_FC_IN_READ32 msgrequest */\n+#define\tMC_CMD_FC_IN_READ32_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_READ32_ADDR_HI_OFST 4\n+#define\tMC_CMD_FC_IN_READ32_ADDR_LO_OFST 8\n+#define\tMC_CMD_FC_IN_READ32_NUMWORDS_OFST 12\n+\n+/* MC_CMD_FC_IN_WRITE32 msgrequest */\n+#define\tMC_CMD_FC_IN_WRITE32_LENMIN 16\n+#define\tMC_CMD_FC_IN_WRITE32_LENMAX 252\n+#define\tMC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4\n+#define\tMC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_OFST 12\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60\n+\n+/* MC_CMD_FC_IN_TRC_READ msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_READ_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TRC_READ_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8\n+\n+/* MC_CMD_FC_IN_TRC_WRITE msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_WRITE_LEN 28\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8\n+#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12\n+#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4\n+\n+/* MC_CMD_FC_IN_GET_VERSION msgrequest */\n+#define\tMC_CMD_FC_IN_GET_VERSION_LEN 4\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_FC_IN_TRC_RX_READ msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8\n+\n+/* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2\n+\n+/* MC_CMD_FC_IN_SFP msgrequest */\n+#define\tMC_CMD_FC_IN_SFP_LEN 28\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* Link speed is 100, 1000, 10000, 40000 */\n+#define\tMC_CMD_FC_IN_SFP_SPEED_OFST 4\n+/* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */\n+#define\tMC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8\n+/* Not relevant for cards with QSFP modules. For older cards, true if module is\n+ * a dual speed SFP+ module.\n+ */\n+#define\tMC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12\n+/* True if an SFP Module is present (other fields valid when true) */\n+#define\tMC_CMD_FC_IN_SFP_PRESENT_OFST 16\n+/* The type of the SFP+ Module. For later cards with QSFP modules, this field\n+ * is unused and the type is communicated by other means.\n+ */\n+#define\tMC_CMD_FC_IN_SFP_TYPE_OFST 20\n+/* Capabilities corresponding to 1 bits. */\n+#define\tMC_CMD_FC_IN_SFP_CAPS_OFST 24\n+\n+/* MC_CMD_FC_IN_DDR_TEST msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_TEST_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_DDR_TEST_OP_LBN 0\n+#define\tMC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8\n+/* enum: DRAM Test Start */\n+#define\tMC_CMD_FC_OP_DDR_TEST_START 0x1\n+/* enum: DRAM Test Poll */\n+#define\tMC_CMD_FC_OP_DDR_TEST_POLL 0x2\n+\n+/* MC_CMD_FC_IN_DDR_TEST_START msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1\n+\n+/* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_TEST_POLL_LEN 12\n+#define\tMC_CMD_FC_IN_DDR_TEST_CMD_OFST 0\n+/*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */\n+/* Clear previous test result and prepare for restarting DDR test */\n+#define\tMC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8\n+\n+/* MC_CMD_FC_IN_GET_ASSERT msgrequest */\n+#define\tMC_CMD_FC_IN_GET_ASSERT_LEN 4\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_FC_IN_FPGA_BUILD msgrequest */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* FPGA build info operation code */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4\n+/* enum: Get the build registers */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1\n+/* enum: Get the services registers */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2\n+/* enum: Get the BSP version */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3\n+/* enum: Get build register for V2 (SFA974X) */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4\n+/* enum: GEt the services register for V2 (SFA974X) */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5\n+\n+/* MC_CMD_FC_IN_READ_MAP msgrequest */\n+#define\tMC_CMD_FC_IN_READ_MAP_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_READ_MAP_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_READ_MAP_OP_LBN 0\n+#define\tMC_CMD_FC_IN_READ_MAP_OP_WIDTH 8\n+/* enum: Get the number of map regions */\n+#define\tMC_CMD_FC_OP_READ_MAP_COUNT 0x1\n+/* enum: Get the specified map */\n+#define\tMC_CMD_FC_OP_READ_MAP_INDEX 0x2\n+\n+/* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */\n+#define\tMC_CMD_FC_IN_READ_MAP_COUNT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */\n+#define\tMC_CMD_FC_IN_READ_MAP_INDEX_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_IN_MAP_INDEX_OFST 8\n+\n+/* MC_CMD_FC_IN_CAPABILITIES msgrequest */\n+#define\tMC_CMD_FC_IN_CAPABILITIES_LEN 4\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1\n+\n+/* MC_CMD_FC_IN_IO_REL msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_IO_REL_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_IO_REL_OP_LBN 0\n+#define\tMC_CMD_FC_IN_IO_REL_OP_WIDTH 8\n+/* enum: Get the base address that the FC applies to relative commands */\n+#define\tMC_CMD_FC_IN_IO_REL_GET_ADDR 0x1\n+/* enum: Read data */\n+#define\tMC_CMD_FC_IN_IO_REL_READ32 0x2\n+/* enum: Write data */\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32 0x3\n+#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8\n+#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8\n+/* enum: Application address space */\n+#define\tMC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1\n+/* enum: Flash address space */\n+#define\tMC_CMD_FC_COMP_TYPE_FLASH 0x2\n+\n+/* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16\n+\n+/* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59\n+\n+/* MC_CMD_FC_IN_UHLINK msgrequest */\n+#define\tMC_CMD_FC_IN_UHLINK_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_UHLINK_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_UHLINK_OP_LBN 0\n+#define\tMC_CMD_FC_IN_UHLINK_OP_WIDTH 8\n+/* enum: Get PHY configuration info */\n+#define\tMC_CMD_FC_OP_UHLINK_PHY 0x1\n+/* enum: Get MAC configuration info */\n+#define\tMC_CMD_FC_OP_UHLINK_MAC 0x2\n+/* enum: Get Rx eye table */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE 0x3\n+/* enum: Get Rx eye plot */\n+#define\tMC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4\n+/* enum: Get Rx eye plot */\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5\n+/* enum: Retune Rx settings */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_TUNE 0x6\n+/* enum: Set loopback mode on fpga port */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7\n+/* enum: Get loopback mode config state on fpga port */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8\n+#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24\n+#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8\n+/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n+ * irrelevant. Port number is derived from pci_fn; passed in FC header.\n+ */\n+#define\tMC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0\n+/* enum: Override default port number. Port number determined by fields\n+ * PORT_TYPE and PORT_IDX.\n+ */\n+#define\tMC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1\n+\n+/* MC_CMD_FC_OP_UHLINK_PHY msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_PHY_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_MAC msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_MAC_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8\n+#define\tMC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */\n+\n+/* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16\n+#define\tMC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */\n+\n+/* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */\n+\n+/* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8\n+\n+/* MC_CMD_FC_IN_SET_LINK msgrequest */\n+#define\tMC_CMD_FC_IN_SET_LINK_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n+#define\tMC_CMD_FC_IN_SET_LINK_MODE_OFST 4\n+#define\tMC_CMD_FC_IN_SET_LINK_SPEED_OFST 8\n+#define\tMC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12\n+#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0\n+#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1\n+#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1\n+#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2\n+#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1\n+\n+/* MC_CMD_FC_IN_LICENSE msgrequest */\n+#define\tMC_CMD_FC_IN_LICENSE_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_LICENSE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_STARTUP msgrequest */\n+#define\tMC_CMD_FC_IN_STARTUP_LEN 40\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_STARTUP_BASE_OFST 4\n+#define\tMC_CMD_FC_IN_STARTUP_LENGTH_OFST 8\n+/* Length of identifier */\n+#define\tMC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12\n+/* Identifier for AOE FPGA */\n+#define\tMC_CMD_FC_IN_STARTUP_ID_OFST 16\n+#define\tMC_CMD_FC_IN_STARTUP_ID_LEN 1\n+#define\tMC_CMD_FC_IN_STARTUP_ID_NUM 24\n+\n+/* MC_CMD_FC_IN_DMA msgrequest */\n+#define\tMC_CMD_FC_IN_DMA_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DMA_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DMA_STOP  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DMA_READ  0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DMA_STOP msgrequest */\n+#define\tMC_CMD_FC_IN_DMA_STOP_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_DMA_OP_OFST 4 */\n+/* FC supplied handle */\n+#define\tMC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8\n+\n+/* MC_CMD_FC_IN_DMA_READ msgrequest */\n+#define\tMC_CMD_FC_IN_DMA_READ_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_DMA_OP_OFST 4 */\n+#define\tMC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8\n+#define\tMC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12\n+\n+/* MC_CMD_FC_IN_TIMED_READ msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TIMED_READ_OP_OFST 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR  0x2 /* enum */\n+\n+/* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_LEN 52\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n+/* Host supplied handle (unique) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8\n+/* Address into which to transfer data in host */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16\n+/* AOE address from which to transfer data */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24\n+/* Length of AOE transfer (total) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28\n+/* Length of host transfer (total) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32\n+/* Offset back from aoe_address to apply operation to */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36\n+/* Data to apply at offset */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_NONE  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_READ  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_WRITE  0x2 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_READWRITE  0x3 /* enum */\n+/* Period at which reads are performed (100ms units) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48\n+\n+/* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n+/* FC supplied handle */\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8\n+\n+/* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n+/* FC supplied handle */\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8\n+\n+/* MC_CMD_FC_IN_LOG msgrequest */\n+#define\tMC_CMD_FC_IN_LOG_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_LOG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART  0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_LOG_OP_OFST 4 */\n+/* Partition offset into flash */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8\n+/* Partition length */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12\n+/* Partition erase size */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16\n+\n+/* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_LOG_OP_OFST 4 */\n+/* Enable/disable printing to JTAG UART */\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8\n+\n+/* MC_CMD_FC_IN_CLOCK msgrequest */\n+#define\tMC_CMD_FC_IN_CLOCK_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_CLOCK_OP_OFST 4\n+#define\tMC_CMD_FC_IN_CLOCK_GET_TIME  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME  0x1 /* enum */\n+/* Perform a clock operation */\n+#define\tMC_CMD_FC_IN_CLOCK_ID_OFST 8\n+#define\tMC_CMD_FC_IN_CLOCK_STATS  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_CLOCK_MAC  0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */\n+#define\tMC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */\n+/* Retrieve the clock value of the specified clock */\n+/*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */\n+\n+/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16\n+/* Set the clock value of the specified clock */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20\n+\n+/* MC_CMD_FC_IN_DDR msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DDR_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DDR_SET_SPD  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_GET_STATUS  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_SET_INFO  0x2 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_OFST 8\n+#define\tMC_CMD_FC_IN_DDR_BANK_B0  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_B1  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_T0  0x2 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_T1  0x3 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_NUM_BANKS  0x4 /* enum */\n+\n+/* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_SET_SPD_LEN 148\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n+/* Affected bank */\n+/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n+/* Flags */\n+#define\tMC_CMD_FC_IN_DDR_FLAGS_OFST 12\n+#define\tMC_CMD_FC_IN_DDR_SET_SPD_ACTIVE  0x1 /* enum */\n+/* 128-byte page of serial presence detect data read from module's EEPROM */\n+#define\tMC_CMD_FC_IN_DDR_SPD_OFST 16\n+#define\tMC_CMD_FC_IN_DDR_SPD_LEN 1\n+#define\tMC_CMD_FC_IN_DDR_SPD_NUM 128\n+/* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */\n+#define\tMC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144\n+\n+/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_SET_INFO_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n+/* Affected bank */\n+/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n+/* Size of DDR */\n+#define\tMC_CMD_FC_IN_DDR_SIZE_OFST 12\n+\n+/* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_GET_STATUS_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n+/* Affected bank */\n+/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n+\n+/* MC_CMD_FC_IN_TIMESTAMP msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* FC timestamp operation code */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_OP_OFST 4\n+/* enum: Read transmit timestamp(s) */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0\n+/* enum: Read snapshot timestamps */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1\n+/* enum: Clear all transmit timestamps */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2\n+\n+/* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4\n+/* Control filtering of the returned timestamp and sequence number specified\n+ * here\n+ */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8\n+/* enum: Return most recent timestamp. No filtering */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0\n+/* enum: Match timestamp against the PTP clock ID, port number and sequence\n+ * number specified\n+ */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1\n+/* Clock identity of PTP packet for which timestamp required */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16\n+/* Port number of PTP packet for which timestamp required */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20\n+/* Sequence number of PTP packet for which timestamp required */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24\n+\n+/* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4\n+\n+/* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4\n+\n+/* MC_CMD_FC_IN_SPI msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* Basic commands for SPI Flash. */\n+#define\tMC_CMD_FC_IN_SPI_OP_OFST 4\n+/* enum: SPI Flash read */\n+#define\tMC_CMD_FC_IN_SPI_READ 0x0\n+/* enum: SPI Flash write */\n+#define\tMC_CMD_FC_IN_SPI_WRITE 0x1\n+/* enum: SPI Flash erase */\n+#define\tMC_CMD_FC_IN_SPI_ERASE 0x2\n+\n+/* MC_CMD_FC_IN_SPI_READ msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_READ_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_SPI_READ_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_READ_ADDR_OFST 8\n+#define\tMC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12\n+\n+/* MC_CMD_FC_IN_SPI_WRITE msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_WRITE_LENMIN 16\n+#define\tMC_CMD_FC_IN_SPI_WRITE_LENMAX 252\n+#define\tMC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_SPI_WRITE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60\n+\n+/* MC_CMD_FC_IN_SPI_ERASE msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_ERASE_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_SPI_ERASE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8\n+#define\tMC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12\n+\n+/* MC_CMD_FC_IN_DIAG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/* Operation code indicating component type */\n+#define\tMC_CMD_FC_IN_DIAG_OP_OFST 4\n+/* enum: Power noise generator. */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE 0x0\n+/* enum: DDR soak test component. */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK 0x1\n+/* enum: Diagnostics datapath control component. */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2\n+\n+/* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4\n+/* Sub-opcode describing the operation to be carried out */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8\n+/* enum: Read the configuration (the 32-bit values in each of the clock enable\n+ * count and toggle count registers)\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0\n+/* enum: Write a new configuration to the clock enable count and toggle count\n+ * registers\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1\n+\n+/* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8\n+\n+/* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8\n+/* The 32-bit value to be written to the toggle count register */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12\n+/* The 32-bit value to be written to the clock enable count register */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4\n+/* Sub-opcode describing the operation to be carried out */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8\n+/* enum: Starts DDR soak test on selected banks */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0\n+/* enum: Read status of DDR soak test */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1\n+/* enum: Stop test */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2\n+/* enum: Set or clear bit that triggers fake errors. These cause subsequent\n+ * tests to fail until the bit is cleared.\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8\n+/* Mask of DDR banks to be tested */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12\n+/* Pattern to use in the soak test */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */\n+/* Either multiple automatic tests until a STOP command is issued, or one\n+ * single test\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8\n+/* DDR bank to read status from */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12\n+#define\tMC_CMD_FC_DDR_BANK0 0x0 /* enum */\n+#define\tMC_CMD_FC_DDR_BANK1 0x1 /* enum */\n+#define\tMC_CMD_FC_DDR_BANK2 0x2 /* enum */\n+#define\tMC_CMD_FC_DDR_BANK3 0x3 /* enum */\n+#define\tMC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8\n+/* Mask of DDR banks to be tested */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8\n+/* Mask of DDR banks to set/clear error flag on */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4\n+/* Sub-opcode describing the operation to be carried out */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8\n+/* enum: Set a known datapath configuration */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0\n+/* enum: Apply raw config to datapath control registers */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1\n+\n+/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8\n+/* Datapath configuration identifier */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8\n+/* Value to write into control register 1 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12\n+/* Value to write into control register 2 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16\n+/* Value to write into control register 3 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20\n+\n+/* MC_CMD_FC_OUT msgresponse */\n+#define\tMC_CMD_FC_OUT_LEN 0\n+\n+/* MC_CMD_FC_OUT_NULL msgresponse */\n+#define\tMC_CMD_FC_OUT_NULL_LEN 0\n+\n+/* MC_CMD_FC_OUT_READ32 msgresponse */\n+#define\tMC_CMD_FC_OUT_READ32_LENMIN 4\n+#define\tMC_CMD_FC_OUT_READ32_LENMAX 252\n+#define\tMC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_OFST 0\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_FC_OUT_WRITE32 msgresponse */\n+#define\tMC_CMD_FC_OUT_WRITE32_LEN 0\n+\n+/* MC_CMD_FC_OUT_TRC_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_READ_LEN 16\n+#define\tMC_CMD_FC_OUT_TRC_READ_DATA_OFST 0\n+#define\tMC_CMD_FC_OUT_TRC_READ_DATA_LEN 4\n+#define\tMC_CMD_FC_OUT_TRC_READ_DATA_NUM 4\n+\n+/* MC_CMD_FC_OUT_TRC_WRITE msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_WRITE_LEN 0\n+\n+/* MC_CMD_FC_OUT_GET_VERSION msgresponse */\n+#define\tMC_CMD_FC_OUT_GET_VERSION_LEN 12\n+#define\tMC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8\n+\n+/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_LEN 8\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2\n+\n+/* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0\n+\n+/* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0\n+\n+/* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_SET_LINK_LEN 0\n+\n+/* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0\n+\n+/* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS\n+#define\tMC_CMD_FC_MAC_RX_STATS_OCTETS  0x0 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_OCTETS_OK  0x1 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS  0x2 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_FRAMES_OK  0x4 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_CRC_ERRORS  0x5 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_VLAN_OK  0x6 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_ERRORS  0x7 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_UCAST_PKTS  0x8 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_MULTICAST_PKTS  0x9 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_BROADCAST_PKTS  0xa /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_DROP_EVENTS  0xb /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS  0xc /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS  0xd /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_64  0xe /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_65_127  0xf /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_128_255  0x10 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_256_511  0x11 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_512_1023  0x12 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518  0x13 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX  0x14 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS  0x15 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_JABBERS  0x16 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_FRAGMENTS  0x17 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES  0x18 /* enum */\n+/* enum: (Last entry) */\n+#define\tMC_CMD_FC_MAC_RX_NSTATS  0x19\n+\n+/* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS\n+#define\tMC_CMD_FC_MAC_TX_STATS_OCTETS  0x0 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_OCTETS_OK  0x1 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS  0x2 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_FRAMES_OK  0x4 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_CRC_ERRORS  0x5 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_VLAN_OK  0x6 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_ERRORS  0x7 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_UCAST_PKTS  0x8 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_MULTICAST_PKTS  0x9 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_BROADCAST_PKTS  0xa /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_DROP_EVENTS  0xb /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS  0xc /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS  0xd /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_64  0xe /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_65_127  0xf /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_128_255  0x10 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_256_511  0x11 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_512_1023  0x12 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518  0x13 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU  0x14 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES  0x15 /* enum */\n+/* enum: (Last entry) */\n+#define\tMC_CMD_FC_MAC_TX_NSTATS  0x16\n+\n+/* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)\n+/* MAC Statistics */\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK\n+\n+/* MC_CMD_FC_OUT_MAC msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_LEN 0\n+\n+/* MC_CMD_FC_OUT_SFP msgresponse */\n+#define\tMC_CMD_FC_OUT_SFP_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_START_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8\n+/* enum: Test not yet initiated */\n+#define\tMC_CMD_FC_OP_DDR_TEST_NONE 0x0\n+/* enum: Test is in progress */\n+#define\tMC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1\n+/* enum: Timed completed */\n+#define\tMC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2\n+/* enum: Test did not complete in specified time */\n+#define\tMC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1\n+/* Test result from FPGA */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */\n+\n+/* MC_CMD_FC_OUT_DDR_TEST msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_LEN 0\n+\n+/* MC_CMD_FC_OUT_GET_ASSERT msgresponse */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_LEN 144\n+/* Assertion status flag. */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8\n+/* enum: No crash data available */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0\n+/* enum: New crash data available */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1\n+/* enum: Crash data has been sent */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8\n+/* enum: No crash has been recorded. */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0\n+/* enum: Crash due to exception. */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1\n+/* enum: Crash due to assertion. */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2\n+/* Failing PC value */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4\n+/* Saved GP regs */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31\n+/* Exception Type */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132\n+/* Instruction at which exception occurred */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136\n+/* BAD Address that triggered address-based exception */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140\n+\n+/* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8\n+#define\tMC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */\n+#define\tMC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1\n+#define\tMC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */\n+#define\tMC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_BSP_VERSION msgresponse */\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_LEN 4\n+/* Qsys system ID */\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4\n+\n+/* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */\n+#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4\n+/* Number of maps */\n+#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0\n+\n+/* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164\n+/* Index of the map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0\n+/* Options for the map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8  0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16  0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32  0x2 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64  0x3 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK  0x3 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC  0x4 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM  0x8 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ  0x10 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE  0x20 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE  0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED  0x40 /* enum */\n+/* Address of start of map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12\n+/* Length of address map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20\n+/* Component information field */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24\n+/* License expiry data for map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32\n+/* Name of the component */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128\n+\n+/* MC_CMD_FC_OUT_READ_MAP msgresponse */\n+#define\tMC_CMD_FC_OUT_READ_MAP_LEN 0\n+\n+/* MC_CMD_FC_OUT_CAPABILITIES msgresponse */\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_LEN 8\n+/* Number of internal ports */\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0\n+/* Number of external ports */\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4\n+\n+/* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */\n+#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0\n+\n+/* MC_CMD_FC_OUT_IO_REL msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_LEN 0\n+\n+/* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4\n+\n+/* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LEN 48\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16\n+/* Transceiver Transmit settings */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16\n+/* Transceiver Receive settings */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16\n+/* Rx eye opening */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16\n+/* PCS status word */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16\n+/* Link status word */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1\n+/* Current SFp parameters applied */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20\n+/* Link speed is 100, 1000, 10000 */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24\n+/* Length of copper cable - zero when not relevant */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28\n+/* True if a dual speed SFP+ module */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32\n+/* True if an SFP Module is present (other fields valid when true) */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36\n+/* The type of the SFP+ Module */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40\n+/* PHY config flags */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1\n+\n+/* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_LEN 20\n+/* MAC configuration applied */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0\n+/* MTU size */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4\n+/* IF Mode status */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8\n+/* MAC address configured */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16\n+\n+/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)\n+/* Rx Eye measurements */\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK\n+\n+/* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)\n+/* Has the eye plot dump completed and data returned is valid? */\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0\n+/* Rx Eye binary plot */\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK\n+\n+/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0\n+\n+/* MC_CMD_FC_OUT_UHLINK msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_LEN 0\n+\n+/* MC_CMD_FC_OUT_SET_LINK msgresponse */\n+#define\tMC_CMD_FC_OUT_SET_LINK_LEN 0\n+\n+/* MC_CMD_FC_OUT_LICENSE msgresponse */\n+#define\tMC_CMD_FC_OUT_LICENSE_LEN 12\n+/* Count of valid keys */\n+#define\tMC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0\n+/* Count of invalid keys */\n+#define\tMC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4\n+/* Count of blacklisted keys */\n+#define\tMC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8\n+\n+/* MC_CMD_FC_OUT_STARTUP msgresponse */\n+#define\tMC_CMD_FC_OUT_STARTUP_LEN 4\n+/* Capabilities of the FPGA/FC */\n+#define\tMC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0\n+#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0\n+#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1\n+\n+/* MC_CMD_FC_OUT_DMA_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_DMA_READ_LENMIN 1\n+#define\tMC_CMD_FC_OUT_DMA_READ_LENMAX 252\n+#define\tMC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))\n+/* The data read */\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_OFST 0\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_LEN 1\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252\n+\n+/* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_SET_LEN 4\n+/* Timer handle */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0\n+\n+/* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_LEN 52\n+/* Host supplied handle (unique) */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0\n+/* Address into which to transfer data in host */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8\n+/* AOE address from which to transfer data */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16\n+/* Length of AOE transfer (total) */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20\n+/* Length of host transfer (total) */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24\n+/* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32\n+/* When active, start read time */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40\n+/* When active, end read time */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48\n+\n+/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */\n+#define\tMC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0\n+\n+/* MC_CMD_FC_OUT_LOG msgresponse */\n+#define\tMC_CMD_FC_OUT_LOG_LEN 0\n+\n+/* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20\n+\n+/* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */\n+#define\tMC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_SET_SPD_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_SET_INFO_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1\n+\n+/* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4\n+\n+/* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31\n+\n+/* MC_CMD_FC_OUT_SPI_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_SPI_READ_LENMIN 4\n+#define\tMC_CMD_FC_OUT_SPI_READ_LENMAX 252\n+#define\tMC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_FC_OUT_SPI_WRITE msgresponse */\n+#define\tMC_CMD_FC_OUT_SPI_WRITE_LEN 0\n+\n+/* MC_CMD_FC_OUT_SPI_ERASE msgresponse */\n+#define\tMC_CMD_FC_OUT_SPI_ERASE_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8\n+/* The 32-bit value read from the toggle count register */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0\n+/* The 32-bit value read from the clock enable count register */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4\n+\n+/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8\n+/* DDR soak test status word; bits [4:0] are relevant. */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1\n+/* DDR soak test error count */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_AOE\n+ * AOE operations on MC\n+ */\n+#define\tMC_CMD_AOE 0xa\n+\n+/* MC_CMD_AOE_IN msgrequest */\n+#define\tMC_CMD_AOE_IN_LEN 4\n+#define\tMC_CMD_AOE_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_AOE_IN_OP_LBN 0\n+#define\tMC_CMD_AOE_IN_OP_WIDTH 8\n+/* enum: FPGA and CPLD information */\n+#define\tMC_CMD_AOE_OP_INFO 0x1\n+/* enum: Currents and voltages read from MCP3424s; DEBUG */\n+#define\tMC_CMD_AOE_OP_CURRENTS 0x2\n+/* enum: Temperatures at locations around the PCB; DEBUG */\n+#define\tMC_CMD_AOE_OP_TEMPERATURES 0x3\n+/* enum: Set CPLD to idle */\n+#define\tMC_CMD_AOE_OP_CPLD_IDLE 0x4\n+/* enum: Read from CPLD register */\n+#define\tMC_CMD_AOE_OP_CPLD_READ 0x5\n+/* enum: Write to CPLD register */\n+#define\tMC_CMD_AOE_OP_CPLD_WRITE 0x6\n+/* enum: Execute CPLD instruction */\n+#define\tMC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7\n+/* enum: Reprogram the CPLD on the AOE device */\n+#define\tMC_CMD_AOE_OP_CPLD_REPROGRAM 0x8\n+/* enum: AOE power control */\n+#define\tMC_CMD_AOE_OP_POWER 0x9\n+/* enum: AOE image loading */\n+#define\tMC_CMD_AOE_OP_LOAD 0xa\n+/* enum: Fan monitoring */\n+#define\tMC_CMD_AOE_OP_FAN_CONTROL 0xb\n+/* enum: Fan failures since last reset */\n+#define\tMC_CMD_AOE_OP_FAN_FAILURES 0xc\n+/* enum: Get generic AOE MAC statistics */\n+#define\tMC_CMD_AOE_OP_MAC_STATS 0xd\n+/* enum: Retrieve PHY specific information */\n+#define\tMC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe\n+/* enum: Write a number of JTAG primitive commands, return will give data */\n+#define\tMC_CMD_AOE_OP_JTAG_WRITE 0xf\n+/* enum: Control access to the FPGA via the Siena JTAG Chain */\n+#define\tMC_CMD_AOE_OP_FPGA_ACCESS 0x10\n+/* enum: Set the MTU offset between Siena and AOE MACs */\n+#define\tMC_CMD_AOE_OP_SET_MTU_OFFSET 0x11\n+/* enum: How link state is handled */\n+#define\tMC_CMD_AOE_OP_LINK_STATE 0x12\n+/* enum: How Siena MAC statistics are reported (deprecated - use\n+ * MC_CMD_AOE_OP_ASIC_STATS)\n+ */\n+#define\tMC_CMD_AOE_OP_SIENA_STATS 0x13\n+/* enum: How native ASIC MAC statistics are reported - replaces the deprecated\n+ * command MC_CMD_AOE_OP_SIENA_STATS\n+ */\n+#define\tMC_CMD_AOE_OP_ASIC_STATS 0x13\n+/* enum: DDR memory information */\n+#define\tMC_CMD_AOE_OP_DDR 0x14\n+/* enum: FC control */\n+#define\tMC_CMD_AOE_OP_FC 0x15\n+/* enum: DDR ECC status reads */\n+#define\tMC_CMD_AOE_OP_DDR_ECC_STATUS 0x16\n+/* enum: Commands for MC-SPI Master emulation */\n+#define\tMC_CMD_AOE_OP_MC_SPI_MASTER 0x17\n+/* enum: Commands for FC boot control */\n+#define\tMC_CMD_AOE_OP_FC_BOOT 0x18\n+\n+/* MC_CMD_AOE_OUT msgresponse */\n+#define\tMC_CMD_AOE_OUT_LEN 0\n+\n+/* MC_CMD_AOE_IN_INFO msgrequest */\n+#define\tMC_CMD_AOE_IN_INFO_LEN 4\n+#define\tMC_CMD_AOE_IN_CMD_OFST 0\n+\n+/* MC_CMD_AOE_IN_CURRENTS msgrequest */\n+#define\tMC_CMD_AOE_IN_CURRENTS_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_AOE_IN_TEMPERATURES msgrequest */\n+#define\tMC_CMD_AOE_IN_TEMPERATURES_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_IDLE_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_AOE_IN_CPLD_READ msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_READ_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4\n+#define\tMC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8\n+\n+/* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_LEN 16\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12\n+\n+/* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4\n+\n+/* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4\n+/* enum: Reprogram CPLD, poll for completion */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1\n+/* enum: Reprogram CPLD, send event on completion */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3\n+/* enum: Get status of reprogramming operation */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4\n+\n+/* MC_CMD_AOE_IN_POWER msgrequest */\n+#define\tMC_CMD_AOE_IN_POWER_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* Turn on or off AOE power */\n+#define\tMC_CMD_AOE_IN_POWER_OP_OFST 4\n+/* enum: Turn off FPGA power */\n+#define\tMC_CMD_AOE_IN_POWER_OFF  0x0\n+/* enum: Turn on FPGA power */\n+#define\tMC_CMD_AOE_IN_POWER_ON  0x1\n+/* enum: Clear peak power measurement */\n+#define\tMC_CMD_AOE_IN_POWER_CLEAR  0x2\n+/* enum: Show current power in sensors output */\n+#define\tMC_CMD_AOE_IN_POWER_SHOW_CURRENT  0x3\n+/* enum: Show peak power in sensors output */\n+#define\tMC_CMD_AOE_IN_POWER_SHOW_PEAK  0x4\n+/* enum: Show current DDR current */\n+#define\tMC_CMD_AOE_IN_POWER_DDR_LAST  0x5\n+/* enum: Show peak DDR current */\n+#define\tMC_CMD_AOE_IN_POWER_DDR_PEAK  0x6\n+/* enum: Clear peak DDR current */\n+#define\tMC_CMD_AOE_IN_POWER_DDR_CLEAR  0x7\n+\n+/* MC_CMD_AOE_IN_LOAD msgrequest */\n+#define\tMC_CMD_AOE_IN_LOAD_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence\n+ */\n+#define\tMC_CMD_AOE_IN_LOAD_IMAGE_OFST 4\n+\n+/* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */\n+#define\tMC_CMD_AOE_IN_FAN_CONTROL_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* If non zero report measured fan RPM rather than nominal */\n+#define\tMC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4\n+\n+/* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */\n+#define\tMC_CMD_AOE_IN_FAN_FAILURES_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_AOE_IN_MAC_STATS msgrequest */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_LEN 24\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* AOE port */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4\n+/* Host memory address for statistics */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16\n+/* Length of DMA data (optional) */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20\n+\n+/* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* AOE port */\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8\n+\n+/* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61\n+\n+/* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* Enable or disable access */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4\n+/* enum: Enable access */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1\n+/* enum: Disable access */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2\n+\n+/* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4\n+/* enum: Apply to all external ports */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000\n+/* enum: Apply to all internal ports */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000\n+/* The MTU offset to be applied to the external ports */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8\n+\n+/* MC_CMD_AOE_IN_LINK_STATE msgrequest */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8\n+/* enum: AOE and associated external port */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE  0x0\n+/* enum: AOE and OR of all external ports */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED  0x1\n+/* enum: Individual ports */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC  0x2\n+/* enum: Configure link state mode on given AOE port */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CUSTOM  0x3\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8\n+/* enum: No-op */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OP_NONE  0x0\n+/* enum: logical OR of all SFP ports link status */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OP_OR  0x1\n+/* enum: logical AND of all SFP ports link status */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OP_AND  0x2\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16\n+\n+/* MC_CMD_AOE_IN_SIENA_STATS msgrequest */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* How MAC statistics are reported */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4\n+/* enum: Statistics from Siena (default) */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA  0x0\n+/* enum: Statistics from AOE external ports */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_STATS_AOE  0x1\n+\n+/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* How MAC statistics are reported */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4\n+/* enum: Statistics from the ASIC (default) */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC  0x0\n+/* enum: Statistics from AOE external ports */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_STATS_AOE  0x1\n+\n+/* MC_CMD_AOE_IN_DDR msgrequest */\n+#define\tMC_CMD_AOE_IN_DDR_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_DDR_BANK_OFST 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */\n+/* Page index of SPD data */\n+#define\tMC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8\n+\n+/* MC_CMD_AOE_IN_FC msgrequest */\n+#define\tMC_CMD_AOE_IN_FC_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */\n+#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */\n+\n+/* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* Basic commands for MC SPI Master emulation. */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4\n+/* enum: MC SPI read */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0\n+/* enum: MC SPI write */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1\n+\n+/* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8\n+\n+/* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12\n+\n+/* MC_CMD_AOE_IN_FC_BOOT msgrequest */\n+#define\tMC_CMD_AOE_IN_FC_BOOT_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/* FC boot control flags */\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1\n+\n+/* MC_CMD_AOE_OUT_INFO msgresponse */\n+#define\tMC_CMD_AOE_OUT_INFO_LEN 44\n+/* JTAG IDCODE of CPLD */\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0\n+/* Version of CPLD */\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4\n+/* JTAG IDCODE of FPGA */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8\n+/* JTAG USERCODE of FPGA */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12\n+/* FPGA type - read from CPLD straps */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2   0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2   0x2 /* enum */\n+/* FPGA state (debug) */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20\n+/* FPGA image - partition from which loaded */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24\n+/* FC state */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28\n+/* enum: Set if watchdog working */\n+#define\tMC_CMD_AOE_OUT_INFO_WATCHDOG 0x1\n+/* enum: Set if MC-FC communications working */\n+#define\tMC_CMD_AOE_OUT_INFO_COMMS 0x2\n+/* Random pieces of information */\n+#define\tMC_CMD_AOE_OUT_INFO_FLAGS_OFST 32\n+/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */\n+#define\tMC_CMD_AOE_OUT_INFO_PEG_POWER            0x1\n+/* enum: CPLD apparently good */\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_GOOD            0x2\n+/* enum: FPGA working normally */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_GOOD            0x4\n+/* enum: FPGA is powered */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_POWER           0x8\n+/* enum: Board has incompatible SODIMMs fitted */\n+#define\tMC_CMD_AOE_OUT_INFO_BAD_SODIMM           0x10\n+/* enum: Board has ByteBlaster connected */\n+#define\tMC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER      0x20\n+/* enum: FPGA Boot flash has an invalid header. */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR    0x40\n+/* enum: FPGA Application flash is accessible. */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD  0x80\n+/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */\n+#define\tMC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36\n+#define\tMC_CMD_AOE_OUT_INFO_UNKNOWN  0x0 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_0  0x10 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_1  0x11 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_2  0x12 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_3  0x13 /* enum */\n+/* Result of FC booting - not valid while a ByteBlaster is connected. */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40\n+/* enum: No error */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0\n+/* enum: Bad address set in CPLD */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1\n+/* enum: Bad header */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2\n+/* enum: Bad text section details */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3\n+/* enum: Bad checksum */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4\n+/* enum: Bad BSP */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5\n+/* enum: Flash mode is invalid */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6\n+/* enum: FC application loaded and execution attempted */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80\n+/* enum: FC application Started */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81\n+/* enum: No bootrom in FPGA */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff\n+\n+/* MC_CMD_AOE_OUT_CURRENTS msgresponse */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_LEN 68\n+/* Set of currents and voltages (mA or mV as appropriate) */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0\n+#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4\n+#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */\n+\n+/* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_LEN 40\n+/* Set of temperatures */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10\n+/* enum: The first set of enum values are for Modena code. */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */\n+/* enum: The second set of enum values are for Sorrento code. */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */\n+\n+/* MC_CMD_AOE_OUT_CPLD_READ msgresponse */\n+#define\tMC_CMD_AOE_OUT_CPLD_READ_LEN 4\n+/* The value read from the CPLD */\n+#define\tMC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0\n+\n+/* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))\n+/* Failure counts for each fan */\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63\n+\n+/* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */\n+#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4\n+/* Results of status command (only) */\n+#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0\n+\n+/* MC_CMD_AOE_OUT_POWER_OFF msgresponse */\n+#define\tMC_CMD_AOE_OUT_POWER_OFF_LEN 0\n+\n+/* MC_CMD_AOE_OUT_POWER_ON msgresponse */\n+#define\tMC_CMD_AOE_OUT_POWER_ON_LEN 0\n+\n+/* MC_CMD_AOE_OUT_LOAD msgresponse */\n+#define\tMC_CMD_AOE_OUT_LOAD_LEN 0\n+\n+/* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0\n+\n+/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA\n+ * for details\n+ */\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS\n+\n+/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))\n+/* in bytes */\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248\n+\n+/* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))\n+/* Used to align the in and out data blocks so the MC can re-use the cmd */\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0\n+/* out bytes */\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61\n+\n+/* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */\n+#define\tMC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0\n+\n+/* MC_CMD_AOE_OUT_DDR msgresponse */\n+#define\tMC_CMD_AOE_OUT_DDR_LENMIN 17\n+#define\tMC_CMD_AOE_OUT_DDR_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))\n+/* Information on the module. */\n+#define\tMC_CMD_AOE_OUT_DDR_FLAGS_OFST 0\n+#define\tMC_CMD_AOE_OUT_DDR_PRESENT_LBN 0\n+#define\tMC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_POWERED_LBN 1\n+#define\tMC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2\n+#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3\n+#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1\n+/* Memory size, in MB. */\n+#define\tMC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4\n+/* The memory type, as reported from SPD information */\n+#define\tMC_CMD_AOE_OUT_DDR_TYPE_OFST 8\n+/* Nominal voltage of the module (as applied) */\n+#define\tMC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12\n+/* SPD data read from the module */\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_OFST 16\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_LEN 1\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236\n+\n+/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */\n+#define\tMC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0\n+\n+/* MC_CMD_AOE_OUT_LINK_STATE msgresponse */\n+#define\tMC_CMD_AOE_OUT_LINK_STATE_LEN 0\n+\n+/* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */\n+#define\tMC_CMD_AOE_OUT_SIENA_STATS_LEN 0\n+\n+/* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */\n+#define\tMC_CMD_AOE_OUT_ASIC_STATS_LEN 0\n+\n+/* MC_CMD_AOE_OUT_FC msgresponse */\n+#define\tMC_CMD_AOE_OUT_FC_LEN 0\n+\n+/* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8\n+/* Flags describing status info on the module. */\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1\n+/* DDR ECC status on the module. */\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8\n+\n+/* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0\n+\n+/* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0\n+\n+/* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0\n+\n+/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */\n+#define\tMC_CMD_AOE_OUT_FC_BOOT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PTP\n+ * Perform PTP operation\n+ */\n+#define\tMC_CMD_PTP 0xb\n+#undef\tMC_CMD_0xb_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_PTP_IN msgrequest */\n+#define\tMC_CMD_PTP_IN_LEN 1\n+/* PTP operation code */\n+#define\tMC_CMD_PTP_IN_OP_OFST 0\n+#define\tMC_CMD_PTP_IN_OP_LEN 1\n+/* enum: Enable PTP packet timestamping operation. */\n+#define\tMC_CMD_PTP_OP_ENABLE 0x1\n+/* enum: Disable PTP packet timestamping operation. */\n+#define\tMC_CMD_PTP_OP_DISABLE 0x2\n+/* enum: Send a PTP packet. */\n+#define\tMC_CMD_PTP_OP_TRANSMIT 0x3\n+/* enum: Read the current NIC time. */\n+#define\tMC_CMD_PTP_OP_READ_NIC_TIME 0x4\n+/* enum: Get the current PTP status. */\n+#define\tMC_CMD_PTP_OP_STATUS 0x5\n+/* enum: Adjust the PTP NIC's time. */\n+#define\tMC_CMD_PTP_OP_ADJUST 0x6\n+/* enum: Synchronize host and NIC time. */\n+#define\tMC_CMD_PTP_OP_SYNCHRONIZE 0x7\n+/* enum: Basic manufacturing tests. */\n+#define\tMC_CMD_PTP_OP_MANFTEST_BASIC 0x8\n+/* enum: Packet based manufacturing tests. */\n+#define\tMC_CMD_PTP_OP_MANFTEST_PACKET 0x9\n+/* enum: Reset some of the PTP related statistics */\n+#define\tMC_CMD_PTP_OP_RESET_STATS 0xa\n+/* enum: Debug operations to MC. */\n+#define\tMC_CMD_PTP_OP_DEBUG 0xb\n+/* enum: Read an FPGA register */\n+#define\tMC_CMD_PTP_OP_FPGAREAD 0xc\n+/* enum: Write an FPGA register */\n+#define\tMC_CMD_PTP_OP_FPGAWRITE 0xd\n+/* enum: Apply an offset to the NIC clock */\n+#define\tMC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe\n+/* enum: Change Apply an offset to the NIC clock */\n+#define\tMC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf\n+/* enum: Set the MC packet filter VLAN tags for received PTP packets */\n+#define\tMC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10\n+/* enum: Set the MC packet filter UUID for received PTP packets */\n+#define\tMC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11\n+/* enum: Set the MC packet filter Domain for received PTP packets */\n+#define\tMC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12\n+/* enum: Set the clock source */\n+#define\tMC_CMD_PTP_OP_SET_CLK_SRC 0x13\n+/* enum: Reset value of Timer Reg. */\n+#define\tMC_CMD_PTP_OP_RST_CLK 0x14\n+/* enum: Enable the forwarding of PPS events to the host */\n+#define\tMC_CMD_PTP_OP_PPS_ENABLE 0x15\n+/* enum: Get the time format used by this NIC for PTP operations */\n+#define\tMC_CMD_PTP_OP_GET_TIME_FORMAT 0x16\n+/* enum: Get the clock attributes. NOTE- extended version of\n+ * MC_CMD_PTP_OP_GET_TIME_FORMAT\n+ */\n+#define\tMC_CMD_PTP_OP_GET_ATTRIBUTES 0x16\n+/* enum: Get corrections that should be applied to the various different\n+ * timestamps\n+ */\n+#define\tMC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17\n+/* enum: Subscribe to receive periodic time events indicating the current NIC\n+ * time\n+ */\n+#define\tMC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18\n+/* enum: Unsubscribe to stop receiving time events */\n+#define\tMC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19\n+/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS\n+ * input on the same NIC.\n+ */\n+#define\tMC_CMD_PTP_OP_MANFTEST_PPS 0x1a\n+/* enum: Set the PTP sync status. Status is used by firmware to report to event\n+ * subscribers.\n+ */\n+#define\tMC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b\n+/* enum: Above this for future use. */\n+#define\tMC_CMD_PTP_OP_MAX 0x1c\n+\n+/* MC_CMD_PTP_IN_ENABLE msgrequest */\n+#define\tMC_CMD_PTP_IN_ENABLE_LEN 16\n+#define\tMC_CMD_PTP_IN_CMD_OFST 0\n+#define\tMC_CMD_PTP_IN_PERIPH_ID_OFST 4\n+/* Event queue for PTP events */\n+#define\tMC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8\n+/* PTP timestamping mode */\n+#define\tMC_CMD_PTP_IN_ENABLE_MODE_OFST 12\n+/* enum: PTP, version 1 */\n+#define\tMC_CMD_PTP_MODE_V1 0x0\n+/* enum: PTP, version 1, with VLAN headers - deprecated */\n+#define\tMC_CMD_PTP_MODE_V1_VLAN 0x1\n+/* enum: PTP, version 2 */\n+#define\tMC_CMD_PTP_MODE_V2 0x2\n+/* enum: PTP, version 2, with VLAN headers - deprecated */\n+#define\tMC_CMD_PTP_MODE_V2_VLAN 0x3\n+/* enum: PTP, version 2, with improved UUID filtering */\n+#define\tMC_CMD_PTP_MODE_V2_ENHANCED 0x4\n+/* enum: FCoE (seconds and microseconds) */\n+#define\tMC_CMD_PTP_MODE_FCOE 0x5\n+\n+/* MC_CMD_PTP_IN_DISABLE msgrequest */\n+#define\tMC_CMD_PTP_IN_DISABLE_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_TRANSMIT msgrequest */\n+#define\tMC_CMD_PTP_IN_TRANSMIT_LENMIN 13\n+#define\tMC_CMD_PTP_IN_TRANSMIT_LENMAX 252\n+#define\tMC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Transmit packet length */\n+#define\tMC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8\n+/* Transmit packet data */\n+#define\tMC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12\n+#define\tMC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1\n+#define\tMC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1\n+#define\tMC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240\n+\n+/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */\n+#define\tMC_CMD_PTP_IN_READ_NIC_TIME_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_STATUS msgrequest */\n+#define\tMC_CMD_PTP_IN_STATUS_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_ADJUST msgrequest */\n+#define\tMC_CMD_PTP_IN_ADJUST_LEN 24\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Frequency adjustment 40 bit fixed point ns */\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_OFST 8\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_LEN 8\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12\n+/* enum: Number of fractional bits in frequency adjustment */\n+#define\tMC_CMD_PTP_IN_ADJUST_BITS 0x28\n+/* Time adjustment in seconds */\n+#define\tMC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16\n+/* Time adjustment major value */\n+#define\tMC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16\n+/* Time adjustment in nanoseconds */\n+#define\tMC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20\n+/* Time adjustment minor value */\n+#define\tMC_CMD_PTP_IN_ADJUST_MINOR_OFST 20\n+\n+/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_LEN 20\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Number of time readings to capture */\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8\n+/* Host address in which to write \"synchronization started\" indication (64\n+ * bits)\n+ */\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16\n+\n+/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */\n+#define\tMC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */\n+#define\tMC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Enable or disable packet testing */\n+#define\tMC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8\n+\n+/* MC_CMD_PTP_IN_RESET_STATS msgrequest */\n+#define\tMC_CMD_PTP_IN_RESET_STATS_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/* Reset PTP statistics */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_DEBUG msgrequest */\n+#define\tMC_CMD_PTP_IN_DEBUG_LEN 12\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Debug operations */\n+#define\tMC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8\n+\n+/* MC_CMD_PTP_IN_FPGAREAD msgrequest */\n+#define\tMC_CMD_PTP_IN_FPGAREAD_LEN 16\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+#define\tMC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8\n+#define\tMC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12\n+\n+/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_LENMIN 13\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_LENMAX 252\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240\n+\n+/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Time adjustment in seconds */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8\n+/* Time adjustment major value */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8\n+/* Time adjustment in nanoseconds */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12\n+/* Time adjustment minor value */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12\n+\n+/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Frequency adjustment 40 bit fixed point ns */\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12\n+/* enum: Number of fractional bits in frequency adjustment */\n+/*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */\n+\n+/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */\n+#define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Number of VLAN tags, 0 if not VLAN */\n+#define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8\n+/* Set of VLAN tags to filter against */\n+#define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12\n+#define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4\n+#define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3\n+\n+/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* 1 to enable UUID filtering, 0 to disable */\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8\n+/* UUID to filter against */\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16\n+\n+/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */\n+#define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* 1 to enable Domain filtering, 0 to disable */\n+#define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8\n+/* Domain number to filter against */\n+#define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12\n+\n+/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */\n+#define\tMC_CMD_PTP_IN_SET_CLK_SRC_LEN 12\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Set the clock source. */\n+#define\tMC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8\n+/* enum: Internal. */\n+#define\tMC_CMD_PTP_CLK_SRC_INTERNAL 0x0\n+/* enum: External. */\n+#define\tMC_CMD_PTP_CLK_SRC_EXTERNAL 0x1\n+\n+/* MC_CMD_PTP_IN_RST_CLK msgrequest */\n+#define\tMC_CMD_PTP_IN_RST_CLK_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/* Reset value of Timer Reg. */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */\n+#define\tMC_CMD_PTP_IN_PPS_ENABLE_LEN 12\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/* Enable or disable */\n+#define\tMC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4\n+/* enum: Enable */\n+#define\tMC_CMD_PTP_ENABLE_PPS 0x0\n+/* enum: Disable */\n+#define\tMC_CMD_PTP_DISABLE_PPS 0x1\n+/* Queue id to send events back */\n+#define\tMC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8\n+\n+/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */\n+#define\tMC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */\n+#define\tMC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */\n+#define\tMC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+\n+/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Original field containing queue ID. Now extended to include flags. */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1\n+\n+/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* Unsubscribe options */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8\n+/* enum: Unsubscribe a single queue */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0\n+/* enum: Unsubscribe all queues */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1\n+/* Event queue ID */\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12\n+\n+/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */\n+#define\tMC_CMD_PTP_IN_MANFTEST_PPS_LEN 12\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* 1 to enable PPS test mode, 0 to disable and return result. */\n+#define\tMC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8\n+\n+/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/* NIC - Host System Clock Synchronization status */\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8\n+/* enum: Host System clock and NIC clock are not in sync */\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0\n+/* enum: Host System clock and NIC clock are synchronized */\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1\n+/* If synchronized, number of seconds until clocks should be considered to be\n+ * no longer in sync.\n+ */\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20\n+\n+/* MC_CMD_PTP_OUT msgresponse */\n+#define\tMC_CMD_PTP_OUT_LEN 0\n+\n+/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_LEN 8\n+/* Value of seconds timestamp */\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0\n+/* Timestamp major value */\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0\n+/* Value of nanoseconds timestamp */\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4\n+/* Timestamp minor value */\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4\n+\n+/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */\n+#define\tMC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0\n+\n+/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */\n+#define\tMC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0\n+\n+/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8\n+/* Value of seconds timestamp */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0\n+/* Timestamp major value */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0\n+/* Value of nanoseconds timestamp */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4\n+/* Timestamp minor value */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4\n+\n+/* MC_CMD_PTP_OUT_STATUS msgresponse */\n+#define\tMC_CMD_PTP_OUT_STATUS_LEN 64\n+/* Frequency of NIC's hardware clock */\n+#define\tMC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0\n+/* Number of packets transmitted and timestamped */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4\n+/* Number of packets received and timestamped */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8\n+/* Number of packets timestamped by the FPGA */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12\n+/* Number of packets filter matched */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16\n+/* Number of packets not filter matched */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20\n+/* Number of PPS overflows (noise on input?) */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24\n+/* Number of PPS bad periods */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28\n+/* Minimum period of PPS pulse in nanoseconds */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32\n+/* Maximum period of PPS pulse in nanoseconds */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36\n+/* Last period of PPS pulse in nanoseconds */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40\n+/* Mean period of PPS pulse in nanoseconds */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44\n+/* Minimum offset of PPS pulse in nanoseconds (signed) */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48\n+/* Maximum offset of PPS pulse in nanoseconds (signed) */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52\n+/* Last offset of PPS pulse in nanoseconds (signed) */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56\n+/* Mean offset of PPS pulse in nanoseconds (signed) */\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60\n+\n+/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))\n+/* A set of host and NIC times */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12\n+/* Host time immediately before NIC's hardware clock read */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0\n+/* Value of seconds timestamp */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4\n+/* Timestamp major value */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4\n+/* Value of nanoseconds timestamp */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8\n+/* Timestamp minor value */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8\n+/* Host time immediately after NIC's hardware clock read */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12\n+/* Number of nanoseconds waited after reading NIC's hardware clock */\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16\n+\n+/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8\n+/* Results of testing */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0\n+/* enum: Successful test */\n+#define\tMC_CMD_PTP_MANF_SUCCESS 0x0\n+/* enum: FPGA load failed */\n+#define\tMC_CMD_PTP_MANF_FPGA_LOAD 0x1\n+/* enum: FPGA version invalid */\n+#define\tMC_CMD_PTP_MANF_FPGA_VERSION 0x2\n+/* enum: FPGA registers incorrect */\n+#define\tMC_CMD_PTP_MANF_FPGA_REGISTERS 0x3\n+/* enum: Oscillator possibly not working? */\n+#define\tMC_CMD_PTP_MANF_OSCILLATOR 0x4\n+/* enum: Timestamps not increasing */\n+#define\tMC_CMD_PTP_MANF_TIMESTAMPS 0x5\n+/* enum: Mismatched packet count */\n+#define\tMC_CMD_PTP_MANF_PACKET_COUNT 0x6\n+/* enum: Mismatched packet count (Siena filter and FPGA) */\n+#define\tMC_CMD_PTP_MANF_FILTER_COUNT 0x7\n+/* enum: Not enough packets to perform timestamp check */\n+#define\tMC_CMD_PTP_MANF_PACKET_ENOUGH 0x8\n+/* enum: Timestamp trigger GPIO not working */\n+#define\tMC_CMD_PTP_MANF_GPIO_TRIGGER 0x9\n+/* enum: Insufficient PPS events to perform checks */\n+#define\tMC_CMD_PTP_MANF_PPS_ENOUGH 0xa\n+/* enum: PPS time event period not sufficiently close to 1s. */\n+#define\tMC_CMD_PTP_MANF_PPS_PERIOD 0xb\n+/* enum: PPS time event nS reading not sufficiently close to zero. */\n+#define\tMC_CMD_PTP_MANF_PPS_NS 0xc\n+/* enum: PTP peripheral registers incorrect */\n+#define\tMC_CMD_PTP_MANF_REGISTERS 0xd\n+/* enum: Failed to read time from PTP peripheral */\n+#define\tMC_CMD_PTP_MANF_CLOCK_READ 0xe\n+/* Presence of external oscillator */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4\n+\n+/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12\n+/* Results of testing */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0\n+/* Number of packets received by FPGA */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4\n+/* Number of packets received by Siena filters */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8\n+\n+/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_LENMIN 1\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_LENMAX 252\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1\n+#define\tMC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252\n+\n+/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */\n+#define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4\n+/* Time format required/used by for this NIC. Applies to all PTP MCDI\n+ * operations that pass times between the host and firmware. If this operation\n+ * is not supported (older firmware) a format of seconds and nanoseconds should\n+ * be assumed.\n+ */\n+#define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0\n+/* enum: Times are in seconds and nanoseconds */\n+#define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0\n+/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */\n+#define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1\n+/* enum: Major register has units of seconds, minor 2^-27s per tick */\n+#define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2\n+\n+/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24\n+/* Time format required/used by for this NIC. Applies to all PTP MCDI\n+ * operations that pass times between the host and firmware. If this operation\n+ * is not supported (older firmware) a format of seconds and nanoseconds should\n+ * be assumed.\n+ */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0\n+/* enum: Times are in seconds and nanoseconds */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0\n+/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1\n+/* enum: Major register has units of seconds, minor 2^-27s per tick */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2\n+/* Minimum acceptable value for a corrected synchronization timeset. When\n+ * comparing host and NIC clock times, the MC returns a set of samples that\n+ * contain the host start and end time, the MC time when the host start was\n+ * detected and the time the MC waited between reading the time and detecting\n+ * the host end. The corrected sync window is the difference between the host\n+ * end and start times minus the time that the MC waited for host end.\n+ */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4\n+/* Various PTP capabilities */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20\n+\n+/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16\n+/* Uncorrected error on PTP transmit timestamps in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0\n+/* Uncorrected error on PTP receive timestamps in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4\n+/* Uncorrected error on PPS output in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8\n+/* Uncorrected error on PPS input in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12\n+\n+/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24\n+/* Uncorrected error on PTP transmit timestamps in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0\n+/* Uncorrected error on PTP receive timestamps in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4\n+/* Uncorrected error on PPS output in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8\n+/* Uncorrected error on PPS input in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12\n+/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16\n+/* Uncorrected error on non-PTP receive timestamps in NIC clock format */\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20\n+\n+/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4\n+/* Results of testing */\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */\n+\n+/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */\n+#define\tMC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_CSR_READ32\n+ * Read 32bit words from the indirect memory map.\n+ */\n+#define\tMC_CMD_CSR_READ32 0xc\n+#undef\tMC_CMD_0xc_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_CSR_READ32_IN msgrequest */\n+#define\tMC_CMD_CSR_READ32_IN_LEN 12\n+/* Address */\n+#define\tMC_CMD_CSR_READ32_IN_ADDR_OFST 0\n+#define\tMC_CMD_CSR_READ32_IN_STEP_OFST 4\n+#define\tMC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8\n+\n+/* MC_CMD_CSR_READ32_OUT msgresponse */\n+#define\tMC_CMD_CSR_READ32_OUT_LENMIN 4\n+#define\tMC_CMD_CSR_READ32_OUT_LENMAX 252\n+#define\tMC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))\n+/* The last dword is the status, not a value read */\n+#define\tMC_CMD_CSR_READ32_OUT_BUFFER_OFST 0\n+#define\tMC_CMD_CSR_READ32_OUT_BUFFER_LEN 4\n+#define\tMC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1\n+#define\tMC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63\n+\n+\n+/***********************************/\n+/* MC_CMD_CSR_WRITE32\n+ * Write 32bit dwords to the indirect memory map.\n+ */\n+#define\tMC_CMD_CSR_WRITE32 0xd\n+#undef\tMC_CMD_0xd_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_CSR_WRITE32_IN msgrequest */\n+#define\tMC_CMD_CSR_WRITE32_IN_LENMIN 12\n+#define\tMC_CMD_CSR_WRITE32_IN_LENMAX 252\n+#define\tMC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))\n+/* Address */\n+#define\tMC_CMD_CSR_WRITE32_IN_ADDR_OFST 0\n+#define\tMC_CMD_CSR_WRITE32_IN_STEP_OFST 4\n+#define\tMC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8\n+#define\tMC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4\n+#define\tMC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1\n+#define\tMC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61\n+\n+/* MC_CMD_CSR_WRITE32_OUT msgresponse */\n+#define\tMC_CMD_CSR_WRITE32_OUT_LEN 4\n+#define\tMC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_HP\n+ * These commands are used for HP related features. They are grouped under one\n+ * MCDI command to avoid creating too many MCDI commands.\n+ */\n+#define\tMC_CMD_HP 0x54\n+#undef\tMC_CMD_0x54_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_HP_IN msgrequest */\n+#define\tMC_CMD_HP_IN_LEN 16\n+/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at\n+ * the specified address with the specified interval.When address is NULL,\n+ * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current\n+ * state / 2: (debug) Show temperature reported by one of the supported\n+ * sensors.\n+ */\n+#define\tMC_CMD_HP_IN_SUBCMD_OFST 0\n+/* enum: OCSD (Option Card Sensor Data) sub-command. */\n+#define\tMC_CMD_HP_IN_OCSD_SUBCMD 0x0\n+/* enum: Last known valid HP sub-command. */\n+#define\tMC_CMD_HP_IN_LAST_SUBCMD 0x0\n+/* The address to the array of sensor fields. (Or NULL to use a sub-command.)\n+ */\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_OFST 4\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_LEN 8\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8\n+/* The requested update interval, in seconds. (Or the sub-command if ADDR is\n+ * NULL.)\n+ */\n+#define\tMC_CMD_HP_IN_OCSD_INTERVAL_OFST 12\n+\n+/* MC_CMD_HP_OUT msgresponse */\n+#define\tMC_CMD_HP_OUT_LEN 4\n+#define\tMC_CMD_HP_OUT_OCSD_STATUS_OFST 0\n+/* enum: OCSD stopped for this card. */\n+#define\tMC_CMD_HP_OUT_OCSD_STOPPED 0x1\n+/* enum: OCSD was successfully started with the address provided. */\n+#define\tMC_CMD_HP_OUT_OCSD_STARTED 0x2\n+/* enum: OCSD was already started for this card. */\n+#define\tMC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3\n+\n+\n+/***********************************/\n+/* MC_CMD_STACKINFO\n+ * Get stack information.\n+ */\n+#define\tMC_CMD_STACKINFO 0xf\n+#undef\tMC_CMD_0xf_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_STACKINFO_IN msgrequest */\n+#define\tMC_CMD_STACKINFO_IN_LEN 0\n+\n+/* MC_CMD_STACKINFO_OUT msgresponse */\n+#define\tMC_CMD_STACKINFO_OUT_LENMIN 12\n+#define\tMC_CMD_STACKINFO_OUT_LENMAX 252\n+#define\tMC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))\n+/* (thread ptr, stack size, free space) for each thread in system */\n+#define\tMC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0\n+#define\tMC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12\n+#define\tMC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1\n+#define\tMC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21\n+\n+\n+/***********************************/\n+/* MC_CMD_MDIO_READ\n+ * MDIO register read.\n+ */\n+#define\tMC_CMD_MDIO_READ 0x10\n+#undef\tMC_CMD_0x10_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MDIO_READ_IN msgrequest */\n+#define\tMC_CMD_MDIO_READ_IN_LEN 16\n+/* Bus number; there are two MDIO buses: one for the internal PHY, and one for\n+ * external devices.\n+ */\n+#define\tMC_CMD_MDIO_READ_IN_BUS_OFST 0\n+/* enum: Internal. */\n+#define\tMC_CMD_MDIO_BUS_INTERNAL 0x0\n+/* enum: External. */\n+#define\tMC_CMD_MDIO_BUS_EXTERNAL 0x1\n+/* Port address */\n+#define\tMC_CMD_MDIO_READ_IN_PRTAD_OFST 4\n+/* Device Address or clause 22. */\n+#define\tMC_CMD_MDIO_READ_IN_DEVAD_OFST 8\n+/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you\n+ * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.\n+ */\n+#define\tMC_CMD_MDIO_CLAUSE22 0x20\n+/* Address */\n+#define\tMC_CMD_MDIO_READ_IN_ADDR_OFST 12\n+\n+/* MC_CMD_MDIO_READ_OUT msgresponse */\n+#define\tMC_CMD_MDIO_READ_OUT_LEN 8\n+/* Value */\n+#define\tMC_CMD_MDIO_READ_OUT_VALUE_OFST 0\n+/* Status the MDIO commands return the raw status bits from the MDIO block. A\n+ * \"good\" transaction should have the DONE bit set and all other bits clear.\n+ */\n+#define\tMC_CMD_MDIO_READ_OUT_STATUS_OFST 4\n+/* enum: Good. */\n+#define\tMC_CMD_MDIO_STATUS_GOOD 0x8\n+\n+\n+/***********************************/\n+/* MC_CMD_MDIO_WRITE\n+ * MDIO register write.\n+ */\n+#define\tMC_CMD_MDIO_WRITE 0x11\n+#undef\tMC_CMD_0x11_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_MDIO_WRITE_IN msgrequest */\n+#define\tMC_CMD_MDIO_WRITE_IN_LEN 20\n+/* Bus number; there are two MDIO buses: one for the internal PHY, and one for\n+ * external devices.\n+ */\n+#define\tMC_CMD_MDIO_WRITE_IN_BUS_OFST 0\n+/* enum: Internal. */\n+/*               MC_CMD_MDIO_BUS_INTERNAL 0x0 */\n+/* enum: External. */\n+/*               MC_CMD_MDIO_BUS_EXTERNAL 0x1 */\n+/* Port address */\n+#define\tMC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4\n+/* Device Address or clause 22. */\n+#define\tMC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8\n+/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you\n+ * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.\n+ */\n+/*               MC_CMD_MDIO_CLAUSE22 0x20 */\n+/* Address */\n+#define\tMC_CMD_MDIO_WRITE_IN_ADDR_OFST 12\n+/* Value */\n+#define\tMC_CMD_MDIO_WRITE_IN_VALUE_OFST 16\n+\n+/* MC_CMD_MDIO_WRITE_OUT msgresponse */\n+#define\tMC_CMD_MDIO_WRITE_OUT_LEN 4\n+/* Status; the MDIO commands return the raw status bits from the MDIO block. A\n+ * \"good\" transaction should have the DONE bit set and all other bits clear.\n+ */\n+#define\tMC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0\n+/* enum: Good. */\n+/*               MC_CMD_MDIO_STATUS_GOOD 0x8 */\n+\n+\n+/***********************************/\n+/* MC_CMD_DBI_WRITE\n+ * Write DBI register(s).\n+ */\n+#define\tMC_CMD_DBI_WRITE 0x12\n+#undef\tMC_CMD_0x12_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DBI_WRITE_IN msgrequest */\n+#define\tMC_CMD_DBI_WRITE_IN_LENMIN 12\n+#define\tMC_CMD_DBI_WRITE_IN_LENMAX 252\n+#define\tMC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))\n+/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset\n+ * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.\n+ */\n+#define\tMC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0\n+#define\tMC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12\n+#define\tMC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1\n+#define\tMC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21\n+\n+/* MC_CMD_DBI_WRITE_OUT msgresponse */\n+#define\tMC_CMD_DBI_WRITE_OUT_LEN 0\n+\n+/* MC_CMD_DBIWROP_TYPEDEF structuredef */\n+#define\tMC_CMD_DBIWROP_TYPEDEF_LEN 12\n+#define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0\n+#define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0\n+#define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32\n+#define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1\n+#define\tMC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14\n+#define\tMC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1\n+#define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32\n+#define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_PORT_READ32\n+ * Read a 32-bit register from the indirect port register map. The port to\n+ * access is implied by the Shared memory channel used.\n+ */\n+#define\tMC_CMD_PORT_READ32 0x14\n+\n+/* MC_CMD_PORT_READ32_IN msgrequest */\n+#define\tMC_CMD_PORT_READ32_IN_LEN 4\n+/* Address */\n+#define\tMC_CMD_PORT_READ32_IN_ADDR_OFST 0\n+\n+/* MC_CMD_PORT_READ32_OUT msgresponse */\n+#define\tMC_CMD_PORT_READ32_OUT_LEN 8\n+/* Value */\n+#define\tMC_CMD_PORT_READ32_OUT_VALUE_OFST 0\n+/* Status */\n+#define\tMC_CMD_PORT_READ32_OUT_STATUS_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_PORT_WRITE32\n+ * Write a 32-bit register to the indirect port register map. The port to\n+ * access is implied by the Shared memory channel used.\n+ */\n+#define\tMC_CMD_PORT_WRITE32 0x15\n+\n+/* MC_CMD_PORT_WRITE32_IN msgrequest */\n+#define\tMC_CMD_PORT_WRITE32_IN_LEN 8\n+/* Address */\n+#define\tMC_CMD_PORT_WRITE32_IN_ADDR_OFST 0\n+/* Value */\n+#define\tMC_CMD_PORT_WRITE32_IN_VALUE_OFST 4\n+\n+/* MC_CMD_PORT_WRITE32_OUT msgresponse */\n+#define\tMC_CMD_PORT_WRITE32_OUT_LEN 4\n+/* Status */\n+#define\tMC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PORT_READ128\n+ * Read a 128-bit register from the indirect port register map. The port to\n+ * access is implied by the Shared memory channel used.\n+ */\n+#define\tMC_CMD_PORT_READ128 0x16\n+\n+/* MC_CMD_PORT_READ128_IN msgrequest */\n+#define\tMC_CMD_PORT_READ128_IN_LEN 4\n+/* Address */\n+#define\tMC_CMD_PORT_READ128_IN_ADDR_OFST 0\n+\n+/* MC_CMD_PORT_READ128_OUT msgresponse */\n+#define\tMC_CMD_PORT_READ128_OUT_LEN 20\n+/* Value */\n+#define\tMC_CMD_PORT_READ128_OUT_VALUE_OFST 0\n+#define\tMC_CMD_PORT_READ128_OUT_VALUE_LEN 16\n+/* Status */\n+#define\tMC_CMD_PORT_READ128_OUT_STATUS_OFST 16\n+\n+\n+/***********************************/\n+/* MC_CMD_PORT_WRITE128\n+ * Write a 128-bit register to the indirect port register map. The port to\n+ * access is implied by the Shared memory channel used.\n+ */\n+#define\tMC_CMD_PORT_WRITE128 0x17\n+\n+/* MC_CMD_PORT_WRITE128_IN msgrequest */\n+#define\tMC_CMD_PORT_WRITE128_IN_LEN 20\n+/* Address */\n+#define\tMC_CMD_PORT_WRITE128_IN_ADDR_OFST 0\n+/* Value */\n+#define\tMC_CMD_PORT_WRITE128_IN_VALUE_OFST 4\n+#define\tMC_CMD_PORT_WRITE128_IN_VALUE_LEN 16\n+\n+/* MC_CMD_PORT_WRITE128_OUT msgresponse */\n+#define\tMC_CMD_PORT_WRITE128_OUT_LEN 4\n+/* Status */\n+#define\tMC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0\n+\n+/* MC_CMD_CAPABILITIES structuredef */\n+#define\tMC_CMD_CAPABILITIES_LEN 4\n+/* Small buf table. */\n+#define\tMC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0\n+#define\tMC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1\n+/* Turbo mode (for Maranello). */\n+#define\tMC_CMD_CAPABILITIES_TURBO_LBN 1\n+#define\tMC_CMD_CAPABILITIES_TURBO_WIDTH 1\n+/* Turbo mode active (for Maranello). */\n+#define\tMC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2\n+#define\tMC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1\n+/* PTP offload. */\n+#define\tMC_CMD_CAPABILITIES_PTP_LBN 3\n+#define\tMC_CMD_CAPABILITIES_PTP_WIDTH 1\n+/* AOE mode. */\n+#define\tMC_CMD_CAPABILITIES_AOE_LBN 4\n+#define\tMC_CMD_CAPABILITIES_AOE_WIDTH 1\n+/* AOE mode active. */\n+#define\tMC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5\n+#define\tMC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1\n+/* AOE mode active. */\n+#define\tMC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6\n+#define\tMC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1\n+#define\tMC_CMD_CAPABILITIES_RESERVED_LBN 7\n+#define\tMC_CMD_CAPABILITIES_RESERVED_WIDTH 25\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_BOARD_CFG\n+ * Returns the MC firmware configuration structure.\n+ */\n+#define\tMC_CMD_GET_BOARD_CFG 0x18\n+#undef\tMC_CMD_0x18_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_BOARD_CFG_IN msgrequest */\n+#define\tMC_CMD_GET_BOARD_CFG_IN_LEN 0\n+\n+/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_LENMIN 96\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_LENMAX 136\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32\n+/* See MC_CMD_CAPABILITIES */\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36\n+/* See MC_CMD_CAPABILITIES */\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68\n+/* This field contains a 16-bit value for each of the types of NVRAM area. The\n+ * values are defined in the firmware/mc/platform/.c file for a specific board\n+ * type, but otherwise have no meaning to the MC; they are used by the driver\n+ * to manage selection of appropriate firmware updates.\n+ */\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32\n+\n+\n+/***********************************/\n+/* MC_CMD_DBI_READX\n+ * Read DBI register(s) -- extended functionality\n+ */\n+#define\tMC_CMD_DBI_READX 0x19\n+#undef\tMC_CMD_0x19_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DBI_READX_IN msgrequest */\n+#define\tMC_CMD_DBI_READX_IN_LENMIN 8\n+#define\tMC_CMD_DBI_READX_IN_LENMAX 248\n+#define\tMC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))\n+/* Each Read op consists of an address (offset 0), VF/CS2) */\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_OFST 0\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_LEN 8\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31\n+\n+/* MC_CMD_DBI_READX_OUT msgresponse */\n+#define\tMC_CMD_DBI_READX_OUT_LENMIN 4\n+#define\tMC_CMD_DBI_READX_OUT_LENMAX 252\n+#define\tMC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))\n+/* Value */\n+#define\tMC_CMD_DBI_READX_OUT_VALUE_OFST 0\n+#define\tMC_CMD_DBI_READX_OUT_VALUE_LEN 4\n+#define\tMC_CMD_DBI_READX_OUT_VALUE_MINNUM 1\n+#define\tMC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63\n+\n+/* MC_CMD_DBIRDOP_TYPEDEF structuredef */\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_LEN 8\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_RAND_SEED\n+ * Set the 16byte seed for the MC pseudo-random generator.\n+ */\n+#define\tMC_CMD_SET_RAND_SEED 0x1a\n+#undef\tMC_CMD_0x1a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_RAND_SEED_IN msgrequest */\n+#define\tMC_CMD_SET_RAND_SEED_IN_LEN 16\n+/* Seed value. */\n+#define\tMC_CMD_SET_RAND_SEED_IN_SEED_OFST 0\n+#define\tMC_CMD_SET_RAND_SEED_IN_SEED_LEN 16\n+\n+/* MC_CMD_SET_RAND_SEED_OUT msgresponse */\n+#define\tMC_CMD_SET_RAND_SEED_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LTSSM_HIST\n+ * Retrieve the history of the LTSSM, if the build supports it.\n+ */\n+#define\tMC_CMD_LTSSM_HIST 0x1b\n+\n+/* MC_CMD_LTSSM_HIST_IN msgrequest */\n+#define\tMC_CMD_LTSSM_HIST_IN_LEN 0\n+\n+/* MC_CMD_LTSSM_HIST_OUT msgresponse */\n+#define\tMC_CMD_LTSSM_HIST_OUT_LENMIN 0\n+#define\tMC_CMD_LTSSM_HIST_OUT_LENMAX 252\n+#define\tMC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))\n+/* variable number of LTSSM values, as bytes. The history is read-to-clear. */\n+#define\tMC_CMD_LTSSM_HIST_OUT_DATA_OFST 0\n+#define\tMC_CMD_LTSSM_HIST_OUT_DATA_LEN 4\n+#define\tMC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63\n+\n+\n+/***********************************/\n+/* MC_CMD_DRV_ATTACH\n+ * Inform MCPU that this port is managed on the host (i.e. driver active). For\n+ * Huntington, also request the preferred datapath firmware to use if possible\n+ * (it may not be possible for this request to be fulfilled; the driver must\n+ * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which\n+ * features are actually available). The FIRMWARE_ID field is ignored by older\n+ * platforms.\n+ */\n+#define\tMC_CMD_DRV_ATTACH 0x1c\n+#undef\tMC_CMD_0x1c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_DRV_ATTACH_IN msgrequest */\n+#define\tMC_CMD_DRV_ATTACH_IN_LEN 12\n+/* new state to set if UPDATE=1 */\n+#define\tMC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0\n+#define\tMC_CMD_DRV_ATTACH_LBN 0\n+#define\tMC_CMD_DRV_ATTACH_WIDTH 1\n+#define\tMC_CMD_DRV_PREBOOT_LBN 1\n+#define\tMC_CMD_DRV_PREBOOT_WIDTH 1\n+/* 1 to set new state, or 0 to just report the existing state */\n+#define\tMC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4\n+/* preferred datapath firmware (for Huntington; ignored for Siena) */\n+#define\tMC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8\n+/* enum: Prefer to use full featured firmware */\n+#define\tMC_CMD_FW_FULL_FEATURED 0x0\n+/* enum: Prefer to use firmware with fewer features but lower latency */\n+#define\tMC_CMD_FW_LOW_LATENCY 0x1\n+/* enum: Prefer to use firmware for SolarCapture packed stream mode */\n+#define\tMC_CMD_FW_PACKED_STREAM 0x2\n+/* enum: Prefer to use firmware with fewer features and simpler TX event\n+ * batching but higher TX packet rate\n+ */\n+#define\tMC_CMD_FW_HIGH_TX_RATE 0x3\n+/* enum: Reserved value */\n+#define\tMC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4\n+/* enum: Prefer to use firmware with additional \"rules engine\" filtering\n+ * support\n+ */\n+#define\tMC_CMD_FW_RULES_ENGINE 0x5\n+/* enum: Only this option is allowed for non-admin functions */\n+#define\tMC_CMD_FW_DONT_CARE  0xffffffff\n+\n+/* MC_CMD_DRV_ATTACH_OUT msgresponse */\n+#define\tMC_CMD_DRV_ATTACH_OUT_LEN 4\n+/* previous or existing state, see the bitmask at NEW_STATE */\n+#define\tMC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0\n+\n+/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_LEN 8\n+/* previous or existing state, see the bitmask at NEW_STATE */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0\n+/* Flags associated with this function */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4\n+/* enum: Labels the lowest-numbered function visible to the OS */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0\n+/* enum: The function can control the link state of the physical port it is\n+ * bound to.\n+ */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1\n+/* enum: The function can perform privileged operations */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2\n+/* enum: The function does not have an active port associated with it. The port\n+ * refers to the Sorrento external FPGA port.\n+ */\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3\n+\n+\n+/***********************************/\n+/* MC_CMD_SHMUART\n+ * Route UART output to circular buffer in shared memory instead.\n+ */\n+#define\tMC_CMD_SHMUART 0x1f\n+\n+/* MC_CMD_SHMUART_IN msgrequest */\n+#define\tMC_CMD_SHMUART_IN_LEN 4\n+/* ??? */\n+#define\tMC_CMD_SHMUART_IN_FLAG_OFST 0\n+\n+/* MC_CMD_SHMUART_OUT msgresponse */\n+#define\tMC_CMD_SHMUART_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PORT_RESET\n+ * Generic per-port reset. There is no equivalent for per-board reset. Locks\n+ * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -\n+ * use MC_CMD_ENTITY_RESET instead.\n+ */\n+#define\tMC_CMD_PORT_RESET 0x20\n+#undef\tMC_CMD_0x20_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_PORT_RESET_IN msgrequest */\n+#define\tMC_CMD_PORT_RESET_IN_LEN 0\n+\n+/* MC_CMD_PORT_RESET_OUT msgresponse */\n+#define\tMC_CMD_PORT_RESET_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_ENTITY_RESET\n+ * Generic per-resource reset. There is no equivalent for per-board reset.\n+ * Locks required: None; Return code: 0, ETIME. NOTE: This command is an\n+ * extended version of the deprecated MC_CMD_PORT_RESET with added fields.\n+ */\n+#define\tMC_CMD_ENTITY_RESET 0x20\n+/*      MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */\n+\n+/* MC_CMD_ENTITY_RESET_IN msgrequest */\n+#define\tMC_CMD_ENTITY_RESET_IN_LEN 4\n+/* Optional flags field. Omitting this will perform a \"legacy\" reset action\n+ * (TBD).\n+ */\n+#define\tMC_CMD_ENTITY_RESET_IN_FLAG_OFST 0\n+#define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0\n+#define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1\n+\n+/* MC_CMD_ENTITY_RESET_OUT msgresponse */\n+#define\tMC_CMD_ENTITY_RESET_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PCIE_CREDITS\n+ * Read instantaneous and minimum flow control thresholds.\n+ */\n+#define\tMC_CMD_PCIE_CREDITS 0x21\n+\n+/* MC_CMD_PCIE_CREDITS_IN msgrequest */\n+#define\tMC_CMD_PCIE_CREDITS_IN_LEN 8\n+/* poll period. 0 is disabled */\n+#define\tMC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0\n+/* wipe statistics */\n+#define\tMC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4\n+\n+/* MC_CMD_PCIE_CREDITS_OUT msgresponse */\n+#define\tMC_CMD_PCIE_CREDITS_OUT_LEN 16\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6\n+#define\tMC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14\n+#define\tMC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2\n+\n+\n+/***********************************/\n+/* MC_CMD_RXD_MONITOR\n+ * Get histogram of RX queue fill level.\n+ */\n+#define\tMC_CMD_RXD_MONITOR 0x22\n+\n+/* MC_CMD_RXD_MONITOR_IN msgrequest */\n+#define\tMC_CMD_RXD_MONITOR_IN_LEN 12\n+#define\tMC_CMD_RXD_MONITOR_IN_QID_OFST 0\n+#define\tMC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4\n+#define\tMC_CMD_RXD_MONITOR_IN_WIPE_OFST 8\n+\n+/* MC_CMD_RXD_MONITOR_OUT msgresponse */\n+#define\tMC_CMD_RXD_MONITOR_OUT_LEN 80\n+#define\tMC_CMD_RXD_MONITOR_OUT_QID_OFST 0\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76\n+\n+\n+/***********************************/\n+/* MC_CMD_PUTS\n+ * Copy the given ASCII string out onto UART and/or out of the network port.\n+ */\n+#define\tMC_CMD_PUTS 0x23\n+#undef\tMC_CMD_0x23_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PUTS_IN msgrequest */\n+#define\tMC_CMD_PUTS_IN_LENMIN 13\n+#define\tMC_CMD_PUTS_IN_LENMAX 252\n+#define\tMC_CMD_PUTS_IN_LEN(num) (12+1*(num))\n+#define\tMC_CMD_PUTS_IN_DEST_OFST 0\n+#define\tMC_CMD_PUTS_IN_UART_LBN 0\n+#define\tMC_CMD_PUTS_IN_UART_WIDTH 1\n+#define\tMC_CMD_PUTS_IN_PORT_LBN 1\n+#define\tMC_CMD_PUTS_IN_PORT_WIDTH 1\n+#define\tMC_CMD_PUTS_IN_DHOST_OFST 4\n+#define\tMC_CMD_PUTS_IN_DHOST_LEN 6\n+#define\tMC_CMD_PUTS_IN_STRING_OFST 12\n+#define\tMC_CMD_PUTS_IN_STRING_LEN 1\n+#define\tMC_CMD_PUTS_IN_STRING_MINNUM 1\n+#define\tMC_CMD_PUTS_IN_STRING_MAXNUM 240\n+\n+/* MC_CMD_PUTS_OUT msgresponse */\n+#define\tMC_CMD_PUTS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PHY_CFG\n+ * Report PHY configuration. This guarantees to succeed even if the PHY is in a\n+ * 'zombie' state. Locks required: None\n+ */\n+#define\tMC_CMD_GET_PHY_CFG 0x24\n+#undef\tMC_CMD_0x24_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PHY_CFG_IN msgrequest */\n+#define\tMC_CMD_GET_PHY_CFG_IN_LEN 0\n+\n+/* MC_CMD_GET_PHY_CFG_OUT msgresponse */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_LEN 72\n+/* flags */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0\n+#define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3\n+#define\tMC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4\n+#define\tMC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5\n+#define\tMC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1\n+/* ?? */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4\n+/* Bitmask of supported capabilities */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8\n+#define\tMC_CMD_PHY_CAP_10HDX_LBN 1\n+#define\tMC_CMD_PHY_CAP_10HDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_10FDX_LBN 2\n+#define\tMC_CMD_PHY_CAP_10FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_100HDX_LBN 3\n+#define\tMC_CMD_PHY_CAP_100HDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_100FDX_LBN 4\n+#define\tMC_CMD_PHY_CAP_100FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_1000HDX_LBN 5\n+#define\tMC_CMD_PHY_CAP_1000HDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_1000FDX_LBN 6\n+#define\tMC_CMD_PHY_CAP_1000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_10000FDX_LBN 7\n+#define\tMC_CMD_PHY_CAP_10000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_PAUSE_LBN 8\n+#define\tMC_CMD_PHY_CAP_PAUSE_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_ASYM_LBN 9\n+#define\tMC_CMD_PHY_CAP_ASYM_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_AN_LBN 10\n+#define\tMC_CMD_PHY_CAP_AN_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_40000FDX_LBN 11\n+#define\tMC_CMD_PHY_CAP_40000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_DDM_LBN 12\n+#define\tMC_CMD_PHY_CAP_DDM_WIDTH 1\n+/* ?? */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12\n+/* ?? */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16\n+/* ?? */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20\n+/* ?? */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24\n+#define\tMC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20\n+/* ?? */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44\n+/* enum: Xaui. */\n+#define\tMC_CMD_MEDIA_XAUI 0x1\n+/* enum: CX4. */\n+#define\tMC_CMD_MEDIA_CX4 0x2\n+/* enum: KX4. */\n+#define\tMC_CMD_MEDIA_KX4 0x3\n+/* enum: XFP Far. */\n+#define\tMC_CMD_MEDIA_XFP 0x4\n+/* enum: SFP+. */\n+#define\tMC_CMD_MEDIA_SFP_PLUS 0x5\n+/* enum: 10GBaseT. */\n+#define\tMC_CMD_MEDIA_BASE_T 0x6\n+/* enum: QSFP+. */\n+#define\tMC_CMD_MEDIA_QSFP_PLUS 0x7\n+#define\tMC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48\n+/* enum: Native clause 22 */\n+#define\tMC_CMD_MMD_CLAUSE22 0x0\n+#define\tMC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */\n+/* enum: Clause22 proxied over clause45 by PHY. */\n+#define\tMC_CMD_MMD_CLAUSE45_C22EXT 0x1d\n+#define\tMC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */\n+#define\tMC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */\n+#define\tMC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52\n+#define\tMC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20\n+\n+\n+/***********************************/\n+/* MC_CMD_START_BIST\n+ * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST\n+ * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)\n+ */\n+#define\tMC_CMD_START_BIST 0x25\n+#undef\tMC_CMD_0x25_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_START_BIST_IN msgrequest */\n+#define\tMC_CMD_START_BIST_IN_LEN 4\n+/* Type of test. */\n+#define\tMC_CMD_START_BIST_IN_TYPE_OFST 0\n+/* enum: Run the PHY's short cable BIST. */\n+#define\tMC_CMD_PHY_BIST_CABLE_SHORT 0x1\n+/* enum: Run the PHY's long cable BIST. */\n+#define\tMC_CMD_PHY_BIST_CABLE_LONG 0x2\n+/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */\n+#define\tMC_CMD_BPX_SERDES_BIST 0x3\n+/* enum: Run the MC loopback tests. */\n+#define\tMC_CMD_MC_LOOPBACK_BIST 0x4\n+/* enum: Run the PHY's standard BIST. */\n+#define\tMC_CMD_PHY_BIST 0x5\n+/* enum: Run MC RAM test. */\n+#define\tMC_CMD_MC_MEM_BIST 0x6\n+/* enum: Run Port RAM test. */\n+#define\tMC_CMD_PORT_MEM_BIST 0x7\n+/* enum: Run register test. */\n+#define\tMC_CMD_REG_BIST 0x8\n+\n+/* MC_CMD_START_BIST_OUT msgresponse */\n+#define\tMC_CMD_START_BIST_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_POLL_BIST\n+ * Poll for BIST completion. Returns a single status code, and optionally some\n+ * PHY specific bist output. The driver should only consume the BIST output\n+ * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't\n+ * successfully parse the BIST output, it should still respect the pass/Fail in\n+ * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,\n+ * EACCES (if PHY_LOCK is not held).\n+ */\n+#define\tMC_CMD_POLL_BIST 0x26\n+#undef\tMC_CMD_0x26_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_POLL_BIST_IN msgrequest */\n+#define\tMC_CMD_POLL_BIST_IN_LEN 0\n+\n+/* MC_CMD_POLL_BIST_OUT msgresponse */\n+#define\tMC_CMD_POLL_BIST_OUT_LEN 8\n+/* result */\n+#define\tMC_CMD_POLL_BIST_OUT_RESULT_OFST 0\n+/* enum: Running. */\n+#define\tMC_CMD_POLL_BIST_RUNNING 0x1\n+/* enum: Passed. */\n+#define\tMC_CMD_POLL_BIST_PASSED 0x2\n+/* enum: Failed. */\n+#define\tMC_CMD_POLL_BIST_FAILED 0x3\n+/* enum: Timed-out. */\n+#define\tMC_CMD_POLL_BIST_TIMEOUT 0x4\n+#define\tMC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4\n+\n+/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_LEN 36\n+/* result */\n+/*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16\n+/* Status of each channel A */\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20\n+/* enum: Ok. */\n+#define\tMC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1\n+/* enum: Open. */\n+#define\tMC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2\n+/* enum: Intra-pair short. */\n+#define\tMC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3\n+/* enum: Inter-pair short. */\n+#define\tMC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4\n+/* enum: Busy. */\n+#define\tMC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9\n+/* Status of each channel B */\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24\n+/*            Enum values, see field(s): */\n+/*               CABLE_STATUS_A */\n+/* Status of each channel C */\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28\n+/*            Enum values, see field(s): */\n+/*               CABLE_STATUS_A */\n+/* Status of each channel D */\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32\n+/*            Enum values, see field(s): */\n+/*               CABLE_STATUS_A */\n+\n+/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */\n+#define\tMC_CMD_POLL_BIST_OUT_MRSFP_LEN 8\n+/* result */\n+/*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */\n+#define\tMC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4\n+/* enum: Complete. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0\n+/* enum: Bus switch off I2C write. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1\n+/* enum: Bus switch off I2C no access IO exp. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2\n+/* enum: Bus switch off I2C no access module. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3\n+/* enum: IO exp I2C configure. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4\n+/* enum: Bus switch I2C no cross talk. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5\n+/* enum: Module presence. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6\n+/* enum: Module ID I2C access. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7\n+/* enum: Module ID sane value. */\n+#define\tMC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8\n+\n+/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_LEN 36\n+/* result */\n+/*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4\n+/* enum: Test has completed. */\n+#define\tMC_CMD_POLL_BIST_MEM_COMPLETE 0x0\n+/* enum: RAM test - walk ones. */\n+#define\tMC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1\n+/* enum: RAM test - walk zeros. */\n+#define\tMC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2\n+/* enum: RAM test - walking inversions zeros/ones. */\n+#define\tMC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3\n+/* enum: RAM test - walking inversions checkerboard. */\n+#define\tMC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4\n+/* enum: Register test - set / clear individual bits. */\n+#define\tMC_CMD_POLL_BIST_MEM_REG 0x5\n+/* enum: ECC error detected. */\n+#define\tMC_CMD_POLL_BIST_MEM_ECC 0x6\n+/* Failure address, only valid if result is POLL_BIST_FAILED */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8\n+/* Bus or address space to which the failure address corresponds */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12\n+/* enum: MC MIPS bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_MC 0x0\n+/* enum: CSR IREG bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_CSR 0x1\n+/* enum: RX0 DPCPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2\n+/* enum: TX0 DPCPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3\n+/* enum: TX1 DPCPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4\n+/* enum: RX0 DICPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5\n+/* enum: TX DICPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6\n+/* enum: RX1 DPCPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7\n+/* enum: RX1 DICPU bus. */\n+#define\tMC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8\n+/* Pattern written to RAM / register */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16\n+/* Actual value read from RAM / register */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20\n+/* ECC error mask */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24\n+/* ECC parity error mask */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28\n+/* ECC fatal error mask */\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32\n+\n+\n+/***********************************/\n+/* MC_CMD_FLUSH_RX_QUEUES\n+ * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ\n+ * flushes should be initiated via this MCDI operation, rather than via\n+ * directly writing FLUSH_CMD.\n+ *\n+ * The flush is completed (either done/fail) asynchronously (after this command\n+ * returns). The driver must still wait for flush done/failure events as usual.\n+ */\n+#define\tMC_CMD_FLUSH_RX_QUEUES 0x27\n+\n+/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1\n+#define\tMC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63\n+\n+/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */\n+#define\tMC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_LOOPBACK_MODES\n+ * Returns a bitmask of loopback modes available at each speed.\n+ */\n+#define\tMC_CMD_GET_LOOPBACK_MODES 0x28\n+#undef\tMC_CMD_0x28_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_IN_LEN 0\n+\n+/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4\n+/* enum: None. */\n+#define\tMC_CMD_LOOPBACK_NONE  0x0\n+/* enum: Data. */\n+#define\tMC_CMD_LOOPBACK_DATA  0x1\n+/* enum: GMAC. */\n+#define\tMC_CMD_LOOPBACK_GMAC  0x2\n+/* enum: XGMII. */\n+#define\tMC_CMD_LOOPBACK_XGMII 0x3\n+/* enum: XGXS. */\n+#define\tMC_CMD_LOOPBACK_XGXS  0x4\n+/* enum: XAUI. */\n+#define\tMC_CMD_LOOPBACK_XAUI  0x5\n+/* enum: GMII. */\n+#define\tMC_CMD_LOOPBACK_GMII  0x6\n+/* enum: SGMII. */\n+#define\tMC_CMD_LOOPBACK_SGMII  0x7\n+/* enum: XGBR. */\n+#define\tMC_CMD_LOOPBACK_XGBR  0x8\n+/* enum: XFI. */\n+#define\tMC_CMD_LOOPBACK_XFI  0x9\n+/* enum: XAUI Far. */\n+#define\tMC_CMD_LOOPBACK_XAUI_FAR  0xa\n+/* enum: GMII Far. */\n+#define\tMC_CMD_LOOPBACK_GMII_FAR  0xb\n+/* enum: SGMII Far. */\n+#define\tMC_CMD_LOOPBACK_SGMII_FAR  0xc\n+/* enum: XFI Far. */\n+#define\tMC_CMD_LOOPBACK_XFI_FAR  0xd\n+/* enum: GPhy. */\n+#define\tMC_CMD_LOOPBACK_GPHY  0xe\n+/* enum: PhyXS. */\n+#define\tMC_CMD_LOOPBACK_PHYXS  0xf\n+/* enum: PCS. */\n+#define\tMC_CMD_LOOPBACK_PCS  0x10\n+/* enum: PMA-PMD. */\n+#define\tMC_CMD_LOOPBACK_PMAPMD  0x11\n+/* enum: Cross-Port. */\n+#define\tMC_CMD_LOOPBACK_XPORT  0x12\n+/* enum: XGMII-Wireside. */\n+#define\tMC_CMD_LOOPBACK_XGMII_WS  0x13\n+/* enum: XAUI Wireside. */\n+#define\tMC_CMD_LOOPBACK_XAUI_WS  0x14\n+/* enum: XAUI Wireside Far. */\n+#define\tMC_CMD_LOOPBACK_XAUI_WS_FAR  0x15\n+/* enum: XAUI Wireside near. */\n+#define\tMC_CMD_LOOPBACK_XAUI_WS_NEAR  0x16\n+/* enum: GMII Wireside. */\n+#define\tMC_CMD_LOOPBACK_GMII_WS  0x17\n+/* enum: XFI Wireside. */\n+#define\tMC_CMD_LOOPBACK_XFI_WS  0x18\n+/* enum: XFI Wireside Far. */\n+#define\tMC_CMD_LOOPBACK_XFI_WS_FAR  0x19\n+/* enum: PhyXS Wireside. */\n+#define\tMC_CMD_LOOPBACK_PHYXS_WS  0x1a\n+/* enum: PMA lanes MAC-Serdes. */\n+#define\tMC_CMD_LOOPBACK_PMA_INT  0x1b\n+/* enum: KR Serdes Parallel (Encoder). */\n+#define\tMC_CMD_LOOPBACK_SD_NEAR  0x1c\n+/* enum: KR Serdes Serial. */\n+#define\tMC_CMD_LOOPBACK_SD_FAR  0x1d\n+/* enum: PMA lanes MAC-Serdes Wireside. */\n+#define\tMC_CMD_LOOPBACK_PMA_INT_WS  0x1e\n+/* enum: KR Serdes Parallel Wireside (Full PCS). */\n+#define\tMC_CMD_LOOPBACK_SD_FEP2_WS  0x1f\n+/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */\n+#define\tMC_CMD_LOOPBACK_SD_FEP1_5_WS  0x20\n+/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */\n+#define\tMC_CMD_LOOPBACK_SD_FEP_WS  0x21\n+/* enum: KR Serdes Serial Wireside. */\n+#define\tMC_CMD_LOOPBACK_SD_FES_WS  0x22\n+/* enum: Near side of AOE Siena side port */\n+#define\tMC_CMD_LOOPBACK_AOE_INT_NEAR  0x23\n+/* enum: Medford Wireside datapath loopback */\n+#define\tMC_CMD_LOOPBACK_DATA_WS  0x24\n+/* enum: Force link up without setting up any physical loopback (snapper use\n+ * only)\n+ */\n+#define\tMC_CMD_LOOPBACK_FORCE_EXT_LINK  0x25\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36\n+/*            Enum values, see field(s): */\n+/*               100M */\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_LINK\n+ * Read the unified MAC/PHY link state. Locks required: None Return code: 0,\n+ * ETIME.\n+ */\n+#define\tMC_CMD_GET_LINK 0x29\n+#undef\tMC_CMD_0x29_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_LINK_IN msgrequest */\n+#define\tMC_CMD_GET_LINK_IN_LEN 0\n+\n+/* MC_CMD_GET_LINK_OUT msgresponse */\n+#define\tMC_CMD_GET_LINK_OUT_LEN 28\n+/* near-side advertised capabilities */\n+#define\tMC_CMD_GET_LINK_OUT_CAP_OFST 0\n+/* link-partner advertised capabilities */\n+#define\tMC_CMD_GET_LINK_OUT_LP_CAP_OFST 4\n+/* Autonegotiated speed in mbit/s. The link may still be down even if this\n+ * reads non-zero.\n+ */\n+#define\tMC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8\n+/* Current loopback setting. */\n+#define\tMC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n+#define\tMC_CMD_GET_LINK_OUT_FLAGS_OFST 16\n+#define\tMC_CMD_GET_LINK_OUT_LINK_UP_LBN 0\n+#define\tMC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1\n+#define\tMC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2\n+#define\tMC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3\n+#define\tMC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6\n+#define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7\n+#define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1\n+/* This returns the negotiated flow control value. */\n+#define\tMC_CMD_GET_LINK_OUT_FCNTL_OFST 20\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */\n+#define\tMC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24\n+#define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0\n+#define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1\n+#define\tMC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1\n+#define\tMC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1\n+#define\tMC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2\n+#define\tMC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1\n+#define\tMC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3\n+#define\tMC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_LINK\n+ * Write the unified MAC/PHY link configuration. Locks required: None. Return\n+ * code: 0, EINVAL, ETIME\n+ */\n+#define\tMC_CMD_SET_LINK 0x2a\n+#undef\tMC_CMD_0x2a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_SET_LINK_IN msgrequest */\n+#define\tMC_CMD_SET_LINK_IN_LEN 16\n+/* ??? */\n+#define\tMC_CMD_SET_LINK_IN_CAP_OFST 0\n+/* Flags */\n+#define\tMC_CMD_SET_LINK_IN_FLAGS_OFST 4\n+#define\tMC_CMD_SET_LINK_IN_LOWPOWER_LBN 0\n+#define\tMC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_POWEROFF_LBN 1\n+#define\tMC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_TXDIS_LBN 2\n+#define\tMC_CMD_SET_LINK_IN_TXDIS_WIDTH 1\n+/* Loopback mode. */\n+#define\tMC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n+/* A loopback speed of \"0\" is supported, and means (choose any available\n+ * speed).\n+ */\n+#define\tMC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12\n+\n+/* MC_CMD_SET_LINK_OUT msgresponse */\n+#define\tMC_CMD_SET_LINK_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_ID_LED\n+ * Set identification LED state. Locks required: None. Return code: 0, EINVAL\n+ */\n+#define\tMC_CMD_SET_ID_LED 0x2b\n+#undef\tMC_CMD_0x2b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_SET_ID_LED_IN msgrequest */\n+#define\tMC_CMD_SET_ID_LED_IN_LEN 4\n+/* Set LED state. */\n+#define\tMC_CMD_SET_ID_LED_IN_STATE_OFST 0\n+#define\tMC_CMD_LED_OFF  0x0 /* enum */\n+#define\tMC_CMD_LED_ON  0x1 /* enum */\n+#define\tMC_CMD_LED_DEFAULT  0x2 /* enum */\n+\n+/* MC_CMD_SET_ID_LED_OUT msgresponse */\n+#define\tMC_CMD_SET_ID_LED_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_MAC\n+ * Set MAC configuration. Locks required: None. Return code: 0, EINVAL\n+ */\n+#define\tMC_CMD_SET_MAC 0x2c\n+#undef\tMC_CMD_0x2c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_MAC_IN msgrequest */\n+#define\tMC_CMD_SET_MAC_IN_LEN 28\n+/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of\n+ * EtherII, VLAN, bug16011 padding).\n+ */\n+#define\tMC_CMD_SET_MAC_IN_MTU_OFST 0\n+#define\tMC_CMD_SET_MAC_IN_DRAIN_OFST 4\n+#define\tMC_CMD_SET_MAC_IN_ADDR_OFST 8\n+#define\tMC_CMD_SET_MAC_IN_ADDR_LEN 8\n+#define\tMC_CMD_SET_MAC_IN_ADDR_LO_OFST 8\n+#define\tMC_CMD_SET_MAC_IN_ADDR_HI_OFST 12\n+#define\tMC_CMD_SET_MAC_IN_REJECT_OFST 16\n+#define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0\n+#define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1\n+#define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_IN_FCNTL_OFST 20\n+/* enum: Flow control is off. */\n+#define\tMC_CMD_FCNTL_OFF 0x0\n+/* enum: Respond to flow control. */\n+#define\tMC_CMD_FCNTL_RESPOND 0x1\n+/* enum: Respond to and Issue flow control. */\n+#define\tMC_CMD_FCNTL_BIDIR 0x2\n+/* enum: Auto neg flow control. */\n+#define\tMC_CMD_FCNTL_AUTO 0x3\n+/* enum: Priority flow control (eftest builds only). */\n+#define\tMC_CMD_FCNTL_QBB 0x4\n+/* enum: Issue flow control. */\n+#define\tMC_CMD_FCNTL_GENERATE 0x5\n+#define\tMC_CMD_SET_MAC_IN_FLAGS_OFST 24\n+#define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0\n+#define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1\n+\n+/* MC_CMD_SET_MAC_EXT_IN msgrequest */\n+#define\tMC_CMD_SET_MAC_EXT_IN_LEN 32\n+/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of\n+ * EtherII, VLAN, bug16011 padding).\n+ */\n+#define\tMC_CMD_SET_MAC_EXT_IN_MTU_OFST 0\n+#define\tMC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20\n+/* enum: Flow control is off. */\n+/*               MC_CMD_FCNTL_OFF 0x0 */\n+/* enum: Respond to flow control. */\n+/*               MC_CMD_FCNTL_RESPOND 0x1 */\n+/* enum: Respond to and Issue flow control. */\n+/*               MC_CMD_FCNTL_BIDIR 0x2 */\n+/* enum: Auto neg flow control. */\n+/*               MC_CMD_FCNTL_AUTO 0x3 */\n+/* enum: Priority flow control (eftest builds only). */\n+/*               MC_CMD_FCNTL_QBB 0x4 */\n+/* enum: Issue flow control. */\n+/*               MC_CMD_FCNTL_GENERATE 0x5 */\n+#define\tMC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24\n+#define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0\n+#define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1\n+/* Select which parameters to configure. A parameter will only be modified if\n+ * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in\n+ * capabilities then this field is ignored (and all flags are assumed to be\n+ * set).\n+ */\n+#define\tMC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1\n+\n+/* MC_CMD_SET_MAC_OUT msgresponse */\n+#define\tMC_CMD_SET_MAC_OUT_LEN 0\n+\n+/* MC_CMD_SET_MAC_V2_OUT msgresponse */\n+#define\tMC_CMD_SET_MAC_V2_OUT_LEN 4\n+/* MTU as configured after processing the request. See comment at\n+ * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL\n+ * to 0.\n+ */\n+#define\tMC_CMD_SET_MAC_V2_OUT_MTU_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PHY_STATS\n+ * Get generic PHY statistics. This call returns the statistics for a generic\n+ * PHY in a sparse array (indexed by the enumerate). Each value is represented\n+ * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the\n+ * statistics may be read from the message response. If DMA_ADDR != 0, then the\n+ * statistics are dmad to that (page-aligned location). Locks required: None.\n+ * Returns: 0, ETIME\n+ */\n+#define\tMC_CMD_PHY_STATS 0x2d\n+#undef\tMC_CMD_0x2d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_PHY_STATS_IN msgrequest */\n+#define\tMC_CMD_PHY_STATS_IN_LEN 8\n+/* ??? */\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4\n+\n+/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */\n+#define\tMC_CMD_PHY_STATS_OUT_DMA_LEN 0\n+\n+/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */\n+#define\tMC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)\n+#define\tMC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0\n+#define\tMC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4\n+#define\tMC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS\n+/* enum: OUI. */\n+#define\tMC_CMD_OUI  0x0\n+/* enum: PMA-PMD Link Up. */\n+#define\tMC_CMD_PMA_PMD_LINK_UP  0x1\n+/* enum: PMA-PMD RX Fault. */\n+#define\tMC_CMD_PMA_PMD_RX_FAULT  0x2\n+/* enum: PMA-PMD TX Fault. */\n+#define\tMC_CMD_PMA_PMD_TX_FAULT  0x3\n+/* enum: PMA-PMD Signal */\n+#define\tMC_CMD_PMA_PMD_SIGNAL  0x4\n+/* enum: PMA-PMD SNR A. */\n+#define\tMC_CMD_PMA_PMD_SNR_A  0x5\n+/* enum: PMA-PMD SNR B. */\n+#define\tMC_CMD_PMA_PMD_SNR_B  0x6\n+/* enum: PMA-PMD SNR C. */\n+#define\tMC_CMD_PMA_PMD_SNR_C  0x7\n+/* enum: PMA-PMD SNR D. */\n+#define\tMC_CMD_PMA_PMD_SNR_D  0x8\n+/* enum: PCS Link Up. */\n+#define\tMC_CMD_PCS_LINK_UP  0x9\n+/* enum: PCS RX Fault. */\n+#define\tMC_CMD_PCS_RX_FAULT  0xa\n+/* enum: PCS TX Fault. */\n+#define\tMC_CMD_PCS_TX_FAULT  0xb\n+/* enum: PCS BER. */\n+#define\tMC_CMD_PCS_BER  0xc\n+/* enum: PCS Block Errors. */\n+#define\tMC_CMD_PCS_BLOCK_ERRORS  0xd\n+/* enum: PhyXS Link Up. */\n+#define\tMC_CMD_PHYXS_LINK_UP  0xe\n+/* enum: PhyXS RX Fault. */\n+#define\tMC_CMD_PHYXS_RX_FAULT  0xf\n+/* enum: PhyXS TX Fault. */\n+#define\tMC_CMD_PHYXS_TX_FAULT  0x10\n+/* enum: PhyXS Align. */\n+#define\tMC_CMD_PHYXS_ALIGN  0x11\n+/* enum: PhyXS Sync. */\n+#define\tMC_CMD_PHYXS_SYNC  0x12\n+/* enum: AN link-up. */\n+#define\tMC_CMD_AN_LINK_UP  0x13\n+/* enum: AN Complete. */\n+#define\tMC_CMD_AN_COMPLETE  0x14\n+/* enum: AN 10GBaseT Status. */\n+#define\tMC_CMD_AN_10GBT_STATUS  0x15\n+/* enum: Clause 22 Link-Up. */\n+#define\tMC_CMD_CL22_LINK_UP  0x16\n+/* enum: (Last entry) */\n+#define\tMC_CMD_PHY_NSTATS  0x17\n+\n+\n+/***********************************/\n+/* MC_CMD_MAC_STATS\n+ * Get generic MAC statistics. This call returns unified statistics maintained\n+ * by the MC as it switches between the GMAC and XMAC. The MC will write out\n+ * all supported stats. The driver should zero initialise the buffer to\n+ * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is\n+ * performed, and the statistics may be read from the message response. If\n+ * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).\n+ * Locks required: None. The PERIODIC_CLEAR option is not used and now has no\n+ * effect. Returns: 0, ETIME\n+ */\n+#define\tMC_CMD_MAC_STATS 0x2e\n+#undef\tMC_CMD_0x2e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAC_STATS_IN msgrequest */\n+#define\tMC_CMD_MAC_STATS_IN_LEN 20\n+/* ??? */\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_IN_CMD_OFST 8\n+#define\tMC_CMD_MAC_STATS_IN_DMA_LBN 0\n+#define\tMC_CMD_MAC_STATS_IN_DMA_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_CLEAR_LBN 1\n+#define\tMC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16\n+#define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16\n+#define\tMC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12\n+/* port id so vadapter stats can be provided */\n+#define\tMC_CMD_MAC_STATS_IN_PORT_ID_OFST 16\n+\n+/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */\n+#define\tMC_CMD_MAC_STATS_OUT_DMA_LEN 0\n+\n+/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS\n+#define\tMC_CMD_MAC_GENERATION_START  0x0 /* enum */\n+#define\tMC_CMD_MAC_DMABUF_START  0x1 /* enum */\n+#define\tMC_CMD_MAC_TX_PKTS  0x1 /* enum */\n+#define\tMC_CMD_MAC_TX_PAUSE_PKTS  0x2 /* enum */\n+#define\tMC_CMD_MAC_TX_CONTROL_PKTS  0x3 /* enum */\n+#define\tMC_CMD_MAC_TX_UNICAST_PKTS  0x4 /* enum */\n+#define\tMC_CMD_MAC_TX_MULTICAST_PKTS  0x5 /* enum */\n+#define\tMC_CMD_MAC_TX_BROADCAST_PKTS  0x6 /* enum */\n+#define\tMC_CMD_MAC_TX_BYTES  0x7 /* enum */\n+#define\tMC_CMD_MAC_TX_BAD_BYTES  0x8 /* enum */\n+#define\tMC_CMD_MAC_TX_LT64_PKTS  0x9 /* enum */\n+#define\tMC_CMD_MAC_TX_64_PKTS  0xa /* enum */\n+#define\tMC_CMD_MAC_TX_65_TO_127_PKTS  0xb /* enum */\n+#define\tMC_CMD_MAC_TX_128_TO_255_PKTS  0xc /* enum */\n+#define\tMC_CMD_MAC_TX_256_TO_511_PKTS  0xd /* enum */\n+#define\tMC_CMD_MAC_TX_512_TO_1023_PKTS  0xe /* enum */\n+#define\tMC_CMD_MAC_TX_1024_TO_15XX_PKTS  0xf /* enum */\n+#define\tMC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS  0x10 /* enum */\n+#define\tMC_CMD_MAC_TX_GTJUMBO_PKTS  0x11 /* enum */\n+#define\tMC_CMD_MAC_TX_BAD_FCS_PKTS  0x12 /* enum */\n+#define\tMC_CMD_MAC_TX_SINGLE_COLLISION_PKTS  0x13 /* enum */\n+#define\tMC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS  0x14 /* enum */\n+#define\tMC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS  0x15 /* enum */\n+#define\tMC_CMD_MAC_TX_LATE_COLLISION_PKTS  0x16 /* enum */\n+#define\tMC_CMD_MAC_TX_DEFERRED_PKTS  0x17 /* enum */\n+#define\tMC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS  0x18 /* enum */\n+#define\tMC_CMD_MAC_TX_NON_TCPUDP_PKTS  0x19 /* enum */\n+#define\tMC_CMD_MAC_TX_MAC_SRC_ERR_PKTS  0x1a /* enum */\n+#define\tMC_CMD_MAC_TX_IP_SRC_ERR_PKTS  0x1b /* enum */\n+#define\tMC_CMD_MAC_RX_PKTS  0x1c /* enum */\n+#define\tMC_CMD_MAC_RX_PAUSE_PKTS  0x1d /* enum */\n+#define\tMC_CMD_MAC_RX_GOOD_PKTS  0x1e /* enum */\n+#define\tMC_CMD_MAC_RX_CONTROL_PKTS  0x1f /* enum */\n+#define\tMC_CMD_MAC_RX_UNICAST_PKTS  0x20 /* enum */\n+#define\tMC_CMD_MAC_RX_MULTICAST_PKTS  0x21 /* enum */\n+#define\tMC_CMD_MAC_RX_BROADCAST_PKTS  0x22 /* enum */\n+#define\tMC_CMD_MAC_RX_BYTES  0x23 /* enum */\n+#define\tMC_CMD_MAC_RX_BAD_BYTES  0x24 /* enum */\n+#define\tMC_CMD_MAC_RX_64_PKTS  0x25 /* enum */\n+#define\tMC_CMD_MAC_RX_65_TO_127_PKTS  0x26 /* enum */\n+#define\tMC_CMD_MAC_RX_128_TO_255_PKTS  0x27 /* enum */\n+#define\tMC_CMD_MAC_RX_256_TO_511_PKTS  0x28 /* enum */\n+#define\tMC_CMD_MAC_RX_512_TO_1023_PKTS  0x29 /* enum */\n+#define\tMC_CMD_MAC_RX_1024_TO_15XX_PKTS  0x2a /* enum */\n+#define\tMC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS  0x2b /* enum */\n+#define\tMC_CMD_MAC_RX_GTJUMBO_PKTS  0x2c /* enum */\n+#define\tMC_CMD_MAC_RX_UNDERSIZE_PKTS  0x2d /* enum */\n+#define\tMC_CMD_MAC_RX_BAD_FCS_PKTS  0x2e /* enum */\n+#define\tMC_CMD_MAC_RX_OVERFLOW_PKTS  0x2f /* enum */\n+#define\tMC_CMD_MAC_RX_FALSE_CARRIER_PKTS  0x30 /* enum */\n+#define\tMC_CMD_MAC_RX_SYMBOL_ERROR_PKTS  0x31 /* enum */\n+#define\tMC_CMD_MAC_RX_ALIGN_ERROR_PKTS  0x32 /* enum */\n+#define\tMC_CMD_MAC_RX_LENGTH_ERROR_PKTS  0x33 /* enum */\n+#define\tMC_CMD_MAC_RX_INTERNAL_ERROR_PKTS  0x34 /* enum */\n+#define\tMC_CMD_MAC_RX_JABBER_PKTS  0x35 /* enum */\n+#define\tMC_CMD_MAC_RX_NODESC_DROPS  0x36 /* enum */\n+#define\tMC_CMD_MAC_RX_LANES01_CHAR_ERR  0x37 /* enum */\n+#define\tMC_CMD_MAC_RX_LANES23_CHAR_ERR  0x38 /* enum */\n+#define\tMC_CMD_MAC_RX_LANES01_DISP_ERR  0x39 /* enum */\n+#define\tMC_CMD_MAC_RX_LANES23_DISP_ERR  0x3a /* enum */\n+#define\tMC_CMD_MAC_RX_MATCH_FAULT  0x3b /* enum */\n+/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS\n+ * capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_TRUNC_BB_OVERFLOW  0x3c\n+/* enum: PM discard_bb_overflow counter. Valid for EF10 with\n+ * PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_DISCARD_BB_OVERFLOW  0x3d\n+/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS\n+ * capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_TRUNC_VFIFO_FULL  0x3e\n+/* enum: PM discard_vfifo_full counter. Valid for EF10 with\n+ * PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_DISCARD_VFIFO_FULL  0x3f\n+/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS\n+ * capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_TRUNC_QBB  0x40\n+/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS\n+ * capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_DISCARD_QBB  0x41\n+/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS\n+ * capability only.\n+ */\n+#define\tMC_CMD_MAC_PM_DISCARD_MAPPING  0x42\n+/* enum: RXDP counter: Number of packets dropped due to the queue being\n+ * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_RXDP_Q_DISABLED_PKTS  0x43\n+/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10\n+ * with PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_RXDP_DI_DROPPED_PKTS  0x45\n+/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with\n+ * PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_RXDP_STREAMING_PKTS  0x46\n+/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.\n+ * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS  0x47\n+/* enum: RXDP counter: Number of times the DPCPU waited for an existing\n+ * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.\n+ */\n+#define\tMC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS  0x48\n+#define\tMC_CMD_MAC_VADAPTER_RX_DMABUF_START  0x4c /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS  0x4c /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES  0x4d /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS  0x4e /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES  0x4f /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS  0x50 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES  0x51 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_BAD_PACKETS  0x52 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_BAD_BYTES  0x53 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_RX_OVERFLOW  0x54 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_DMABUF_START  0x57 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS  0x57 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES  0x58 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS  0x59 /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES  0x5a /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS  0x5b /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES  0x5c /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_BAD_PACKETS  0x5d /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_BAD_BYTES  0x5e /* enum */\n+#define\tMC_CMD_MAC_VADAPTER_TX_OVERFLOW  0x5f /* enum */\n+/* enum: Start of GMAC stats buffer space, for Siena only. */\n+#define\tMC_CMD_GMAC_DMABUF_START  0x40\n+/* enum: End of GMAC stats buffer space, for Siena only. */\n+#define\tMC_CMD_GMAC_DMABUF_END    0x5f\n+#define\tMC_CMD_MAC_GENERATION_END 0x60 /* enum */\n+#define\tMC_CMD_MAC_NSTATS  0x61 /* enum */\n+\n+\n+/***********************************/\n+/* MC_CMD_SRIOV\n+ * to be documented\n+ */\n+#define\tMC_CMD_SRIOV 0x30\n+\n+/* MC_CMD_SRIOV_IN msgrequest */\n+#define\tMC_CMD_SRIOV_IN_LEN 12\n+#define\tMC_CMD_SRIOV_IN_ENABLE_OFST 0\n+#define\tMC_CMD_SRIOV_IN_VI_BASE_OFST 4\n+#define\tMC_CMD_SRIOV_IN_VF_COUNT_OFST 8\n+\n+/* MC_CMD_SRIOV_OUT msgresponse */\n+#define\tMC_CMD_SRIOV_OUT_LEN 8\n+#define\tMC_CMD_SRIOV_OUT_VI_SCALE_OFST 0\n+#define\tMC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4\n+\n+/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32\n+/* this is only used for the first record */\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MEMCPY\n+ * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data\n+ * embedded directly in the command.\n+ *\n+ * A common pattern is for a client to use generation counts to signal a dma\n+ * update of a datastructure. To facilitate this, this MCDI operation can\n+ * contain multiple requests which are executed in strict order. Requests take\n+ * the form of duplicating the entire MCDI request continuously (including the\n+ * requests record, which is ignored in all but the first structure)\n+ *\n+ * The source data can either come from a DMA from the host, or it can be\n+ * embedded within the request directly, thereby eliminating a DMA read. To\n+ * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and\n+ * ADDR_LO=offset, and inserts the data at %offset from the start of the\n+ * payload. It's the callers responsibility to ensure that the embedded data\n+ * doesn't overlap the records.\n+ *\n+ * Returns: 0, EINVAL (invalid RID)\n+ */\n+#define\tMC_CMD_MEMCPY 0x31\n+\n+/* MC_CMD_MEMCPY_IN msgrequest */\n+#define\tMC_CMD_MEMCPY_IN_LENMIN 32\n+#define\tMC_CMD_MEMCPY_IN_LENMAX 224\n+#define\tMC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))\n+/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */\n+#define\tMC_CMD_MEMCPY_IN_RECORD_OFST 0\n+#define\tMC_CMD_MEMCPY_IN_RECORD_LEN 32\n+#define\tMC_CMD_MEMCPY_IN_RECORD_MINNUM 1\n+#define\tMC_CMD_MEMCPY_IN_RECORD_MAXNUM 7\n+\n+/* MC_CMD_MEMCPY_OUT msgresponse */\n+#define\tMC_CMD_MEMCPY_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_WOL_FILTER_SET\n+ * Set a WoL filter.\n+ */\n+#define\tMC_CMD_WOL_FILTER_SET 0x32\n+#undef\tMC_CMD_0x32_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_WOL_FILTER_SET_IN msgrequest */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LEN 192\n+#define\tMC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0\n+#define\tMC_CMD_FILTER_MODE_SIMPLE    0x0 /* enum */\n+#define\tMC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */\n+/* A type value of 1 is unused. */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4\n+/* enum: Magic */\n+#define\tMC_CMD_WOL_TYPE_MAGIC      0x0\n+/* enum: MS Windows Magic */\n+#define\tMC_CMD_WOL_TYPE_WIN_MAGIC 0x2\n+/* enum: IPv4 Syn */\n+#define\tMC_CMD_WOL_TYPE_IPV4_SYN   0x3\n+/* enum: IPv6 Syn */\n+#define\tMC_CMD_WOL_TYPE_IPV6_SYN   0x4\n+/* enum: Bitmap */\n+#define\tMC_CMD_WOL_TYPE_BITMAP     0x5\n+/* enum: Link */\n+#define\tMC_CMD_WOL_TYPE_LINK       0x6\n+/* enum: (Above this for future use) */\n+#define\tMC_CMD_WOL_TYPE_MAX        0x7\n+#define\tMC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4\n+#define\tMC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46\n+\n+/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12\n+\n+/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2\n+\n+/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2\n+\n+/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186\n+#define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1\n+\n+/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1\n+\n+/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */\n+#define\tMC_CMD_WOL_FILTER_SET_OUT_LEN 4\n+#define\tMC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_WOL_FILTER_REMOVE\n+ * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS\n+ */\n+#define\tMC_CMD_WOL_FILTER_REMOVE 0x33\n+#undef\tMC_CMD_0x33_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */\n+#define\tMC_CMD_WOL_FILTER_REMOVE_IN_LEN 4\n+#define\tMC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0\n+\n+/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */\n+#define\tMC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_WOL_FILTER_RESET\n+ * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,\n+ * ENOSYS\n+ */\n+#define\tMC_CMD_WOL_FILTER_RESET 0x34\n+#undef\tMC_CMD_0x34_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */\n+#define\tMC_CMD_WOL_FILTER_RESET_IN_LEN 4\n+#define\tMC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0\n+#define\tMC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */\n+#define\tMC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */\n+\n+/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */\n+#define\tMC_CMD_WOL_FILTER_RESET_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_MCAST_HASH\n+ * Set the MCAST hash value without otherwise reconfiguring the MAC\n+ */\n+#define\tMC_CMD_SET_MCAST_HASH 0x35\n+\n+/* MC_CMD_SET_MCAST_HASH_IN msgrequest */\n+#define\tMC_CMD_SET_MCAST_HASH_IN_LEN 32\n+#define\tMC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0\n+#define\tMC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16\n+#define\tMC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16\n+#define\tMC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16\n+\n+/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */\n+#define\tMC_CMD_SET_MCAST_HASH_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_TYPES\n+ * Return bitfield indicating available types of virtual NVRAM partitions.\n+ * Locks required: none. Returns: 0\n+ */\n+#define\tMC_CMD_NVRAM_TYPES 0x36\n+#undef\tMC_CMD_0x36_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_TYPES_IN msgrequest */\n+#define\tMC_CMD_NVRAM_TYPES_IN_LEN 0\n+\n+/* MC_CMD_NVRAM_TYPES_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_TYPES_OUT_LEN 4\n+/* Bit mask of supported types. */\n+#define\tMC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0\n+/* enum: Disabled callisto. */\n+#define\tMC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0\n+/* enum: MC firmware. */\n+#define\tMC_CMD_NVRAM_TYPE_MC_FW 0x1\n+/* enum: MC backup firmware. */\n+#define\tMC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2\n+/* enum: Static configuration Port0. */\n+#define\tMC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3\n+/* enum: Static configuration Port1. */\n+#define\tMC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4\n+/* enum: Dynamic configuration Port0. */\n+#define\tMC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5\n+/* enum: Dynamic configuration Port1. */\n+#define\tMC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6\n+/* enum: Expansion Rom. */\n+#define\tMC_CMD_NVRAM_TYPE_EXP_ROM 0x7\n+/* enum: Expansion Rom Configuration Port0. */\n+#define\tMC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8\n+/* enum: Expansion Rom Configuration Port1. */\n+#define\tMC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9\n+/* enum: Phy Configuration Port0. */\n+#define\tMC_CMD_NVRAM_TYPE_PHY_PORT0 0xa\n+/* enum: Phy Configuration Port1. */\n+#define\tMC_CMD_NVRAM_TYPE_PHY_PORT1 0xb\n+/* enum: Log. */\n+#define\tMC_CMD_NVRAM_TYPE_LOG 0xc\n+/* enum: FPGA image. */\n+#define\tMC_CMD_NVRAM_TYPE_FPGA 0xd\n+/* enum: FPGA backup image */\n+#define\tMC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe\n+/* enum: FC firmware. */\n+#define\tMC_CMD_NVRAM_TYPE_FC_FW 0xf\n+/* enum: FC backup firmware. */\n+#define\tMC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10\n+/* enum: CPLD image. */\n+#define\tMC_CMD_NVRAM_TYPE_CPLD 0x11\n+/* enum: Licensing information. */\n+#define\tMC_CMD_NVRAM_TYPE_LICENSE 0x12\n+/* enum: FC Log. */\n+#define\tMC_CMD_NVRAM_TYPE_FC_LOG 0x13\n+/* enum: Additional flash on FPGA. */\n+#define\tMC_CMD_NVRAM_TYPE_FC_EXTRA 0x14\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_INFO\n+ * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,\n+ * EINVAL (bad type).\n+ */\n+#define\tMC_CMD_NVRAM_INFO 0x37\n+#undef\tMC_CMD_0x37_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_INFO_IN msgrequest */\n+#define\tMC_CMD_NVRAM_INFO_IN_LEN 4\n+#define\tMC_CMD_NVRAM_INFO_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+\n+/* MC_CMD_NVRAM_INFO_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_INFO_OUT_LEN 24\n+#define\tMC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4\n+#define\tMC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8\n+#define\tMC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12\n+#define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0\n+#define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_TLV_LBN 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5\n+#define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6\n+#define\tMC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_A_B_LBN 7\n+#define\tMC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16\n+#define\tMC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20\n+\n+/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_LEN 28\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20\n+/* Writes must be multiples of this size. Added to support the MUM on Sorrento.\n+ */\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_UPDATE_START\n+ * Start a group of update operations on a virtual NVRAM partition. Locks\n+ * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if\n+ * PHY_LOCK required and not held).\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_START 0x38\n+#undef\tMC_CMD_0x38_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.\n+ * Use NVRAM_UPDATE_START_V2_IN in new code\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_START_IN_LEN 4\n+#define\tMC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+\n+/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START\n+ * request with additional flags indicating version of command in use. See\n+ * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use\n+ * paired up with NVRAM_UPDATE_FINISH_V2_IN.\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1\n+\n+/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_UPDATE_START_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_READ\n+ * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if\n+ * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if\n+ * PHY_LOCK required and not held)\n+ */\n+#define\tMC_CMD_NVRAM_READ 0x39\n+#undef\tMC_CMD_0x39_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_READ_IN msgrequest */\n+#define\tMC_CMD_NVRAM_READ_IN_LEN 12\n+#define\tMC_CMD_NVRAM_READ_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_READ_IN_OFFSET_OFST 4\n+/* amount to read in bytes */\n+#define\tMC_CMD_NVRAM_READ_IN_LENGTH_OFST 8\n+\n+/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_LEN 16\n+#define\tMC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4\n+/* amount to read in bytes */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8\n+/* Optional control info. If a partition is stored with an A/B versioning\n+ * scheme (i.e. in more than one physical partition in NVRAM) the host can set\n+ * this to control which underlying physical partition is used to read data\n+ * from. This allows it to perform a read-modify-write-verify with the write\n+ * lock continuously held by calling NVRAM_UPDATE_START, reading the old\n+ * contents using MODE=TARGET_CURRENT, overwriting the old partition and then\n+ * verifying by reading with MODE=TARGET_BACKUP.\n+ */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12\n+/* enum: Same as omitting MODE: caller sees data in current partition unless it\n+ * holds the write lock in which case it sees data in the partition it is\n+ * updating.\n+ */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0\n+/* enum: Read from the current partition of an A/B pair, even if holding the\n+ * write lock.\n+ */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1\n+/* enum: Read from the non-current (i.e. to be updated) partition of an A/B\n+ * pair\n+ */\n+#define\tMC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2\n+\n+/* MC_CMD_NVRAM_READ_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_READ_OUT_LENMIN 1\n+#define\tMC_CMD_NVRAM_READ_OUT_LENMAX 252\n+#define\tMC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))\n+#define\tMC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0\n+#define\tMC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1\n+#define\tMC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1\n+#define\tMC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_WRITE\n+ * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if\n+ * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if\n+ * PHY_LOCK required and not held)\n+ */\n+#define\tMC_CMD_NVRAM_WRITE 0x3a\n+#undef\tMC_CMD_0x3a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_WRITE_IN msgrequest */\n+#define\tMC_CMD_NVRAM_WRITE_IN_LENMIN 13\n+#define\tMC_CMD_NVRAM_WRITE_IN_LENMAX 252\n+#define\tMC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))\n+#define\tMC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4\n+#define\tMC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8\n+#define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12\n+#define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1\n+#define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1\n+#define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240\n+\n+/* MC_CMD_NVRAM_WRITE_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_WRITE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_ERASE\n+ * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if\n+ * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if\n+ * PHY_LOCK required and not held)\n+ */\n+#define\tMC_CMD_NVRAM_ERASE 0x3b\n+#undef\tMC_CMD_0x3b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_ERASE_IN msgrequest */\n+#define\tMC_CMD_NVRAM_ERASE_IN_LEN 12\n+#define\tMC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4\n+#define\tMC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8\n+\n+/* MC_CMD_NVRAM_ERASE_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_ERASE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_UPDATE_FINISH\n+ * Finish a group of update operations on a virtual NVRAM partition. Locks\n+ * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad\n+ * type/offset/length), EACCES (if PHY_LOCK required and not held)\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH 0x3c\n+#undef\tMC_CMD_0x3c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH\n+ * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4\n+\n+/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH\n+ * request with additional flags indicating version of NVRAM_UPDATE commands in\n+ * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended\n+ * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1\n+\n+/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH\n+ * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0\n+\n+/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:\n+ *\n+ * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure\n+ * firmware validation where applicable back to the host.\n+ *\n+ * Medford only: For signed firmware images, such as those for medford, the MC\n+ * firmware verifies the signature before marking the firmware image as valid.\n+ * This process takes a few seconds to complete. So is likely to take more than\n+ * the MCDI timeout. Hence signature verification is initiated when\n+ * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the\n+ * MCDI command is run in a background MCDI processing thread. This response\n+ * payload includes the results of the signature verification. Note that the\n+ * per-partition nvram lock in firmware is only released after the verification\n+ * has completed.\n+ */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4\n+/* Result of nvram update completion processing */\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0\n+/* enum: Invalid return code; only non-zero values are defined. Defined as\n+ * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.\n+ */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0\n+/* enum: Verify succeeded without any errors. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1\n+/* enum: CMS format verification failed due to an internal error. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2\n+/* enum: Invalid CMS format in image metadata. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3\n+/* enum: Message digest verification failed due to an internal error. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4\n+/* enum: Error in message digest calculated over the reflash-header, payload\n+ * and reflash-trailer.\n+ */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5\n+/* enum: Signature verification failed due to an internal error. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6\n+/* enum: There are no valid signatures in the image. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7\n+/* enum: Trusted approvers verification failed due to an internal error. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8\n+/* enum: The Trusted approver's list is empty. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9\n+/* enum: Signature chain verification failed due to an internal error. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa\n+/* enum: The signers of the signatures in the image are not listed in the\n+ * Trusted approver's list.\n+ */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb\n+/* enum: The image contains a test-signed certificate, but the adapter accepts\n+ * only production signed images.\n+ */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc\n+\n+\n+/***********************************/\n+/* MC_CMD_REBOOT\n+ * Reboot the MC.\n+ *\n+ * The AFTER_ASSERTION flag is intended to be used when the driver notices an\n+ * assertion failure (at which point it is expected to perform a complete tear\n+ * down and reinitialise), to allow both ports to reset the MC once in an\n+ * atomic fashion.\n+ *\n+ * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,\n+ * which means that they will automatically reboot out of the assertion\n+ * handler, so this is in practise an optional operation. It is still\n+ * recommended that drivers execute this to support custom firmwares with\n+ * REBOOT_ON_ASSERT=0.\n+ *\n+ * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,\n+ * DATALEN=0\n+ */\n+#define\tMC_CMD_REBOOT 0x3d\n+#undef\tMC_CMD_0x3d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_REBOOT_IN msgrequest */\n+#define\tMC_CMD_REBOOT_IN_LEN 4\n+#define\tMC_CMD_REBOOT_IN_FLAGS_OFST 0\n+#define\tMC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */\n+\n+/* MC_CMD_REBOOT_OUT msgresponse */\n+#define\tMC_CMD_REBOOT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SCHEDINFO\n+ * Request scheduler info. Locks required: NONE. Returns: An array of\n+ * (timeslice,maximum overrun), one for each thread, in ascending order of\n+ * thread address.\n+ */\n+#define\tMC_CMD_SCHEDINFO 0x3e\n+#undef\tMC_CMD_0x3e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SCHEDINFO_IN msgrequest */\n+#define\tMC_CMD_SCHEDINFO_IN_LEN 0\n+\n+/* MC_CMD_SCHEDINFO_OUT msgresponse */\n+#define\tMC_CMD_SCHEDINFO_OUT_LENMIN 4\n+#define\tMC_CMD_SCHEDINFO_OUT_LENMAX 252\n+#define\tMC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_SCHEDINFO_OUT_DATA_OFST 0\n+#define\tMC_CMD_SCHEDINFO_OUT_DATA_LEN 4\n+#define\tMC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1\n+#define\tMC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63\n+\n+\n+/***********************************/\n+/* MC_CMD_REBOOT_MODE\n+ * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot\n+ * mode to the specified value. Returns the old mode.\n+ */\n+#define\tMC_CMD_REBOOT_MODE 0x3f\n+#undef\tMC_CMD_0x3f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_REBOOT_MODE_IN msgrequest */\n+#define\tMC_CMD_REBOOT_MODE_IN_LEN 4\n+#define\tMC_CMD_REBOOT_MODE_IN_VALUE_OFST 0\n+/* enum: Normal. */\n+#define\tMC_CMD_REBOOT_MODE_NORMAL 0x0\n+/* enum: Power-on Reset. */\n+#define\tMC_CMD_REBOOT_MODE_POR 0x2\n+/* enum: Snapper. */\n+#define\tMC_CMD_REBOOT_MODE_SNAPPER 0x3\n+/* enum: snapper fake POR */\n+#define\tMC_CMD_REBOOT_MODE_SNAPPER_POR 0x4\n+#define\tMC_CMD_REBOOT_MODE_IN_FAKE_LBN 7\n+#define\tMC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1\n+\n+/* MC_CMD_REBOOT_MODE_OUT msgresponse */\n+#define\tMC_CMD_REBOOT_MODE_OUT_LEN 4\n+#define\tMC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SENSOR_INFO\n+ * Returns information about every available sensor.\n+ *\n+ * Each sensor has a single (16bit) value, and a corresponding state. The\n+ * mapping between value and state is nominally determined by the MC, but may\n+ * be implemented using up to 2 ranges per sensor.\n+ *\n+ * This call returns a mask (32bit) of the sensors that are supported by this\n+ * platform, then an array of sensor information structures, in order of sensor\n+ * type (but without gaps for unimplemented sensors). Each structure defines\n+ * the ranges for the corresponding sensor. An unused range is indicated by\n+ * equal limit values. If one range is used, a value outside that range results\n+ * in STATE_FATAL. If two ranges are used, a value outside the second range\n+ * results in STATE_FATAL while a value outside the first and inside the second\n+ * range results in STATE_WARNING.\n+ *\n+ * Sensor masks and sensor information arrays are organised into pages. For\n+ * backward compatibility, older host software can only use sensors in page 0.\n+ * Bit 32 in the sensor mask was previously unused, and is no reserved for use\n+ * as the next page flag.\n+ *\n+ * If the request does not contain a PAGE value then firmware will only return\n+ * page 0 of sensor information, with bit 31 in the sensor mask cleared.\n+ *\n+ * If the request contains a PAGE value then firmware responds with the sensor\n+ * mask and sensor information array for that page of sensors. In this case bit\n+ * 31 in the mask is set if another page exists.\n+ *\n+ * Locks required: None Returns: 0\n+ */\n+#define\tMC_CMD_SENSOR_INFO 0x41\n+#undef\tMC_CMD_0x41_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SENSOR_INFO_IN msgrequest */\n+#define\tMC_CMD_SENSOR_INFO_IN_LEN 0\n+\n+/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */\n+#define\tMC_CMD_SENSOR_INFO_EXT_IN_LEN 4\n+/* Which page of sensors to report.\n+ *\n+ * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).\n+ *\n+ * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.\n+ */\n+#define\tMC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0\n+\n+/* MC_CMD_SENSOR_INFO_OUT msgresponse */\n+#define\tMC_CMD_SENSOR_INFO_OUT_LENMIN 4\n+#define\tMC_CMD_SENSOR_INFO_OUT_LENMAX 252\n+#define\tMC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))\n+#define\tMC_CMD_SENSOR_INFO_OUT_MASK_OFST 0\n+/* enum: Controller temperature: degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_TEMP  0x0\n+/* enum: Phy common temperature: degC */\n+#define\tMC_CMD_SENSOR_PHY_COMMON_TEMP  0x1\n+/* enum: Controller cooling: bool */\n+#define\tMC_CMD_SENSOR_CONTROLLER_COOLING  0x2\n+/* enum: Phy 0 temperature: degC */\n+#define\tMC_CMD_SENSOR_PHY0_TEMP  0x3\n+/* enum: Phy 0 cooling: bool */\n+#define\tMC_CMD_SENSOR_PHY0_COOLING  0x4\n+/* enum: Phy 1 temperature: degC */\n+#define\tMC_CMD_SENSOR_PHY1_TEMP  0x5\n+/* enum: Phy 1 cooling: bool */\n+#define\tMC_CMD_SENSOR_PHY1_COOLING  0x6\n+/* enum: 1.0v power: mV */\n+#define\tMC_CMD_SENSOR_IN_1V0  0x7\n+/* enum: 1.2v power: mV */\n+#define\tMC_CMD_SENSOR_IN_1V2  0x8\n+/* enum: 1.8v power: mV */\n+#define\tMC_CMD_SENSOR_IN_1V8  0x9\n+/* enum: 2.5v power: mV */\n+#define\tMC_CMD_SENSOR_IN_2V5  0xa\n+/* enum: 3.3v power: mV */\n+#define\tMC_CMD_SENSOR_IN_3V3  0xb\n+/* enum: 12v power: mV */\n+#define\tMC_CMD_SENSOR_IN_12V0  0xc\n+/* enum: 1.2v analogue power: mV */\n+#define\tMC_CMD_SENSOR_IN_1V2A  0xd\n+/* enum: reference voltage: mV */\n+#define\tMC_CMD_SENSOR_IN_VREF  0xe\n+/* enum: AOE FPGA power: mV */\n+#define\tMC_CMD_SENSOR_OUT_VAOE  0xf\n+/* enum: AOE FPGA temperature: degC */\n+#define\tMC_CMD_SENSOR_AOE_TEMP  0x10\n+/* enum: AOE FPGA PSU temperature: degC */\n+#define\tMC_CMD_SENSOR_PSU_AOE_TEMP  0x11\n+/* enum: AOE PSU temperature: degC */\n+#define\tMC_CMD_SENSOR_PSU_TEMP  0x12\n+/* enum: Fan 0 speed: RPM */\n+#define\tMC_CMD_SENSOR_FAN_0  0x13\n+/* enum: Fan 1 speed: RPM */\n+#define\tMC_CMD_SENSOR_FAN_1  0x14\n+/* enum: Fan 2 speed: RPM */\n+#define\tMC_CMD_SENSOR_FAN_2  0x15\n+/* enum: Fan 3 speed: RPM */\n+#define\tMC_CMD_SENSOR_FAN_3  0x16\n+/* enum: Fan 4 speed: RPM */\n+#define\tMC_CMD_SENSOR_FAN_4  0x17\n+/* enum: AOE FPGA input power: mV */\n+#define\tMC_CMD_SENSOR_IN_VAOE  0x18\n+/* enum: AOE FPGA current: mA */\n+#define\tMC_CMD_SENSOR_OUT_IAOE  0x19\n+/* enum: AOE FPGA input current: mA */\n+#define\tMC_CMD_SENSOR_IN_IAOE  0x1a\n+/* enum: NIC power consumption: W */\n+#define\tMC_CMD_SENSOR_NIC_POWER  0x1b\n+/* enum: 0.9v power voltage: mV */\n+#define\tMC_CMD_SENSOR_IN_0V9  0x1c\n+/* enum: 0.9v power current: mA */\n+#define\tMC_CMD_SENSOR_IN_I0V9  0x1d\n+/* enum: 1.2v power current: mA */\n+#define\tMC_CMD_SENSOR_IN_I1V2  0x1e\n+/* enum: Not a sensor: reserved for the next page flag */\n+#define\tMC_CMD_SENSOR_PAGE0_NEXT  0x1f\n+/* enum: 0.9v power voltage (at ADC): mV */\n+#define\tMC_CMD_SENSOR_IN_0V9_ADC  0x20\n+/* enum: Controller temperature 2: degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_2_TEMP  0x21\n+/* enum: Voltage regulator internal temperature: degC */\n+#define\tMC_CMD_SENSOR_VREG_INTERNAL_TEMP  0x22\n+/* enum: 0.9V voltage regulator temperature: degC */\n+#define\tMC_CMD_SENSOR_VREG_0V9_TEMP  0x23\n+/* enum: 1.2V voltage regulator temperature: degC */\n+#define\tMC_CMD_SENSOR_VREG_1V2_TEMP  0x24\n+/* enum: controller internal temperature sensor voltage (internal ADC): mV */\n+#define\tMC_CMD_SENSOR_CONTROLLER_VPTAT  0x25\n+/* enum: controller internal temperature (internal ADC): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP  0x26\n+/* enum: controller internal temperature sensor voltage (external ADC): mV */\n+#define\tMC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC  0x27\n+/* enum: controller internal temperature (external ADC): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC  0x28\n+/* enum: ambient temperature: degC */\n+#define\tMC_CMD_SENSOR_AMBIENT_TEMP  0x29\n+/* enum: air flow: bool */\n+#define\tMC_CMD_SENSOR_AIRFLOW  0x2a\n+/* enum: voltage between VSS08D and VSS08D at CSR: mV */\n+#define\tMC_CMD_SENSOR_VDD08D_VSS08D_CSR  0x2b\n+/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */\n+#define\tMC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC  0x2c\n+/* enum: Hotpoint temperature: degC */\n+#define\tMC_CMD_SENSOR_HOTPOINT_TEMP  0x2d\n+/* enum: Port 0 PHY power switch over-current: bool */\n+#define\tMC_CMD_SENSOR_PHY_POWER_PORT0  0x2e\n+/* enum: Port 1 PHY power switch over-current: bool */\n+#define\tMC_CMD_SENSOR_PHY_POWER_PORT1  0x2f\n+/* enum: Mop-up microcontroller reference voltage (millivolts) */\n+#define\tMC_CMD_SENSOR_MUM_VCC  0x30\n+/* enum: 0.9v power phase A voltage: mV */\n+#define\tMC_CMD_SENSOR_IN_0V9_A  0x31\n+/* enum: 0.9v power phase A current: mA */\n+#define\tMC_CMD_SENSOR_IN_I0V9_A  0x32\n+/* enum: 0.9V voltage regulator phase A temperature: degC */\n+#define\tMC_CMD_SENSOR_VREG_0V9_A_TEMP  0x33\n+/* enum: 0.9v power phase B voltage: mV */\n+#define\tMC_CMD_SENSOR_IN_0V9_B  0x34\n+/* enum: 0.9v power phase B current: mA */\n+#define\tMC_CMD_SENSOR_IN_I0V9_B  0x35\n+/* enum: 0.9V voltage regulator phase B temperature: degC */\n+#define\tMC_CMD_SENSOR_VREG_0V9_B_TEMP  0x36\n+/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */\n+#define\tMC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY  0x37\n+/* enum: CCOM AVREG 1v2 supply (external ADC): mV */\n+#define\tMC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC  0x38\n+/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */\n+#define\tMC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY  0x39\n+/* enum: CCOM AVREG 1v8 supply (external ADC): mV */\n+#define\tMC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC  0x3a\n+/* enum: CCOM RTS temperature: degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_RTS  0x3b\n+/* enum: Not a sensor: reserved for the next page flag */\n+#define\tMC_CMD_SENSOR_PAGE1_NEXT  0x3f\n+/* enum: controller internal temperature sensor voltage on master core\n+ * (internal ADC): mV\n+ */\n+#define\tMC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT  0x40\n+/* enum: controller internal temperature on master core (internal ADC): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP  0x41\n+/* enum: controller internal temperature sensor voltage on master core\n+ * (external ADC): mV\n+ */\n+#define\tMC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC  0x42\n+/* enum: controller internal temperature on master core (external ADC): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC  0x43\n+/* enum: controller internal temperature on slave core sensor voltage (internal\n+ * ADC): mV\n+ */\n+#define\tMC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT  0x44\n+/* enum: controller internal temperature on slave core (internal ADC): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP  0x45\n+/* enum: controller internal temperature on slave core sensor voltage (external\n+ * ADC): mV\n+ */\n+#define\tMC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC  0x46\n+/* enum: controller internal temperature on slave core (external ADC): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC  0x47\n+/* enum: Voltage supplied to the SODIMMs from their power supply: mV */\n+#define\tMC_CMD_SENSOR_SODIMM_VOUT  0x49\n+/* enum: Temperature of SODIMM 0 (if installed): degC */\n+#define\tMC_CMD_SENSOR_SODIMM_0_TEMP  0x4a\n+/* enum: Temperature of SODIMM 1 (if installed): degC */\n+#define\tMC_CMD_SENSOR_SODIMM_1_TEMP  0x4b\n+/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */\n+#define\tMC_CMD_SENSOR_PHY0_VCC  0x4c\n+/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */\n+#define\tMC_CMD_SENSOR_PHY1_VCC  0x4d\n+/* enum: Controller die temperature (TDIODE): degC */\n+#define\tMC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP  0x4e\n+/* enum: Board temperature (front): degC */\n+#define\tMC_CMD_SENSOR_BOARD_FRONT_TEMP  0x4f\n+/* enum: Board temperature (back): degC */\n+#define\tMC_CMD_SENSOR_BOARD_BACK_TEMP  0x50\n+/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */\n+#define\tMC_CMD_SENSOR_ENTRY_OFST 4\n+#define\tMC_CMD_SENSOR_ENTRY_LEN 8\n+#define\tMC_CMD_SENSOR_ENTRY_LO_OFST 4\n+#define\tMC_CMD_SENSOR_ENTRY_HI_OFST 8\n+#define\tMC_CMD_SENSOR_ENTRY_MINNUM 0\n+#define\tMC_CMD_SENSOR_ENTRY_MAXNUM 31\n+\n+/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_SENSOR_INFO_OUT */\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1\n+/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */\n+/*            MC_CMD_SENSOR_ENTRY_OFST 4 */\n+/*            MC_CMD_SENSOR_ENTRY_LEN 8 */\n+/*            MC_CMD_SENSOR_ENTRY_LO_OFST 4 */\n+/*            MC_CMD_SENSOR_ENTRY_HI_OFST 8 */\n+/*            MC_CMD_SENSOR_ENTRY_MINNUM 0 */\n+/*            MC_CMD_SENSOR_ENTRY_MAXNUM 31 */\n+\n+/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48\n+#define\tMC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16\n+\n+\n+/***********************************/\n+/* MC_CMD_READ_SENSORS\n+ * Returns the current reading from each sensor. DMAs an array of sensor\n+ * readings, in order of sensor type (but without gaps for unimplemented\n+ * sensors), into host memory. Each array element is a\n+ * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.\n+ *\n+ * If the request does not contain the LENGTH field then only sensors 0 to 30\n+ * are reported, to avoid DMA buffer overflow in older host software. If the\n+ * sensor reading require more space than the LENGTH allows, then return\n+ * EINVAL.\n+ *\n+ * The MC will send a SENSOREVT event every time any sensor changes state. The\n+ * driver is responsible for ensuring that it doesn't miss any events. The\n+ * board will function normally if all sensors are in STATE_OK or\n+ * STATE_WARNING. Otherwise the board should not be expected to function.\n+ */\n+#define\tMC_CMD_READ_SENSORS 0x42\n+#undef\tMC_CMD_0x42_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_READ_SENSORS_IN msgrequest */\n+#define\tMC_CMD_READ_SENSORS_IN_LEN 8\n+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4\n+\n+/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_LEN 12\n+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4\n+/* Size in bytes of host buffer. */\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8\n+\n+/* MC_CMD_READ_SENSORS_OUT msgresponse */\n+#define\tMC_CMD_READ_SENSORS_OUT_LEN 0\n+\n+/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */\n+#define\tMC_CMD_READ_SENSORS_EXT_OUT_LEN 0\n+\n+/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1\n+/* enum: Ok. */\n+#define\tMC_CMD_SENSOR_STATE_OK  0x0\n+/* enum: Breached warning threshold. */\n+#define\tMC_CMD_SENSOR_STATE_WARNING  0x1\n+/* enum: Breached fatal threshold. */\n+#define\tMC_CMD_SENSOR_STATE_FATAL  0x2\n+/* enum: Fault with sensor. */\n+#define\tMC_CMD_SENSOR_STATE_BROKEN  0x3\n+/* enum: Sensor is working but does not currently have a reading. */\n+#define\tMC_CMD_SENSOR_STATE_NO_READING  0x4\n+/* enum: Sensor initialisation failed. */\n+#define\tMC_CMD_SENSOR_STATE_INIT_FAILED  0x5\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24\n+#define\tMC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PHY_STATE\n+ * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot\n+ * (e.g. due to missing or corrupted firmware). Locks required: None. Return\n+ * code: 0\n+ */\n+#define\tMC_CMD_GET_PHY_STATE 0x43\n+#undef\tMC_CMD_0x43_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PHY_STATE_IN msgrequest */\n+#define\tMC_CMD_GET_PHY_STATE_IN_LEN 0\n+\n+/* MC_CMD_GET_PHY_STATE_OUT msgresponse */\n+#define\tMC_CMD_GET_PHY_STATE_OUT_LEN 4\n+#define\tMC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0\n+/* enum: Ok. */\n+#define\tMC_CMD_PHY_STATE_OK 0x1\n+/* enum: Faulty. */\n+#define\tMC_CMD_PHY_STATE_ZOMBIE 0x2\n+\n+\n+/***********************************/\n+/* MC_CMD_SETUP_8021QBB\n+ * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to\n+ * disable 802.Qbb for a given priority.\n+ */\n+#define\tMC_CMD_SETUP_8021QBB 0x44\n+\n+/* MC_CMD_SETUP_8021QBB_IN msgrequest */\n+#define\tMC_CMD_SETUP_8021QBB_IN_LEN 32\n+#define\tMC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0\n+#define\tMC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32\n+\n+/* MC_CMD_SETUP_8021QBB_OUT msgresponse */\n+#define\tMC_CMD_SETUP_8021QBB_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_WOL_FILTER_GET\n+ * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS\n+ */\n+#define\tMC_CMD_WOL_FILTER_GET 0x45\n+#undef\tMC_CMD_0x45_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_WOL_FILTER_GET_IN msgrequest */\n+#define\tMC_CMD_WOL_FILTER_GET_IN_LEN 0\n+\n+/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */\n+#define\tMC_CMD_WOL_FILTER_GET_OUT_LEN 4\n+#define\tMC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD\n+ * Add a protocol offload to NIC for lights-out state. Locks required: None.\n+ * Returns: 0, ENOSYS\n+ */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46\n+#undef\tMC_CMD_0x46_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0\n+#define\tMC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */\n+#define\tMC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS  0x2 /* enum */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62\n+\n+/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14\n+/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10\n+\n+/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42\n+/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16\n+\n+/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD\n+ * Remove a protocol offload from NIC for lights-out state. Locks required:\n+ * None. Returns: 0, ENOSYS\n+ */\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47\n+#undef\tMC_CMD_0x47_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK\n+\n+/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4\n+\n+/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_MAC_RESET_RESTORE\n+ * Restore MAC after block reset. Locks required: None. Returns: 0.\n+ */\n+#define\tMC_CMD_MAC_RESET_RESTORE 0x48\n+\n+/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */\n+#define\tMC_CMD_MAC_RESET_RESTORE_IN_LEN 0\n+\n+/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */\n+#define\tMC_CMD_MAC_RESET_RESTORE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TESTASSERT\n+ * Deliberately trigger an assert-detonation in the firmware for testing\n+ * purposes (i.e. to allow tests that the driver copes gracefully). Locks\n+ * required: None Returns: 0\n+ */\n+#define\tMC_CMD_TESTASSERT 0x49\n+#undef\tMC_CMD_0x49_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TESTASSERT_IN msgrequest */\n+#define\tMC_CMD_TESTASSERT_IN_LEN 0\n+\n+/* MC_CMD_TESTASSERT_OUT msgresponse */\n+#define\tMC_CMD_TESTASSERT_OUT_LEN 0\n+\n+/* MC_CMD_TESTASSERT_V2_IN msgrequest */\n+#define\tMC_CMD_TESTASSERT_V2_IN_LEN 4\n+/* How to provoke the assertion */\n+#define\tMC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0\n+/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless\n+ * you're testing firmware, this is what you want.\n+ */\n+#define\tMC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES  0x0\n+/* enum: Assert using assert(0); */\n+#define\tMC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE  0x1\n+/* enum: Deliberately trigger a watchdog */\n+#define\tMC_CMD_TESTASSERT_V2_IN_WATCHDOG  0x2\n+/* enum: Deliberately trigger a trap by loading from an invalid address */\n+#define\tMC_CMD_TESTASSERT_V2_IN_LOAD_TRAP  0x3\n+/* enum: Deliberately trigger a trap by storing to an invalid address */\n+#define\tMC_CMD_TESTASSERT_V2_IN_STORE_TRAP  0x4\n+/* enum: Jump to an invalid address */\n+#define\tMC_CMD_TESTASSERT_V2_IN_JUMP_TRAP  0x5\n+\n+/* MC_CMD_TESTASSERT_V2_OUT msgresponse */\n+#define\tMC_CMD_TESTASSERT_V2_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_WORKAROUND\n+ * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't\n+ * understand the given workaround number - which should not be treated as a\n+ * hard error by client code. This op does not imply any semantics about each\n+ * workaround, that's between the driver and the mcfw on a per-workaround\n+ * basis. Locks required: None. Returns: 0, EINVAL .\n+ */\n+#define\tMC_CMD_WORKAROUND 0x4a\n+#undef\tMC_CMD_0x4a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_WORKAROUND_IN msgrequest */\n+#define\tMC_CMD_WORKAROUND_IN_LEN 8\n+/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */\n+#define\tMC_CMD_WORKAROUND_IN_TYPE_OFST 0\n+/* enum: Bug 17230 work around. */\n+#define\tMC_CMD_WORKAROUND_BUG17230 0x1\n+/* enum: Bug 35388 work around (unsafe EVQ writes). */\n+#define\tMC_CMD_WORKAROUND_BUG35388 0x2\n+/* enum: Bug35017 workaround (A64 tables must be identity map) */\n+#define\tMC_CMD_WORKAROUND_BUG35017 0x3\n+/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */\n+#define\tMC_CMD_WORKAROUND_BUG41750 0x4\n+/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution\n+ * - before adding code that queries this workaround, remember that there's\n+ * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,\n+ * and will hence (incorrectly) report that the bug doesn't exist.\n+ */\n+#define\tMC_CMD_WORKAROUND_BUG42008 0x5\n+/* enum: Bug 26807 features present in firmware (multicast filter chaining)\n+ * This feature cannot be turned on/off while there are any filters already\n+ * present. The behaviour in such case depends on the acting client's privilege\n+ * level. If the client has the admin privilege, then all functions that have\n+ * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise\n+ * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.\n+ */\n+#define\tMC_CMD_WORKAROUND_BUG26807 0x6\n+/* enum: Bug 61265 work around (broken EVQ TMR writes). */\n+#define\tMC_CMD_WORKAROUND_BUG61265 0x7\n+/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable\n+ * the workaround\n+ */\n+#define\tMC_CMD_WORKAROUND_IN_ENABLED_OFST 4\n+\n+/* MC_CMD_WORKAROUND_OUT msgresponse */\n+#define\tMC_CMD_WORKAROUND_OUT_LEN 0\n+\n+/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used\n+ * when (TYPE == MC_CMD_WORKAROUND_BUG26807)\n+ */\n+#define\tMC_CMD_WORKAROUND_EXT_OUT_LEN 4\n+#define\tMC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0\n+#define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PHY_MEDIA_INFO\n+ * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for\n+ * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG\n+ * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the\n+ * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1\n+ * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.\n+ * Anything else: currently undefined. Locks required: None. Return code: 0.\n+ */\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO 0x4b\n+#undef\tMC_CMD_0x4b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0\n+\n+/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))\n+/* in bytes */\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_TEST\n+ * Test a particular NVRAM partition for valid contents (where \"valid\" depends\n+ * on the type of partition).\n+ */\n+#define\tMC_CMD_NVRAM_TEST 0x4c\n+#undef\tMC_CMD_0x4c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_TEST_IN msgrequest */\n+#define\tMC_CMD_NVRAM_TEST_IN_LEN 4\n+#define\tMC_CMD_NVRAM_TEST_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n+\n+/* MC_CMD_NVRAM_TEST_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_TEST_OUT_LEN 4\n+#define\tMC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0\n+/* enum: Passed. */\n+#define\tMC_CMD_NVRAM_TEST_PASS 0x0\n+/* enum: Failed. */\n+#define\tMC_CMD_NVRAM_TEST_FAIL 0x1\n+/* enum: Not supported. */\n+#define\tMC_CMD_NVRAM_TEST_NOTSUPP 0x2\n+\n+\n+/***********************************/\n+/* MC_CMD_MRSFP_TWEAK\n+ * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.\n+ * I2C I/O expander bits are always read; if equaliser parameters are supplied,\n+ * they are configured first. Locks required: None. Return code: 0, EINVAL.\n+ */\n+#define\tMC_CMD_MRSFP_TWEAK 0x4d\n+\n+/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16\n+/* 0-6 low->high de-emph. */\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0\n+/* 0-8 low->high ref.V */\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4\n+/* 0-8 0-8 low->high boost */\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8\n+/* 0-8 low->high ref.V */\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12\n+\n+/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */\n+#define\tMC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0\n+\n+/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_LEN 12\n+/* input bits */\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0\n+/* output bits */\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4\n+/* direction */\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8\n+/* enum: Out. */\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0\n+/* enum: In. */\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1\n+\n+\n+/***********************************/\n+/* MC_CMD_SENSOR_SET_LIMS\n+ * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:\n+ * ENOENT if the sensor specified does not exist, EINVAL if the limits are out\n+ * of range.\n+ */\n+#define\tMC_CMD_SENSOR_SET_LIMS 0x4e\n+#undef\tMC_CMD_0x4e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_LEN 20\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */\n+/* interpretation is is sensor-specific. */\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4\n+/* interpretation is is sensor-specific. */\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8\n+/* interpretation is is sensor-specific. */\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12\n+/* interpretation is is sensor-specific. */\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16\n+\n+/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */\n+#define\tMC_CMD_SENSOR_SET_LIMS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_RESOURCE_LIMITS\n+ */\n+#define\tMC_CMD_GET_RESOURCE_LIMITS 0x4f\n+\n+/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0\n+\n+/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_PARTITIONS\n+ * Reads the list of available virtual NVRAM partition types. Locks required:\n+ * none. Returns: 0, EINVAL (bad type).\n+ */\n+#define\tMC_CMD_NVRAM_PARTITIONS 0x51\n+#undef\tMC_CMD_0x51_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */\n+#define\tMC_CMD_NVRAM_PARTITIONS_IN_LEN 0\n+\n+/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))\n+/* total number of partitions */\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0\n+/* type ID code for each of NUM_PARTITIONS partitions */\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_METADATA\n+ * Reads soft metadata for a virtual NVRAM partition type. Locks required:\n+ * none. Returns: 0, EINVAL (bad type).\n+ */\n+#define\tMC_CMD_NVRAM_METADATA 0x52\n+#undef\tMC_CMD_0x52_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_METADATA_IN msgrequest */\n+#define\tMC_CMD_NVRAM_METADATA_IN_LEN 4\n+/* Partition type ID code */\n+#define\tMC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0\n+\n+/* MC_CMD_NVRAM_METADATA_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_LENMIN 20\n+#define\tMC_CMD_NVRAM_METADATA_OUT_LENMAX 252\n+#define\tMC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))\n+/* Partition type ID code */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0\n+#define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1\n+/* Subtype ID code for content of this partition */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8\n+/* 1st component of W.X.Y.Z version number for content of this partition */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2\n+/* 2nd component of W.X.Y.Z version number for content of this partition */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2\n+/* 3rd component of W.X.Y.Z version number for content of this partition */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2\n+/* 4th component of W.X.Y.Z version number for content of this partition */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2\n+/* Zero-terminated string describing the content of this partition */\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_MAC_ADDRESSES\n+ * Returns the base MAC, count and stride for the requesting function\n+ */\n+#define\tMC_CMD_GET_MAC_ADDRESSES 0x55\n+#undef\tMC_CMD_0x55_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */\n+#define\tMC_CMD_GET_MAC_ADDRESSES_IN_LEN 0\n+\n+/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16\n+/* Base MAC address */\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6\n+/* Padding */\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2\n+/* Number of allocated MAC addresses */\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8\n+/* Spacing of allocated MAC addresses */\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12\n+\n+\n+/***********************************/\n+/* MC_CMD_CLP\n+ * Perform a CLP related operation\n+ */\n+#define\tMC_CMD_CLP 0x56\n+#undef\tMC_CMD_0x56_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_CLP_IN msgrequest */\n+#define\tMC_CMD_CLP_IN_LEN 4\n+/* Sub operation */\n+#define\tMC_CMD_CLP_IN_OP_OFST 0\n+/* enum: Return to factory default settings */\n+#define\tMC_CMD_CLP_OP_DEFAULT 0x1\n+/* enum: Set MAC address */\n+#define\tMC_CMD_CLP_OP_SET_MAC 0x2\n+/* enum: Get MAC address */\n+#define\tMC_CMD_CLP_OP_GET_MAC 0x3\n+/* enum: Set UEFI/GPXE boot mode */\n+#define\tMC_CMD_CLP_OP_SET_BOOT 0x4\n+/* enum: Get UEFI/GPXE boot mode */\n+#define\tMC_CMD_CLP_OP_GET_BOOT 0x5\n+\n+/* MC_CMD_CLP_OUT msgresponse */\n+#define\tMC_CMD_CLP_OUT_LEN 0\n+\n+/* MC_CMD_CLP_IN_DEFAULT msgrequest */\n+#define\tMC_CMD_CLP_IN_DEFAULT_LEN 4\n+/*            MC_CMD_CLP_IN_OP_OFST 0 */\n+\n+/* MC_CMD_CLP_OUT_DEFAULT msgresponse */\n+#define\tMC_CMD_CLP_OUT_DEFAULT_LEN 0\n+\n+/* MC_CMD_CLP_IN_SET_MAC msgrequest */\n+#define\tMC_CMD_CLP_IN_SET_MAC_LEN 12\n+/*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/* MAC address assigned to port */\n+#define\tMC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4\n+#define\tMC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6\n+/* Padding */\n+#define\tMC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10\n+#define\tMC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2\n+\n+/* MC_CMD_CLP_OUT_SET_MAC msgresponse */\n+#define\tMC_CMD_CLP_OUT_SET_MAC_LEN 0\n+\n+/* MC_CMD_CLP_IN_GET_MAC msgrequest */\n+#define\tMC_CMD_CLP_IN_GET_MAC_LEN 4\n+/*            MC_CMD_CLP_IN_OP_OFST 0 */\n+\n+/* MC_CMD_CLP_OUT_GET_MAC msgresponse */\n+#define\tMC_CMD_CLP_OUT_GET_MAC_LEN 8\n+/* MAC address assigned to port */\n+#define\tMC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0\n+#define\tMC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6\n+/* Padding */\n+#define\tMC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6\n+#define\tMC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2\n+\n+/* MC_CMD_CLP_IN_SET_BOOT msgrequest */\n+#define\tMC_CMD_CLP_IN_SET_BOOT_LEN 5\n+/*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/* Boot flag */\n+#define\tMC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4\n+#define\tMC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1\n+\n+/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */\n+#define\tMC_CMD_CLP_OUT_SET_BOOT_LEN 0\n+\n+/* MC_CMD_CLP_IN_GET_BOOT msgrequest */\n+#define\tMC_CMD_CLP_IN_GET_BOOT_LEN 4\n+/*            MC_CMD_CLP_IN_OP_OFST 0 */\n+\n+/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */\n+#define\tMC_CMD_CLP_OUT_GET_BOOT_LEN 4\n+/* Boot flag */\n+#define\tMC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0\n+#define\tMC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1\n+/* Padding */\n+#define\tMC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1\n+#define\tMC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3\n+\n+\n+/***********************************/\n+/* MC_CMD_MUM\n+ * Perform a MUM operation\n+ */\n+#define\tMC_CMD_MUM 0x57\n+#undef\tMC_CMD_0x57_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_MUM_IN msgrequest */\n+#define\tMC_CMD_MUM_IN_LEN 4\n+#define\tMC_CMD_MUM_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_MUM_IN_OP_LBN 0\n+#define\tMC_CMD_MUM_IN_OP_WIDTH 8\n+/* enum: NULL MCDI command to MUM */\n+#define\tMC_CMD_MUM_OP_NULL 0x1\n+/* enum: Get MUM version */\n+#define\tMC_CMD_MUM_OP_GET_VERSION 0x2\n+/* enum: Issue raw I2C command to MUM */\n+#define\tMC_CMD_MUM_OP_RAW_CMD 0x3\n+/* enum: Read from registers on devices connected to MUM. */\n+#define\tMC_CMD_MUM_OP_READ 0x4\n+/* enum: Write to registers on devices connected to MUM. */\n+#define\tMC_CMD_MUM_OP_WRITE 0x5\n+/* enum: Control UART logging. */\n+#define\tMC_CMD_MUM_OP_LOG 0x6\n+/* enum: Operations on MUM GPIO lines */\n+#define\tMC_CMD_MUM_OP_GPIO 0x7\n+/* enum: Get sensor readings from MUM */\n+#define\tMC_CMD_MUM_OP_READ_SENSORS 0x8\n+/* enum: Initiate clock programming on the MUM */\n+#define\tMC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9\n+/* enum: Initiate FPGA load from flash on the MUM */\n+#define\tMC_CMD_MUM_OP_FPGA_LOAD 0xa\n+/* enum: Request sensor reading from MUM ADC resulting from earlier request via\n+ * MUM ATB\n+ */\n+#define\tMC_CMD_MUM_OP_READ_ATB_SENSOR 0xb\n+/* enum: Send commands relating to the QSFP ports via the MUM for PHY\n+ * operations\n+ */\n+#define\tMC_CMD_MUM_OP_QSFP 0xc\n+/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage\n+ * level) from MUM\n+ */\n+#define\tMC_CMD_MUM_OP_READ_DDR_INFO 0xd\n+\n+/* MC_CMD_MUM_IN_NULL msgrequest */\n+#define\tMC_CMD_MUM_IN_NULL_LEN 4\n+/* MUM cmd header */\n+#define\tMC_CMD_MUM_IN_CMD_OFST 0\n+\n+/* MC_CMD_MUM_IN_GET_VERSION msgrequest */\n+#define\tMC_CMD_MUM_IN_GET_VERSION_LEN 4\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_MUM_IN_READ msgrequest */\n+#define\tMC_CMD_MUM_IN_READ_LEN 16\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/* ID of (device connected to MUM) to read from registers of */\n+#define\tMC_CMD_MUM_IN_READ_DEVICE_OFST 4\n+/* enum: Hittite HMC1035 clock generator on Sorrento board */\n+#define\tMC_CMD_MUM_DEV_HITTITE 0x1\n+/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */\n+#define\tMC_CMD_MUM_DEV_HITTITE_NIC 0x2\n+/* 32-bit address to read from */\n+#define\tMC_CMD_MUM_IN_READ_ADDR_OFST 8\n+/* Number of words to read. */\n+#define\tMC_CMD_MUM_IN_READ_NUMWORDS_OFST 12\n+\n+/* MC_CMD_MUM_IN_WRITE msgrequest */\n+#define\tMC_CMD_MUM_IN_WRITE_LENMIN 16\n+#define\tMC_CMD_MUM_IN_WRITE_LENMAX 252\n+#define\tMC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/* ID of (device connected to MUM) to write to registers of */\n+#define\tMC_CMD_MUM_IN_WRITE_DEVICE_OFST 4\n+/* enum: Hittite HMC1035 clock generator on Sorrento board */\n+/*               MC_CMD_MUM_DEV_HITTITE 0x1 */\n+/* 32-bit address to write to */\n+#define\tMC_CMD_MUM_IN_WRITE_ADDR_OFST 8\n+/* Words to write */\n+#define\tMC_CMD_MUM_IN_WRITE_BUFFER_OFST 12\n+#define\tMC_CMD_MUM_IN_WRITE_BUFFER_LEN 4\n+#define\tMC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1\n+#define\tMC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60\n+\n+/* MC_CMD_MUM_IN_RAW_CMD msgrequest */\n+#define\tMC_CMD_MUM_IN_RAW_CMD_LENMIN 17\n+#define\tMC_CMD_MUM_IN_RAW_CMD_LENMAX 252\n+#define\tMC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/* MUM I2C cmd code */\n+#define\tMC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4\n+/* Number of bytes to write */\n+#define\tMC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8\n+/* Number of bytes to read */\n+#define\tMC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12\n+/* Bytes to write */\n+#define\tMC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16\n+#define\tMC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1\n+#define\tMC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1\n+#define\tMC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236\n+\n+/* MC_CMD_MUM_IN_LOG msgrequest */\n+#define\tMC_CMD_MUM_IN_LOG_LEN 8\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_LOG_OP_OFST 4\n+#define\tMC_CMD_MUM_IN_LOG_OP_UART  0x1 /* enum */\n+\n+/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */\n+#define\tMC_CMD_MUM_IN_LOG_OP_UART_LEN 12\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_LOG_OP_OFST 4 */\n+/* Enable/disable debug output to UART */\n+#define\tMC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8\n+\n+/* MC_CMD_MUM_IN_GPIO msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_LEN 8\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OPCODE_LBN 0\n+#define\tMC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8\n+#define\tMC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */\n+\n+/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_IN_READ_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4\n+\n+/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4\n+/* The first 32-bit word to be written to the GPIO OUT register. */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8\n+/* The second 32-bit word to be written to the GPIO OUT register. */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12\n+\n+/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4\n+\n+/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4\n+/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8\n+/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12\n+\n+/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4\n+\n+/* MC_CMD_MUM_IN_GPIO_OP msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8\n+#define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16\n+#define\tMC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8\n+\n+/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4\n+\n+/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8\n+\n+/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8\n+\n+/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8\n+\n+/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_LEN 8\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8\n+\n+/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/* Bit-mask of clocks to be programmed */\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4\n+#define\tMC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */\n+#define\tMC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */\n+#define\tMC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */\n+/* Control flags for clock programming */\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1\n+\n+/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */\n+#define\tMC_CMD_MUM_IN_FPGA_LOAD_LEN 8\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/* Enable/Disable FPGA config from flash */\n+#define\tMC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4\n+\n+/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */\n+#define\tMC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_MUM_IN_QSFP msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_LEN 12\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_OPCODE_LBN 0\n+#define\tMC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4\n+#define\tMC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */\n+#define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */\n+#define\tMC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */\n+#define\tMC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */\n+#define\tMC_CMD_MUM_IN_QSFP_IDX_OFST 8\n+\n+/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_LEN 16\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12\n+\n+/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20\n+\n+/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8\n+\n+/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12\n+\n+/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8\n+\n+/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */\n+#define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+#define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8\n+\n+/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */\n+#define\tMC_CMD_MUM_IN_READ_DDR_INFO_LEN 4\n+/* MUM cmd header */\n+/*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+\n+/* MC_CMD_MUM_OUT msgresponse */\n+#define\tMC_CMD_MUM_OUT_LEN 0\n+\n+/* MC_CMD_MUM_OUT_NULL msgresponse */\n+#define\tMC_CMD_MUM_OUT_NULL_LEN 0\n+\n+/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_LEN 12\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8\n+\n+/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_LENMIN 1\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_LENMAX 252\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))\n+/* returned data */\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1\n+#define\tMC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252\n+\n+/* MC_CMD_MUM_OUT_READ msgresponse */\n+#define\tMC_CMD_MUM_OUT_READ_LENMIN 4\n+#define\tMC_CMD_MUM_OUT_READ_LENMAX 252\n+#define\tMC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MUM_OUT_READ_BUFFER_OFST 0\n+#define\tMC_CMD_MUM_OUT_READ_BUFFER_LEN 4\n+#define\tMC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1\n+#define\tMC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_MUM_OUT_WRITE msgresponse */\n+#define\tMC_CMD_MUM_OUT_WRITE_LEN 0\n+\n+/* MC_CMD_MUM_OUT_LOG msgresponse */\n+#define\tMC_CMD_MUM_OUT_LOG_LEN 0\n+\n+/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */\n+#define\tMC_CMD_MUM_OUT_LOG_OP_UART_LEN 0\n+\n+/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8\n+/* The first 32-bit word read from the GPIO IN register. */\n+#define\tMC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0\n+/* The second 32-bit word read from the GPIO IN register. */\n+#define\tMC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4\n+\n+/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0\n+\n+/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8\n+/* The first 32-bit word read from the GPIO OUT register. */\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0\n+/* The second 32-bit word read from the GPIO OUT register. */\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4\n+\n+/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0\n+\n+/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4\n+\n+/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4\n+#define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0\n+\n+/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0\n+\n+/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0\n+\n+/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */\n+#define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0\n+\n+/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8\n+\n+/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */\n+#define\tMC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4\n+#define\tMC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0\n+\n+/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */\n+#define\tMC_CMD_MUM_OUT_FPGA_LOAD_LEN 0\n+\n+/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */\n+#define\tMC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4\n+#define\tMC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0\n+\n+/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */\n+#define\tMC_CMD_MUM_OUT_QSFP_INIT_LEN 0\n+\n+/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1\n+\n+/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0\n+\n+/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))\n+/* in bytes */\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248\n+\n+/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */\n+#define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8\n+#define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4\n+\n+/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */\n+#define\tMC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4\n+#define\tMC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0\n+\n+/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))\n+/* Discrete (soldered) DDR resistor strap info */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16\n+/* Number of SODIMM info records */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4\n+/* Array of SODIMM info records */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8\n+/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0\n+/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1\n+/* enum: Total number of SODIMM banks */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */\n+/* enum: Values 5-15 are reserved for future usage */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4\n+/* enum: No module present */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0\n+/* enum: Module present supported and powered on */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1\n+/* enum: Module present but bad type */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2\n+/* enum: Module present but incompatible voltage */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3\n+/* enum: Module present but unknown SPD */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4\n+/* enum: Module present but slot cannot support it */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5\n+/* enum: Modules may or may not be present, but cannot establish contact by I2C\n+ */\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12\n+\n+/* MC_CMD_RESOURCE_SPECIFIER enum */\n+/* enum: Any */\n+#define\tMC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff\n+/* enum: None */\n+#define\tMC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe\n+\n+/* EVB_PORT_ID structuredef */\n+#define\tEVB_PORT_ID_LEN 4\n+#define\tEVB_PORT_ID_PORT_ID_OFST 0\n+/* enum: An invalid port handle. */\n+#define\tEVB_PORT_ID_NULL  0x0\n+/* enum: The port assigned to this function.. */\n+#define\tEVB_PORT_ID_ASSIGNED  0x1000000\n+/* enum: External network port 0 */\n+#define\tEVB_PORT_ID_MAC0  0x2000000\n+/* enum: External network port 1 */\n+#define\tEVB_PORT_ID_MAC1  0x2000001\n+/* enum: External network port 2 */\n+#define\tEVB_PORT_ID_MAC2  0x2000002\n+/* enum: External network port 3 */\n+#define\tEVB_PORT_ID_MAC3  0x2000003\n+#define\tEVB_PORT_ID_PORT_ID_LBN 0\n+#define\tEVB_PORT_ID_PORT_ID_WIDTH 32\n+\n+/* EVB_VLAN_TAG structuredef */\n+#define\tEVB_VLAN_TAG_LEN 2\n+/* The VLAN tag value */\n+#define\tEVB_VLAN_TAG_VLAN_ID_LBN 0\n+#define\tEVB_VLAN_TAG_VLAN_ID_WIDTH 12\n+#define\tEVB_VLAN_TAG_MODE_LBN 12\n+#define\tEVB_VLAN_TAG_MODE_WIDTH 4\n+/* enum: Insert the VLAN. */\n+#define\tEVB_VLAN_TAG_INSERT  0x0\n+/* enum: Replace the VLAN if already present. */\n+#define\tEVB_VLAN_TAG_REPLACE 0x1\n+\n+/* BUFTBL_ENTRY structuredef */\n+#define\tBUFTBL_ENTRY_LEN 12\n+/* the owner ID */\n+#define\tBUFTBL_ENTRY_OID_OFST 0\n+#define\tBUFTBL_ENTRY_OID_LEN 2\n+#define\tBUFTBL_ENTRY_OID_LBN 0\n+#define\tBUFTBL_ENTRY_OID_WIDTH 16\n+/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */\n+#define\tBUFTBL_ENTRY_PGSZ_OFST 2\n+#define\tBUFTBL_ENTRY_PGSZ_LEN 2\n+#define\tBUFTBL_ENTRY_PGSZ_LBN 16\n+#define\tBUFTBL_ENTRY_PGSZ_WIDTH 16\n+/* the raw 64-bit address field from the SMC, not adjusted for page size */\n+#define\tBUFTBL_ENTRY_RAWADDR_OFST 4\n+#define\tBUFTBL_ENTRY_RAWADDR_LEN 8\n+#define\tBUFTBL_ENTRY_RAWADDR_LO_OFST 4\n+#define\tBUFTBL_ENTRY_RAWADDR_HI_OFST 8\n+#define\tBUFTBL_ENTRY_RAWADDR_LBN 32\n+#define\tBUFTBL_ENTRY_RAWADDR_WIDTH 64\n+\n+/* NVRAM_PARTITION_TYPE structuredef */\n+#define\tNVRAM_PARTITION_TYPE_LEN 2\n+#define\tNVRAM_PARTITION_TYPE_ID_OFST 0\n+#define\tNVRAM_PARTITION_TYPE_ID_LEN 2\n+/* enum: Primary MC firmware partition */\n+#define\tNVRAM_PARTITION_TYPE_MC_FIRMWARE          0x100\n+/* enum: Secondary MC firmware partition */\n+#define\tNVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP   0x200\n+/* enum: Expansion ROM partition */\n+#define\tNVRAM_PARTITION_TYPE_EXPANSION_ROM        0x300\n+/* enum: Static configuration TLV partition */\n+#define\tNVRAM_PARTITION_TYPE_STATIC_CONFIG        0x400\n+/* enum: Dynamic configuration TLV partition */\n+#define\tNVRAM_PARTITION_TYPE_DYNAMIC_CONFIG       0x500\n+/* enum: Expansion ROM configuration data for port 0 */\n+#define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0  0x600\n+/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */\n+#define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG        0x600\n+/* enum: Expansion ROM configuration data for port 1 */\n+#define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1  0x601\n+/* enum: Expansion ROM configuration data for port 2 */\n+#define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2  0x602\n+/* enum: Expansion ROM configuration data for port 3 */\n+#define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3  0x603\n+/* enum: Non-volatile log output partition */\n+#define\tNVRAM_PARTITION_TYPE_LOG                  0x700\n+/* enum: Non-volatile log output of second core on dual-core device */\n+#define\tNVRAM_PARTITION_TYPE_LOG_SLAVE            0x701\n+/* enum: Device state dump output partition */\n+#define\tNVRAM_PARTITION_TYPE_DUMP                 0x800\n+/* enum: Application license key storage partition */\n+#define\tNVRAM_PARTITION_TYPE_LICENSE              0x900\n+/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */\n+#define\tNVRAM_PARTITION_TYPE_PHY_MIN              0xa00\n+/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */\n+#define\tNVRAM_PARTITION_TYPE_PHY_MAX              0xaff\n+/* enum: Primary FPGA partition */\n+#define\tNVRAM_PARTITION_TYPE_FPGA                 0xb00\n+/* enum: Secondary FPGA partition */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_BACKUP          0xb01\n+/* enum: FC firmware partition */\n+#define\tNVRAM_PARTITION_TYPE_FC_FIRMWARE          0xb02\n+/* enum: FC License partition */\n+#define\tNVRAM_PARTITION_TYPE_FC_LICENSE           0xb03\n+/* enum: Non-volatile log output partition for FC */\n+#define\tNVRAM_PARTITION_TYPE_FC_LOG               0xb04\n+/* enum: MUM firmware partition */\n+#define\tNVRAM_PARTITION_TYPE_MUM_FIRMWARE         0xc00\n+/* enum: MUM Non-volatile log output partition. */\n+#define\tNVRAM_PARTITION_TYPE_MUM_LOG              0xc01\n+/* enum: MUM Application table partition. */\n+#define\tNVRAM_PARTITION_TYPE_MUM_APPTABLE         0xc02\n+/* enum: MUM boot rom partition. */\n+#define\tNVRAM_PARTITION_TYPE_MUM_BOOT_ROM         0xc03\n+/* enum: MUM production signatures & calibration rom partition. */\n+#define\tNVRAM_PARTITION_TYPE_MUM_PROD_ROM         0xc04\n+/* enum: MUM user signatures & calibration rom partition. */\n+#define\tNVRAM_PARTITION_TYPE_MUM_USER_ROM         0xc05\n+/* enum: MUM fuses and lockbits partition. */\n+#define\tNVRAM_PARTITION_TYPE_MUM_FUSELOCK         0xc06\n+/* enum: UEFI expansion ROM if separate from PXE */\n+#define\tNVRAM_PARTITION_TYPE_EXPANSION_UEFI       0xd00\n+/* enum: Spare partition 0 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_0              0x1000\n+/* enum: Used for XIP code of shmbooted images */\n+#define\tNVRAM_PARTITION_TYPE_XIP_SCRATCH          0x1100\n+/* enum: Spare partition 2 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_2              0x1200\n+/* enum: Manufacturing partition. Used during manufacture to pass information\n+ * between XJTAG and Manftest.\n+ */\n+#define\tNVRAM_PARTITION_TYPE_MANUFACTURING        0x1300\n+/* enum: Spare partition 4 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_4              0x1400\n+/* enum: Spare partition 5 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_5              0x1500\n+/* enum: Partition for reporting MC status. See mc_flash_layout.h\n+ * medford_mc_status_hdr_t for layout on Medford.\n+ */\n+#define\tNVRAM_PARTITION_TYPE_STATUS               0x1600\n+/* enum: Start of reserved value range (firmware may use for any purpose) */\n+#define\tNVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN  0xff00\n+/* enum: End of reserved value range (firmware may use for any purpose) */\n+#define\tNVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX  0xfffd\n+/* enum: Recovery partition map (provided if real map is missing or corrupt) */\n+#define\tNVRAM_PARTITION_TYPE_RECOVERY_MAP         0xfffe\n+/* enum: Partition map (real map as stored in flash) */\n+#define\tNVRAM_PARTITION_TYPE_PARTITION_MAP        0xffff\n+#define\tNVRAM_PARTITION_TYPE_ID_LBN 0\n+#define\tNVRAM_PARTITION_TYPE_ID_WIDTH 16\n+\n+/* LICENSED_APP_ID structuredef */\n+#define\tLICENSED_APP_ID_LEN 4\n+#define\tLICENSED_APP_ID_ID_OFST 0\n+/* enum: OpenOnload */\n+#define\tLICENSED_APP_ID_ONLOAD                  0x1\n+/* enum: PTP timestamping */\n+#define\tLICENSED_APP_ID_PTP                     0x2\n+/* enum: SolarCapture Pro */\n+#define\tLICENSED_APP_ID_SOLARCAPTURE_PRO        0x4\n+/* enum: SolarSecure filter engine */\n+#define\tLICENSED_APP_ID_SOLARSECURE             0x8\n+/* enum: Performance monitor */\n+#define\tLICENSED_APP_ID_PERF_MONITOR            0x10\n+/* enum: SolarCapture Live */\n+#define\tLICENSED_APP_ID_SOLARCAPTURE_LIVE       0x20\n+/* enum: Capture SolarSystem */\n+#define\tLICENSED_APP_ID_CAPTURE_SOLARSYSTEM     0x40\n+/* enum: Network Access Control */\n+#define\tLICENSED_APP_ID_NETWORK_ACCESS_CONTROL  0x80\n+/* enum: TCP Direct */\n+#define\tLICENSED_APP_ID_TCP_DIRECT              0x100\n+/* enum: Low Latency */\n+#define\tLICENSED_APP_ID_LOW_LATENCY             0x200\n+/* enum: SolarCapture Tap */\n+#define\tLICENSED_APP_ID_SOLARCAPTURE_TAP        0x400\n+/* enum: Capture SolarSystem 40G */\n+#define\tLICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800\n+/* enum: Capture SolarSystem 1G */\n+#define\tLICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G  0x1000\n+#define\tLICENSED_APP_ID_ID_LBN 0\n+#define\tLICENSED_APP_ID_ID_WIDTH 32\n+\n+/* LICENSED_FEATURES structuredef */\n+#define\tLICENSED_FEATURES_LEN 8\n+/* Bitmask of licensed firmware features */\n+#define\tLICENSED_FEATURES_MASK_OFST 0\n+#define\tLICENSED_FEATURES_MASK_LEN 8\n+#define\tLICENSED_FEATURES_MASK_LO_OFST 0\n+#define\tLICENSED_FEATURES_MASK_HI_OFST 4\n+#define\tLICENSED_FEATURES_RX_CUT_THROUGH_LBN 0\n+#define\tLICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1\n+#define\tLICENSED_FEATURES_PIO_LBN 1\n+#define\tLICENSED_FEATURES_PIO_WIDTH 1\n+#define\tLICENSED_FEATURES_EVQ_TIMER_LBN 2\n+#define\tLICENSED_FEATURES_EVQ_TIMER_WIDTH 1\n+#define\tLICENSED_FEATURES_CLOCK_LBN 3\n+#define\tLICENSED_FEATURES_CLOCK_WIDTH 1\n+#define\tLICENSED_FEATURES_RX_TIMESTAMPS_LBN 4\n+#define\tLICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_FEATURES_TX_TIMESTAMPS_LBN 5\n+#define\tLICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_FEATURES_RX_SNIFF_LBN 6\n+#define\tLICENSED_FEATURES_RX_SNIFF_WIDTH 1\n+#define\tLICENSED_FEATURES_TX_SNIFF_LBN 7\n+#define\tLICENSED_FEATURES_TX_SNIFF_WIDTH 1\n+#define\tLICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8\n+#define\tLICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1\n+#define\tLICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9\n+#define\tLICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tLICENSED_FEATURES_MASK_LBN 0\n+#define\tLICENSED_FEATURES_MASK_WIDTH 64\n+\n+/* LICENSED_V3_APPS structuredef */\n+#define\tLICENSED_V3_APPS_LEN 8\n+/* Bitmask of licensed applications */\n+#define\tLICENSED_V3_APPS_MASK_OFST 0\n+#define\tLICENSED_V3_APPS_MASK_LEN 8\n+#define\tLICENSED_V3_APPS_MASK_LO_OFST 0\n+#define\tLICENSED_V3_APPS_MASK_HI_OFST 4\n+#define\tLICENSED_V3_APPS_ONLOAD_LBN 0\n+#define\tLICENSED_V3_APPS_ONLOAD_WIDTH 1\n+#define\tLICENSED_V3_APPS_PTP_LBN 1\n+#define\tLICENSED_V3_APPS_PTP_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARSECURE_LBN 3\n+#define\tLICENSED_V3_APPS_SOLARSECURE_WIDTH 1\n+#define\tLICENSED_V3_APPS_PERF_MONITOR_LBN 4\n+#define\tLICENSED_V3_APPS_PERF_MONITOR_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1\n+#define\tLICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7\n+#define\tLICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1\n+#define\tLICENSED_V3_APPS_TCP_DIRECT_LBN 8\n+#define\tLICENSED_V3_APPS_TCP_DIRECT_WIDTH 1\n+#define\tLICENSED_V3_APPS_LOW_LATENCY_LBN 9\n+#define\tLICENSED_V3_APPS_LOW_LATENCY_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1\n+#define\tLICENSED_V3_APPS_MASK_LBN 0\n+#define\tLICENSED_V3_APPS_MASK_WIDTH 64\n+\n+/* LICENSED_V3_FEATURES structuredef */\n+#define\tLICENSED_V3_FEATURES_LEN 8\n+/* Bitmask of licensed firmware features */\n+#define\tLICENSED_V3_FEATURES_MASK_OFST 0\n+#define\tLICENSED_V3_FEATURES_MASK_LEN 8\n+#define\tLICENSED_V3_FEATURES_MASK_LO_OFST 0\n+#define\tLICENSED_V3_FEATURES_MASK_HI_OFST 4\n+#define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0\n+#define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_PIO_LBN 1\n+#define\tLICENSED_V3_FEATURES_PIO_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_EVQ_TIMER_LBN 2\n+#define\tLICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_CLOCK_LBN 3\n+#define\tLICENSED_V3_FEATURES_CLOCK_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4\n+#define\tLICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5\n+#define\tLICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_RX_SNIFF_LBN 6\n+#define\tLICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_TX_SNIFF_LBN 7\n+#define\tLICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8\n+#define\tLICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9\n+#define\tLICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_MASK_LBN 0\n+#define\tLICENSED_V3_FEATURES_MASK_WIDTH 64\n+\n+/* TX_TIMESTAMP_EVENT structuredef */\n+#define\tTX_TIMESTAMP_EVENT_LEN 6\n+/* lower 16 bits of timestamp data */\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16\n+/* Type of TX event, ordinary TX completion, low or high part of TX timestamp\n+ */\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1\n+/* enum: This is a TX completion event, not a timestamp */\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_COMPLETION  0x0\n+/* enum: This is the low part of a TX timestamp event */\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO  0x51\n+/* enum: This is the high part of a TX timestamp event */\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI  0x52\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8\n+/* upper 16 bits of timestamp data */\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32\n+#define\tTX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16\n+\n+/* RSS_MODE structuredef */\n+#define\tRSS_MODE_LEN 1\n+/* The RSS mode for a particular packet type is a value from 0 - 15 which can\n+ * be considered as 4 bits selecting which fields are included in the hash. (A\n+ * value 0 effectively disables RSS spreading for the packet type.) The YAML\n+ * generation tools require this structure to be a whole number of bytes wide,\n+ * but only 4 bits are relevant.\n+ */\n+#define\tRSS_MODE_HASH_SELECTOR_OFST 0\n+#define\tRSS_MODE_HASH_SELECTOR_LEN 1\n+#define\tRSS_MODE_HASH_SRC_ADDR_LBN 0\n+#define\tRSS_MODE_HASH_SRC_ADDR_WIDTH 1\n+#define\tRSS_MODE_HASH_DST_ADDR_LBN 1\n+#define\tRSS_MODE_HASH_DST_ADDR_WIDTH 1\n+#define\tRSS_MODE_HASH_SRC_PORT_LBN 2\n+#define\tRSS_MODE_HASH_SRC_PORT_WIDTH 1\n+#define\tRSS_MODE_HASH_DST_PORT_LBN 3\n+#define\tRSS_MODE_HASH_DST_PORT_WIDTH 1\n+#define\tRSS_MODE_HASH_SELECTOR_LBN 0\n+#define\tRSS_MODE_HASH_SELECTOR_WIDTH 8\n+\n+/* CTPIO_STATS_MAP structuredef */\n+#define\tCTPIO_STATS_MAP_LEN 4\n+/* The (function relative) VI number */\n+#define\tCTPIO_STATS_MAP_VI_OFST 0\n+#define\tCTPIO_STATS_MAP_VI_LEN 2\n+#define\tCTPIO_STATS_MAP_VI_LBN 0\n+#define\tCTPIO_STATS_MAP_VI_WIDTH 16\n+/* The target bucket for the VI */\n+#define\tCTPIO_STATS_MAP_BUCKET_OFST 2\n+#define\tCTPIO_STATS_MAP_BUCKET_LEN 2\n+#define\tCTPIO_STATS_MAP_BUCKET_LBN 16\n+#define\tCTPIO_STATS_MAP_BUCKET_WIDTH 16\n+\n+\n+/***********************************/\n+/* MC_CMD_READ_REGS\n+ * Get a dump of the MCPU registers\n+ */\n+#define\tMC_CMD_READ_REGS 0x50\n+#undef\tMC_CMD_0x50_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_READ_REGS_IN msgrequest */\n+#define\tMC_CMD_READ_REGS_IN_LEN 0\n+\n+/* MC_CMD_READ_REGS_OUT msgresponse */\n+#define\tMC_CMD_READ_REGS_OUT_LEN 308\n+/* Whether the corresponding register entry contains a valid value */\n+#define\tMC_CMD_READ_REGS_OUT_MASK_OFST 0\n+#define\tMC_CMD_READ_REGS_OUT_MASK_LEN 16\n+/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,\n+ * fir, fp)\n+ */\n+#define\tMC_CMD_READ_REGS_OUT_REGS_OFST 16\n+#define\tMC_CMD_READ_REGS_OUT_REGS_LEN 4\n+#define\tMC_CMD_READ_REGS_OUT_REGS_NUM 73\n+\n+\n+/***********************************/\n+/* MC_CMD_INIT_EVQ\n+ * Set up an event queue according to the supplied parameters. The IN arguments\n+ * end with an address for each 4k of host memory required to back the EVQ.\n+ */\n+#define\tMC_CMD_INIT_EVQ 0x80\n+#undef\tMC_CMD_0x80_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_INIT_EVQ_IN msgrequest */\n+#define\tMC_CMD_INIT_EVQ_IN_LENMIN 44\n+#define\tMC_CMD_INIT_EVQ_IN_LENMAX 548\n+#define\tMC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_EVQ_IN_SIZE_OFST 0\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4\n+/* The initial timer value. The load value is ignored if the timer mode is DIS.\n+ */\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8\n+/* The reload value is ignored in one-shot modes */\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12\n+/* tbd */\n+#define\tMC_CMD_INIT_EVQ_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0\n+/* enum: Immediate */\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1\n+/* enum: Triggered */\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2\n+/* enum: Hold-off */\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3\n+/* Target EVQ for wakeups if in wakeup mode. */\n+#define\tMC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24\n+/* Target interrupt if in interrupting mode (note union with target EVQ). Use\n+ * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test\n+ * purposes.\n+ */\n+#define\tMC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24\n+/* Event Counter Mode. */\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3\n+/* Event queue packet count threshold. */\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64\n+\n+/* MC_CMD_INIT_EVQ_OUT msgresponse */\n+#define\tMC_CMD_INIT_EVQ_OUT_LEN 4\n+/* Only valid if INTRFLAG was true */\n+#define\tMC_CMD_INIT_EVQ_OUT_IRQ_OFST 0\n+\n+/* MC_CMD_INIT_EVQ_V2_IN msgrequest */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_LENMIN 44\n+#define\tMC_CMD_INIT_EVQ_V2_IN_LENMAX 548\n+#define\tMC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4\n+/* The initial timer value. The load value is ignored if the timer mode is DIS.\n+ */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8\n+/* The reload value is ignored in one-shot modes */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12\n+/* tbd */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4\n+/* enum: All initialisation flags specified by host. */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0\n+/* enum: MEDFORD only. Certain initialisation flags specified by host may be\n+ * over-ridden by firmware based on licenses and firmware variant in order to\n+ * provide the lowest latency achievable. See\n+ * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.\n+ */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1\n+/* enum: MEDFORD only. Certain initialisation flags specified by host may be\n+ * over-ridden by firmware based on licenses and firmware variant in order to\n+ * provide the best throughput achievable. See\n+ * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.\n+ */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2\n+/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by\n+ * firmware based on licenses and firmware variant. See\n+ * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.\n+ */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0\n+/* enum: Immediate */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1\n+/* enum: Triggered */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2\n+/* enum: Hold-off */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3\n+/* Target EVQ for wakeups if in wakeup mode. */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24\n+/* Target interrupt if in interrupting mode (note union with target EVQ). Use\n+ * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test\n+ * purposes.\n+ */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24\n+/* Event Counter Mode. */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2\n+/* enum: Disabled */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3\n+/* Event queue packet count threshold. */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64\n+\n+/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_LEN 8\n+/* Only valid if INTRFLAG was true */\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0\n+/* Actual configuration applied on the card */\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1\n+\n+/* QUEUE_CRC_MODE structuredef */\n+#define\tQUEUE_CRC_MODE_LEN 1\n+#define\tQUEUE_CRC_MODE_MODE_LBN 0\n+#define\tQUEUE_CRC_MODE_MODE_WIDTH 4\n+/* enum: No CRC. */\n+#define\tQUEUE_CRC_MODE_NONE  0x0\n+/* enum: CRC Fiber channel over ethernet. */\n+#define\tQUEUE_CRC_MODE_FCOE  0x1\n+/* enum: CRC (digest) iSCSI header only. */\n+#define\tQUEUE_CRC_MODE_ISCSI_HDR  0x2\n+/* enum: CRC (digest) iSCSI header and payload. */\n+#define\tQUEUE_CRC_MODE_ISCSI  0x3\n+/* enum: CRC Fiber channel over IP over ethernet. */\n+#define\tQUEUE_CRC_MODE_FCOIPOE  0x4\n+/* enum: CRC MPA. */\n+#define\tQUEUE_CRC_MODE_MPA  0x5\n+#define\tQUEUE_CRC_MODE_SPARE_LBN 4\n+#define\tQUEUE_CRC_MODE_SPARE_WIDTH 4\n+\n+\n+/***********************************/\n+/* MC_CMD_INIT_RXQ\n+ * set up a receive queue according to the supplied parameters. The IN\n+ * arguments end with an address for each 4k of host memory required to back\n+ * the RXQ.\n+ */\n+#define\tMC_CMD_INIT_RXQ 0x81\n+#undef\tMC_CMD_0x81_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version\n+ * in new code.\n+ */\n+#define\tMC_CMD_INIT_RXQ_IN_LENMIN 36\n+#define\tMC_CMD_INIT_RXQ_IN_LENMAX 252\n+#define\tMC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_RXQ_IN_SIZE_OFST 0\n+/* The EVQ to send events to. This is an index originally specified to INIT_EVQ\n+ */\n+#define\tMC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4\n+/* The value to put in the event data. Check hardware spec. for valid range. */\n+#define\tMC_CMD_INIT_RXQ_IN_LABEL_OFST 8\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12\n+/* There will be more flags here. */\n+#define\tMC_CMD_INIT_RXQ_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3\n+#define\tMC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_UNUSED_LBN 10\n+#define\tMC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1\n+/* Owner ID to use if in buffer mode (zero if physical) */\n+#define\tMC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20\n+/* The port ID associated with the v-adaptor which should contain this DMAQ. */\n+#define\tMC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28\n+\n+/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode\n+ * flags\n+ */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_LEN 544\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0\n+/* The EVQ to send events to. This is an index originally specified to INIT_EVQ\n+ */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4\n+/* The value to put in the event data. Check hardware spec. for valid range. */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12\n+/* There will be more flags here. */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4\n+/* enum: One packet per descriptor (for normal networking) */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET  0x0\n+/* enum: Pack multiple packets into large descriptors (for SolarCapture) */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM  0x1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M  0x0 /* enum */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K  0x1 /* enum */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K  0x2 /* enum */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K  0x3 /* enum */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K  0x4 /* enum */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n+/* Owner ID to use if in buffer mode (zero if physical) */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20\n+/* The port ID associated with the v-adaptor which should contain this DMAQ. */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64\n+/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540\n+\n+/* MC_CMD_INIT_RXQ_OUT msgresponse */\n+#define\tMC_CMD_INIT_RXQ_OUT_LEN 0\n+\n+/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */\n+#define\tMC_CMD_INIT_RXQ_EXT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_INIT_TXQ\n+ */\n+#define\tMC_CMD_INIT_TXQ 0x82\n+#undef\tMC_CMD_0x82_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version\n+ * in new code.\n+ */\n+#define\tMC_CMD_INIT_TXQ_IN_LENMIN 36\n+#define\tMC_CMD_INIT_TXQ_IN_LENMAX 252\n+#define\tMC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_TXQ_IN_SIZE_OFST 0\n+/* The EVQ to send events to. This is an index originally specified to\n+ * INIT_EVQ.\n+ */\n+#define\tMC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4\n+/* The value to put in the event data. Check hardware spec. for valid range. */\n+#define\tMC_CMD_INIT_TXQ_IN_LABEL_OFST 8\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12\n+/* There will be more flags here. */\n+#define\tMC_CMD_INIT_TXQ_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4\n+#define\tMC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1\n+/* Owner ID to use if in buffer mode (zero if physical) */\n+#define\tMC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20\n+/* The port ID associated with the v-adaptor which should contain this DMAQ. */\n+#define\tMC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28\n+\n+/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode\n+ * flags\n+ */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_LEN 544\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0\n+/* The EVQ to send events to. This is an index originally specified to\n+ * INIT_EVQ.\n+ */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4\n+/* The value to put in the event data. Check hardware spec. for valid range. */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12\n+/* There will be more flags here. */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1\n+/* Owner ID to use if in buffer mode (zero if physical) */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20\n+/* The port ID associated with the v-adaptor which should contain this DMAQ. */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64\n+/* Flags related to Qbb flow control mode. */\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3\n+\n+/* MC_CMD_INIT_TXQ_OUT msgresponse */\n+#define\tMC_CMD_INIT_TXQ_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_FINI_EVQ\n+ * Teardown an EVQ.\n+ *\n+ * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first\n+ * or the operation will fail with EBUSY\n+ */\n+#define\tMC_CMD_FINI_EVQ 0x83\n+#undef\tMC_CMD_0x83_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_FINI_EVQ_IN msgrequest */\n+#define\tMC_CMD_FINI_EVQ_IN_LEN 4\n+/* Instance of EVQ to destroy. Should be the same instance as that previously\n+ * passed to INIT_EVQ\n+ */\n+#define\tMC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0\n+\n+/* MC_CMD_FINI_EVQ_OUT msgresponse */\n+#define\tMC_CMD_FINI_EVQ_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_FINI_RXQ\n+ * Teardown a RXQ.\n+ */\n+#define\tMC_CMD_FINI_RXQ 0x84\n+#undef\tMC_CMD_0x84_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_FINI_RXQ_IN msgrequest */\n+#define\tMC_CMD_FINI_RXQ_IN_LEN 4\n+/* Instance of RXQ to destroy */\n+#define\tMC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0\n+\n+/* MC_CMD_FINI_RXQ_OUT msgresponse */\n+#define\tMC_CMD_FINI_RXQ_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_FINI_TXQ\n+ * Teardown a TXQ.\n+ */\n+#define\tMC_CMD_FINI_TXQ 0x85\n+#undef\tMC_CMD_0x85_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_FINI_TXQ_IN msgrequest */\n+#define\tMC_CMD_FINI_TXQ_IN_LEN 4\n+/* Instance of TXQ to destroy */\n+#define\tMC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0\n+\n+/* MC_CMD_FINI_TXQ_OUT msgresponse */\n+#define\tMC_CMD_FINI_TXQ_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_DRIVER_EVENT\n+ * Generate an event on an EVQ belonging to the function issuing the command.\n+ */\n+#define\tMC_CMD_DRIVER_EVENT 0x86\n+#undef\tMC_CMD_0x86_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_DRIVER_EVENT_IN msgrequest */\n+#define\tMC_CMD_DRIVER_EVENT_IN_LEN 12\n+/* Handle of target EVQ */\n+#define\tMC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0\n+/* Bits 0 - 63 of event */\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_OFST 4\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_LEN 8\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8\n+\n+/* MC_CMD_DRIVER_EVENT_OUT msgresponse */\n+#define\tMC_CMD_DRIVER_EVENT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PROXY_CMD\n+ * Execute an arbitrary MCDI command on behalf of a different function, subject\n+ * to security restrictions. The command to be proxied follows immediately\n+ * afterward in the host buffer (or on the UART). This command supercedes\n+ * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.\n+ */\n+#define\tMC_CMD_PROXY_CMD 0x5b\n+#undef\tMC_CMD_0x5b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PROXY_CMD_IN msgrequest */\n+#define\tMC_CMD_PROXY_CMD_IN_LEN 4\n+/* The handle of the target function. */\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_OFST 0\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16\n+#define\tMC_CMD_PROXY_CMD_IN_VF_NULL  0xffff /* enum */\n+\n+/* MC_CMD_PROXY_CMD_OUT msgresponse */\n+#define\tMC_CMD_PROXY_CMD_OUT_LEN 0\n+\n+/* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to\n+ * manage proxied requests\n+ */\n+#define\tMC_PROXY_STATUS_BUFFER_LEN 16\n+/* Handle allocated by the firmware for this proxy transaction */\n+#define\tMC_PROXY_STATUS_BUFFER_HANDLE_OFST 0\n+/* enum: An invalid handle. */\n+#define\tMC_PROXY_STATUS_BUFFER_HANDLE_INVALID  0x0\n+#define\tMC_PROXY_STATUS_BUFFER_HANDLE_LBN 0\n+#define\tMC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32\n+/* The requesting physical function number */\n+#define\tMC_PROXY_STATUS_BUFFER_PF_OFST 4\n+#define\tMC_PROXY_STATUS_BUFFER_PF_LEN 2\n+#define\tMC_PROXY_STATUS_BUFFER_PF_LBN 32\n+#define\tMC_PROXY_STATUS_BUFFER_PF_WIDTH 16\n+/* The requesting virtual function number. Set to VF_NULL if the target is a\n+ * PF.\n+ */\n+#define\tMC_PROXY_STATUS_BUFFER_VF_OFST 6\n+#define\tMC_PROXY_STATUS_BUFFER_VF_LEN 2\n+#define\tMC_PROXY_STATUS_BUFFER_VF_LBN 48\n+#define\tMC_PROXY_STATUS_BUFFER_VF_WIDTH 16\n+/* The target function RID. */\n+#define\tMC_PROXY_STATUS_BUFFER_RID_OFST 8\n+#define\tMC_PROXY_STATUS_BUFFER_RID_LEN 2\n+#define\tMC_PROXY_STATUS_BUFFER_RID_LBN 64\n+#define\tMC_PROXY_STATUS_BUFFER_RID_WIDTH 16\n+/* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */\n+#define\tMC_PROXY_STATUS_BUFFER_STATUS_OFST 10\n+#define\tMC_PROXY_STATUS_BUFFER_STATUS_LEN 2\n+#define\tMC_PROXY_STATUS_BUFFER_STATUS_LBN 80\n+#define\tMC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16\n+/* If a request is authorized rather than carried out by the host, this is the\n+ * elevated privilege mask granted to the requesting function.\n+ */\n+#define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12\n+#define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96\n+#define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_PROXY_CONFIGURE\n+ * Enable/disable authorization of MCDI requests from unprivileged functions by\n+ * a designated admin function\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE 0x58\n+#undef\tMC_CMD_0x58_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PROXY_CONFIGURE_IN msgrequest */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_LEN 108\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1\n+/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n+ * of blocks, each of the size REQUEST_BLOCK_SIZE.\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8\n+/* Must be a power of 2 */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12\n+/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n+ * of blocks, each of the size REPLY_BLOCK_SIZE.\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20\n+/* Must be a power of 2 */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24\n+/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n+ * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if\n+ * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32\n+/* Must be a power of 2, or zero if this buffer is not provided */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36\n+/* Applies to all three buffers */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40\n+/* A bit mask defining which MCDI operations may be proxied */\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64\n+\n+/* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1\n+/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n+ * of blocks, each of the size REQUEST_BLOCK_SIZE.\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8\n+/* Must be a power of 2 */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12\n+/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n+ * of blocks, each of the size REPLY_BLOCK_SIZE.\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20\n+/* Must be a power of 2 */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24\n+/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n+ * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if\n+ * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.\n+ */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32\n+/* Must be a power of 2, or zero if this buffer is not provided */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36\n+/* Applies to all three buffers */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40\n+/* A bit mask defining which MCDI operations may be proxied */\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108\n+\n+/* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */\n+#define\tMC_CMD_PROXY_CONFIGURE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PROXY_COMPLETE\n+ * Tells FW that a requested proxy operation has either been completed (by\n+ * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the\n+ * function that enabled proxying/authorization (by using\n+ * MC_CMD_PROXY_CONFIGURE).\n+ */\n+#define\tMC_CMD_PROXY_COMPLETE 0x5f\n+#undef\tMC_CMD_0x5f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PROXY_COMPLETE_IN msgrequest */\n+#define\tMC_CMD_PROXY_COMPLETE_IN_LEN 12\n+#define\tMC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0\n+#define\tMC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4\n+/* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply\n+ * is stored in the REPLY_BUFF.\n+ */\n+#define\tMC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0\n+/* enum: The operation has been authorized. The originating function may now\n+ * try again.\n+ */\n+#define\tMC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1\n+/* enum: The operation has been declined. */\n+#define\tMC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2\n+/* enum: The authorization failed because the relevant application did not\n+ * respond in time.\n+ */\n+#define\tMC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3\n+#define\tMC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8\n+\n+/* MC_CMD_PROXY_COMPLETE_OUT msgresponse */\n+#define\tMC_CMD_PROXY_COMPLETE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_ALLOC_BUFTBL_CHUNK\n+ * Allocate a set of buffer table entries using the specified owner ID. This\n+ * operation allocates the required buffer table entries (and fails if it\n+ * cannot do so). The buffer table entries will initially be zeroed.\n+ */\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK 0x87\n+#undef\tMC_CMD_0x87_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8\n+/* Owner ID to use */\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0\n+/* Size of buffer table pages to use, in bytes (note that only a few values are\n+ * legal on any specific hardware).\n+ */\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4\n+\n+/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4\n+/* Buffer table IDs for use in DMA descriptors. */\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_PROGRAM_BUFTBL_ENTRIES\n+ * Reprogram a set of buffer table entries in the specified chunk.\n+ */\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88\n+#undef\tMC_CMD_0x88_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0\n+/* ID */\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4\n+/* Num entries */\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8\n+/* Buffer table entry address */\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32\n+\n+/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_FREE_BUFTBL_CHUNK\n+ */\n+#define\tMC_CMD_FREE_BUFTBL_CHUNK 0x89\n+#undef\tMC_CMD_0x89_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */\n+#define\tMC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4\n+#define\tMC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0\n+\n+/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */\n+#define\tMC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0\n+\n+/* PORT_CONFIG_ENTRY structuredef */\n+#define\tPORT_CONFIG_ENTRY_LEN 16\n+/* External port number (label) */\n+#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0\n+#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1\n+#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0\n+#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8\n+/* Port core location */\n+#define\tPORT_CONFIG_ENTRY_CORE_OFST 1\n+#define\tPORT_CONFIG_ENTRY_CORE_LEN 1\n+#define\tPORT_CONFIG_ENTRY_STANDALONE  0x0 /* enum */\n+#define\tPORT_CONFIG_ENTRY_MASTER  0x1 /* enum */\n+#define\tPORT_CONFIG_ENTRY_SLAVE  0x2 /* enum */\n+#define\tPORT_CONFIG_ENTRY_CORE_LBN 8\n+#define\tPORT_CONFIG_ENTRY_CORE_WIDTH 8\n+/* Internal number (HW resource) relative to the core */\n+#define\tPORT_CONFIG_ENTRY_INT_NUMBER_OFST 2\n+#define\tPORT_CONFIG_ENTRY_INT_NUMBER_LEN 1\n+#define\tPORT_CONFIG_ENTRY_INT_NUMBER_LBN 16\n+#define\tPORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8\n+/* Reserved */\n+#define\tPORT_CONFIG_ENTRY_RSVD_OFST 3\n+#define\tPORT_CONFIG_ENTRY_RSVD_LEN 1\n+#define\tPORT_CONFIG_ENTRY_RSVD_LBN 24\n+#define\tPORT_CONFIG_ENTRY_RSVD_WIDTH 8\n+/* Bitmask of KR lanes used by the port */\n+#define\tPORT_CONFIG_ENTRY_LANES_OFST 4\n+#define\tPORT_CONFIG_ENTRY_LANES_LBN 32\n+#define\tPORT_CONFIG_ENTRY_LANES_WIDTH 32\n+/* Port capabilities (MC_CMD_PHY_CAP_*) */\n+#define\tPORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8\n+#define\tPORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64\n+#define\tPORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32\n+/* Reserved (align to 16 bytes) */\n+#define\tPORT_CONFIG_ENTRY_RSVD2_OFST 12\n+#define\tPORT_CONFIG_ENTRY_RSVD2_LBN 96\n+#define\tPORT_CONFIG_ENTRY_RSVD2_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_FILTER_OP\n+ * Multiplexed MCDI call for filter operations\n+ */\n+#define\tMC_CMD_FILTER_OP 0x8a\n+#undef\tMC_CMD_0x8a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_FILTER_OP_IN msgrequest */\n+#define\tMC_CMD_FILTER_OP_IN_LEN 108\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_FILTER_OP_IN_OP_OFST 0\n+/* enum: single-recipient filter insert */\n+#define\tMC_CMD_FILTER_OP_IN_OP_INSERT  0x0\n+/* enum: single-recipient filter remove */\n+#define\tMC_CMD_FILTER_OP_IN_OP_REMOVE  0x1\n+/* enum: multi-recipient filter subscribe */\n+#define\tMC_CMD_FILTER_OP_IN_OP_SUBSCRIBE  0x2\n+/* enum: multi-recipient filter unsubscribe */\n+#define\tMC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE  0x3\n+/* enum: replace one recipient with another (warning - the filter handle may\n+ * change)\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_OP_REPLACE  0x4\n+/* filter handle (for remove / unsubscribe operations) */\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_OFST 4\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_LEN 8\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8\n+/* The port ID associated with the v-adaptor which should contain this filter.\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_PORT_ID_OFST 12\n+/* fields to include in match criteria */\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n+/* receive destination */\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_OFST 20\n+/* enum: drop packets */\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_DROP  0x0\n+/* enum: receive to host */\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_HOST  0x1\n+/* enum: receive to MC */\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_MC  0x2\n+/* enum: loop back to TXDP 0 */\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_TX0  0x3\n+/* enum: loop back to TXDP 1 */\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_TX1  0x4\n+/* receive queue handle (for multiple queue modes, this is the base queue) */\n+#define\tMC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24\n+/* receive mode */\n+#define\tMC_CMD_FILTER_OP_IN_RX_MODE_OFST 28\n+/* enum: receive to just the specified queue */\n+#define\tMC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE  0x0\n+/* enum: receive to multiple queues using RSS context */\n+#define\tMC_CMD_FILTER_OP_IN_RX_MODE_RSS  0x1\n+/* enum: receive to multiple queues using .1p mapping */\n+#define\tMC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING  0x2\n+/* enum: install a filter entry that will never match; for test purposes only\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH  0x80000000\n+/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for\n+ * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or\n+ * MC_CMD_DOT1P_MAPPING_ALLOC.\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32\n+/* transmit domain (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36\n+/* transmit destination (either set the MAC and/or PM bits for explicit\n+ * control, or set this field to TX_DEST_DEFAULT for sensible default\n+ * behaviour)\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_OFST 40\n+/* enum: request default behaviour (based on filter type) */\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT  0xffffffff\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1\n+/* source MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44\n+#define\tMC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6\n+/* source port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50\n+#define\tMC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2\n+/* destination MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_DST_MAC_OFST 52\n+#define\tMC_CMD_FILTER_OP_IN_DST_MAC_LEN 6\n+/* destination port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_DST_PORT_OFST 58\n+#define\tMC_CMD_FILTER_OP_IN_DST_PORT_LEN 2\n+/* Ethernet type to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60\n+#define\tMC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2\n+/* Inner VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62\n+#define\tMC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2\n+/* Outer VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64\n+#define\tMC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2\n+/* IP protocol to match (in low byte; set high byte to 0) */\n+#define\tMC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66\n+#define\tMC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2\n+/* Firmware defined register 0 to match (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_IN_FWDEF0_OFST 68\n+/* Firmware defined register 1 to match (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_IN_FWDEF1_OFST 72\n+/* source IP address to match (as bytes in network order; set last 12 bytes to\n+ * 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_SRC_IP_OFST 76\n+#define\tMC_CMD_FILTER_OP_IN_SRC_IP_LEN 16\n+/* destination IP address to match (as bytes in network order; set last 12\n+ * bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_IN_DST_IP_OFST 92\n+#define\tMC_CMD_FILTER_OP_IN_DST_IP_LEN 16\n+\n+/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to\n+ * include handling of VXLAN/NVGRE encapsulated frame filtering (which is\n+ * supported on Medford only).\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_LEN 172\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_OP_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FILTER_OP_IN/OP */\n+/* filter handle (for remove / unsubscribe operations) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8\n+/* The port ID associated with the v-adaptor which should contain this filter.\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12\n+/* fields to include in match criteria */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n+/* receive destination */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20\n+/* enum: drop packets */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP  0x0\n+/* enum: receive to host */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST  0x1\n+/* enum: receive to MC */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC  0x2\n+/* enum: loop back to TXDP 0 */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0  0x3\n+/* enum: loop back to TXDP 1 */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1  0x4\n+/* receive queue handle (for multiple queue modes, this is the base queue) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24\n+/* receive mode */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28\n+/* enum: receive to just the specified queue */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE  0x0\n+/* enum: receive to multiple queues using RSS context */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS  0x1\n+/* enum: receive to multiple queues using .1p mapping */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING  0x2\n+/* enum: install a filter entry that will never match; for test purposes only\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH  0x80000000\n+/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for\n+ * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or\n+ * MC_CMD_DOT1P_MAPPING_ALLOC.\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32\n+/* transmit domain (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36\n+/* transmit destination (either set the MAC and/or PM bits for explicit\n+ * control, or set this field to TX_DEST_DEFAULT for sensible default\n+ * behaviour)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40\n+/* enum: request default behaviour (based on filter type) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT  0xffffffff\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1\n+/* source MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44\n+#define\tMC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6\n+/* source port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50\n+#define\tMC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2\n+/* destination MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52\n+#define\tMC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6\n+/* destination port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58\n+#define\tMC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2\n+/* Ethernet type to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60\n+#define\tMC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2\n+/* Inner VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62\n+#define\tMC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2\n+/* Outer VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64\n+#define\tMC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2\n+/* IP protocol to match (in low byte; set high byte to 0) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2\n+/* Firmware defined register 0 to match (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68\n+/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP\n+ * protocol is GRE) to match (as bytes in network order; set last byte to 0 for\n+ * VXLAN/NVGRE, or 1 for Geneve)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8\n+/* enum: Match VXLAN traffic with this VNI */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN  0x0\n+/* enum: Match Geneve traffic with this VNI */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE  0x1\n+/* enum: Reserved for experimental development use */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL  0xfe\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8\n+/* enum: Match NVGRE traffic with this VSID */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE  0x0\n+/* source IP address to match (as bytes in network order; set last 12 bytes to\n+ * 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76\n+#define\tMC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16\n+/* destination IP address to match (as bytes in network order; set last 12\n+ * bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92\n+#define\tMC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16\n+/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network\n+ * order)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6\n+/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2\n+/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in\n+ * network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6\n+/* VXLAN/NVGRE inner frame destination port to match (as bytes in network\n+ * order)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2\n+/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2\n+/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2\n+/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2\n+/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to\n+ * 0)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2\n+/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set\n+ * to 0)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132\n+/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set\n+ * to 0)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136\n+/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network\n+ * order; set last 12 bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16\n+/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network\n+ * order; set last 12 bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16\n+\n+/* MC_CMD_FILTER_OP_OUT msgresponse */\n+#define\tMC_CMD_FILTER_OP_OUT_LEN 12\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_FILTER_OP_OUT_OP_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FILTER_OP_IN/OP */\n+/* Returned filter handle (for insert / subscribe operations). Note that these\n+ * handles should be considered opaque to the host, although a value of\n+ * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.\n+ */\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_OFST 4\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_LEN 8\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8\n+/* enum: guaranteed invalid filter handle (low 32 bits) */\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID  0xffffffff\n+/* enum: guaranteed invalid filter handle (high 32 bits) */\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID  0xffffffff\n+\n+/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_LEN 12\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FILTER_OP_EXT_IN/OP */\n+/* Returned filter handle (for insert / subscribe operations). Note that these\n+ * handles should be considered opaque to the host, although a value of\n+ * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.\n+ */\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FILTER_OP_OUT/HANDLE */\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PARSER_DISP_INFO\n+ * Get information related to the parser-dispatcher subsystem\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO 0xe4\n+#undef\tMC_CMD_0xe4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0\n+/* enum: read the list of supported RX filter matches */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES  0x1\n+/* enum: read flags indicating restrictions on filter insertion for the calling\n+ * client\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS  0x2\n+/* enum: read properties relating to security rules (Medford-only; for use by\n+ * SolarSecure apps, not directly by drivers. See SF-114946-SW.)\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO  0x3\n+/* enum: read the list of supported RX filter matches for VXLAN/NVGRE\n+ * encapsulated frames, which follow a different match sequence to normal\n+ * frames (Medford only)\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES  0x4\n+\n+/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n+/* number of supported match types */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4\n+/* array of supported match types (valid MATCH_FIELDS values for\n+ * MC_CMD_FILTER_OP) sorted in decreasing priority order\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61\n+\n+/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n+/* bitfield of filter insertion restrictions */\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1\n+\n+/* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse:\n+ * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO.\n+ * (Medford-only; for use by SolarSecure apps, not directly by drivers. See\n+ * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet\n+ * been used in any released code and may change during development. This note\n+ * will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n+/* a version number representing the set of rule lookups that are implemented\n+ * by the currently running firmware\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4\n+/* enum: implements lookup sequences described in SF-114946-SW draft C */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C  0x0\n+/* the number of nodes in the subnet map */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8\n+/* the number of entries in one subnet map node */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12\n+/* minimum valid value for a subnet ID in a subnet map leaf */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16\n+/* maximum valid value for a subnet ID in a subnet map leaf */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20\n+/* the number of entries in the local and remote port range maps */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24\n+/* minimum valid value for a portrange ID in a port range map leaf */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28\n+/* maximum valid value for a portrange ID in a port range map leaf */\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32\n+\n+\n+/***********************************/\n+/* MC_CMD_PARSER_DISP_RW\n+ * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.\n+ * Please note that this interface is only of use to debug tools which have\n+ * knowledge of firmware and hardware data structures; nothing here is intended\n+ * for use by normal driver code.\n+ */\n+#define\tMC_CMD_PARSER_DISP_RW 0xe5\n+#undef\tMC_CMD_0xe5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PARSER_DISP_RW_IN msgrequest */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LEN 32\n+/* identifies the target of the operation */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0\n+/* enum: RX dispatcher CPU */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_RX_DICPU  0x0\n+/* enum: TX dispatcher CPU */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_TX_DICPU  0x1\n+/* enum: Lookup engine (with original metadata format) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LUE  0x2\n+/* enum: Lookup engine (with requested metadata format) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA  0x3\n+/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_RX0_DICPU  0x0\n+/* enum: RX1 dispatcher CPU (only valid for Medford) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_RX1_DICPU  0x4\n+/* enum: Miscellaneous other state (only valid for Medford) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_MISC_STATE  0x5\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_OP_OFST 4\n+/* enum: read a word of DICPU DMEM or a LUE entry */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_READ  0x0\n+/* enum: write a word of DICPU DMEM or a LUE entry */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_WRITE  0x1\n+/* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_RMW  0x2\n+/* data memory address (DICPU targets) or LUE index (LUE targets) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8\n+/* selector (for MISC_STATE target) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8\n+/* enum: Port to datapath mapping */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING  0x1\n+/* value to write (for DMEM writes) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12\n+/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12\n+/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16\n+/* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12\n+/* value to write (for LUE writes) */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20\n+\n+/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_LEN 52\n+/* value read (for DMEM reads) */\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0\n+/* value read (for LUE reads) */\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20\n+/* up to 8 32-bit words of additional soft state from the LUE manager (the\n+ * exact content is firmware-dependent and intended only for debug use)\n+ */\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32\n+/* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_DP0  0x1 /* enum */\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_DP1  0x2 /* enum */\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PF_COUNT\n+ * Get number of PFs on the device.\n+ */\n+#define\tMC_CMD_GET_PF_COUNT 0xb6\n+#undef\tMC_CMD_0xb6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PF_COUNT_IN msgrequest */\n+#define\tMC_CMD_GET_PF_COUNT_IN_LEN 0\n+\n+/* MC_CMD_GET_PF_COUNT_OUT msgresponse */\n+#define\tMC_CMD_GET_PF_COUNT_OUT_LEN 1\n+/* Identifies the number of PFs on the device. */\n+#define\tMC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0\n+#define\tMC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_PF_COUNT\n+ * Set number of PFs on the device.\n+ */\n+#define\tMC_CMD_SET_PF_COUNT 0xb7\n+\n+/* MC_CMD_SET_PF_COUNT_IN msgrequest */\n+#define\tMC_CMD_SET_PF_COUNT_IN_LEN 4\n+/* New number of PFs on the device. */\n+#define\tMC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0\n+\n+/* MC_CMD_SET_PF_COUNT_OUT msgresponse */\n+#define\tMC_CMD_SET_PF_COUNT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PORT_ASSIGNMENT\n+ * Get port assignment for current PCI function.\n+ */\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT 0xb8\n+#undef\tMC_CMD_0xb8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0\n+\n+/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4\n+/* Identifies the port assignment for this function. */\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_PORT_ASSIGNMENT\n+ * Set port assignment for current PCI function.\n+ */\n+#define\tMC_CMD_SET_PORT_ASSIGNMENT 0xb9\n+#undef\tMC_CMD_0xb9_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */\n+#define\tMC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4\n+/* Identifies the port assignment for this function. */\n+#define\tMC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0\n+\n+/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */\n+#define\tMC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_ALLOC_VIS\n+ * Allocate VIs for current PCI function.\n+ */\n+#define\tMC_CMD_ALLOC_VIS 0x8b\n+#undef\tMC_CMD_0x8b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_ALLOC_VIS_IN msgrequest */\n+#define\tMC_CMD_ALLOC_VIS_IN_LEN 8\n+/* The minimum number of VIs that is acceptable */\n+#define\tMC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0\n+/* The maximum number of VIs that would be useful */\n+#define\tMC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4\n+\n+/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.\n+ * Use extended version in new code.\n+ */\n+#define\tMC_CMD_ALLOC_VIS_OUT_LEN 8\n+/* The number of VIs allocated on this function */\n+#define\tMC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0\n+/* The base absolute VI number allocated to this function. Required to\n+ * correctly interpret wakeup events.\n+ */\n+#define\tMC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4\n+\n+/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_LEN 12\n+/* The number of VIs allocated on this function */\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0\n+/* The base absolute VI number allocated to this function. Required to\n+ * correctly interpret wakeup events.\n+ */\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4\n+/* Function's port vi_shift value (always 0 on Huntington) */\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_FREE_VIS\n+ * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,\n+ * but not freed.\n+ */\n+#define\tMC_CMD_FREE_VIS 0x8c\n+#undef\tMC_CMD_0x8c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_FREE_VIS_IN msgrequest */\n+#define\tMC_CMD_FREE_VIS_IN_LEN 0\n+\n+/* MC_CMD_FREE_VIS_OUT msgresponse */\n+#define\tMC_CMD_FREE_VIS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_SRIOV_CFG\n+ * Get SRIOV config for this PF.\n+ */\n+#define\tMC_CMD_GET_SRIOV_CFG 0xba\n+#undef\tMC_CMD_0xba_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */\n+#define\tMC_CMD_GET_SRIOV_CFG_IN_LEN 0\n+\n+/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_LEN 20\n+/* Number of VFs currently enabled. */\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0\n+/* Max number of VFs before sriov stride and offset may need to be changed. */\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1\n+/* RID offset of first VF from PF. */\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12\n+/* RID offset of each subsequent VF from the previous. */\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_SRIOV_CFG\n+ * Set SRIOV config for this PF.\n+ */\n+#define\tMC_CMD_SET_SRIOV_CFG 0xbb\n+#undef\tMC_CMD_0xbb_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_LEN 20\n+/* Number of VFs currently enabled. */\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0\n+/* Max number of VFs before sriov stride and offset may need to be changed. */\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1\n+/* RID offset of first VF from PF, or 0 for no change, or\n+ * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.\n+ */\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12\n+/* RID offset of each subsequent VF from the previous, 0 for no change, or\n+ * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.\n+ */\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16\n+\n+/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */\n+#define\tMC_CMD_SET_SRIOV_CFG_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_VI_ALLOC_INFO\n+ * Get information about number of VI's and base VI number allocated to this\n+ * function.\n+ */\n+#define\tMC_CMD_GET_VI_ALLOC_INFO 0x8d\n+#undef\tMC_CMD_0x8d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0\n+\n+/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12\n+/* The number of VIs allocated on this function */\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0\n+/* The base absolute VI number allocated to this function. Required to\n+ * correctly interpret wakeup events.\n+ */\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4\n+/* Function's port vi_shift value (always 0 on Huntington) */\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_DUMP_VI_STATE\n+ * For CmdClient use. Dump pertinent information on a specific absolute VI.\n+ */\n+#define\tMC_CMD_DUMP_VI_STATE 0x8e\n+#undef\tMC_CMD_0x8e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_DUMP_VI_STATE_IN msgrequest */\n+#define\tMC_CMD_DUMP_VI_STATE_IN_LEN 4\n+/* The VI number to query. */\n+#define\tMC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0\n+\n+/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_LEN 96\n+/* The PF part of the function owning this VI. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2\n+/* The VF part of the function owning this VI. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2\n+/* Base of VIs allocated to this function. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2\n+/* Count of VIs allocated to the owner function. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2\n+/* Base interrupt vector allocated to this function. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2\n+/* Number of interrupt vectors allocated to this function. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2\n+/* Raw evq ptr table data. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16\n+/* Raw evq timer table data. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24\n+/* Combined metadata field. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8\n+/* TXDPCPU raw table data for queue. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36\n+/* TXDPCPU raw table data for queue. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44\n+/* TXDPCPU raw table data for queue. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52\n+/* Combined metadata field. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24\n+/* RXDPCPU raw table data for queue. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68\n+/* RXDPCPU raw table data for queue. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76\n+/* Reserved, currently 0. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84\n+/* Combined metadata field. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8\n+\n+\n+/***********************************/\n+/* MC_CMD_ALLOC_PIOBUF\n+ * Allocate a push I/O buffer for later use with a tx queue.\n+ */\n+#define\tMC_CMD_ALLOC_PIOBUF 0x8f\n+#undef\tMC_CMD_0x8f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */\n+#define\tMC_CMD_ALLOC_PIOBUF_IN_LEN 0\n+\n+/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */\n+#define\tMC_CMD_ALLOC_PIOBUF_OUT_LEN 4\n+/* Handle for allocated push I/O buffer. */\n+#define\tMC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_FREE_PIOBUF\n+ * Free a push I/O buffer.\n+ */\n+#define\tMC_CMD_FREE_PIOBUF 0x90\n+#undef\tMC_CMD_0x90_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_FREE_PIOBUF_IN msgrequest */\n+#define\tMC_CMD_FREE_PIOBUF_IN_LEN 4\n+/* Handle for allocated push I/O buffer. */\n+#define\tMC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0\n+\n+/* MC_CMD_FREE_PIOBUF_OUT msgresponse */\n+#define\tMC_CMD_FREE_PIOBUF_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_VI_TLP_PROCESSING\n+ * Get TLP steering and ordering information for a VI.\n+ */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING 0xb0\n+#undef\tMC_CMD_0xb0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4\n+/* VI number to get information for. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0\n+\n+/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4\n+/* Transaction processing steering hint 1 for use with the Rx Queue. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1\n+/* Transaction processing steering hint 2 for use with the Ev Queue. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1\n+/* Use Relaxed ordering model for TLPs on this VI. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1\n+/* Use ID based ordering for TLPs on this VI. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1\n+/* Set no snoop bit for TLPs on this VI. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1\n+/* Enable TPH for TLPs on this VI. */\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_VI_TLP_PROCESSING\n+ * Set TLP steering and ordering information for a VI.\n+ */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING 0xb1\n+#undef\tMC_CMD_0xb1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8\n+/* VI number to set information for. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0\n+/* Transaction processing steering hint 1 for use with the Rx Queue. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1\n+/* Transaction processing steering hint 2 for use with the Ev Queue. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1\n+/* Use Relaxed ordering model for TLPs on this VI. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1\n+/* Use ID based ordering for TLPs on this VI. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1\n+/* Set the no snoop bit for TLPs on this VI. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1\n+/* Enable TPH for TLPs on this VI. */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4\n+\n+/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_TLP_PROCESSING_GLOBALS\n+ * Get global PCIe steering and transaction processing configuration.\n+ */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc\n+#undef\tMC_CMD_0xbc_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0\n+/* enum: MISC. */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC  0x0\n+/* enum: IDO. */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO  0x1\n+/* enum: RO. */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO  0x2\n+/* enum: TPH Type. */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE  0x3\n+\n+/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */\n+/* Amalgamated TLP info word. */\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_TLP_PROCESSING_GLOBALS\n+ * Set global PCIe steering and transaction processing configuration.\n+ */\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd\n+#undef\tMC_CMD_0xbd_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */\n+/* Amalgamated TLP info word. */\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22\n+\n+/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SATELLITE_DOWNLOAD\n+ * Download a new set of images to the satellite CPUs from the host.\n+ */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD 0x91\n+#undef\tMC_CMD_0x91_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs\n+ * are subtle, and so downloads must proceed in a number of phases.\n+ *\n+ * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.\n+ *\n+ * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download\n+ * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should\n+ * be a checksum (a simple 32-bit sum) of the transferred data. An individual\n+ * download may be aborted using CHUNK_ID_ABORT.\n+ *\n+ * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),\n+ * similar to PHASE_IMEMS.\n+ *\n+ * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.\n+ *\n+ * After any error (a requested abort is not considered to be an error) the\n+ * sequence must be restarted from PHASE_RESET.\n+ */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))\n+/* Download phase. (Note: the IDLE phase is used internally and is never valid\n+ * in a command from the host.)\n+ */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE     0x0 /* enum */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET    0x1 /* enum */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS    0x2 /* enum */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS  0x3 /* enum */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY    0x4 /* enum */\n+/* Target for download. (These match the blob numbers defined in\n+ * mc_flash_layout.h.)\n+ */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT  0x0\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT  0x1\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT  0x2\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT  0x3\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT  0x4\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG  0x5\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT  0x6\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG  0x7\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM  0x8\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM  0x9\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM  0xa\n+/* enum: Valid in phase 2 (PHASE_IMEMS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM  0xb\n+/* enum: Valid in phase 3 (PHASE_VECTORS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0  0xc\n+/* enum: Valid in phase 3 (PHASE_VECTORS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0  0xd\n+/* enum: Valid in phase 3 (PHASE_VECTORS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1  0xe\n+/* enum: Valid in phase 3 (PHASE_VECTORS) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1  0xf\n+/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL  0xffffffff\n+/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8\n+/* enum: Last chunk, containing checksum rather than data */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST  0xffffffff\n+/* enum: Abort download of this item */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT  0xfffffffe\n+/* Length of this chunk in bytes */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12\n+/* Data for this chunk */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59\n+\n+/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8\n+/* Same as MC_CMD_ERR field, but included as 0 in success cases */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0\n+/* Extra status information */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4\n+/* enum: Code download OK, completed. */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE  0x0\n+/* enum: Code download aborted as requested. */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED  0x1\n+/* enum: Code download OK so far, send next chunk. */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK  0x2\n+/* enum: Download phases out of sequence */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE  0x100\n+/* enum: Bad target for this phase */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET  0x101\n+/* enum: Chunk ID out of sequence */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID  0x200\n+/* enum: Chunk length zero or too large */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN  0x201\n+/* enum: Checksum was incorrect */\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM  0x300\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_CAPABILITIES\n+ * Get device capabilities.\n+ *\n+ * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to\n+ * reference inherent device capabilities as opposed to current NVRAM config.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES 0xbe\n+#undef\tMC_CMD_0xbe_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_CAPABILITIES_IN msgrequest */\n+#define\tMC_CMD_GET_CAPABILITIES_IN_LEN 0\n+\n+/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_LEN 20\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP  0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY  0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST  0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH  0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD  0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST  0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE  0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE  0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS  0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT  0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP  0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY  0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST  0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT  0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS  0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR  0x103\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY  0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM  0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY  0xf\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY  0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16\n+\n+/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_IN_LEN 0\n+\n+/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP  0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY  0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST  0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH  0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD  0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST  0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE  0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE  0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS  0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT  0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP  0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY  0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST  0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT  0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS  0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR  0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY  0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM  0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY  0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY  0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present\n+ * on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED  0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT  0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED  0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT  0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED  0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT  0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2\n+\n+/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP  0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY  0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST  0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH  0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD  0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST  0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE  0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE  0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS  0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT  0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP  0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY  0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST  0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT  0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS  0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR  0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY  0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM  0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY  0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY  0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present\n+ * on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED  0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT  0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED  0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT  0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED  0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT  0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2\n+/* On chips later than Medford the amount of address space assigned to each VI\n+ * is configurable. This is a global setting that the driver must query to\n+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available\n+ * with 8k VI windows.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1\n+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.\n+ * CTPIO is not mapped.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K   0x0\n+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K  0x1\n+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K  0x2\n+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1\n+/* Number of buffers per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n+\n+\n+/***********************************/\n+/* MC_CMD_V2_EXTN\n+ * Encapsulation for a v2 extended command\n+ */\n+#define\tMC_CMD_V2_EXTN 0x7f\n+\n+/* MC_CMD_V2_EXTN_IN msgrequest */\n+#define\tMC_CMD_V2_EXTN_IN_LEN 4\n+/* the extended command number */\n+#define\tMC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0\n+#define\tMC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED_LBN 15\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1\n+/* the actual length of the encapsulated command (which is not in the v1\n+ * header)\n+ */\n+#define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16\n+#define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED2_LBN 26\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_BUCKET_ALLOC\n+ * Allocate a pacer bucket (for qau rp or a snapper test)\n+ */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC 0xb2\n+#undef\tMC_CMD_0xb2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0\n+\n+/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_BUCKET_FREE\n+ * Free a pacer bucket\n+ */\n+#define\tMC_CMD_TCM_BUCKET_FREE 0xb3\n+#undef\tMC_CMD_0xb3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_FREE_IN_LEN 4\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0\n+\n+/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */\n+#define\tMC_CMD_TCM_BUCKET_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_BUCKET_INIT\n+ * Initialise pacer bucket with a given rate\n+ */\n+#define\tMC_CMD_TCM_BUCKET_INIT 0xb4\n+#undef\tMC_CMD_0xb4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_LEN 8\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0\n+/* the rate in mbps */\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4\n+\n+/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0\n+/* the rate in mbps */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4\n+/* the desired maximum fill level */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8\n+\n+/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */\n+#define\tMC_CMD_TCM_BUCKET_INIT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_TXQ_INIT\n+ * Initialise txq in pacer with given options or set options\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT 0xb5\n+#undef\tMC_CMD_0xb5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_LEN 28\n+/* the txq id */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0\n+/* the static priority associated with the txq */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4\n+/* bitmask of the priority queues this txq is inserted into when inserted. */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1\n+/* the reaction point (RP) bucket */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12\n+/* an already reserved bucket (typically set to bucket associated with outer\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16\n+/* an already reserved bucket (typically set to bucket associated with inner\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20\n+/* the min bucket (typically for ETS/minimum bandwidth) */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24\n+\n+/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32\n+/* the txq id */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0\n+/* the static priority associated with the txq */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4\n+/* bitmask of the priority queues this txq is inserted into when inserted. */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1\n+/* the reaction point (RP) bucket */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12\n+/* an already reserved bucket (typically set to bucket associated with outer\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16\n+/* an already reserved bucket (typically set to bucket associated with inner\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20\n+/* the min bucket (typically for ETS/minimum bandwidth) */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24\n+/* the static priority associated with the txq */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28\n+\n+/* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */\n+#define\tMC_CMD_TCM_TXQ_INIT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LINK_PIOBUF\n+ * Link a push I/O buffer to a TxQ\n+ */\n+#define\tMC_CMD_LINK_PIOBUF 0x92\n+#undef\tMC_CMD_0x92_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_LINK_PIOBUF_IN msgrequest */\n+#define\tMC_CMD_LINK_PIOBUF_IN_LEN 8\n+/* Handle for allocated push I/O buffer. */\n+#define\tMC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0\n+/* Function Local Instance (VI) number. */\n+#define\tMC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4\n+\n+/* MC_CMD_LINK_PIOBUF_OUT msgresponse */\n+#define\tMC_CMD_LINK_PIOBUF_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_UNLINK_PIOBUF\n+ * Unlink a push I/O buffer from a TxQ\n+ */\n+#define\tMC_CMD_UNLINK_PIOBUF 0x93\n+#undef\tMC_CMD_0x93_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */\n+#define\tMC_CMD_UNLINK_PIOBUF_IN_LEN 4\n+/* Function Local Instance (VI) number. */\n+#define\tMC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0\n+\n+/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */\n+#define\tMC_CMD_UNLINK_PIOBUF_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VSWITCH_ALLOC\n+ * allocate and initialise a v-switch.\n+ */\n+#define\tMC_CMD_VSWITCH_ALLOC 0x94\n+#undef\tMC_CMD_0x94_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_LEN 16\n+/* The port to connect to the v-switch's upstream port. */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+/* The type of v-switch to create. */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4\n+/* enum: VLAN */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN  0x1\n+/* enum: VEB */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB  0x2\n+/* enum: VEPA (obsolete) */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA  0x3\n+/* enum: MUX */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX  0x4\n+/* enum: Snapper specific; semantics TBD */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST  0x5\n+/* Flags controlling v-port creation */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1\n+/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,\n+ * this must be one or greated, and the attached v-ports must have exactly this\n+ * number of tags. For other v-switch types, this must be zero of greater, and\n+ * is an upper limit on the number of VLAN tags for attached v-ports. An error\n+ * will be returned if existing configuration means we can't support attached\n+ * v-ports with this number of tags.\n+ */\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12\n+\n+/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_VSWITCH_ALLOC_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VSWITCH_FREE\n+ * de-allocate a v-switch.\n+ */\n+#define\tMC_CMD_VSWITCH_FREE 0x95\n+#undef\tMC_CMD_0x95_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VSWITCH_FREE_IN msgrequest */\n+#define\tMC_CMD_VSWITCH_FREE_IN_LEN 4\n+/* The port to which the v-switch is connected. */\n+#define\tMC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0\n+\n+/* MC_CMD_VSWITCH_FREE_OUT msgresponse */\n+#define\tMC_CMD_VSWITCH_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VSWITCH_QUERY\n+ * read some config of v-switch. For now this command is an empty placeholder.\n+ * It may be used to check if a v-switch is connected to a given EVB port (if\n+ * not, then the command returns ENOENT).\n+ */\n+#define\tMC_CMD_VSWITCH_QUERY 0x63\n+#undef\tMC_CMD_0x63_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VSWITCH_QUERY_IN msgrequest */\n+#define\tMC_CMD_VSWITCH_QUERY_IN_LEN 4\n+/* The port to which the v-switch is connected. */\n+#define\tMC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0\n+\n+/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */\n+#define\tMC_CMD_VSWITCH_QUERY_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VPORT_ALLOC\n+ * allocate a v-port.\n+ */\n+#define\tMC_CMD_VPORT_ALLOC 0x96\n+#undef\tMC_CMD_0x96_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VPORT_ALLOC_IN msgrequest */\n+#define\tMC_CMD_VPORT_ALLOC_IN_LEN 20\n+/* The port to which the v-switch is connected. */\n+#define\tMC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+/* The type of the new v-port. */\n+#define\tMC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4\n+/* enum: VLAN (obsolete) */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN  0x1\n+/* enum: VEB (obsolete) */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB  0x2\n+/* enum: VEPA (obsolete) */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA  0x3\n+/* enum: A normal v-port receives packets which match a specified MAC and/or\n+ * VLAN.\n+ */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL  0x4\n+/* enum: An expansion v-port packets traffic which don't match any other\n+ * v-port.\n+ */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION  0x5\n+/* enum: An test v-port receives packets which match any filters installed by\n+ * its downstream components.\n+ */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST  0x6\n+/* Flags controlling v-port creation */\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1\n+/* The number of VLAN tags to insert/remove. An error will be returned if\n+ * incompatible with the number of VLAN tags specified for the upstream\n+ * v-switch.\n+ */\n+#define\tMC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12\n+/* The actual VLAN tags to insert/remove */\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16\n+\n+/* MC_CMD_VPORT_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_VPORT_ALLOC_OUT_LEN 4\n+/* The handle of the new v-port */\n+#define\tMC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VPORT_FREE\n+ * de-allocate a v-port.\n+ */\n+#define\tMC_CMD_VPORT_FREE 0x97\n+#undef\tMC_CMD_0x97_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VPORT_FREE_IN msgrequest */\n+#define\tMC_CMD_VPORT_FREE_IN_LEN 4\n+/* The handle of the v-port */\n+#define\tMC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0\n+\n+/* MC_CMD_VPORT_FREE_OUT msgresponse */\n+#define\tMC_CMD_VPORT_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VADAPTOR_ALLOC\n+ * allocate a v-adaptor.\n+ */\n+#define\tMC_CMD_VADAPTOR_ALLOC 0x98\n+#undef\tMC_CMD_0x98_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_LEN 30\n+/* The port to connect to the v-adaptor's port. */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+/* Flags controlling v-adaptor creation */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+/* The number of VLAN tags to strip on receive */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12\n+/* The number of VLAN tags to transparently insert/remove. */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16\n+/* The actual VLAN tags to insert/remove */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16\n+/* The MAC address to assign to this v-adaptor */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6\n+/* enum: Derive the MAC address from the upstream port */\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC  0x0\n+\n+/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_VADAPTOR_ALLOC_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VADAPTOR_FREE\n+ * de-allocate a v-adaptor.\n+ */\n+#define\tMC_CMD_VADAPTOR_FREE 0x99\n+#undef\tMC_CMD_0x99_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VADAPTOR_FREE_IN msgrequest */\n+#define\tMC_CMD_VADAPTOR_FREE_IN_LEN 4\n+/* The port to which the v-adaptor is connected. */\n+#define\tMC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0\n+\n+/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */\n+#define\tMC_CMD_VADAPTOR_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VADAPTOR_SET_MAC\n+ * assign a new MAC address to a v-adaptor.\n+ */\n+#define\tMC_CMD_VADAPTOR_SET_MAC 0x5d\n+#undef\tMC_CMD_0x5d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */\n+#define\tMC_CMD_VADAPTOR_SET_MAC_IN_LEN 10\n+/* The port to which the v-adaptor is connected. */\n+#define\tMC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0\n+/* The new MAC address to assign to this v-adaptor */\n+#define\tMC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4\n+#define\tMC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6\n+\n+/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */\n+#define\tMC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VADAPTOR_GET_MAC\n+ * read the MAC address assigned to a v-adaptor.\n+ */\n+#define\tMC_CMD_VADAPTOR_GET_MAC 0x5e\n+#undef\tMC_CMD_0x5e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */\n+#define\tMC_CMD_VADAPTOR_GET_MAC_IN_LEN 4\n+/* The port to which the v-adaptor is connected. */\n+#define\tMC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0\n+\n+/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */\n+#define\tMC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6\n+/* The MAC address assigned to this v-adaptor */\n+#define\tMC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0\n+#define\tMC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6\n+\n+\n+/***********************************/\n+/* MC_CMD_VADAPTOR_QUERY\n+ * read some config of v-adaptor.\n+ */\n+#define\tMC_CMD_VADAPTOR_QUERY 0x61\n+#undef\tMC_CMD_0x61_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */\n+#define\tMC_CMD_VADAPTOR_QUERY_IN_LEN 4\n+/* The port to which the v-adaptor is connected. */\n+#define\tMC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0\n+\n+/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_LEN 12\n+/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0\n+/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4\n+/* The number of VLAN tags that may still be added */\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_EVB_PORT_ASSIGN\n+ * assign a port to a PCI function.\n+ */\n+#define\tMC_CMD_EVB_PORT_ASSIGN 0x9a\n+#undef\tMC_CMD_0x9a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_LEN 8\n+/* The port to assign. */\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0\n+/* The target function to modify. */\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16\n+\n+/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */\n+#define\tMC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_RDWR_A64_REGIONS\n+ * Assign the 64 bit region addresses.\n+ */\n+#define\tMC_CMD_RDWR_A64_REGIONS 0x9b\n+#undef\tMC_CMD_0x9b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_LEN 17\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12\n+/* Write enable bits 0-3, set to write, clear to read. */\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1\n+\n+/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included\n+ * regardless of state of write bits in the request.\n+ */\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_LEN 16\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12\n+\n+\n+/***********************************/\n+/* MC_CMD_ONLOAD_STACK_ALLOC\n+ * Allocate an Onload stack ID.\n+ */\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC 0x9c\n+#undef\tMC_CMD_0x9c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4\n+/* The handle of the owning upstream port */\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+\n+/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4\n+/* The handle of the new Onload stack */\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_ONLOAD_STACK_FREE\n+ * Free an Onload stack ID.\n+ */\n+#define\tMC_CMD_ONLOAD_STACK_FREE 0x9d\n+#undef\tMC_CMD_0x9d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n+\n+/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */\n+#define\tMC_CMD_ONLOAD_STACK_FREE_IN_LEN 4\n+/* The handle of the Onload stack */\n+#define\tMC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0\n+\n+/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */\n+#define\tMC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_ALLOC\n+ * Allocate an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC 0x9e\n+#undef\tMC_CMD_0x9e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12\n+/* The handle of the owning upstream port */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+/* The type of context to allocate */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4\n+/* enum: Allocate a context for exclusive use. The key and indirection table\n+ * must be explicitly configured.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE  0x0\n+/* enum: Allocate a context for shared use; this will spread across a range of\n+ * queues, but the key and indirection table are pre-configured and may not be\n+ * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED  0x1\n+/* Number of queues spanned by this context, in the range 1-64; valid offsets\n+ * in the indirection table will be in the range 0 to NUM_QUEUES-1.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8\n+\n+/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4\n+/* The handle of the new RSS context. This should be considered opaque to the\n+ * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid\n+ * handle.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0\n+/* enum: guaranteed invalid RSS context handle value */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID  0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_FREE\n+ * Free an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_FREE 0x9f\n+#undef\tMC_CMD_0x9f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_FREE_IN_LEN 4\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0\n+\n+/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_SET_KEY\n+ * Set the Toeplitz hash key for an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY 0xa0\n+#undef\tMC_CMD_0xa0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0\n+/* The 40-byte Toeplitz hash key (TBD endianness issues?) */\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40\n+\n+/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_GET_KEY\n+ * Get the Toeplitz hash key for an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY 0xa1\n+#undef\tMC_CMD_0xa1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0\n+\n+/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44\n+/* The 40-byte Toeplitz hash key (TBD endianness issues?) */\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_SET_TABLE\n+ * Set the indirection table for an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE 0xa2\n+#undef\tMC_CMD_0xa2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0\n+/* The 128-byte indirection table (1 byte per entry) */\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128\n+\n+/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_GET_TABLE\n+ * Get the indirection table for an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE 0xa3\n+#undef\tMC_CMD_0xa3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0\n+\n+/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132\n+/* The 128-byte indirection table (1 byte per entry) */\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_SET_FLAGS\n+ * Set various control flags for an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1\n+#undef\tMC_CMD_0xe1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0\n+/* Hash control flags. The _EN bits are always supported, but new modes are\n+ * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:\n+ * in this case, the MODE fields may be set to non-zero values, and will take\n+ * effect regardless of the settings of the _EN flags. See the RSS_MODE\n+ * structure for the meaning of the mode bits. Drivers must check the\n+ * capability before trying to set any _MODE fields, as older firmware will\n+ * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In\n+ * the case where all the _MODE flags are zero, the _EN flags take effect,\n+ * providing backward compatibility for existing drivers. (Setting all _MODE\n+ * *and* all _EN flags to zero is valid, to disable RSS spreading for that\n+ * particular packet type.)\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4\n+\n+/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_GET_FLAGS\n+ * Get various control flags for an RSS context.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2\n+#undef\tMC_CMD_0xe2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0\n+\n+/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8\n+/* Hash control flags. If all _MODE bits are zero (which will always be true\n+ * for older firmware which does not report the ADDITIONAL_RSS_MODES\n+ * capability), the _EN bits report the state. If any _MODE bits are non-zero\n+ * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)\n+ * then the _EN bits should be disregarded, although the _MODE flags are\n+ * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS\n+ * context and in the case where the _EN flags were used in the SET. This\n+ * provides backward compatibility: old drivers will not be attempting to\n+ * derive any meaning from the _MODE bits (and can never set them to any value\n+ * not representable by the _EN bits); new drivers can always determine the\n+ * mode by looking only at the _MODE bits; the value returned by a GET can\n+ * always be used for a SET regardless of old/new driver vs. old/new firmware.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4\n+\n+\n+/***********************************/\n+/* MC_CMD_DOT1P_MAPPING_ALLOC\n+ * Allocate a .1p mapping.\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC 0xa4\n+#undef\tMC_CMD_0xa4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8\n+/* The handle of the owning upstream port */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+/* Number of queues spanned by this mapping, in the range 1-64; valid fixed\n+ * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and\n+ * referenced RSS contexts must span no more than this number.\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4\n+\n+/* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4\n+/* The handle of the new .1p mapping. This should be considered opaque to the\n+ * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid\n+ * handle.\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0\n+/* enum: guaranteed invalid .1p mapping handle value */\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID  0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_DOT1P_MAPPING_FREE\n+ * Free a .1p mapping.\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_FREE 0xa5\n+#undef\tMC_CMD_0xa5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */\n+#define\tMC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4\n+/* The handle of the .1p mapping */\n+#define\tMC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0\n+\n+/* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */\n+#define\tMC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_DOT1P_MAPPING_SET_TABLE\n+ * Set the mapping table for a .1p mapping.\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6\n+#undef\tMC_CMD_0xa6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36\n+/* The handle of the .1p mapping */\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0\n+/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context\n+ * handle)\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32\n+\n+/* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_DOT1P_MAPPING_GET_TABLE\n+ * Get the mapping table for a .1p mapping.\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7\n+#undef\tMC_CMD_0xa7_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4\n+/* The handle of the .1p mapping */\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0\n+\n+/* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36\n+/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context\n+ * handle)\n+ */\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_VECTOR_CFG\n+ * Get Interrupt Vector config for this PF.\n+ */\n+#define\tMC_CMD_GET_VECTOR_CFG 0xbf\n+#undef\tMC_CMD_0xbf_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */\n+#define\tMC_CMD_GET_VECTOR_CFG_IN_LEN 0\n+\n+/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_LEN 12\n+/* Base absolute interrupt vector number. */\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0\n+/* Number of interrupt vectors allocate to this PF. */\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4\n+/* Number of interrupt vectors to allocate per VF. */\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_VECTOR_CFG\n+ * Set Interrupt Vector config for this PF.\n+ */\n+#define\tMC_CMD_SET_VECTOR_CFG 0xc0\n+#undef\tMC_CMD_0xc0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_LEN 12\n+/* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to\n+ * let the system find a suitable base.\n+ */\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0\n+/* Number of interrupt vectors allocate to this PF. */\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4\n+/* Number of interrupt vectors to allocate per VF. */\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8\n+\n+/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */\n+#define\tMC_CMD_SET_VECTOR_CFG_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VPORT_ADD_MAC_ADDRESS\n+ * Add a MAC address to a v-port\n+ */\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8\n+#undef\tMC_CMD_0xa8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10\n+/* The handle of the v-port */\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0\n+/* MAC address to add */\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6\n+\n+/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VPORT_DEL_MAC_ADDRESS\n+ * Delete a MAC address from a v-port\n+ */\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9\n+#undef\tMC_CMD_0xa9_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10\n+/* The handle of the v-port */\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0\n+/* MAC address to add */\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6\n+\n+/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VPORT_GET_MAC_ADDRESSES\n+ * Delete a MAC address from a v-port\n+ */\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa\n+#undef\tMC_CMD_0xaa_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4\n+/* The handle of the v-port */\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0\n+\n+/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))\n+/* The number of MAC addresses returned */\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0\n+/* Array of MAC addresses */\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41\n+\n+\n+/***********************************/\n+/* MC_CMD_VPORT_RECONFIGURE\n+ * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port\n+ * has already been passed to another function (v-port's user), then that\n+ * function will be reset before applying the changes.\n+ */\n+#define\tMC_CMD_VPORT_RECONFIGURE 0xeb\n+#undef\tMC_CMD_0xeb_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_LEN 44\n+/* The handle of the v-port */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0\n+/* Flags requesting what should be changed. */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1\n+/* The number of VLAN tags to insert/remove. An error will be returned if\n+ * incompatible with the number of VLAN tags specified for the upstream\n+ * v-switch.\n+ */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8\n+/* The actual VLAN tags to insert/remove */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16\n+/* The number of MAC addresses to add */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16\n+/* MAC addresses to add */\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4\n+\n+/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */\n+#define\tMC_CMD_VPORT_RECONFIGURE_OUT_LEN 4\n+#define\tMC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0\n+#define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1\n+\n+\n+/***********************************/\n+/* MC_CMD_EVB_PORT_QUERY\n+ * read some config of v-port.\n+ */\n+#define\tMC_CMD_EVB_PORT_QUERY 0x62\n+#undef\tMC_CMD_0x62_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_EVB_PORT_QUERY_IN msgrequest */\n+#define\tMC_CMD_EVB_PORT_QUERY_IN_LEN 4\n+/* The handle of the v-port */\n+#define\tMC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0\n+\n+/* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */\n+#define\tMC_CMD_EVB_PORT_QUERY_OUT_LEN 8\n+/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */\n+#define\tMC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0\n+/* The number of VLAN tags that may be used on a v-adaptor connected to this\n+ * EVB port.\n+ */\n+#define\tMC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_DUMP_BUFTBL_ENTRIES\n+ * Dump buffer table entries, mainly for command client debug use. Dumps\n+ * absolute entries, and does not use chunk handles. All entries must be in\n+ * range, and used for q page mapping, Although the latter restriction may be\n+ * lifted in future.\n+ */\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES 0xab\n+#undef\tMC_CMD_0xab_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8\n+/* Index of the first buffer table entry. */\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0\n+/* Number of buffer table entries to dump. */\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4\n+\n+/* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))\n+/* Raw buffer table entries, layed out as BUFTBL_ENTRY. */\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_RXDP_CONFIG\n+ * Set global RXDP configuration settings\n+ */\n+#define\tMC_CMD_SET_RXDP_CONFIG 0xc1\n+#undef\tMC_CMD_0xc1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_LEN 4\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2\n+/* enum: pad to 64 bytes */\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64  0x0\n+/* enum: pad to 128 bytes (Medford only) */\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128  0x1\n+/* enum: pad to 256 bytes (Medford only) */\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256   0x2\n+\n+/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_SET_RXDP_CONFIG_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_RXDP_CONFIG\n+ * Get global RXDP configuration settings\n+ */\n+#define\tMC_CMD_GET_RXDP_CONFIG 0xc2\n+#undef\tMC_CMD_0xc2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */\n+#define\tMC_CMD_GET_RXDP_CONFIG_IN_LEN 0\n+\n+/* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_LEN 4\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_CLOCK\n+ * Return the system and PDCPU clock frequencies.\n+ */\n+#define\tMC_CMD_GET_CLOCK 0xac\n+#undef\tMC_CMD_0xac_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_CLOCK_IN msgrequest */\n+#define\tMC_CMD_GET_CLOCK_IN_LEN 0\n+\n+/* MC_CMD_GET_CLOCK_OUT msgresponse */\n+#define\tMC_CMD_GET_CLOCK_OUT_LEN 8\n+/* System frequency, MHz */\n+#define\tMC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0\n+/* DPCPU frequency, MHz */\n+#define\tMC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_CLOCK\n+ * Control the system and DPCPU clock frequencies. Changes are lost reboot.\n+ */\n+#define\tMC_CMD_SET_CLOCK 0xad\n+#undef\tMC_CMD_0xad_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_CLOCK_IN msgrequest */\n+#define\tMC_CMD_SET_CLOCK_IN_LEN 28\n+/* Requested frequency in MHz for system clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0\n+/* enum: Leave the system clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE  0x0\n+/* Requested frequency in MHz for inter-core clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4\n+/* enum: Leave the inter-core clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE  0x0\n+/* Requested frequency in MHz for DPCPU clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8\n+/* enum: Leave the DPCPU clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE  0x0\n+/* Requested frequency in MHz for PCS clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12\n+/* enum: Leave the PCS clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE  0x0\n+/* Requested frequency in MHz for MC clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16\n+/* enum: Leave the MC clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE  0x0\n+/* Requested frequency in MHz for rmon clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20\n+/* enum: Leave the rmon clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE  0x0\n+/* Requested frequency in MHz for vswitch clock domain */\n+#define\tMC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24\n+/* enum: Leave the vswitch clock domain frequency unchanged */\n+#define\tMC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE  0x0\n+\n+/* MC_CMD_SET_CLOCK_OUT msgresponse */\n+#define\tMC_CMD_SET_CLOCK_OUT_LEN 28\n+/* Resulting system frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0\n+/* enum: The system clock domain doesn't exist */\n+#define\tMC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED  0x0\n+/* Resulting inter-core frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4\n+/* enum: The inter-core clock domain doesn't exist / isn't used */\n+#define\tMC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED  0x0\n+/* Resulting DPCPU frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8\n+/* enum: The dpcpu clock domain doesn't exist */\n+#define\tMC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED  0x0\n+/* Resulting PCS frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12\n+/* enum: The PCS clock domain doesn't exist / isn't controlled */\n+#define\tMC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED  0x0\n+/* Resulting MC frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16\n+/* enum: The MC clock domain doesn't exist / isn't controlled */\n+#define\tMC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED  0x0\n+/* Resulting rmon frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20\n+/* enum: The rmon clock domain doesn't exist / isn't controlled */\n+#define\tMC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED  0x0\n+/* Resulting vswitch frequency in MHz */\n+#define\tMC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24\n+/* enum: The vswitch clock domain doesn't exist / isn't controlled */\n+#define\tMC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED  0x0\n+\n+\n+/***********************************/\n+/* MC_CMD_DPCPU_RPC\n+ * Send an arbitrary DPCPU message.\n+ */\n+#define\tMC_CMD_DPCPU_RPC 0xae\n+#undef\tMC_CMD_0xae_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DPCPU_RPC_IN msgrequest */\n+#define\tMC_CMD_DPCPU_RPC_IN_LEN 36\n+#define\tMC_CMD_DPCPU_RPC_IN_CPU_OFST 0\n+/* enum: RxDPCPU0 */\n+#define\tMC_CMD_DPCPU_RPC_IN_DPCPU_RX0  0x0\n+/* enum: TxDPCPU0 */\n+#define\tMC_CMD_DPCPU_RPC_IN_DPCPU_TX0  0x1\n+/* enum: TxDPCPU1 */\n+#define\tMC_CMD_DPCPU_RPC_IN_DPCPU_TX1  0x2\n+/* enum: RxDPCPU1 (Medford only) */\n+#define\tMC_CMD_DPCPU_RPC_IN_DPCPU_RX1   0x3\n+/* enum: RxDPCPU (will be for the calling function; for now, just an alias of\n+ * DPCPU_RX0)\n+ */\n+#define\tMC_CMD_DPCPU_RPC_IN_DPCPU_RX   0x80\n+/* enum: TxDPCPU (will be for the calling function; for now, just an alias of\n+ * DPCPU_TX0)\n+ */\n+#define\tMC_CMD_DPCPU_RPC_IN_DPCPU_TX   0x81\n+/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be\n+ * initialised to zero\n+ */\n+#define\tMC_CMD_DPCPU_RPC_IN_DATA_OFST 4\n+#define\tMC_CMD_DPCPU_RPC_IN_DATA_LEN 32\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ  0x6 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE  0x7 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST  0xc /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS  0xe /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ  0x46 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE  0x47 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST  0x4a /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS  0x4c /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT  0x4d /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT  0x0 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ  0x1 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE  0x2 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ  0x3 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ  0x4 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH  0x1 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD  0x2 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST  0x3 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_WDATA_OFST 12\n+#define\tMC_CMD_DPCPU_RPC_IN_WDATA_LEN 24\n+/* Register data to write. Only valid in write/write-read. */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16\n+/* Register address. */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20\n+\n+/* MC_CMD_DPCPU_RPC_OUT msgresponse */\n+#define\tMC_CMD_DPCPU_RPC_OUT_LEN 36\n+#define\tMC_CMD_DPCPU_RPC_OUT_RC_OFST 0\n+/* DATA */\n+#define\tMC_CMD_DPCPU_RPC_OUT_DATA_OFST 4\n+#define\tMC_CMD_DPCPU_RPC_OUT_DATA_LEN 32\n+#define\tMC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32\n+#define\tMC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12\n+#define\tMC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24\n+\n+\n+/***********************************/\n+/* MC_CMD_TRIGGER_INTERRUPT\n+ * Trigger an interrupt by prodding the BIU.\n+ */\n+#define\tMC_CMD_TRIGGER_INTERRUPT 0xe3\n+#undef\tMC_CMD_0xe3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */\n+#define\tMC_CMD_TRIGGER_INTERRUPT_IN_LEN 4\n+/* Interrupt level relative to base for function. */\n+#define\tMC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0\n+\n+/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */\n+#define\tMC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SHMBOOT_OP\n+ * Special operations to support (for now) shmboot.\n+ */\n+#define\tMC_CMD_SHMBOOT_OP 0xe6\n+#undef\tMC_CMD_0xe6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SHMBOOT_OP_IN msgrequest */\n+#define\tMC_CMD_SHMBOOT_OP_IN_LEN 4\n+/* Identifies the operation to perform */\n+#define\tMC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0\n+/* enum: Copy slave_data section to the slave core. (Greenport only) */\n+#define\tMC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA  0x0\n+\n+/* MC_CMD_SHMBOOT_OP_OUT msgresponse */\n+#define\tMC_CMD_SHMBOOT_OP_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_CAP_BLK_READ\n+ * Read multiple 64bit words from capture block memory\n+ */\n+#define\tMC_CMD_CAP_BLK_READ 0xe7\n+#undef\tMC_CMD_0xe7_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_CAP_BLK_READ_IN msgrequest */\n+#define\tMC_CMD_CAP_BLK_READ_IN_LEN 12\n+#define\tMC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0\n+#define\tMC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4\n+#define\tMC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8\n+\n+/* MC_CMD_CAP_BLK_READ_OUT msgresponse */\n+#define\tMC_CMD_CAP_BLK_READ_OUT_LENMIN 8\n+#define\tMC_CMD_CAP_BLK_READ_OUT_LENMAX 248\n+#define\tMC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31\n+\n+\n+/***********************************/\n+/* MC_CMD_DUMP_DO\n+ * Take a dump of the DUT state\n+ */\n+#define\tMC_CMD_DUMP_DO 0xe8\n+#undef\tMC_CMD_0xe8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DUMP_DO_IN msgrequest */\n+#define\tMC_CMD_DUMP_DO_IN_LEN 52\n+#define\tMC_CMD_DUMP_DO_IN_PADDING_OFST 0\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM  0x0 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT  0x1 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8\n+#define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM  0x1 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY  0x2 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI  0x3 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART  0x4 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE  0x1000 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20\n+#define\tMC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH  0x2 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12\n+/* enum: The uart port this command was received over (if using a uart\n+ * transport)\n+ */\n+#define\tMC_CMD_DUMP_DO_IN_UART_PORT_SRC  0xff\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM  0x0 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION  0x1 /* enum */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48\n+\n+/* MC_CMD_DUMP_DO_OUT msgresponse */\n+#define\tMC_CMD_DUMP_DO_OUT_LEN 4\n+#define\tMC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED\n+ * Configure unsolicited dumps\n+ */\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9\n+#undef\tMC_CMD_0xe9_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_PSU\n+ * Adjusts power supply parameters. This is a warranty-voiding operation.\n+ * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if\n+ * the parameter is out of range.\n+ */\n+#define\tMC_CMD_SET_PSU 0xea\n+#undef\tMC_CMD_0xea_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_PSU_IN msgrequest */\n+#define\tMC_CMD_SET_PSU_IN_LEN 12\n+#define\tMC_CMD_SET_PSU_IN_PARAM_OFST 0\n+#define\tMC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE  0x0 /* enum */\n+#define\tMC_CMD_SET_PSU_IN_RAIL_OFST 4\n+#define\tMC_CMD_SET_PSU_IN_RAIL_0V9  0x0 /* enum */\n+#define\tMC_CMD_SET_PSU_IN_RAIL_1V2  0x1 /* enum */\n+/* desired value, eg voltage in mV */\n+#define\tMC_CMD_SET_PSU_IN_VALUE_OFST 8\n+\n+/* MC_CMD_SET_PSU_OUT msgresponse */\n+#define\tMC_CMD_SET_PSU_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_FUNCTION_INFO\n+ * Get function information. PF and VF number.\n+ */\n+#define\tMC_CMD_GET_FUNCTION_INFO 0xec\n+#undef\tMC_CMD_0xec_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */\n+#define\tMC_CMD_GET_FUNCTION_INFO_IN_LEN 0\n+\n+/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */\n+#define\tMC_CMD_GET_FUNCTION_INFO_OUT_LEN 8\n+#define\tMC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0\n+#define\tMC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_ENABLE_OFFLINE_BIST\n+ * Enters offline BIST mode. All queues are torn down, chip enters quiescent\n+ * mode, calling function gets exclusive MCDI ownership. The only way out is\n+ * reboot.\n+ */\n+#define\tMC_CMD_ENABLE_OFFLINE_BIST 0xed\n+#undef\tMC_CMD_0xed_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */\n+#define\tMC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0\n+\n+/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */\n+#define\tMC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_UART_SEND_DATA\n+ * Send checksummed[sic] block of data over the uart. Response is a placeholder\n+ * should we wish to make this reliable; currently requests are fire-and-\n+ * forget.\n+ */\n+#define\tMC_CMD_UART_SEND_DATA 0xee\n+#undef\tMC_CMD_0xee_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_UART_SEND_DATA_OUT msgrequest */\n+#define\tMC_CMD_UART_SEND_DATA_OUT_LENMIN 16\n+#define\tMC_CMD_UART_SEND_DATA_OUT_LENMAX 252\n+#define\tMC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))\n+/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */\n+#define\tMC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0\n+/* Offset at which to write the data */\n+#define\tMC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4\n+/* Length of data */\n+#define\tMC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8\n+/* Reserved for future use */\n+#define\tMC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12\n+#define\tMC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16\n+#define\tMC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1\n+#define\tMC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236\n+\n+/* MC_CMD_UART_SEND_DATA_IN msgresponse */\n+#define\tMC_CMD_UART_SEND_DATA_IN_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_UART_RECV_DATA\n+ * Request checksummed[sic] block of data over the uart. Only a placeholder,\n+ * subject to change and not currently implemented.\n+ */\n+#define\tMC_CMD_UART_RECV_DATA 0xef\n+#undef\tMC_CMD_0xef_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_UART_RECV_DATA_OUT msgrequest */\n+#define\tMC_CMD_UART_RECV_DATA_OUT_LEN 16\n+/* CRC32 over OFFSET, LENGTH, RESERVED */\n+#define\tMC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0\n+/* Offset from which to read the data */\n+#define\tMC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4\n+/* Length of data */\n+#define\tMC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8\n+/* Reserved for future use */\n+#define\tMC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12\n+\n+/* MC_CMD_UART_RECV_DATA_IN msgresponse */\n+#define\tMC_CMD_UART_RECV_DATA_IN_LENMIN 16\n+#define\tMC_CMD_UART_RECV_DATA_IN_LENMAX 252\n+#define\tMC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))\n+/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */\n+#define\tMC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0\n+/* Offset at which to write the data */\n+#define\tMC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4\n+/* Length of data */\n+#define\tMC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8\n+/* Reserved for future use */\n+#define\tMC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12\n+#define\tMC_CMD_UART_RECV_DATA_IN_DATA_OFST 16\n+#define\tMC_CMD_UART_RECV_DATA_IN_DATA_LEN 1\n+#define\tMC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0\n+#define\tMC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236\n+\n+\n+/***********************************/\n+/* MC_CMD_READ_FUSES\n+ * Read data programmed into the device One-Time-Programmable (OTP) Fuses\n+ */\n+#define\tMC_CMD_READ_FUSES 0xf0\n+#undef\tMC_CMD_0xf0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_READ_FUSES_IN msgrequest */\n+#define\tMC_CMD_READ_FUSES_IN_LEN 8\n+/* Offset in OTP to read */\n+#define\tMC_CMD_READ_FUSES_IN_OFFSET_OFST 0\n+/* Length of data to read in bytes */\n+#define\tMC_CMD_READ_FUSES_IN_LENGTH_OFST 4\n+\n+/* MC_CMD_READ_FUSES_OUT msgresponse */\n+#define\tMC_CMD_READ_FUSES_OUT_LENMIN 4\n+#define\tMC_CMD_READ_FUSES_OUT_LENMAX 252\n+#define\tMC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))\n+/* Length of returned OTP data in bytes */\n+#define\tMC_CMD_READ_FUSES_OUT_LENGTH_OFST 0\n+/* Returned data */\n+#define\tMC_CMD_READ_FUSES_OUT_DATA_OFST 4\n+#define\tMC_CMD_READ_FUSES_OUT_DATA_LEN 1\n+#define\tMC_CMD_READ_FUSES_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248\n+\n+\n+/***********************************/\n+/* MC_CMD_KR_TUNE\n+ * Get or set KR Serdes RXEQ and TX Driver settings\n+ */\n+#define\tMC_CMD_KR_TUNE 0xf1\n+#undef\tMC_CMD_0xf1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_KR_TUNE_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_IN_LENMIN 4\n+#define\tMC_CMD_KR_TUNE_IN_LENMAX 252\n+#define\tMC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1\n+/* enum: Get current RXEQ settings */\n+#define\tMC_CMD_KR_TUNE_IN_RXEQ_GET  0x0\n+/* enum: Override RXEQ settings */\n+#define\tMC_CMD_KR_TUNE_IN_RXEQ_SET  0x1\n+/* enum: Get current TX Driver settings */\n+#define\tMC_CMD_KR_TUNE_IN_TXEQ_GET  0x2\n+/* enum: Override TX Driver settings */\n+#define\tMC_CMD_KR_TUNE_IN_TXEQ_SET  0x3\n+/* enum: Force KR Serdes reset / recalibration */\n+#define\tMC_CMD_KR_TUNE_IN_RECAL  0x4\n+/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid\n+ * signal.\n+ */\n+#define\tMC_CMD_KR_TUNE_IN_START_EYE_PLOT  0x5\n+/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The\n+ * caller should call this command repeatedly after starting eye plot, until no\n+ * more data is returned.\n+ */\n+#define\tMC_CMD_KR_TUNE_IN_POLL_EYE_PLOT  0x6\n+/* enum: Read Figure Of Merit (eye quality, higher is better). */\n+#define\tMC_CMD_KR_TUNE_IN_READ_FOM  0x7\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3\n+/* Arguments specific to the operation */\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0\n+#define\tMC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62\n+\n+/* MC_CMD_KR_TUNE_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_OUT_LEN 0\n+\n+/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))\n+/* RXEQ Parameter */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8\n+/* enum: Attenuation (0-15, Huntington) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT  0x0\n+/* enum: CTLE Boost (0-15, Huntington) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST  0x1\n+/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max\n+ * positive, Medford - 0-31)\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1  0x2\n+/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max\n+ * positive, Medford - 0-31)\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2  0x3\n+/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max\n+ * positive, Medford - 0-16)\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3  0x4\n+/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max\n+ * positive, Medford - 0-16)\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4  0x5\n+/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max\n+ * positive, Medford - 0-16)\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5  0x6\n+/* enum: Edge DFE DLEV (0-128 for Medford) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV  0x7\n+/* enum: Variable Gain Amplifier (0-15, Medford) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA  0x8\n+/* enum: CTLE EQ Capacitor (0-15, Medford) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC  0x9\n+/* enum: CTLE EQ Resistor (0-7, Medford) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES  0xa\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0  0x0 /* enum */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1  0x1 /* enum */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2  0x2 /* enum */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3  0x3 /* enum */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL  0x4 /* enum */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8\n+\n+/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3\n+/* RXEQ Parameter */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8\n+\n+/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0\n+\n+/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))\n+/* TXEQ Parameter */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8\n+/* enum: TX Amplitude (Huntington, Medford) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV  0x0\n+/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE  0x1\n+/* enum: De-Emphasis Tap1 Fine */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV  0x2\n+/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2  0x3\n+/* enum: De-Emphasis Tap2 Fine (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV  0x4\n+/* enum: Pre-Emphasis Magnitude (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E  0x5\n+/* enum: Pre-Emphasis Fine (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV  0x6\n+/* enum: TX Slew Rate Coarse control (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY  0x7\n+/* enum: TX Slew Rate Fine control (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET  0x8\n+/* enum: TX Termination Impedance control (Huntington) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET  0x9\n+/* enum: TX Amplitude Fine control (Medford) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE  0xa\n+/* enum: Pre-shoot Tap (Medford) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV  0xb\n+/* enum: De-emphasis Tap (Medford) */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY  0xc\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0  0x0 /* enum */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1  0x1 /* enum */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2  0x2 /* enum */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3  0x3 /* enum */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL  0x4 /* enum */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8\n+\n+/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3\n+/* TXEQ Parameter */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8\n+\n+/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0\n+\n+/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_RECAL_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_RECAL_OUT_LEN 0\n+\n+/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4\n+\n+/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0\n+\n+/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0\n+#define\tMC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126\n+\n+/* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LEN 8\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4\n+\n+/* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4\n+#define\tMC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PCIE_TUNE\n+ * Get or set PCIE Serdes RXEQ and TX Driver settings\n+ */\n+#define\tMC_CMD_PCIE_TUNE 0xf2\n+#undef\tMC_CMD_0xf2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PCIE_TUNE_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_IN_LENMIN 4\n+#define\tMC_CMD_PCIE_TUNE_IN_LENMAX 252\n+#define\tMC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))\n+/* Requested operation */\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1\n+/* enum: Get current RXEQ settings */\n+#define\tMC_CMD_PCIE_TUNE_IN_RXEQ_GET  0x0\n+/* enum: Override RXEQ settings */\n+#define\tMC_CMD_PCIE_TUNE_IN_RXEQ_SET  0x1\n+/* enum: Get current TX Driver settings */\n+#define\tMC_CMD_PCIE_TUNE_IN_TXEQ_GET  0x2\n+/* enum: Override TX Driver settings */\n+#define\tMC_CMD_PCIE_TUNE_IN_TXEQ_SET  0x3\n+/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */\n+#define\tMC_CMD_PCIE_TUNE_IN_START_EYE_PLOT  0x5\n+/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The\n+ * caller should call this command repeatedly after starting eye plot, until no\n+ * more data is returned.\n+ */\n+#define\tMC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT  0x6\n+/* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */\n+#define\tMC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE  0x7\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3\n+/* Arguments specific to the operation */\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0\n+#define\tMC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62\n+\n+/* MC_CMD_PCIE_TUNE_OUT msgresponse */\n+#define\tMC_CMD_PCIE_TUNE_OUT_LEN 0\n+\n+/* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))\n+/* RXEQ Parameter */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8\n+/* enum: Attenuation (0-15) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT  0x0\n+/* enum: CTLE Boost (0-15) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST  0x1\n+/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1  0x2\n+/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2  0x3\n+/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3  0x4\n+/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4  0x5\n+/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5  0x6\n+/* enum: DFE DLev */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV  0x7\n+/* enum: Figure of Merit */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM  0x8\n+/* enum: CTLE EQ Capacitor (HF Gain) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC  0x9\n+/* enum: CTLE EQ Resistor (DC Gain) */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES  0xa\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0  0x0 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1  0x1 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2  0x2 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3  0x3 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4  0x4 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5  0x5 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6  0x6 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7  0x7 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8  0x8 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9  0x9 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10  0xa /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11  0xb /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12  0xc /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13  0xd /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14  0xe /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15  0xf /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL  0x10 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8\n+\n+/* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))\n+/* Requested operation */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3\n+/* RXEQ Parameter */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8\n+\n+/* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0\n+\n+/* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))\n+/* RXEQ Parameter */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8\n+/* enum: TxMargin (PIPE) */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN  0x0\n+/* enum: TxSwing (PIPE) */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING  0x1\n+/* enum: De-emphasis coefficient C(-1) (PIPE) */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1  0x2\n+/* enum: De-emphasis coefficient C(0) (PIPE) */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0  0x3\n+/* enum: De-emphasis coefficient C(+1) (PIPE) */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1  0x4\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8\n+\n+/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8\n+/* Requested operation */\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4\n+\n+/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0\n+\n+/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4\n+/* Requested operation */\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3\n+\n+/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0\n+#define\tMC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126\n+\n+/* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0\n+\n+/* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */\n+#define\tMC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSING\n+ * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition\n+ * - not used for V3 licensing\n+ */\n+#define\tMC_CMD_LICENSING 0xf3\n+#undef\tMC_CMD_0xf3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSING_IN msgrequest */\n+#define\tMC_CMD_LICENSING_IN_LEN 4\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_LICENSING_IN_OP_OFST 0\n+/* enum: re-read and apply licenses after a license key partition update; note\n+ * that this operation returns a zero-length response\n+ */\n+#define\tMC_CMD_LICENSING_IN_OP_UPDATE_LICENSE  0x0\n+/* enum: report counts of installed licenses */\n+#define\tMC_CMD_LICENSING_IN_OP_GET_KEY_STATS  0x1\n+\n+/* MC_CMD_LICENSING_OUT msgresponse */\n+#define\tMC_CMD_LICENSING_OUT_LEN 28\n+/* count of application keys which are valid */\n+#define\tMC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0\n+/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with\n+ * MC_CMD_FC_OP_LICENSE)\n+ */\n+#define\tMC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4\n+/* count of application keys which are invalid due to being blacklisted */\n+#define\tMC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8\n+/* count of application keys which are invalid due to being unverifiable */\n+#define\tMC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12\n+/* count of application keys which are invalid due to being for the wrong node\n+ */\n+#define\tMC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16\n+/* licensing state (for diagnostics; the exact meaning of the bits in this\n+ * field are private to the firmware)\n+ */\n+#define\tMC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20\n+/* licensing subsystem self-test report (for manftest) */\n+#define\tMC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24\n+/* enum: licensing subsystem self-test failed */\n+#define\tMC_CMD_LICENSING_OUT_SELF_TEST_FAIL  0x0\n+/* enum: licensing subsystem self-test passed */\n+#define\tMC_CMD_LICENSING_OUT_SELF_TEST_PASS  0x1\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSING_V3\n+ * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition\n+ * - V3 licensing (Medford)\n+ */\n+#define\tMC_CMD_LICENSING_V3 0xd0\n+#undef\tMC_CMD_0xd0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSING_V3_IN msgrequest */\n+#define\tMC_CMD_LICENSING_V3_IN_LEN 4\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_LICENSING_V3_IN_OP_OFST 0\n+/* enum: re-read and apply licenses after a license key partition update; note\n+ * that this operation returns a zero-length response\n+ */\n+#define\tMC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE  0x0\n+/* enum: report counts of installed licenses Returns EAGAIN if license\n+ * processing (updating) has been started but not yet completed.\n+ */\n+#define\tMC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE  0x1\n+\n+/* MC_CMD_LICENSING_V3_OUT msgresponse */\n+#define\tMC_CMD_LICENSING_V3_OUT_LEN 88\n+/* count of keys which are valid */\n+#define\tMC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0\n+/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with\n+ * MC_CMD_FC_OP_LICENSE)\n+ */\n+#define\tMC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4\n+/* count of keys which are invalid due to being unverifiable */\n+#define\tMC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8\n+/* count of keys which are invalid due to being for the wrong node */\n+#define\tMC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12\n+/* licensing state (for diagnostics; the exact meaning of the bits in this\n+ * field are private to the firmware)\n+ */\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16\n+/* licensing subsystem self-test report (for manftest) */\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20\n+/* enum: licensing subsystem self-test failed */\n+#define\tMC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL  0x0\n+/* enum: licensing subsystem self-test passed */\n+#define\tMC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS  0x1\n+/* bitmask of licensed applications */\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28\n+/* reserved for future use */\n+#define\tMC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32\n+#define\tMC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24\n+/* bitmask of licensed features */\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60\n+/* reserved for future use */\n+#define\tMC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64\n+#define\tMC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSING_GET_ID_V3\n+ * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license\n+ * partition - V3 licensing (Medford)\n+ */\n+#define\tMC_CMD_LICENSING_GET_ID_V3 0xd1\n+#undef\tMC_CMD_0xd1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */\n+#define\tMC_CMD_LICENSING_GET_ID_V3_IN_LEN 0\n+\n+/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))\n+/* type of license (eg 3) */\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0\n+/* length of the license ID (in bytes) */\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4\n+/* the unique license ID of the adapter */\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244\n+\n+\n+/***********************************/\n+/* MC_CMD_MC2MC_PROXY\n+ * Execute an arbitrary MCDI command on the slave MC of a dual-core device.\n+ * This will fail on a single-core system.\n+ */\n+#define\tMC_CMD_MC2MC_PROXY 0xf4\n+#undef\tMC_CMD_0xf4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MC2MC_PROXY_IN msgrequest */\n+#define\tMC_CMD_MC2MC_PROXY_IN_LEN 0\n+\n+/* MC_CMD_MC2MC_PROXY_OUT msgresponse */\n+#define\tMC_CMD_MC2MC_PROXY_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_LICENSED_APP_STATE\n+ * Query the state of an individual licensed application. (Note that the actual\n+ * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation\n+ * or a reboot of the MC.) Not used for V3 licensing\n+ */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE 0xf5\n+#undef\tMC_CMD_0xf5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4\n+/* application ID to query (LICENSED_APP_ID_xxx) */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0\n+\n+/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4\n+/* state of this application */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0\n+/* enum: no (or invalid) license is present for the application */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED  0x0\n+/* enum: a valid license is present for the application */\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED  0x1\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_LICENSED_V3_APP_STATE\n+ * Query the state of an individual licensed application. (Note that the actual\n+ * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE\n+ * operation or a reboot of the MC.) Used for V3 licensing (Medford)\n+ */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE 0xd2\n+#undef\tMC_CMD_0xd2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8\n+/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit\n+ * mask\n+ */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4\n+\n+/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4\n+/* state of this application */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0\n+/* enum: no (or invalid) license is present for the application */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED  0x0\n+/* enum: a valid license is present for the application */\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED  0x1\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES\n+ * Query the state of an one or more licensed features. (Note that the actual\n+ * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE\n+ * operation or a reboot of the MC.) Used for V3 licensing (Medford)\n+ */\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3\n+#undef\tMC_CMD_0xd3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8\n+/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or\n+ * more bits set\n+ */\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4\n+\n+/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8\n+/* states of these features - bit set for licensed, clear for not licensed */\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSED_APP_OP\n+ * Perform an action for an individual licensed application - not used for V3\n+ * licensing.\n+ */\n+#define\tMC_CMD_LICENSED_APP_OP 0xf6\n+#undef\tMC_CMD_0xf6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSED_APP_OP_IN msgrequest */\n+#define\tMC_CMD_LICENSED_APP_OP_IN_LENMIN 8\n+#define\tMC_CMD_LICENSED_APP_OP_IN_LENMAX 252\n+#define\tMC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))\n+/* application ID */\n+#define\tMC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0\n+/* the type of operation requested */\n+#define\tMC_CMD_LICENSED_APP_OP_IN_OP_OFST 4\n+/* enum: validate application */\n+#define\tMC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE  0x0\n+/* enum: mask application */\n+#define\tMC_CMD_LICENSED_APP_OP_IN_OP_MASK  0x1\n+/* arguments specific to this particular operation */\n+#define\tMC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8\n+#define\tMC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4\n+#define\tMC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0\n+#define\tMC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61\n+\n+/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_LENMIN 0\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_LENMAX 252\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))\n+/* result specific to this particular operation */\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0\n+#define\tMC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63\n+\n+/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72\n+/* application ID */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0\n+/* the type of operation requested */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4\n+/* validation challenge */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64\n+\n+/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68\n+/* feature expiry (time_t) */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0\n+/* validation response */\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64\n+\n+/* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12\n+/* application ID */\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0\n+/* the type of operation requested */\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4\n+/* flag */\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8\n+\n+/* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSED_V3_VALIDATE_APP\n+ * Perform validation for an individual licensed application - V3 licensing\n+ * (Medford)\n+ */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP 0xd4\n+#undef\tMC_CMD_0xd4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56\n+/* challenge for validation (384 bits) */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48\n+/* application ID expressed as a single bit mask */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52\n+\n+/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116\n+/* validation response to challenge in the form of ECDSA signature consisting\n+ * of two 384-bit integers, r and s, in big-endian order. The signature signs a\n+ * SHA-384 digest of a message constructed from the concatenation of the input\n+ * message and the remaining fields of this output message, e.g. challenge[48\n+ * bytes] ... expiry_time[4 bytes] ...\n+ */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96\n+/* application expiry time */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96\n+/* application expiry units */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100\n+/* enum: expiry units are accounting units */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC  0x0\n+/* enum: expiry units are calendar days */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS  0x1\n+/* base MAC address of the NIC stored in NVRAM (note that this is a constant\n+ * value for a given NIC regardless which function is calling, effectively this\n+ * is PF0 base MAC address)\n+ */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6\n+/* MAC address of v-adaptor associated with the client. If no such v-adapator\n+ * exists, then the field is filled with 0xFF.\n+ */\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSED_V3_MASK_FEATURES\n+ * Mask features - V3 licensing (Medford)\n+ */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES 0xd5\n+#undef\tMC_CMD_0xd5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12\n+/* mask to be applied to features to be changed */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4\n+/* whether to turn on or turn off the masked features */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8\n+/* enum: turn the features off */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF  0x0\n+/* enum: turn the features back on */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON  0x1\n+\n+/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LICENSING_V3_TEMPORARY\n+ * Perform operations to support installation of a single temporary license in\n+ * the adapter, in addition to those found in the licensing partition. See\n+ * SF-116124-SW for an overview of how this could be used. The license is\n+ * stored in MC persistent data and so will survive a MC reboot, but will be\n+ * erased when the adapter is power cycled\n+ */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY 0xd6\n+#undef\tMC_CMD_0xd6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4\n+/* operation code */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0\n+/* enum: install a new license, overwriting any existing temporary license.\n+ * This is an asynchronous operation owing to the time taken to validate an\n+ * ECDSA license\n+ */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_SET  0x0\n+/* enum: clear the license immediately rather than waiting for the next power\n+ * cycle\n+ */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_CLEAR  0x1\n+/* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET\n+ * operation\n+ */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_STATUS  0x2\n+\n+/* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0\n+/* ECDSA license and signature */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160\n+\n+/* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0\n+\n+/* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0\n+\n+/* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12\n+/* status code */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0\n+/* enum: finished validating and installing license */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK  0x0\n+/* enum: license validation and installation in progress */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS  0x1\n+/* enum: licensing error. More specific error messages are not provided to\n+ * avoid exposing details of the licensing system to the client\n+ */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR  0x2\n+/* bitmask of licensed features */\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_PORT_SNIFF_CONFIG\n+ * Configure RX port sniffing for the physical port associated with the calling\n+ * function. Only a privileged function may change the port sniffing\n+ * configuration. A copy of all traffic delivered to the host (non-promiscuous\n+ * mode) or all traffic arriving at the port (promiscuous mode) may be\n+ * delivered to a specific queue, or a set of queues with RSS.\n+ */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG 0xf7\n+#undef\tMC_CMD_0xf7_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16\n+/* configuration flags */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1\n+/* receive queue handle (for RSS mode, this is the base queue) */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4\n+/* receive mode */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8\n+/* enum: receive to just the specified queue */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE  0x0\n+/* enum: receive to multiple queues using RSS context */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS  0x1\n+/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note\n+ * that these handles should be considered opaque to the host, although a value\n+ * of 0xFFFFFFFF is guaranteed never to be a valid handle.\n+ */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12\n+\n+/* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PORT_SNIFF_CONFIG\n+ * Obtain the current RX port sniffing configuration for the physical port\n+ * associated with the calling function. Only a privileged function may read\n+ * the configuration.\n+ */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG 0xf8\n+#undef\tMC_CMD_0xf8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0\n+\n+/* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16\n+/* configuration flags */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1\n+/* receiving queue handle (for RSS mode, this is the base queue) */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4\n+/* receive mode */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8\n+/* enum: receiving to just the specified queue */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE  0x0\n+/* enum: receiving to multiple queues using RSS context */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS  0x1\n+/* RSS context (for RX_MODE_RSS) */\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_PARSER_DISP_CONFIG\n+ * Change configuration related to the parser-dispatcher subsystem.\n+ */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG 0xf9\n+#undef\tMC_CMD_0xf9_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))\n+/* the type of configuration setting to change */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0\n+/* enum: Per-TXQ enable for multicast UDP destination lookup for possible\n+ * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)\n+ */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN  0x0\n+/* enum: Per-v-adaptor enable for suppression of self-transmissions on the\n+ * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single\n+ * boolean.)\n+ */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX  0x1\n+/* handle for the entity to update: queue handle, EVB port ID, etc. depending\n+ * on the type of configuration setting being changed\n+ */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4\n+/* new value: the details depend on the type of configuration setting being\n+ * changed\n+ */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61\n+\n+/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PARSER_DISP_CONFIG\n+ * Read configuration related to the parser-dispatcher subsystem.\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG 0xfa\n+#undef\tMC_CMD_0xfa_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8\n+/* the type of configuration setting to read */\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */\n+/* handle for the entity to query: queue handle, EVB port ID, etc. depending on\n+ * the type of configuration setting being read\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4\n+\n+/* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))\n+/* current value: the details depend on the type of configuration setting being\n+ * read\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG\n+ * Configure TX port sniffing for the physical port associated with the calling\n+ * function. Only a privileged function may change the port sniffing\n+ * configuration. A copy of all traffic transmitted through the port may be\n+ * delivered to a specific queue, or a set of queues with RSS. Note that these\n+ * packets are delivered with transmit timestamps in the packet prefix, not\n+ * receive timestamps, so it is likely that the queue(s) will need to be\n+ * dedicated as TX sniff receivers.\n+ */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb\n+#undef\tMC_CMD_0xfb_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16\n+/* configuration flags */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1\n+/* receive queue handle (for RSS mode, this is the base queue) */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4\n+/* receive mode */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8\n+/* enum: receive to just the specified queue */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE  0x0\n+/* enum: receive to multiple queues using RSS context */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS  0x1\n+/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note\n+ * that these handles should be considered opaque to the host, although a value\n+ * of 0xFFFFFFFF is guaranteed never to be a valid handle.\n+ */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12\n+\n+/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG\n+ * Obtain the current TX port sniffing configuration for the physical port\n+ * associated with the calling function. Only a privileged function may read\n+ * the configuration.\n+ */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc\n+#undef\tMC_CMD_0xfc_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0\n+\n+/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16\n+/* configuration flags */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1\n+/* receiving queue handle (for RSS mode, this is the base queue) */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4\n+/* receive mode */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8\n+/* enum: receiving to just the specified queue */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE  0x0\n+/* enum: receiving to multiple queues using RSS context */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS  0x1\n+/* RSS context (for RX_MODE_RSS) */\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12\n+\n+\n+/***********************************/\n+/* MC_CMD_RMON_STATS_RX_ERRORS\n+ * Per queue rx error stats.\n+ */\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS 0xfe\n+#undef\tMC_CMD_0xfe_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8\n+/* The rx queue to get stats for. */\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1\n+\n+/* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PCIE_RESOURCE_INFO\n+ * Find out about available PCIE resources\n+ */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO 0xfd\n+\n+/* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0\n+\n+/* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28\n+/* The maximum number of PFs the device can expose */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0\n+/* The maximum number of VFs the device can expose in total */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4\n+/* The maximum number of MSI-X vectors the device can provide in total */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8\n+/* the number of MSI-X vectors the device will allocate by default to each PF\n+ */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12\n+/* the number of MSI-X vectors the device will allocate by default to each VF\n+ */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16\n+/* the maximum number of MSI-X vectors the device can allocate to any one PF */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20\n+/* the maximum number of MSI-X vectors the device can allocate to any one VF */\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_PORT_MODES\n+ * Find out about available port modes\n+ */\n+#define\tMC_CMD_GET_PORT_MODES 0xff\n+#undef\tMC_CMD_0xff_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_PORT_MODES_IN msgrequest */\n+#define\tMC_CMD_GET_PORT_MODES_IN_LEN 0\n+\n+/* MC_CMD_GET_PORT_MODES_OUT msgresponse */\n+#define\tMC_CMD_GET_PORT_MODES_OUT_LEN 12\n+/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */\n+#define\tMC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0\n+/* Default (canonical) board mode */\n+#define\tMC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4\n+/* Current board mode */\n+#define\tMC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_READ_ATB\n+ * Sample voltages on the ATB\n+ */\n+#define\tMC_CMD_READ_ATB 0x100\n+#undef\tMC_CMD_0x100_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_READ_ATB_IN msgrequest */\n+#define\tMC_CMD_READ_ATB_IN_LEN 16\n+#define\tMC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0\n+#define\tMC_CMD_READ_ATB_IN_BUS_CCOM  0x0 /* enum */\n+#define\tMC_CMD_READ_ATB_IN_BUS_CKR  0x1 /* enum */\n+#define\tMC_CMD_READ_ATB_IN_BUS_CPCIE  0x8 /* enum */\n+#define\tMC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4\n+#define\tMC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8\n+#define\tMC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12\n+\n+/* MC_CMD_READ_ATB_OUT msgresponse */\n+#define\tMC_CMD_READ_ATB_OUT_LEN 4\n+#define\tMC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_WORKAROUNDS\n+ * Read the list of all implemented and all currently enabled workarounds. The\n+ * enums here must correspond with those in MC_CMD_WORKAROUND.\n+ */\n+#define\tMC_CMD_GET_WORKAROUNDS 0x59\n+#undef\tMC_CMD_0x59_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_LEN 8\n+/* Each workaround is represented by a single bit according to the enums below.\n+ */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4\n+/* enum: Bug 17230 work around. */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2\n+/* enum: Bug 35388 work around (unsafe EVQ writes). */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4\n+/* enum: Bug35017 workaround (A64 tables must be identity map) */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8\n+/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10\n+/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution\n+ * - before adding code that queries this workaround, remember that there's\n+ * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,\n+ * and will hence (incorrectly) report that the bug doesn't exist.\n+ */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20\n+/* enum: Bug 26807 features present in firmware (multicast filter chaining) */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40\n+/* enum: Bug 61265 work around (broken EVQ TMR writes). */\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80\n+\n+\n+/***********************************/\n+/* MC_CMD_PRIVILEGE_MASK\n+ * Read/set privileges of an arbitrary PCIe function\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK 0x5a\n+#undef\tMC_CMD_0x5a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_LEN 8\n+/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF\n+ * 1,3 = 0x00030001\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_VF_NULL  0xffff /* enum */\n+/* New privilege mask to be set. The mask will only be changed if the MSB is\n+ * set to 1.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN             0x1 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_LINK              0x2 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD            0x4 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_PTP               0x8 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS  0x10 /* enum */\n+/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING      0x20\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST           0x40 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST         0x80 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST         0x100 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST     0x200 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS       0x400 /* enum */\n+/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC\n+ * adress.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX   0x800\n+/* enum: Privilege that allows a Function to change the MAC address configured\n+ * in its associated vAdapter/vPort.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC        0x1000\n+/* enum: Privilege that allows a Function to install filters that specify VLANs\n+ * that are not in the permit list for the associated vPort. This privilege is\n+ * primarily to support ESX where vPorts are created that restrict traffic to\n+ * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN  0x2000\n+/* enum: Set this bit to indicate that a new privilege mask is to be set,\n+ * otherwise the command will only read the existing mask.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE             0x80000000\n+\n+/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */\n+#define\tMC_CMD_PRIVILEGE_MASK_OUT_LEN 4\n+/* For an admin function, always all the privileges are reported. */\n+#define\tMC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LINK_STATE_MODE\n+ * Read/set link state mode of a VF\n+ */\n+#define\tMC_CMD_LINK_STATE_MODE 0x5c\n+#undef\tMC_CMD_0x5c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_LINK_STATE_MODE_IN msgrequest */\n+#define\tMC_CMD_LINK_STATE_MODE_IN_LEN 8\n+/* The target function to have its link state mode read or set, must be a VF\n+ * e.g. VF 1,3 = 0x00030001\n+ */\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16\n+/* New link state mode to be set */\n+#define\tMC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4\n+#define\tMC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO       0x0 /* enum */\n+#define\tMC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP         0x1 /* enum */\n+#define\tMC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN       0x2 /* enum */\n+/* enum: Use this value to just read the existing setting without modifying it.\n+ */\n+#define\tMC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE         0xffffffff\n+\n+/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */\n+#define\tMC_CMD_LINK_STATE_MODE_OUT_LEN 4\n+#define\tMC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_SNAPSHOT_LENGTH\n+ * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH\n+ * parameter to MC_CMD_INIT_RXQ.\n+ */\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH 0x101\n+#undef\tMC_CMD_0x101_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0\n+\n+/* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8\n+/* Minimum acceptable snapshot length. */\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0\n+/* Maximum acceptable snapshot length. */\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_FUSE_DIAGS\n+ * Additional fuse diagnostics\n+ */\n+#define\tMC_CMD_FUSE_DIAGS 0x102\n+#undef\tMC_CMD_0x102_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_FUSE_DIAGS_IN msgrequest */\n+#define\tMC_CMD_FUSE_DIAGS_IN_LEN 0\n+\n+/* MC_CMD_FUSE_DIAGS_OUT msgresponse */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_LEN 48\n+/* Total number of mismatched bits between pairs in area 0 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0\n+/* Total number of unexpectedly clear (set in B but not A) bits in area 0 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4\n+/* Total number of unexpectedly clear (set in A but not B) bits in area 0 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8\n+/* Checksum of data after logical OR of pairs in area 0 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12\n+/* Total number of mismatched bits between pairs in area 1 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16\n+/* Total number of unexpectedly clear (set in B but not A) bits in area 1 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20\n+/* Total number of unexpectedly clear (set in A but not B) bits in area 1 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24\n+/* Checksum of data after logical OR of pairs in area 1 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28\n+/* Total number of mismatched bits between pairs in area 2 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32\n+/* Total number of unexpectedly clear (set in B but not A) bits in area 2 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36\n+/* Total number of unexpectedly clear (set in A but not B) bits in area 2 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40\n+/* Checksum of data after logical OR of pairs in area 2 */\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44\n+\n+\n+/***********************************/\n+/* MC_CMD_PRIVILEGE_MODIFY\n+ * Modify the privileges of a set of PCIe functions. Note that this operation\n+ * only effects non-admin functions unless the admin privilege itself is\n+ * included in one of the masks provided.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MODIFY 0x60\n+#undef\tMC_CMD_0x60_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_LEN 16\n+/* The groups of functions to have their privilege masks modified. */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_NONE       0x0 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_ALL        0x1 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY   0x2 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY   0x3 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF  0x4 /* enum */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_ONE        0x5 /* enum */\n+/* For VFS_OF_PF specify the PF, for ONE specify the target function */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16\n+/* Privileges to be added to the target functions. For privilege definitions\n+ * refer to the command MC_CMD_PRIVILEGE_MASK\n+ */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8\n+/* Privileges to be removed from the target functions. For privilege\n+ * definitions refer to the command MC_CMD_PRIVILEGE_MASK\n+ */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12\n+\n+/* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */\n+#define\tMC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_READ_BYTES\n+ * Read XPM memory\n+ */\n+#define\tMC_CMD_XPM_READ_BYTES 0x103\n+#undef\tMC_CMD_0x103_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_READ_BYTES_IN msgrequest */\n+#define\tMC_CMD_XPM_READ_BYTES_IN_LEN 8\n+/* Start address (byte) */\n+#define\tMC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0\n+/* Count (bytes) */\n+#define\tMC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4\n+\n+/* MC_CMD_XPM_READ_BYTES_OUT msgresponse */\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_LENMIN 0\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_LENMAX 252\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))\n+/* Data */\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_WRITE_BYTES\n+ * Write XPM memory\n+ */\n+#define\tMC_CMD_XPM_WRITE_BYTES 0x104\n+#undef\tMC_CMD_0x104_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))\n+/* Start address (byte) */\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0\n+/* Count (bytes) */\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4\n+/* Data */\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244\n+\n+/* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */\n+#define\tMC_CMD_XPM_WRITE_BYTES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_READ_SECTOR\n+ * Read XPM sector\n+ */\n+#define\tMC_CMD_XPM_READ_SECTOR 0x105\n+#undef\tMC_CMD_0x105_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_READ_SECTOR_IN msgrequest */\n+#define\tMC_CMD_XPM_READ_SECTOR_IN_LEN 8\n+/* Sector index */\n+#define\tMC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0\n+/* Sector size */\n+#define\tMC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4\n+\n+/* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))\n+/* Sector type */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_BLANK            0x0 /* enum */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128   0x1 /* enum */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256   0x2 /* enum */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_INVALID          0xff /* enum */\n+/* Sector data */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_WRITE_SECTOR\n+ * Write XPM sector\n+ */\n+#define\tMC_CMD_XPM_WRITE_SECTOR 0x106\n+#undef\tMC_CMD_0x106_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))\n+/* If writing fails due to an uncorrectable error, try up to RETRIES following\n+ * sectors (or until no more space available). If 0, only one write attempt is\n+ * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair\n+ * mechanism.\n+ */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3\n+/* Sector type */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */\n+/* Sector size */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8\n+/* Sector data */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32\n+\n+/* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4\n+/* New sector index */\n+#define\tMC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_INVALIDATE_SECTOR\n+ * Invalidate XPM sector\n+ */\n+#define\tMC_CMD_XPM_INVALIDATE_SECTOR 0x107\n+#undef\tMC_CMD_0x107_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */\n+#define\tMC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4\n+/* Sector index */\n+#define\tMC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0\n+\n+/* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */\n+#define\tMC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_BLANK_CHECK\n+ * Blank-check XPM memory and report bad locations\n+ */\n+#define\tMC_CMD_XPM_BLANK_CHECK 0x108\n+#undef\tMC_CMD_0x108_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */\n+#define\tMC_CMD_XPM_BLANK_CHECK_IN_LEN 8\n+/* Start address (byte) */\n+#define\tMC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0\n+/* Count (bytes) */\n+#define\tMC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4\n+\n+/* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))\n+/* Total number of bad (non-blank) locations */\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0\n+/* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit\n+ * into MCDI response)\n+ */\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_REPAIR\n+ * Blank-check and repair XPM memory\n+ */\n+#define\tMC_CMD_XPM_REPAIR 0x109\n+#undef\tMC_CMD_0x109_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_REPAIR_IN msgrequest */\n+#define\tMC_CMD_XPM_REPAIR_IN_LEN 8\n+/* Start address (byte) */\n+#define\tMC_CMD_XPM_REPAIR_IN_ADDR_OFST 0\n+/* Count (bytes) */\n+#define\tMC_CMD_XPM_REPAIR_IN_COUNT_OFST 4\n+\n+/* MC_CMD_XPM_REPAIR_OUT msgresponse */\n+#define\tMC_CMD_XPM_REPAIR_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_DECODER_TEST\n+ * Test XPM memory address decoders for gross manufacturing defects. Can only\n+ * be performed on an unprogrammed part.\n+ */\n+#define\tMC_CMD_XPM_DECODER_TEST 0x10a\n+#undef\tMC_CMD_0x10a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_DECODER_TEST_IN msgrequest */\n+#define\tMC_CMD_XPM_DECODER_TEST_IN_LEN 0\n+\n+/* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */\n+#define\tMC_CMD_XPM_DECODER_TEST_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_WRITE_TEST\n+ * XPM memory write test. Test XPM write logic for gross manufacturing defects\n+ * by writing to a dedicated test row. There are 16 locations in the test row\n+ * and the test can only be performed on locations that have not been\n+ * previously used (i.e. can be run at most 16 times). The test will pick the\n+ * first available location to use, or fail with ENOSPC if none left.\n+ */\n+#define\tMC_CMD_XPM_WRITE_TEST 0x10b\n+#undef\tMC_CMD_0x10b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_WRITE_TEST_IN msgrequest */\n+#define\tMC_CMD_XPM_WRITE_TEST_IN_LEN 0\n+\n+/* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */\n+#define\tMC_CMD_XPM_WRITE_TEST_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_EXEC_SIGNED\n+ * Check the CMAC of the contents of IMEM and DMEM against the value supplied\n+ * and if correct begin execution from the start of IMEM. The caller supplies a\n+ * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC\n+ * computation runs from the start of IMEM, and from the start of DMEM + 16k,\n+ * to match flash booting. The command will respond with EINVAL if the CMAC\n+ * does match, otherwise it will respond with success before it jumps to IMEM.\n+ */\n+#define\tMC_CMD_EXEC_SIGNED 0x10c\n+#undef\tMC_CMD_0x10c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_EXEC_SIGNED_IN msgrequest */\n+#define\tMC_CMD_EXEC_SIGNED_IN_LEN 28\n+/* the length of code to include in the CMAC */\n+#define\tMC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0\n+/* the length of date to include in the CMAC */\n+#define\tMC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4\n+/* the XPM sector containing the key to use */\n+#define\tMC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8\n+/* the expected CMAC value */\n+#define\tMC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12\n+#define\tMC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16\n+\n+/* MC_CMD_EXEC_SIGNED_OUT msgresponse */\n+#define\tMC_CMD_EXEC_SIGNED_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_PREPARE_SIGNED\n+ * Prepare to upload a signed image. This will scrub the specified length of\n+ * the data region, which must be at least as large as the DATALEN supplied to\n+ * MC_CMD_EXEC_SIGNED.\n+ */\n+#define\tMC_CMD_PREPARE_SIGNED 0x10d\n+#undef\tMC_CMD_0x10d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_PREPARE_SIGNED_IN msgrequest */\n+#define\tMC_CMD_PREPARE_SIGNED_IN_LEN 4\n+/* the length of data area to clear */\n+#define\tMC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0\n+\n+/* MC_CMD_PREPARE_SIGNED_OUT msgresponse */\n+#define\tMC_CMD_PREPARE_SIGNED_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_SECURITY_RULE\n+ * Set blacklist and/or whitelist action for a particular match criteria.\n+ * (Medford-only; for use by SolarSecure apps, not directly by drivers. See\n+ * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet\n+ * been used in any released code and may change during development. This note\n+ * will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE 0x10f\n+#undef\tMC_CMD_0x10f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_SECURITY_RULE_IN msgrequest */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LEN 92\n+/* fields to include in match criteria */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1\n+/* remote MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6\n+/* remote port to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2\n+/* local MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6\n+/* local port to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2\n+/* Ethernet type to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2\n+/* Inner VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2\n+/* Outer VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2\n+/* IP protocol to match (in low byte; set high byte to 0) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2\n+/* Physical port to match (as little-endian 32-bit value) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28\n+/* Reserved; set to 0 */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32\n+/* remote IP address to match (as bytes in network order; set last 12 bytes to\n+ * 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16\n+/* local IP address to match (as bytes in network order; set last 12 bytes to 0\n+ * for IPv4 address)\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16\n+/* remote subnet ID to match (as little-endian 32-bit value); note that remote\n+ * subnets are matched by mapping the remote IP address to a \"subnet ID\" via a\n+ * data structure which must already have been configured using\n+ * MC_CMD_SUBNET_MAP_SET_NODE appropriately\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68\n+/* remote portrange ID to match (as little-endian 32-bit value); note that\n+ * remote port ranges are matched by mapping the remote port to a \"portrange\n+ * ID\" via a data structure which must already have been configured using\n+ * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72\n+/* local portrange ID to match (as little-endian 32-bit value); note that local\n+ * port ranges are matched by mapping the local port to a \"portrange ID\" via a\n+ * data structure which must already have been configured using\n+ * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76\n+/* set the action for transmitted packets matching this rule */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80\n+/* enum: make no decision */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE  0x0\n+/* enum: decide to accept the packet */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST  0x1\n+/* enum: decide to drop the packet */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST  0x2\n+/* enum: do not change the current TX action */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED  0xffffffff\n+/* set the action for received packets matching this rule */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84\n+/* enum: make no decision */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE  0x0\n+/* enum: decide to accept the packet */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST  0x1\n+/* enum: decide to drop the packet */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST  0x2\n+/* enum: do not change the current RX action */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED  0xffffffff\n+/* counter ID to associate with this rule; IDs are allocated using\n+ * MC_CMD_SECURITY_RULE_COUNTER_ALLOC\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88\n+/* enum: special value for the null counter ID */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE  0x0\n+\n+/* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LEN 28\n+/* new reference count for uses of counter ID */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0\n+/* constructed match bits for this rule (as a tracing aid only) */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12\n+/* constructed discriminator bits for this rule (as a tracing aid only) */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16\n+/* base location for probes for this rule (as a tracing aid only) */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20\n+/* step for probes for this rule (as a tracing aid only) */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24\n+\n+\n+/***********************************/\n+/* MC_CMD_RESET_SECURITY_RULES\n+ * Reset all blacklist and whitelist actions for a particular physical port, or\n+ * all ports. (Medford-only; for use by SolarSecure apps, not directly by\n+ * drivers. See SF-114946-SW.) NOTE - this message definition is provisional.\n+ * It has not yet been used in any released code and may change during\n+ * development. This note will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_RESET_SECURITY_RULES 0x110\n+#undef\tMC_CMD_0x110_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */\n+#define\tMC_CMD_RESET_SECURITY_RULES_IN_LEN 4\n+/* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */\n+#define\tMC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0\n+/* enum: special value to reset all physical ports */\n+#define\tMC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS  0xffffffff\n+\n+/* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */\n+#define\tMC_CMD_RESET_SECURITY_RULES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_SECURITY_RULESET_VERSION\n+ * Return a large hash value representing a \"version\" of the complete set of\n+ * currently active blacklist / whitelist rules and associated data structures.\n+ * (Medford-only; for use by SolarSecure apps, not directly by drivers. See\n+ * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet\n+ * been used in any released code and may change during development. This note\n+ * will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION 0x111\n+#undef\tMC_CMD_0x111_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0\n+\n+/* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num))\n+/* Opaque hash value; length may vary depending on the hash scheme used */\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252\n+\n+\n+/***********************************/\n+/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC\n+ * Allocate counters for use with blacklist / whitelist rules. (Medford-only;\n+ * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.)\n+ * NOTE - this message definition is provisional. It has not yet been used in\n+ * any released code and may change during development. This note will be\n+ * removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112\n+#undef\tMC_CMD_0x112_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4\n+/* the number of new counter IDs to request */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0\n+\n+/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num))\n+/* the number of new counter IDs allocated (may be less than the number\n+ * requested if resources are unavailable)\n+ */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0\n+/* new counter ID(s) */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62\n+\n+\n+/***********************************/\n+/* MC_CMD_SECURITY_RULE_COUNTER_FREE\n+ * Allocate counters for use with blacklist / whitelist rules. (Medford-only;\n+ * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.)\n+ * NOTE - this message definition is provisional. It has not yet been used in\n+ * any released code and may change during development. This note will be\n+ * removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE 0x113\n+#undef\tMC_CMD_0x113_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num))\n+/* the number of counter IDs to free */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0\n+/* the counter ID(s) to free */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62\n+\n+/* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SUBNET_MAP_SET_NODE\n+ * Atomically update a trie node in the map of subnets to subnet IDs. The\n+ * constants in the descriptions of the fields of this message may be retrieved\n+ * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford-\n+ * only; for use by SolarSecure apps, not directly by drivers. See\n+ * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet\n+ * been used in any released code and may change during development. This note\n+ * will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE 0x114\n+#undef\tMC_CMD_0x114_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num))\n+/* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0\n+/* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer\n+ * to the next node, expressed as an offset in the trie memory (i.e. node ID\n+ * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range\n+ * SUBNET_ID_MIN .. SUBNET_ID_MAX\n+ */\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124\n+\n+/* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0\n+\n+/* PORTRANGE_TREE_ENTRY structuredef */\n+#define\tPORTRANGE_TREE_ENTRY_LEN 4\n+/* key for branch nodes (<= key takes left branch, > key takes right branch),\n+ * or magic value for leaf nodes\n+ */\n+#define\tPORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0\n+#define\tPORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2\n+#define\tPORTRANGE_TREE_ENTRY_LEAF_NODE_KEY  0xffff /* enum */\n+#define\tPORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0\n+#define\tPORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16\n+/* final portrange ID for leaf nodes (don't care for branch nodes) */\n+#define\tPORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2\n+#define\tPORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2\n+#define\tPORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16\n+#define\tPORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16\n+\n+\n+/***********************************/\n+/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE\n+ * Atomically update the entire tree mapping remote port ranges to portrange\n+ * IDs. The constants in the descriptions of the fields of this message may be\n+ * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO.\n+ * (Medford-only; for use by SolarSecure apps, not directly by drivers. See\n+ * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet\n+ * been used in any released code and may change during development. This note\n+ * will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115\n+#undef\tMC_CMD_0x115_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))\n+/* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a\n+ * PORTRANGE_TREE_ENTRY\n+ */\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63\n+\n+/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE\n+ * Atomically update the entire tree mapping remote port ranges to portrange\n+ * IDs. The constants in the descriptions of the fields of this message may be\n+ * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO.\n+ * (Medford-only; for use by SolarSecure apps, not directly by drivers. See\n+ * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet\n+ * been used in any released code and may change during development. This note\n+ * will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116\n+#undef\tMC_CMD_0x116_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))\n+/* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a\n+ * PORTRANGE_TREE_ENTRY\n+ */\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63\n+\n+/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0\n+\n+/* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4\n+/* UDP port (the standard ports are named below but any port may be used) */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2\n+/* enum: the IANA allocated UDP port for VXLAN */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT  0x12b5\n+/* enum: the IANA allocated UDP port for Geneve */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT  0x17c1\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16\n+/* tunnel encapsulation protocol (only those named below are supported) */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2\n+/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN  0x0\n+/* enum: This port will be used for Geneve on both IPv4 and IPv6 */\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE  0x1\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16\n+#define\tTUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS\n+ * Configure UDP ports for tunnel encapsulation hardware acceleration. The\n+ * parser-dispatcher will attempt to parse traffic on these ports as tunnel\n+ * encapsulation PDUs and filter them using the tunnel encapsulation filter\n+ * chain rather than the standard filter chain. Note that this command can\n+ * cause all functions to see a reset. (Available on Medford only.)\n+ */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117\n+#undef\tMC_CMD_0x117_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))\n+/* Flags */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1\n+/* The number of entries in the ENTRIES array */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2\n+/* Entries defining the UDP port to protocol mapping, each laid out as a\n+ * TUNNEL_ENCAP_UDP_PORT_ENTRY\n+ */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16\n+\n+/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2\n+/* Flags */\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1\n+\n+\n+/***********************************/\n+/* MC_CMD_RX_BALANCING\n+ * Configure a port upconverter to distribute the packets on both RX engines.\n+ * Packets are distributed based on a table with the destination vFIFO. The\n+ * index of the table is a hash of source and destination of IPV4 and VLAN\n+ * priority.\n+ */\n+#define\tMC_CMD_RX_BALANCING 0x118\n+#undef\tMC_CMD_0x118_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_RX_BALANCING_IN msgrequest */\n+#define\tMC_CMD_RX_BALANCING_IN_LEN 16\n+/* The RX port whose upconverter table will be modified */\n+#define\tMC_CMD_RX_BALANCING_IN_PORT_OFST 0\n+/* The VLAN priority associated to the table index and vFIFO */\n+#define\tMC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4\n+/* The resulting bit of SRC^DST for indexing the table */\n+#define\tMC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8\n+/* The RX engine to which the vFIFO in the table entry will point to */\n+#define\tMC_CMD_RX_BALANCING_IN_ENG_OFST 12\n+\n+/* MC_CMD_RX_BALANCING_OUT msgresponse */\n+#define\tMC_CMD_RX_BALANCING_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_BIND\n+ * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more\n+ * info in respect to the binding protocol. This MCDI command is only available\n+ * over a TLS secure connection between the TSAN and TSAC, and is not available\n+ * to host software. Note- The messages definitions that do comprise this MCDI\n+ * command deemed as provisional. This MCDI command has not yet been used in\n+ * any released code and may change during development. This note will be\n+ * removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_TSA_BIND 0x119\n+#undef\tMC_CMD_0x119_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */\n+#define\tMC_CMD_TSA_BIND_IN_LEN 4\n+#define\tMC_CMD_TSA_BIND_IN_OP_OFST 0\n+/* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for\n+ * the network adapter. More specifically, TSAN ID equals the MAC address of\n+ * the network adapter. TSAN ID is used as part of the TSAN authentication\n+ * protocol. Refer to SF-114946-SW for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_GET_ID 0x1\n+/* enum: Get a binding ticket from the TSAN. The binding ticket is used as part\n+ * of the binding procedure to authorize the binding of an adapter to a TSAID.\n+ * Refer to SF-114946-SW for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_GET_TICKET 0x2\n+/* enum: Opcode associated with the propagation of a private key that TSAN uses\n+ * as part of post-binding authentication procedure. More specifically, TSAN\n+ * uses this key for a signing operation. TSAC uses the counterpart public key\n+ * to verify the signature. Note - The post-binding authentication occurs when\n+ * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to\n+ * SF-114946-SW for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_SET_KEY 0x3\n+/* enum: Request an unbinding operation. Note- TSAN clears the binding ticket\n+ * from the Nvram section.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_UNBIND 0x4\n+\n+/* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */\n+#define\tMC_CMD_TSA_BIND_IN_GET_ID_LEN 20\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0\n+/* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates\n+ * the nonce every time as part of the TSAN post-binding authentication\n+ * procedure when the TSAN-TSAC connection terminates and TSAN does need to re-\n+ * connect to the TSAC. Refer to SF-114946-SW for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16\n+\n+/* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */\n+#define\tMC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0\n+\n+/* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num))\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0\n+/* This data blob contains the private key generated by the TSAC. TSAN uses\n+ * this key for a signing operation. Note- This private key is used in\n+ * conjunction with the post-binding TSAN authentication procedure that occurs\n+ * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer\n+ * to SF-114946-SW for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248\n+\n+/* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_LEN 10\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0\n+/* TSAN unique identifier for the network adapter */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6\n+\n+/* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num))\n+/* The operation completion code. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0\n+/* Rules engine type. Note- The rules engine type allows TSAC to further\n+ * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the\n+ * proper action accordingly. As an example, TSAC uses the rules engine type to\n+ * select the SF key that differs in the case of TSAN vs. NIC Emulator.\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4\n+/* enum: Hardware rules engine. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1\n+/* enum: Nic emulator rules engine. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2\n+/* enum: SSFE. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3\n+/* TSAN unique identifier for the network adapter */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6\n+/* The signature data blob. The signature is computed against the message\n+ * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC\n+ * for more information also in respect to the private keys that are used to\n+ * sign the message based on TSAN pre/post-binding authentication procedure.\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238\n+\n+/* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num))\n+/* The operation completion code. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0\n+/* The ticket represents the data blob construct that TSAN sends to TSAC as\n+ * part of the binding protocol. From the TSAN perspective the ticket is an\n+ * opaque construct. For more info refer to SF-115479-TC.\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248\n+\n+/* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4\n+/* The operation completion code. */\n+#define\tMC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0\n+\n+/* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_LEN 8\n+/* Same as MC_CMD_ERR field, but included as 0 in success cases */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0\n+/* Extra status information */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4\n+/* enum: Unbind successful. */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND  0x0\n+/* enum: TSANID mismatch */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID  0x1\n+/* enum: Unable to remove the binding ticket from persistent storage. */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET  0x2\n+/* enum: TSAN is not bound to a binding ticket. */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND  0x3\n+\n+\n+/***********************************/\n+/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE\n+ * Manage the persistent NVRAM cache of security rules created with\n+ * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated\n+ * as rules are added or removed; the active ruleset must be explicitly\n+ * committed to the cache. The cache may also be explicitly invalidated,\n+ * without affecting the currently active ruleset. When the cache is valid, it\n+ * will be loaded at power on or MC reboot, instead of the default ruleset.\n+ * Rollback of the currently active ruleset to the cached version (when it is\n+ * valid) is also supported. (Medford-only; for use by SolarSecure apps, not\n+ * directly by drivers. See SF-114946-SW.) NOTE - this message definition is\n+ * provisional. It has not yet been used in any released code and may change\n+ * during development. This note will be removed once it is regarded as stable.\n+ */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a\n+#undef\tMC_CMD_0x11a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4\n+/* the operation to perform */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0\n+/* enum: reports the ruleset version that is cached in persistent storage but\n+ * performs no other action\n+ */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION  0x0\n+/* enum: rolls back the active state to the cached version. (May fail with\n+ * ENOENT if there is no valid cached version.)\n+ */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK  0x1\n+/* enum: commits the active state to the persistent cache */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT  0x2\n+/* enum: invalidates the persistent cache without affecting the active state */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE  0x3\n+\n+/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num))\n+/* indicates whether the persistent cache is valid (after completion of the\n+ * requested operation in the case of rollback, commit, or invalidate)\n+ */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0\n+/* enum: persistent cache is invalid (the VERSION field will be empty in this\n+ * case)\n+ */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID  0x0\n+/* enum: persistent cache is valid */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID  0x1\n+/* cached ruleset version (after completion of the requested operation, in the\n+ * case of rollback, commit, or invalidate) as an opaque hash value in the same\n+ * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION\n+ */\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248\n+\n+\n+/***********************************/\n+/* MC_CMD_NVRAM_PRIVATE_APPEND\n+ * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST\n+ * if the tag is already present.\n+ */\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND 0x11c\n+#undef\tMC_CMD_0x11c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))\n+/* The tag to be appended */\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0\n+/* The length of the data */\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4\n+/* The data to be contained in the TLV structure */\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244\n+\n+/* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_XPM_VERIFY_CONTENTS\n+ * Verify that the contents of the XPM memory is correct (Medford only). This\n+ * is used during manufacture to check that the XPM memory has been programmed\n+ * correctly at ATE.\n+ */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS 0x11b\n+#undef\tMC_CMD_0x11b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4\n+/* Data type to be checked */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0\n+\n+/* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))\n+/* Number of sectors found (test builds only) */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0\n+/* Number of bytes found (test builds only) */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4\n+/* Length of signature */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8\n+/* Signature */\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_EVQ_TMR\n+ * Update the timer load, timer reload and timer mode values for a given EVQ.\n+ * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will\n+ * be rounded up to the granularity supported by the hardware, then truncated\n+ * to the range supported by the hardware. The resulting value after the\n+ * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS\n+ * and TMR_RELOAD_ACT_NS).\n+ */\n+#define\tMC_CMD_SET_EVQ_TMR 0x120\n+#undef\tMC_CMD_0x120_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_EVQ_TMR_IN msgrequest */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_LEN 16\n+/* Function-relative queue instance */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0\n+/* Requested value for timer load (in nanoseconds) */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4\n+/* Requested value for timer reload (in nanoseconds) */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8\n+/* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS  0x0 /* enum */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START  0x1 /* enum */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START  0x2 /* enum */\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF  0x3 /* enum */\n+\n+/* MC_CMD_SET_EVQ_TMR_OUT msgresponse */\n+#define\tMC_CMD_SET_EVQ_TMR_OUT_LEN 8\n+/* Actual value for timer load (in nanoseconds) */\n+#define\tMC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0\n+/* Actual value for timer reload (in nanoseconds) */\n+#define\tMC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_EVQ_TMR_PROPERTIES\n+ * Query properties about the event queue timers.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES 0x122\n+#undef\tMC_CMD_0x122_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0\n+\n+/* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36\n+/* Reserved for future use. */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0\n+/* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in\n+ * nanoseconds) for each increment of the timer load/reload count. The\n+ * requested duration of a timer is this value multiplied by the timer\n+ * load/reload count.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4\n+/* For timers updated via writes to EVQ_TMR_REG, this is the maximum value\n+ * allowed for timer load/reload counts.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8\n+/* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a\n+ * multiple of this step size will be rounded in an implementation defined\n+ * manner.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12\n+/* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only\n+ * meaningful if MC_CMD_SET_EVQ_TMR is implemented.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16\n+/* Timer durations requested via MCDI that are not a multiple of this step size\n+ * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20\n+/* For timers updated using the bug35388 workaround, this is the time interval\n+ * (in nanoseconds) for each increment of the timer load/reload count. The\n+ * requested duration of a timer is this value multiplied by the timer\n+ * load/reload count. This field is only meaningful if the bug35388 workaround\n+ * is enabled.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24\n+/* For timers updated using the bug35388 workaround, this is the maximum value\n+ * allowed for timer load/reload counts. This field is only meaningful if the\n+ * bug35388 workaround is enabled.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28\n+/* For timers updated using the bug35388 workaround, timer load/reload counts\n+ * not a multiple of this step size will be rounded in an implementation\n+ * defined manner. This field is only meaningful if the bug35388 workaround is\n+ * enabled.\n+ */\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32\n+\n+\n+/***********************************/\n+/* MC_CMD_ALLOCATE_TX_VFIFO_CP\n+ * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the\n+ * non used switch buffers.\n+ */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d\n+#undef\tMC_CMD_0x11d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0\n+/* Will the common pool be used as TX_vFIFO_ULL (1) */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED       0x1 /* enum */\n+/* enum: Using this interface without TX_vFIFO_ULL is not supported for now */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED      0x0\n+/* Number of buffers to reserve for the common pool */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8\n+/* TX datapath to which the Common Pool is connected to. */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12\n+/* enum: Extracts information from function */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE          -0x1\n+/* Network port or RX Engine to which the common pool connects. */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16\n+/* enum: Extracts information from function */\n+/*               MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE          -0x1 */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0          0x0 /* enum */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1          0x1 /* enum */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2          0x2 /* enum */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3          0x3 /* enum */\n+/* enum: To enable Switch loopback with Rx engine 0 */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0     0x4\n+/* enum: To enable Switch loopback with Rx engine 1 */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1     0x5\n+\n+/* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4\n+/* ID of the common pool allocated */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0\n+\n+\n+/***********************************/\n+/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO\n+ * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the\n+ * previously allocated common pools.\n+ */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e\n+#undef\tMC_CMD_0x11e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20\n+/* Common pool previously allocated to which the new vFIFO will be associated\n+ */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0\n+/* Port or RX engine to associate the vFIFO egress */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4\n+/* enum: Extracts information from common pool */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE   -0x1\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0          0x0 /* enum */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1          0x1 /* enum */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2          0x2 /* enum */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3          0x3 /* enum */\n+/* enum: To enable Switch loopback with Rx engine 0 */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0     0x4\n+/* enum: To enable Switch loopback with Rx engine 1 */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1     0x5\n+/* Minimum number of buffers that the pool must have */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8\n+/* enum: Do not check the space available */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM     0x0\n+/* Will the vFIFO be used as TX_vFIFO_ULL */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12\n+/* Network priority of the vFIFO,if applicable */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16\n+/* enum: Search for the lowest unused priority */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE  -0x1\n+\n+/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8\n+/* Short vFIFO ID */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0\n+/* Network priority of the vFIFO */\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_TEARDOWN_TX_VFIFO_VF\n+ * This interface clears the configuration of the given vFIFO and leaves it\n+ * ready to be re-used.\n+ */\n+#define\tMC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f\n+#undef\tMC_CMD_0x11f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */\n+#define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4\n+/* Short vFIFO ID */\n+#define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0\n+\n+/* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */\n+#define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_DEALLOCATE_TX_VFIFO_CP\n+ * This interface clears the configuration of the given common pool and leaves\n+ * it ready to be re-used.\n+ */\n+#define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121\n+#undef\tMC_CMD_0x121_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */\n+#define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4\n+/* Common pool ID given when pool allocated */\n+#define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0\n+\n+/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */\n+#define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_REKEY\n+ * This request causes the NIC to generate a new per-NIC key and program it\n+ * into the write-once memory. During the process all flash partitions that are\n+ * protected with a CMAC are verified with the old per-NIC key and then signed\n+ * with the new per-NIC key. If the NIC has already reached its rekey limit the\n+ * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until\n+ * completion or it may return 0 and continue processing, therefore the caller\n+ * must poll at least once to confirm that the rekeying has completed. The POLL\n+ * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running\n+ * otherwise it will return the result of the last completed rekey operation,\n+ * or 0 if there has not been a previous rekey.\n+ */\n+#define\tMC_CMD_REKEY 0x123\n+#undef\tMC_CMD_0x123_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_REKEY_IN msgrequest */\n+#define\tMC_CMD_REKEY_IN_LEN 4\n+/* the type of operation requested */\n+#define\tMC_CMD_REKEY_IN_OP_OFST 0\n+/* enum: Start the rekeying operation */\n+#define\tMC_CMD_REKEY_IN_OP_REKEY  0x0\n+/* enum: Poll for completion of the rekeying operation */\n+#define\tMC_CMD_REKEY_IN_OP_POLL  0x1\n+\n+/* MC_CMD_REKEY_OUT msgresponse */\n+#define\tMC_CMD_REKEY_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS\n+ * This interface allows the host to find out how many common pool buffers are\n+ * not yet assigned.\n+ */\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124\n+#undef\tMC_CMD_0x124_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0\n+\n+/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8\n+/* Available buffers for the ENG to NET vFIFOs. */\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0\n+/* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_SECURITY_FUSES\n+ * Change the security level of the adapter by setting bits in the write-once\n+ * memory. The firmware maps each flag in the message to a set of one or more\n+ * hardware-defined or software-defined bits and sets these bits in the write-\n+ * once memory. For Medford the hardware-defined bits are defined in\n+ * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0\n+ * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of\n+ * the required bits were not set.\n+ */\n+#define\tMC_CMD_SET_SECURITY_FUSES 0x126\n+#undef\tMC_CMD_0x126_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_LEN 4\n+/* Flags specifying what type of security features are being set */\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1\n+\n+/* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */\n+#define\tMC_CMD_SET_SECURITY_FUSES_OUT_LEN 0\n+\n+#endif /* _SIENA_MC_DRIVER_PCOL_H */\n+/*! \\cidoxg_end */\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "05/55"
    ]
}