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GET /api/patches/17318/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 17318,
    "url": "https://patches.dpdk.org/api/patches/17318/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-46-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1480436367-20749-46-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1480436367-20749-46-git-send-email-arybchenko@solarflare.com",
    "date": "2016-11-29T16:19:17",
    "name": "[dpdk-dev,v2,45/55] net/sfc: implement Rx queue setup release operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "3fc0e95412638aec3adad381735ca4ee6993e832",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-46-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/17318/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/17318/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C41D5FAE3;\n\tTue, 29 Nov 2016 17:22:51 +0100 (CET)",
            "from nbfkord-smmo01.seg.att.com (nbfkord-smmo01.seg.att.com\n\t[209.65.160.76]) by dpdk.org (Postfix) with ESMTP id 8CB184A59\n\tfor <dev@dpdk.org>; Tue, 29 Nov 2016 17:20:56 +0100 (CET)",
            "from unknown [12.187.104.26] (EHLO nbfkord-smmo01.seg.att.com)\n\tby nbfkord-smmo01.seg.att.com(mxl_mta-7.2.4-7) with ESMTP id\n\t8eaad385.2b3e4de02940.83618.00-2486.174003.nbfkord-smmo01.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tTue, 29 Nov 2016 16:20:56 +0000 (UTC)",
            "from unknown [12.187.104.26]\n\tby nbfkord-smmo01.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\t6eaad385.0.83424.00-2358.173938.nbfkord-smmo01.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tTue, 29 Nov 2016 16:20:55 +0000 (UTC)",
            "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Tue, 29 Nov 2016 08:20:26 -0800",
            "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Tue, 29 Nov 2016 08:20:25 -0800",
            "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuATGKOlE030035; Tue, 29 Nov 2016 16:20:24 GMT",
            "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuATGKM1r021233; Tue, 29 Nov 2016 16:20:24 GMT"
        ],
        "X-MXL-Hash": [
            "583daae81f962cce-e6bd97982b3ae853848e80bfd5d8ca9f5897e9c7",
            "583daae71c673de7-26a611eb1ee68755940214f09a31ab138a13eec7"
        ],
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>",
        "Date": "Tue, 29 Nov 2016 16:19:17 +0000",
        "Message-ID": "<1480436367-20749-46-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>\n\t<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-AnalysisOut": [
            "[v=2.1 cv=UoJlQrEB c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]",
            "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=7SYgjl-cy90FXsqJQ]",
            "[kMA:9 a=PA03WX8tBzeizutn5_OT:22]"
        ],
        "X-Spam": "[F=0.4296722620; CM=0.500; S=0.429(2015072901)]",
        "X-MAIL-FROM": "<arybchenko@solarflare.com>",
        "X-SOURCE-IP": "[12.187.104.26]",
        "Subject": "[dpdk-dev] [PATCH v2 45/55] net/sfc: implement Rx queue setup\n\trelease operations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Reviewed-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/sfc_ethdev.c |  60 ++++++++++++++++++\n drivers/net/sfc/sfc_ev.h     |   2 +\n drivers/net/sfc/sfc_rx.c     | 147 +++++++++++++++++++++++++++++++++++++++++++\n drivers/net/sfc/sfc_rx.h     |  64 +++++++++++++++++++\n 4 files changed, 273 insertions(+)",
    "diff": "diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c\nindex f39addb..594ae7a 100644\n--- a/drivers/net/sfc/sfc_ethdev.c\n+++ b/drivers/net/sfc/sfc_ethdev.c\n@@ -38,6 +38,7 @@\n #include \"sfc_log.h\"\n #include \"sfc_kvargs.h\"\n #include \"sfc_ev.h\"\n+#include \"sfc_rx.h\"\n \n \n static void\n@@ -51,6 +52,8 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \n \tdev_info->max_rx_pktlen = EFX_MAC_PDU_MAX;\n \n+\tdev_info->max_rx_queues = sa->rxq_max;\n+\n \t/* By default packets are dropped if no descriptors are available */\n \tdev_info->default_rxconf.rx_drop_en = 1;\n \n@@ -193,6 +196,61 @@ sfc_dev_close(struct rte_eth_dev *dev)\n \tsfc_log_init(sa, \"done\");\n }\n \n+static int\n+sfc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n+\t\t   uint16_t nb_rx_desc, unsigned int socket_id,\n+\t\t   const struct rte_eth_rxconf *rx_conf,\n+\t\t   struct rte_mempool *mb_pool)\n+{\n+\tstruct sfc_adapter *sa = dev->data->dev_private;\n+\tint rc;\n+\n+\tsfc_log_init(sa, \"RxQ=%u nb_rx_desc=%u socket_id=%u\",\n+\t\t     rx_queue_id, nb_rx_desc, socket_id);\n+\n+\tsfc_adapter_lock(sa);\n+\n+\trc = sfc_rx_qinit(sa, rx_queue_id, nb_rx_desc, socket_id,\n+\t\t\t  rx_conf, mb_pool);\n+\tif (rc != 0)\n+\t\tgoto fail_rx_qinit;\n+\n+\tdev->data->rx_queues[rx_queue_id] = sa->rxq_info[rx_queue_id].rxq;\n+\n+\tsfc_adapter_unlock(sa);\n+\n+\treturn 0;\n+\n+fail_rx_qinit:\n+\tsfc_adapter_unlock(sa);\n+\tSFC_ASSERT(rc > 0);\n+\treturn -rc;\n+}\n+\n+static void\n+sfc_rx_queue_release(void *queue)\n+{\n+\tstruct sfc_rxq *rxq = queue;\n+\tstruct sfc_adapter *sa;\n+\tunsigned int sw_index;\n+\n+\tif (rxq == NULL)\n+\t\treturn;\n+\n+\tsa = rxq->evq->sa;\n+\tsfc_adapter_lock(sa);\n+\n+\tsw_index = sfc_rxq_sw_index(rxq);\n+\n+\tsfc_log_init(sa, \"RxQ=%u\", sw_index);\n+\n+\tsa->eth_dev->data->rx_queues[sw_index] = NULL;\n+\n+\tsfc_rx_qfini(sa, sw_index);\n+\n+\tsfc_adapter_unlock(sa);\n+}\n+\n static const struct eth_dev_ops sfc_eth_dev_ops = {\n \t.dev_configure\t\t\t= sfc_dev_configure,\n \t.dev_start\t\t\t= sfc_dev_start,\n@@ -200,6 +258,8 @@ static const struct eth_dev_ops sfc_eth_dev_ops = {\n \t.dev_close\t\t\t= sfc_dev_close,\n \t.link_update\t\t\t= sfc_dev_link_update,\n \t.dev_infos_get\t\t\t= sfc_dev_infos_get,\n+\t.rx_queue_setup\t\t\t= sfc_rx_queue_setup,\n+\t.rx_queue_release\t\t= sfc_rx_queue_release,\n };\n \n static int\ndiff --git a/drivers/net/sfc/sfc_ev.h b/drivers/net/sfc/sfc_ev.h\nindex 8455fda..f38e6b8 100644\n--- a/drivers/net/sfc/sfc_ev.h\n+++ b/drivers/net/sfc/sfc_ev.h\n@@ -40,6 +40,7 @@ extern \"C\" {\n #define SFC_MGMT_EVQ_ENTRIES\t(EFX_EVQ_MINNEVS)\n \n struct sfc_adapter;\n+struct sfc_rxq;\n \n enum sfc_evq_state {\n \tSFC_EVQ_UNINITIALIZED = 0,\n@@ -56,6 +57,7 @@ struct sfc_evq {\n \tunsigned int\t\tread_ptr;\n \tboolean_t\t\texception;\n \tefsys_mem_t\t\tmem;\n+\tstruct sfc_rxq\t\t*rxq;\n \n \t/* Not used on datapath */\n \tstruct sfc_adapter\t*sa;\ndiff --git a/drivers/net/sfc/sfc_rx.c b/drivers/net/sfc/sfc_rx.c\nindex 88e3319..00bcc9d 100644\n--- a/drivers/net/sfc/sfc_rx.c\n+++ b/drivers/net/sfc/sfc_rx.c\n@@ -31,9 +31,148 @@\n \n #include \"sfc.h\"\n #include \"sfc_log.h\"\n+#include \"sfc_ev.h\"\n #include \"sfc_rx.h\"\n \n static int\n+sfc_rx_qcheck_conf(struct sfc_adapter *sa,\n+\t\t   const struct rte_eth_rxconf *rx_conf)\n+{\n+\tint rc = 0;\n+\n+\tif (rx_conf->rx_thresh.pthresh != 0 ||\n+\t    rx_conf->rx_thresh.hthresh != 0 ||\n+\t    rx_conf->rx_thresh.wthresh != 0) {\n+\t\tsfc_err(sa,\n+\t\t\t\"RxQ prefetch/host/writeback thresholds are not supported\");\n+\t\trc = EINVAL;\n+\t}\n+\n+\tif (rx_conf->rx_free_thresh != 0) {\n+\t\tsfc_err(sa, \"RxQ free threshold is not supported\");\n+\t\trc = EINVAL;\n+\t}\n+\n+\tif (rx_conf->rx_drop_en == 0) {\n+\t\tsfc_err(sa, \"RxQ drop disable is not supported\");\n+\t\trc = EINVAL;\n+\t}\n+\n+\tif (rx_conf->rx_deferred_start != 0) {\n+\t\tsfc_err(sa, \"RxQ deferred start is not supported\");\n+\t\trc = EINVAL;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,\n+\t     uint16_t nb_rx_desc, unsigned int socket_id,\n+\t     const struct rte_eth_rxconf *rx_conf,\n+\t     struct rte_mempool *mb_pool)\n+{\n+\tint rc;\n+\tstruct sfc_rxq_info *rxq_info;\n+\tunsigned int evq_index;\n+\tstruct sfc_evq *evq;\n+\tstruct sfc_rxq *rxq;\n+\n+\trc = sfc_rx_qcheck_conf(sa, rx_conf);\n+\tif (rc != 0)\n+\t\tgoto fail_bad_conf;\n+\n+\tif (rte_pktmbuf_data_room_size(mb_pool) <= RTE_PKTMBUF_HEADROOM) {\n+\t\tsfc_err(sa, \"RxQ %u mbuf is too small, %u vs headroom %u\",\n+\t\t\tsw_index, rte_pktmbuf_data_room_size(mb_pool),\n+\t\t\tRTE_PKTMBUF_HEADROOM);\n+\t\tgoto fail_bad_conf;\n+\t}\n+\n+\tSFC_ASSERT(sw_index < sa->rxq_count);\n+\trxq_info = &sa->rxq_info[sw_index];\n+\n+\tSFC_ASSERT(nb_rx_desc <= rxq_info->max_entries);\n+\trxq_info->entries = nb_rx_desc;\n+\trxq_info->type = EFX_RXQ_TYPE_DEFAULT;\n+\n+\tevq_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index);\n+\n+\trc = sfc_ev_qinit(sa, evq_index, rxq_info->entries, socket_id);\n+\tif (rc != 0)\n+\t\tgoto fail_ev_qinit;\n+\n+\tevq = sa->evq_info[evq_index].evq;\n+\n+\trc = ENOMEM;\n+\trxq = rte_zmalloc_socket(\"sfc-rxq\", sizeof(*rxq), RTE_CACHE_LINE_SIZE,\n+\t\t\t\t socket_id);\n+\tif (rxq == NULL)\n+\t\tgoto fail_rxq_alloc;\n+\n+\trc = sfc_dma_alloc(sa, \"rxq\", sw_index, EFX_RXQ_SIZE(rxq_info->entries),\n+\t\t\t   socket_id, &rxq->mem);\n+\tif (rc != 0)\n+\t\tgoto fail_dma_alloc;\n+\n+\trc = ENOMEM;\n+\trxq->sw_desc = rte_calloc_socket(\"sfc-rxq-sw_desc\", rxq_info->entries,\n+\t\t\t\t\t sizeof(*rxq->sw_desc),\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (rxq->sw_desc == NULL)\n+\t\tgoto fail_desc_alloc;\n+\n+\tevq->rxq = rxq;\n+\trxq->evq = evq;\n+\trxq->ptr_mask = rxq_info->entries - 1;\n+\trxq->refill_mb_pool = mb_pool;\n+\trxq->hw_index = sw_index;\n+\n+\trxq->state = SFC_RXQ_INITIALIZED;\n+\n+\trxq_info->rxq = rxq;\n+\n+\treturn 0;\n+\n+fail_desc_alloc:\n+\tsfc_dma_free(sa, &rxq->mem);\n+\n+fail_dma_alloc:\n+\trte_free(rxq);\n+\n+fail_rxq_alloc:\n+\tsfc_ev_qfini(sa, evq_index);\n+\n+fail_ev_qinit:\n+\trxq_info->entries = 0;\n+\n+fail_bad_conf:\n+\tsfc_log_init(sa, \"failed %d\", rc);\n+\treturn rc;\n+}\n+\n+void\n+sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)\n+{\n+\tstruct sfc_rxq_info *rxq_info;\n+\tstruct sfc_rxq *rxq;\n+\n+\tSFC_ASSERT(sw_index < sa->rxq_count);\n+\n+\trxq_info = &sa->rxq_info[sw_index];\n+\n+\trxq = rxq_info->rxq;\n+\tSFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);\n+\n+\trxq_info->rxq = NULL;\n+\trxq_info->entries = 0;\n+\n+\trte_free(rxq->sw_desc);\n+\tsfc_dma_free(sa, &rxq->mem);\n+\trte_free(rxq);\n+}\n+\n+static int\n sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)\n {\n \tstruct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];\n@@ -158,6 +297,14 @@ sfc_rx_init(struct sfc_adapter *sa)\n void\n sfc_rx_fini(struct sfc_adapter *sa)\n {\n+\tunsigned int sw_index;\n+\n+\tsw_index = sa->rxq_count;\n+\twhile (sw_index-- > 0) {\n+\t\tif (sa->rxq_info[sw_index].rxq != NULL)\n+\t\t\tsfc_rx_qfini(sa, sw_index);\n+\t}\n+\n \trte_free(sa->rxq_info);\n \tsa->rxq_info = NULL;\n \tsa->rxq_count = 0;\ndiff --git a/drivers/net/sfc/sfc_rx.h b/drivers/net/sfc/sfc_rx.h\nindex 2e27b53..b506d9a 100644\n--- a/drivers/net/sfc/sfc_rx.h\n+++ b/drivers/net/sfc/sfc_rx.h\n@@ -30,11 +30,66 @@\n #ifndef _SFC_RX_H\n #define _SFC_RX_H\n \n+#include <rte_mbuf.h>\n+#include <rte_mempool.h>\n+#include <rte_ethdev.h>\n+\n+#include \"efx.h\"\n+\n #ifdef __cplusplus\n extern \"C\" {\n #endif\n \n struct sfc_adapter;\n+struct sfc_evq;\n+\n+/**\n+ * Software Rx descriptor information associated with hardware Rx\n+ * descriptor.\n+ */\n+struct sfc_rx_sw_desc {\n+\tstruct rte_mbuf\t\t*mbuf;\n+\tunsigned int\t\tflags;\n+\tunsigned int\t\tsize;\n+};\n+\n+/** Receive queue state bits */\n+enum sfc_rxq_state_bit {\n+\tSFC_RXQ_INITIALIZED_BIT = 0,\n+#define SFC_RXQ_INITIALIZED\t(1 << SFC_RXQ_INITIALIZED_BIT)\n+};\n+\n+/**\n+ * Receive queue information used on data path.\n+ * Allocated on the socket specified on the queue setup.\n+ */\n+struct sfc_rxq {\n+\t/* Used on data path */\n+\tstruct sfc_evq\t\t*evq;\n+\tstruct sfc_rx_sw_desc\t*sw_desc;\n+\tunsigned int\t\tstate;\n+\tunsigned int\t\tptr_mask;\n+\n+\t/* Used on refill */\n+\tstruct rte_mempool\t*refill_mb_pool;\n+\tefx_rxq_t\t\t*common;\n+\tefsys_mem_t\t\tmem;\n+\n+\t/* Not used on data path */\n+\tunsigned int\t\thw_index;\n+};\n+\n+static inline unsigned int\n+sfc_rxq_sw_index_by_hw_index(unsigned int hw_index)\n+{\n+\treturn hw_index;\n+}\n+\n+static inline unsigned int\n+sfc_rxq_sw_index(const struct sfc_rxq *rxq)\n+{\n+\treturn sfc_rxq_sw_index_by_hw_index(rxq->hw_index);\n+}\n \n /**\n  * Receive queue information used during setup/release only.\n@@ -42,11 +97,20 @@ struct sfc_adapter;\n  */\n struct sfc_rxq_info {\n \tunsigned int\t\tmax_entries;\n+\tunsigned int\t\tentries;\n+\tefx_rxq_type_t\t\ttype;\n+\tstruct sfc_rxq\t\t*rxq;\n };\n \n int sfc_rx_init(struct sfc_adapter *sa);\n void sfc_rx_fini(struct sfc_adapter *sa);\n \n+int sfc_rx_qinit(struct sfc_adapter *sa, unsigned int rx_queue_id,\n+\t\t uint16_t nb_rx_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_rxconf *rx_conf,\n+\t\t struct rte_mempool *mb_pool);\n+void sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index);\n+\n #ifdef __cplusplus\n }\n #endif\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "45/55"
    ]
}