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GET /api/patches/17291/?format=api
{ "id": 17291, "url": "https://patches.dpdk.org/api/patches/17291/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-12-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1480436367-20749-12-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1480436367-20749-12-git-send-email-arybchenko@solarflare.com", "date": "2016-11-29T16:18:43", "name": "[dpdk-dev,v2,11/55] net/sfc: import libefx SFN8xxx family support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7130b47f485e3039a77e1f80672bc62c94971579", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-12-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/17291/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/17291/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 6FA19FA33;\n\tTue, 29 Nov 2016 17:21:47 +0100 (CET)", "from nbfkord-smmo01.seg.att.com (nbfkord-smmo01.seg.att.com\n\t[209.65.160.76]) by dpdk.org (Postfix) with ESMTP id 9328A376D\n\tfor <dev@dpdk.org>; Tue, 29 Nov 2016 17:20:48 +0100 (CET)", "from unknown [12.187.104.26] (EHLO nbfkord-smmo01.seg.att.com)\n\tby nbfkord-smmo01.seg.att.com(mxl_mta-7.2.4-7) with ESMTP id\n\t0eaad385.2b3e74c2d940.83540.00-2488.173796.nbfkord-smmo01.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tTue, 29 Nov 2016 16:20:48 +0000 (UTC)", "from unknown [12.187.104.26]\n\tby nbfkord-smmo01.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\t2daad385.0.83424.00-2367.173534.nbfkord-smmo01.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tTue, 29 Nov 2016 16:20:36 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Tue, 29 Nov 2016 08:20:25 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Tue, 29 Nov 2016 08:20:24 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuATGKNWJ029924; Tue, 29 Nov 2016 16:20:23 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuATGKM1J021233; Tue, 29 Nov 2016 16:20:23 GMT" ], "X-MXL-Hash": [ "583daae02c14b6c6-38001860a1a95d59092eaea2b7ada967ad853dd7", "583daad45c0b76af-065796432e3d317d9802405ae50bf850f720d13f" ], "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>", "Date": "Tue, 29 Nov 2016 16:18:43 +0000", "Message-ID": "<1480436367-20749-12-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>", "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>\n\t<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-AnalysisOut": [ "[v=2.1 cv=UoJlQrEB c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]", "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=wblLTvVIIfb6VRMdX]", "[-UA:9 a=FHsUUGxHFtHFkDp0:21 a=PeIqcLfyJtHa0Dz2:21 a=vIdcND]", "[jzfnfLYjCp:21 a=PA03WX8tBzeizutn5_OT:22]" ], "X-Spam": "[F=0.2000000000; CM=0.500; S=0.200(2015072901)]", "X-MAIL-FROM": "<arybchenko@solarflare.com>", "X-SOURCE-IP": "[12.187.104.26]", "Subject": "[dpdk-dev] [PATCH v2 11/55] net/sfc: import libefx SFN8xxx family\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "SFN8xxx is the second family based on EF10 architecture.\n\nIt has few differences from SFN7xxx adapters family.\n\nEFSYS_OPT_MEDFORD should be enabled to use it.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_impl.h | 6 +-\n drivers/net/sfc/base/efx_check.h | 2 +\n drivers/net/sfc/base/efx_ev.c | 6 +\n drivers/net/sfc/base/efx_filter.c | 6 +\n drivers/net/sfc/base/efx_impl.h | 4 +\n drivers/net/sfc/base/efx_intr.c | 6 +\n drivers/net/sfc/base/efx_mac.c | 7 +\n drivers/net/sfc/base/efx_mcdi.c | 6 +\n drivers/net/sfc/base/efx_nic.c | 54 +++++\n drivers/net/sfc/base/efx_phy.c | 5 +\n drivers/net/sfc/base/efx_rx.c | 6 +\n drivers/net/sfc/base/efx_tx.c | 29 +++\n drivers/net/sfc/base/medford_impl.h | 67 ++++++\n drivers/net/sfc/base/medford_nic.c | 398 ++++++++++++++++++++++++++++++++++++\n 14 files changed, 601 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/sfc/base/medford_impl.h\n create mode 100644 drivers/net/sfc/base/medford_nic.c", "diff": "diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h\nindex b901ccc..697e99b 100644\n--- a/drivers/net/sfc/base/ef10_impl.h\n+++ b/drivers/net/sfc/base/ef10_impl.h\n@@ -35,8 +35,12 @@\n extern \"C\" {\n #endif\n \n-#if EFSYS_OPT_HUNTINGTON\n+#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)\n+#define\tEF10_MAX_PIOBUF_NBUFS\tMAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)\n+#elif EFSYS_OPT_HUNTINGTON\n #define\tEF10_MAX_PIOBUF_NBUFS\tHUNT_PIOBUF_NBUFS\n+#elif EFSYS_OPT_MEDFORD\n+#define\tEF10_MAX_PIOBUF_NBUFS\tMEDFORD_PIOBUF_NBUFS\n #endif\n \n /*\ndiff --git a/drivers/net/sfc/base/efx_check.h b/drivers/net/sfc/base/efx_check.h\nindex 63c809c..ef88645 100644\n--- a/drivers/net/sfc/base/efx_check.h\n+++ b/drivers/net/sfc/base/efx_check.h\n@@ -209,7 +209,9 @@\n \n #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC\n /* Support adapters with missing static config (for factory use only) */\n+# if !EFSYS_OPT_MEDFORD\n # error \"ALLOW_UNCONFIGURED_NIC requires MEDFORD\"\n+# endif\n #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */\n \n #endif /* _SYS_EFX_CHECK_H */\ndiff --git a/drivers/net/sfc/base/efx_ev.c b/drivers/net/sfc/base/efx_ev.c\nindex 65094c1..8cb78be 100644\n--- a/drivers/net/sfc/base/efx_ev.c\n+++ b/drivers/net/sfc/base/efx_ev.c\n@@ -134,6 +134,12 @@ efx_ev_init(\n \t\tbreak;\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\teevop = &__efx_ev_ef10_ops;\n+\t\tbreak;\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(0);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/net/sfc/base/efx_filter.c b/drivers/net/sfc/base/efx_filter.c\nindex 47e2ae4..c878b78 100644\n--- a/drivers/net/sfc/base/efx_filter.c\n+++ b/drivers/net/sfc/base/efx_filter.c\n@@ -165,6 +165,12 @@ efx_filter_init(\n \t\tbreak;\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\tefop = &__efx_filter_ef10_ops;\n+\t\tbreak;\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(0);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h\nindex 10ab36b..97057e4 100644\n--- a/drivers/net/sfc/base/efx_impl.h\n+++ b/drivers/net/sfc/base/efx_impl.h\n@@ -49,6 +49,10 @@\n #include \"hunt_impl.h\"\n #endif\t/* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+#include \"medford_impl.h\"\n+#endif\t/* EFSYS_OPT_MEDFORD */\n+\n #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)\n #include \"ef10_impl.h\"\n #endif\t/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */\ndiff --git a/drivers/net/sfc/base/efx_intr.c b/drivers/net/sfc/base/efx_intr.c\nindex 50cf388..f0422d5 100644\n--- a/drivers/net/sfc/base/efx_intr.c\n+++ b/drivers/net/sfc/base/efx_intr.c\n@@ -150,6 +150,12 @@ efx_intr_init(\n \t\tbreak;\n #endif\t/* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\teiop = &__efx_intr_ef10_ops;\n+\t\tbreak;\n+#endif\t/* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(B_FALSE);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/net/sfc/base/efx_mac.c b/drivers/net/sfc/base/efx_mac.c\nindex 1d50128..c10c79a 100644\n--- a/drivers/net/sfc/base/efx_mac.c\n+++ b/drivers/net/sfc/base/efx_mac.c\n@@ -516,6 +516,13 @@ efx_mac_select(\n \t\tbreak;\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\temop = &__efx_ef10_mac_ops;\n+\t\ttype = EFX_MAC_MEDFORD;\n+\t\tbreak;\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\trc = EINVAL;\n \t\tgoto fail1;\ndiff --git a/drivers/net/sfc/base/efx_mcdi.c b/drivers/net/sfc/base/efx_mcdi.c\nindex 338ff49..8d91812 100644\n--- a/drivers/net/sfc/base/efx_mcdi.c\n+++ b/drivers/net/sfc/base/efx_mcdi.c\n@@ -110,6 +110,12 @@ efx_mcdi_init(\n \t\tbreak;\n #endif\t/* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\temcop = &__efx_mcdi_ef10_ops;\n+\t\tbreak;\n+#endif\t/* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(0);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/net/sfc/base/efx_nic.c b/drivers/net/sfc/base/efx_nic.c\nindex 701c6e3..3ce8514 100644\n--- a/drivers/net/sfc/base/efx_nic.c\n+++ b/drivers/net/sfc/base/efx_nic.c\n@@ -74,6 +74,24 @@ efx_family(\n \t\t\treturn (0);\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\t\tcase EFX_PCI_DEVID_MEDFORD_PF_UNINIT:\n+\t\t\t/*\n+\t\t\t * Hardware default for PF0 of uninitialised Medford.\n+\t\t\t * manftest must be able to cope with this device id.\n+\t\t\t */\n+\t\t\t*efp = EFX_FAMILY_MEDFORD;\n+\t\t\treturn (0);\n+\n+\t\tcase EFX_PCI_DEVID_MEDFORD:\n+\t\t\t*efp = EFX_FAMILY_MEDFORD;\n+\t\t\treturn (0);\n+\n+\t\tcase EFX_PCI_DEVID_MEDFORD_VF:\n+\t\t\t*efp = EFX_FAMILY_MEDFORD;\n+\t\t\treturn (0);\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \t\tcase EFX_PCI_DEVID_FALCON:\t/* Obsolete, not supported */\n \t\tdefault:\n \t\t\tbreak;\n@@ -188,6 +206,22 @@ static const efx_nic_ops_t\t__efx_nic_hunt_ops = {\n \n #endif\t/* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\n+static const efx_nic_ops_t\t__efx_nic_medford_ops = {\n+\tef10_nic_probe,\t\t\t/* eno_probe */\n+\tmedford_board_cfg,\t\t/* eno_board_cfg */\n+\tef10_nic_set_drv_limits,\t/* eno_set_drv_limits */\n+\tef10_nic_reset,\t\t\t/* eno_reset */\n+\tef10_nic_init,\t\t\t/* eno_init */\n+\tef10_nic_get_vi_pool,\t\t/* eno_get_vi_pool */\n+\tef10_nic_get_bar_region,\t/* eno_get_bar_region */\n+\tef10_nic_fini,\t\t\t/* eno_fini */\n+\tef10_nic_unprobe,\t\t/* eno_unprobe */\n+};\n+\n+#endif\t/* EFSYS_OPT_MEDFORD */\n+\n \n \t__checkReturn\tefx_rc_t\n efx_nic_create(\n@@ -246,6 +280,26 @@ efx_nic_create(\n \t\tbreak;\n #endif\t/* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\tenp->en_enop = &__efx_nic_medford_ops;\n+\t\t/*\n+\t\t * FW_ASSISTED_TSO omitted as Medford only supports firmware\n+\t\t * assisted TSO version 2, not the v1 scheme used on Huntington.\n+\t\t */\n+\t\tenp->en_features =\n+\t\t EFX_FEATURE_IPV6 |\n+\t\t EFX_FEATURE_LINK_EVENTS |\n+\t\t EFX_FEATURE_PERIODIC_MAC_STATS |\n+\t\t EFX_FEATURE_MCDI |\n+\t\t EFX_FEATURE_MAC_HEADER_FILTERS |\n+\t\t EFX_FEATURE_MCDI_DMA |\n+\t\t EFX_FEATURE_PIO_BUFFERS |\n+\t\t EFX_FEATURE_FW_ASSISTED_TSO_V2 |\n+\t\t EFX_FEATURE_PACKED_STREAM;\n+\t\tbreak;\n+#endif\t/* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\trc = ENOTSUP;\n \t\tgoto fail2;\ndiff --git a/drivers/net/sfc/base/efx_phy.c b/drivers/net/sfc/base/efx_phy.c\nindex b663cf8..e7e915e 100644\n--- a/drivers/net/sfc/base/efx_phy.c\n+++ b/drivers/net/sfc/base/efx_phy.c\n@@ -78,6 +78,11 @@ efx_phy_probe(\n \t\tepop = &__efx_phy_ef10_ops;\n \t\tbreak;\n #endif\t/* EFSYS_OPT_HUNTINGTON */\n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\tepop = &__efx_phy_ef10_ops;\n+\t\tbreak;\n+#endif\t/* EFSYS_OPT_MEDFORD */\n \tdefault:\n \t\trc = ENOTSUP;\n \t\tgoto fail1;\ndiff --git a/drivers/net/sfc/base/efx_rx.c b/drivers/net/sfc/base/efx_rx.c\nindex 8ca5731..2899a0f 100644\n--- a/drivers/net/sfc/base/efx_rx.c\n+++ b/drivers/net/sfc/base/efx_rx.c\n@@ -152,6 +152,12 @@ efx_rx_init(\n \t\tbreak;\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\terxop = &__efx_rx_ef10_ops;\n+\t\tbreak;\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(0);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/net/sfc/base/efx_tx.c b/drivers/net/sfc/base/efx_tx.c\nindex ed66695..16834af 100644\n--- a/drivers/net/sfc/base/efx_tx.c\n+++ b/drivers/net/sfc/base/efx_tx.c\n@@ -152,6 +152,29 @@ static const efx_tx_ops_t\t__efx_tx_hunt_ops = {\n };\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+static const efx_tx_ops_t\t__efx_tx_medford_ops = {\n+\tef10_tx_init,\t\t\t\t/* etxo_init */\n+\tef10_tx_fini,\t\t\t\t/* etxo_fini */\n+\tef10_tx_qcreate,\t\t\t/* etxo_qcreate */\n+\tef10_tx_qdestroy,\t\t\t/* etxo_qdestroy */\n+\tef10_tx_qpost,\t\t\t\t/* etxo_qpost */\n+\tef10_tx_qpush,\t\t\t\t/* etxo_qpush */\n+\tef10_tx_qpace,\t\t\t\t/* etxo_qpace */\n+\tef10_tx_qflush,\t\t\t\t/* etxo_qflush */\n+\tef10_tx_qenable,\t\t\t/* etxo_qenable */\n+\tef10_tx_qpio_enable,\t\t\t/* etxo_qpio_enable */\n+\tef10_tx_qpio_disable,\t\t\t/* etxo_qpio_disable */\n+\tef10_tx_qpio_write,\t\t\t/* etxo_qpio_write */\n+\tef10_tx_qpio_post,\t\t\t/* etxo_qpio_post */\n+\tef10_tx_qdesc_post,\t\t\t/* etxo_qdesc_post */\n+\tef10_tx_qdesc_dma_create,\t\t/* etxo_qdesc_dma_create */\n+\tNULL,\t\t\t\t\t/* etxo_qdesc_tso_create */\n+\tef10_tx_qdesc_tso2_create,\t\t/* etxo_qdesc_tso2_create */\n+\tef10_tx_qdesc_vlantci_create,\t\t/* etxo_qdesc_vlantci_create */\n+};\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \t__checkReturn\tefx_rc_t\n efx_tx_init(\n \t__in\t\tefx_nic_t *enp)\n@@ -185,6 +208,12 @@ efx_tx_init(\n \t\tbreak;\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n+#if EFSYS_OPT_MEDFORD\n+\tcase EFX_FAMILY_MEDFORD:\n+\t\tetxop = &__efx_tx_medford_ops;\n+\t\tbreak;\n+#endif /* EFSYS_OPT_MEDFORD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(0);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/net/sfc/base/medford_impl.h b/drivers/net/sfc/base/medford_impl.h\nnew file mode 100644\nindex 0000000..de2f5cf\n--- /dev/null\n+++ b/drivers/net/sfc/base/medford_impl.h\n@@ -0,0 +1,67 @@\n+/*\n+ * Copyright (c) 2015-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef\t_SYS_MEDFORD_IMPL_H\n+#define\t_SYS_MEDFORD_IMPL_H\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+/* Alignment requirement for value written to RX WPTR:\n+ * the WPTR must be aligned to an 8 descriptor boundary\n+ *\n+ * FIXME: Is this the same on Medford as Huntington?\n+ */\n+#define\tMEDFORD_RX_WPTR_ALIGN\t8\n+\n+\n+\n+#ifndef\tER_EZ_TX_PIOBUF_SIZE\n+#define\tER_EZ_TX_PIOBUF_SIZE\t4096\n+#endif\n+\n+\n+#define\tMEDFORD_PIOBUF_NBUFS\t(16)\n+#define\tMEDFORD_PIOBUF_SIZE\t(ER_EZ_TX_PIOBUF_SIZE)\n+\n+#define\tMEDFORD_MIN_PIO_ALLOC_SIZE\t(MEDFORD_PIOBUF_SIZE / 32)\n+\n+\n+extern\t__checkReturn\tefx_rc_t\n+medford_board_cfg(\n+\t__in\t\tefx_nic_t *enp);\n+\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif\t/* _SYS_MEDFORD_IMPL_H */\ndiff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c\nnew file mode 100644\nindex 0000000..6ad68c6\n--- /dev/null\n+++ b/drivers/net/sfc/base/medford_nic.c\n@@ -0,0 +1,398 @@\n+/*\n+ * Copyright (c) 2015-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\n+#if EFSYS_OPT_MEDFORD\n+\n+static\t__checkReturn\tefx_rc_t\n+efx_mcdi_get_rxdp_config(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *end_paddingp)\n+{\n+\tefx_mcdi_req_t req;\n+\tuint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,\n+\t\t\t MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];\n+\tuint32_t end_padding;\n+\tefx_rc_t rc;\n+\n+\tmemset(payload, 0, sizeof (payload));\n+\treq.emr_cmd = MC_CMD_GET_RXDP_CONFIG;\n+\treq.emr_in_buf = payload;\n+\treq.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;\n+\treq.emr_out_buf = payload;\n+\treq.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;\n+\n+\tefx_mcdi_execute(enp, &req);\n+\tif (req.emr_rc != 0) {\n+\t\trc = req.emr_rc;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,\n+\t\t\t\t GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {\n+\t\t/* RX DMA end padding is disabled */\n+\t\tend_padding = 0;\n+\t} else {\n+\t\tswitch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,\n+\t\t\t\t\t GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {\n+\t\tcase MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:\n+\t\t\tend_padding = 64;\n+\t\t\tbreak;\n+\t\tcase MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:\n+\t\t\tend_padding = 128;\n+\t\t\tbreak;\n+\t\tcase MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:\n+\t\t\tend_padding = 256;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trc = ENOTSUP;\n+\t\t\tgoto fail2;\n+\t\t}\n+\t}\n+\n+\t*end_paddingp = end_padding;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+static\t__checkReturn\tefx_rc_t\n+medford_nic_get_required_pcie_bandwidth(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *bandwidth_mbpsp)\n+{\n+\tuint32_t port_modes;\n+\tuint32_t current_mode;\n+\tuint32_t bandwidth;\n+\tefx_rc_t rc;\n+\n+\tif ((rc = efx_mcdi_get_port_modes(enp, &port_modes,\n+\t\t\t\t ¤t_mode)) != 0) {\n+\t\t/* No port mode info available. */\n+\t\tbandwidth = 0;\n+\t\tgoto out;\n+\t}\n+\n+\tif ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,\n+\t\t\t\t\t\t &bandwidth)) != 0)\n+\t\tgoto fail1;\n+\n+out:\n+\t*bandwidth_mbpsp = bandwidth;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+medford_board_cfg(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tuint8_t mac_addr[6] = { 0 };\n+\tuint32_t board_type = 0;\n+\tef10_link_state_t els;\n+\tefx_port_t *epp = &(enp->en_port);\n+\tuint32_t port;\n+\tuint32_t pf;\n+\tuint32_t vf;\n+\tuint32_t mask;\n+\tuint32_t sysclk, dpcpu_clk;\n+\tuint32_t base, nvec;\n+\tuint32_t end_padding;\n+\tuint32_t bandwidth;\n+\tefx_rc_t rc;\n+\n+\t/*\n+\t * FIXME: Likely to be incomplete and incorrect.\n+\t * Parts of this should be shared with Huntington.\n+\t */\n+\n+\tif ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)\n+\t\tgoto fail1;\n+\n+\t/*\n+\t * NOTE: The MCDI protocol numbers ports from zero.\n+\t * The common code MCDI interface numbers ports from one.\n+\t */\n+\temip->emi_port = port + 1;\n+\n+\tif ((rc = ef10_external_port_mapping(enp, port,\n+\t\t &encp->enc_external_port)) != 0)\n+\t\tgoto fail2;\n+\n+\t/*\n+\t * Get PCIe function number from firmware (used for\n+\t * per-function privilege and dynamic config info).\n+\t * - PCIe PF: pf = PF number, vf = 0xffff.\n+\t * - PCIe VF: pf = parent PF, vf = VF number.\n+\t */\n+\tif ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)\n+\t\tgoto fail3;\n+\n+\tencp->enc_pf = pf;\n+\tencp->enc_vf = vf;\n+\n+\t/* MAC address for this function */\n+\tif (EFX_PCI_FUNCTION_IS_PF(encp)) {\n+\t\trc = efx_mcdi_get_mac_address_pf(enp, mac_addr);\n+#if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC\n+\t\t/* Disable static config checking for Medford NICs, ONLY\n+\t\t * for manufacturing test and setup at the factory, to\n+\t\t * allow the static config to be installed.\n+\t\t */\n+#else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */\n+\t\tif ((rc == 0) && (mac_addr[0] & 0x02)) {\n+\t\t\t/*\n+\t\t\t * If the static config does not include a global MAC\n+\t\t\t * address pool then the board may return a locally\n+\t\t\t * administered MAC address (this should only happen on\n+\t\t\t * incorrectly programmed boards).\n+\t\t\t */\n+\t\t\trc = EINVAL;\n+\t\t}\n+#endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */\n+\t} else {\n+\t\trc = efx_mcdi_get_mac_address_vf(enp, mac_addr);\n+\t}\n+\tif (rc != 0)\n+\t\tgoto fail4;\n+\n+\tEFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);\n+\n+\t/* Board configuration */\n+\trc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);\n+\tif (rc != 0) {\n+\t\t/* Unprivileged functions may not be able to read board cfg */\n+\t\tif (rc == EACCES)\n+\t\t\tboard_type = 0;\n+\t\telse\n+\t\t\tgoto fail5;\n+\t}\n+\n+\tencp->enc_board_type = board_type;\n+\tencp->enc_clk_mult = 1; /* not used for Medford */\n+\n+\t/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */\n+\tif ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)\n+\t\tgoto fail6;\n+\n+\t/* Obtain the default PHY advertised capabilities */\n+\tif ((rc = ef10_phy_get_link(enp, &els)) != 0)\n+\t\tgoto fail7;\n+\tepp->ep_default_adv_cap_mask = els.els_adv_cap_mask;\n+\tepp->ep_adv_cap_mask = els.els_adv_cap_mask;\n+\n+\t/*\n+\t * Enable firmware workarounds for hardware errata.\n+\t * Expected responses are:\n+\t * - 0 (zero):\n+\t *\tSuccess: workaround enabled or disabled as requested.\n+\t * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):\n+\t *\tFirmware does not support the MC_CMD_WORKAROUND request.\n+\t *\t(assume that the workaround is not supported).\n+\t * - MC_CMD_ERR_ENOENT (reported as ENOENT):\n+\t *\tFirmware does not support the requested workaround.\n+\t * - MC_CMD_ERR_EPERM (reported as EACCES):\n+\t *\tUnprivileged function cannot enable/disable workarounds.\n+\t *\n+\t * See efx_mcdi_request_errcode() for MCDI error translations.\n+\t */\n+\n+\n+\tif (EFX_PCI_FUNCTION_IS_VF(encp)) {\n+\t\t/*\n+\t\t * Interrupt testing does not work for VFs. See bug50084.\n+\t\t * FIXME: Does this still apply to Medford?\n+\t\t */\n+\t\tencp->enc_bug41750_workaround = B_TRUE;\n+\t}\n+\n+\t/* Chained multicast is always enabled on Medford */\n+\tencp->enc_bug26807_workaround = B_TRUE;\n+\n+\t/*\n+\t * If the bug61265 workaround is enabled, then interrupt holdoff timers\n+\t * cannot be controlled by timer table writes, so MCDI must be used\n+\t * (timer table writes can still be used for wakeup timers).\n+\t */\n+\trc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,\n+\t NULL);\n+\tif ((rc == 0) || (rc == EACCES))\n+\t\tencp->enc_bug61265_workaround = B_TRUE;\n+\telse if ((rc == ENOTSUP) || (rc == ENOENT))\n+\t\tencp->enc_bug61265_workaround = B_FALSE;\n+\telse\n+\t\tgoto fail8;\n+\n+\t/* Get clock frequencies (in MHz). */\n+\tif ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)\n+\t\tgoto fail9;\n+\n+\t/*\n+\t * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for\n+\t * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.\n+\t */\n+\tencp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */\n+\tencp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<\n+\t\t FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;\n+\n+\t/* Check capabilities of running datapath firmware */\n+\tif ((rc = ef10_get_datapath_caps(enp)) != 0)\n+\t\tgoto fail10;\n+\n+\t/* Alignment for receive packet DMA buffers */\n+\tencp->enc_rx_buf_align_start = 1;\n+\n+\t/* Get the RX DMA end padding alignment configuration */\n+\tif ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {\n+\t\tif (rc != EACCES)\n+\t\t\tgoto fail11;\n+\n+\t\t/* Assume largest tail padding size supported by hardware */\n+\t\tend_padding = 256;\n+\t}\n+\tencp->enc_rx_buf_align_end = end_padding;\n+\n+\t/* Alignment for WPTR updates */\n+\tencp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;\n+\n+\t/*\n+\t * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use\n+\t * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available\n+\t * resources (allocated to this PCIe function), which is zero until\n+\t * after we have allocated VIs.\n+\t */\n+\tencp->enc_evq_limit = 1024;\n+\tencp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;\n+\tencp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;\n+\n+\t/*\n+\t * The maximum supported transmit queue size is 2048. TXQs with 4096\n+\t * descriptors are not supported as the top bit is used for vfifo\n+\t * stuffing.\n+\t */\n+\tencp->enc_txq_max_ndescs = 2048;\n+\n+\tencp->enc_buftbl_limit = 0xFFFFFFFF;\n+\n+\tencp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;\n+\tencp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;\n+\tencp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;\n+\n+\t/*\n+\t * Get the current privilege mask. Note that this may be modified\n+\t * dynamically, so this value is informational only. DO NOT use\n+\t * the privilege mask to check for sufficient privileges, as that\n+\t * can result in time-of-check/time-of-use bugs.\n+\t */\n+\tif ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)\n+\t\tgoto fail12;\n+\tencp->enc_privilege_mask = mask;\n+\n+\t/* Get interrupt vector limits */\n+\tif ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {\n+\t\tif (EFX_PCI_FUNCTION_IS_PF(encp))\n+\t\t\tgoto fail13;\n+\n+\t\t/* Ignore error (cannot query vector limits from a VF). */\n+\t\tbase = 0;\n+\t\tnvec = 1024;\n+\t}\n+\tencp->enc_intr_vec_base = base;\n+\tencp->enc_intr_limit = nvec;\n+\n+\t/*\n+\t * Maximum number of bytes into the frame the TCP header can start for\n+\t * firmware assisted TSO to work.\n+\t */\n+\tencp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;\n+\n+\t/*\n+\t * Medford stores a single global copy of VPD, not per-PF as on\n+\t * Huntington.\n+\t */\n+\tencp->enc_vpd_is_global = B_TRUE;\n+\n+\trc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);\n+\tif (rc != 0)\n+\t\tgoto fail14;\n+\tencp->enc_required_pcie_bandwidth_mbps = bandwidth;\n+\tencp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;\n+\n+\treturn (0);\n+\n+fail14:\n+\tEFSYS_PROBE(fail14);\n+fail13:\n+\tEFSYS_PROBE(fail13);\n+fail12:\n+\tEFSYS_PROBE(fail12);\n+fail11:\n+\tEFSYS_PROBE(fail11);\n+fail10:\n+\tEFSYS_PROBE(fail10);\n+fail9:\n+\tEFSYS_PROBE(fail9);\n+fail8:\n+\tEFSYS_PROBE(fail8);\n+fail7:\n+\tEFSYS_PROBE(fail7);\n+fail6:\n+\tEFSYS_PROBE(fail6);\n+fail5:\n+\tEFSYS_PROBE(fail5);\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_MEDFORD */\n", "prefixes": [ "dpdk-dev", "v2", "11/55" ] }