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GET /api/patches/17285/?format=api
{ "id": 17285, "url": "https://patches.dpdk.org/api/patches/17285/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-18-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1480436367-20749-18-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1480436367-20749-18-git-send-email-arybchenko@solarflare.com", "date": "2016-11-29T16:18:49", "name": "[dpdk-dev,v2,17/55] net/sfc: import libefx PHY LEDs control support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8c9fea1a06c0360487e3b048b3659f559720af3b", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1480436367-20749-18-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/17285/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/17285/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 327155597;\n\tTue, 29 Nov 2016 17:21:32 +0100 (CET)", "from nbfkord-smmo01.seg.att.com (nbfkord-smmo01.seg.att.com\n\t[209.65.160.76]) by dpdk.org (Postfix) with ESMTP id 0BC97374C\n\tfor <dev@dpdk.org>; Tue, 29 Nov 2016 17:20:46 +0100 (CET)", "from unknown [12.187.104.26] (EHLO nbfkord-smmo01.seg.att.com)\n\tby nbfkord-smmo01.seg.att.com(mxl_mta-7.2.4-7) with ESMTP id\n\tfdaad385.2b3e8964e940.83537.00-2491.173770.nbfkord-smmo01.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tTue, 29 Nov 2016 16:20:47 +0000 (UTC)", "from unknown [12.187.104.26]\n\tby nbfkord-smmo01.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\t2daad385.0.83400.00-2391.173523.nbfkord-smmo01.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tTue, 29 Nov 2016 16:20:35 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Tue, 29 Nov 2016 08:20:25 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Tue, 29 Nov 2016 08:20:25 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuATGKNCj029944; Tue, 29 Nov 2016 16:20:23 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuATGKM1P021233; Tue, 29 Nov 2016 16:20:23 GMT" ], "X-MXL-Hash": [ "583daadf6fb35b50-788b8f33091b853e866d9a40da30977ea0b7f6b3", "583daad3415926db-d51cb050d810073ff806621a9d0b818f3d769436" ], "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>", "Date": "Tue, 29 Nov 2016 16:18:49 +0000", "Message-ID": "<1480436367-20749-18-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>", "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>\n\t<1480436367-20749-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-AnalysisOut": [ "[v=2.1 cv=UoJlQrEB c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]", "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=h-oMn7fAq0X2csz2K]", "[yUA:9 a=NKL-hYtPDVaMleMY:21 a=hRfpdNTMX39VvMfy:21 a=8DUjIp]", "[f0rZZqWCZ8:21 a=PA03WX8tBzeizutn5_OT:22]" ], "X-Spam": "[F=0.5016706479; CM=0.500; S=0.501(2015072901)]", "X-MAIL-FROM": "<arybchenko@solarflare.com>", "X-SOURCE-IP": "[12.187.104.26]", "Subject": "[dpdk-dev] [PATCH v2 17/55] net/sfc: import libefx PHY LEDs control\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "EFSYS_OPT_PHY_LED_CONTROL should be enabled to use it.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_phy.c | 19 +++++++++++++++++\n drivers/net/sfc/base/efx.h | 20 ++++++++++++++++++\n drivers/net/sfc/base/efx_check.h | 7 +++++++\n drivers/net/sfc/base/efx_impl.h | 3 +++\n drivers/net/sfc/base/efx_mcdi.c | 5 +++++\n drivers/net/sfc/base/efx_phy.c | 45 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/sfc/base/siena_phy.c | 19 +++++++++++++++++\n 7 files changed, 118 insertions(+)", "diff": "diff --git a/drivers/net/sfc/base/ef10_phy.c b/drivers/net/sfc/base/ef10_phy.c\nindex b15b693..cc00250 100644\n--- a/drivers/net/sfc/base/ef10_phy.c\n+++ b/drivers/net/sfc/base/ef10_phy.c\n@@ -314,7 +314,26 @@ ef10_phy_reconfigure(\n \treq.emr_out_buf = payload;\n \treq.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;\n \n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\tswitch (epp->ep_phy_led_mode) {\n+\tcase EFX_PHY_LED_DEFAULT:\n+\t\tled_mode = MC_CMD_LED_DEFAULT;\n+\t\tbreak;\n+\tcase EFX_PHY_LED_OFF:\n+\t\tled_mode = MC_CMD_LED_OFF;\n+\t\tbreak;\n+\tcase EFX_PHY_LED_ON:\n+\t\tled_mode = MC_CMD_LED_ON;\n+\t\tbreak;\n+\tdefault:\n+\t\tEFSYS_ASSERT(0);\n+\t\tled_mode = MC_CMD_LED_DEFAULT;\n+\t}\n+\n+\tMCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);\n+#else\n \tMCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n \n \tefx_mcdi_execute(enp, &req);\n \ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex d2fe43e..794ba4b 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -463,6 +463,23 @@ extern\t__checkReturn\tefx_rc_t\n efx_phy_verify(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\n+typedef enum efx_phy_led_mode_e {\n+\tEFX_PHY_LED_DEFAULT = 0,\n+\tEFX_PHY_LED_OFF,\n+\tEFX_PHY_LED_ON,\n+\tEFX_PHY_LED_FLASH,\n+\tEFX_PHY_LED_NMODES\n+} efx_phy_led_mode_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_phy_led_set(\n+\t__in\tefx_nic_t *enp,\n+\t__in\tefx_phy_led_mode_t mode);\n+\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n+\n extern\t__checkReturn\tefx_rc_t\n efx_port_init(\n \t__in\t\tefx_nic_t *enp);\n@@ -745,6 +762,9 @@ typedef struct efx_nic_cfg_s {\n #if EFSYS_OPT_PHY_FLAGS\n \tuint32_t\t\tenc_phy_flags_mask;\n #endif\t/* EFSYS_OPT_PHY_FLAGS */\n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\tuint32_t\t\tenc_led_mask;\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n #if EFSYS_OPT_PHY_STATS\n \tuint64_t\t\tenc_phy_stat_mask;\n #endif\t/* EFSYS_OPT_PHY_STATS */\ndiff --git a/drivers/net/sfc/base/efx_check.h b/drivers/net/sfc/base/efx_check.h\nindex adda531..4e76dc1 100644\n--- a/drivers/net/sfc/base/efx_check.h\n+++ b/drivers/net/sfc/base/efx_check.h\n@@ -173,6 +173,13 @@\n # endif\n #endif /* EFSYS_OPT_PHY_FLAGS */\n \n+#if EFSYS_OPT_PHY_LED_CONTROL\n+/* Support for PHY LED control */\n+# if !EFSYS_OPT_SIENA\n+# error \"PHY_LED_CONTROL requires SIENA\"\n+# endif\n+#endif /* EFSYS_OPT_PHY_LED_CONTROL */\n+\n #ifdef EFSYS_OPT_PHY_NULL\n # error \"PHY_NULL is obsolete and is not supported.\"\n #endif\ndiff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h\nindex 2b81768..6077114 100644\n--- a/drivers/net/sfc/base/efx_impl.h\n+++ b/drivers/net/sfc/base/efx_impl.h\n@@ -244,6 +244,9 @@ typedef struct efx_port_s {\n #if EFSYS_OPT_PHY_FLAGS\n \tuint32_t\t\tep_phy_flags;\n #endif\t/* EFSYS_OPT_PHY_FLAGS */\n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\tefx_phy_led_mode_t\tep_phy_led_mode;\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n \tefx_phy_media_type_t\tep_fixed_port_type;\n \tefx_phy_media_type_t\tep_module_type;\n \tuint32_t\t\tep_adv_cap_mask;\ndiff --git a/drivers/net/sfc/base/efx_mcdi.c b/drivers/net/sfc/base/efx_mcdi.c\nindex c5422da..34ba960 100644\n--- a/drivers/net/sfc/base/efx_mcdi.c\n+++ b/drivers/net/sfc/base/efx_mcdi.c\n@@ -1409,6 +1409,11 @@ efx_mcdi_get_phy_cfg(\n \t\tMCDI_OUT2(req, char, GET_PHY_CFG_OUT_REVISION),\n \t\tMIN(sizeof (encp->enc_phy_revision) - 1,\n \t\t MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN));\n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\tencp->enc_led_mask = ((1 << EFX_PHY_LED_DEFAULT) |\n+\t\t\t (1 << EFX_PHY_LED_OFF) |\n+\t\t\t (1 << EFX_PHY_LED_ON));\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n \n \t/* Get the media type of the fixed port, if recognised. */\n \tEFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI);\ndiff --git a/drivers/net/sfc/base/efx_phy.c b/drivers/net/sfc/base/efx_phy.c\nindex 20debd3..752cd52 100644\n--- a/drivers/net/sfc/base/efx_phy.c\n+++ b/drivers/net/sfc/base/efx_phy.c\n@@ -132,6 +132,51 @@ efx_phy_verify(\n \treturn (epop->epo_verify(enp));\n }\n \n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\n+\t__checkReturn\tefx_rc_t\n+efx_phy_led_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_phy_led_mode_t mode)\n+{\n+\tefx_nic_cfg_t *encp = (&enp->en_nic_cfg);\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\tuint32_t mask;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif (epp->ep_phy_led_mode == mode)\n+\t\tgoto done;\n+\n+\tmask = (1 << EFX_PHY_LED_DEFAULT);\n+\tmask |= encp->enc_led_mask;\n+\n+\tif (!((1 << mode) & mask)) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\tEFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);\n+\tepp->ep_phy_led_mode = mode;\n+\n+\tif ((rc = epop->epo_reconfigure(enp)) != 0)\n+\t\tgoto fail2;\n+\n+done:\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n+\n \t\t\tvoid\n efx_phy_adv_cap_get(\n \t__in\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/base/siena_phy.c b/drivers/net/sfc/base/siena_phy.c\nindex 73690f1..9aeef23 100644\n--- a/drivers/net/sfc/base/siena_phy.c\n+++ b/drivers/net/sfc/base/siena_phy.c\n@@ -298,7 +298,26 @@ siena_phy_reconfigure(\n \treq.emr_out_buf = payload;\n \treq.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;\n \n+#if EFSYS_OPT_PHY_LED_CONTROL\n+\tswitch (epp->ep_phy_led_mode) {\n+\tcase EFX_PHY_LED_DEFAULT:\n+\t\tled_mode = MC_CMD_LED_DEFAULT;\n+\t\tbreak;\n+\tcase EFX_PHY_LED_OFF:\n+\t\tled_mode = MC_CMD_LED_OFF;\n+\t\tbreak;\n+\tcase EFX_PHY_LED_ON:\n+\t\tled_mode = MC_CMD_LED_ON;\n+\t\tbreak;\n+\tdefault:\n+\t\tEFSYS_ASSERT(0);\n+\t\tled_mode = MC_CMD_LED_DEFAULT;\n+\t}\n+\n+\tMCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);\n+#else\n \tMCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);\n+#endif\t/* EFSYS_OPT_PHY_LED_CONTROL */\n \n \tefx_mcdi_execute(enp, &req);\n \n", "prefixes": [ "dpdk-dev", "v2", "17/55" ] }