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GET /api/patches/17115/?format=api
{ "id": 17115, "url": "https://patches.dpdk.org/api/patches/17115/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-13-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1479740470-6723-13-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1479740470-6723-13-git-send-email-arybchenko@solarflare.com", "date": "2016-11-21T15:00:26", "name": "[dpdk-dev,12/56] net/sfc: import libefx diagnostics support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "1581b6b2ee7eb43c01500e91e218473ee32b58d4", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-13-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/17115/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/17115/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1E2F9D494;\n\tMon, 21 Nov 2016 16:02:46 +0100 (CET)", "from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com\n\t[209.65.160.78]) by dpdk.org (Postfix) with ESMTP id 812EC532C\n\tfor <dev@dpdk.org>; Mon, 21 Nov 2016 16:01:30 +0100 (CET)", "from unknown [12.187.104.26]\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\ta4c03385.0.1541296.00-2307.3424191.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:30 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 21 Nov 2016 07:01:21 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 21 Nov 2016 07:01:21 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1JlH007130 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:19 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1J33006765 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:19 GMT" ], "X-MXL-Hash": "58330c4a3392db8a-030a90ad0cfd1a6bd348ccea2c81ef2e4e155b21", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Mon, 21 Nov 2016 15:00:26 +0000", "Message-ID": "<1479740470-6723-13-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>", "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-AnalysisOut": [ "[v=2.1 cv=UI/baXry c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]", "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=9L2yPZHjBX76XaYyZ]", "[rgA:9 a=8WFdC95M9lDdCqiA:21 a=FgtK5FAYxCvVRxI6:21 a=4M_vrc]", "[Hv_aKuSUA4:21 a=PA03WX8tBzeizutn5_OT:22]" ], "X-Spam": "[F=0.5000550566; CM=0.500; S=0.500(2015072901)]", "X-MAIL-FROM": "<arybchenko@solarflare.com>", "X-SOURCE-IP": "[12.187.104.26]", "Subject": "[dpdk-dev] [PATCH 12/56] net/sfc: import libefx diagnostics support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "EFSYS_OPT_DIAG should be enabled to use it.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/efx/base/ef10_impl.h | 8 ++\n drivers/net/sfc/efx/base/ef10_nic.c | 27 ++++++\n drivers/net/sfc/efx/base/efx.h | 33 +++++++\n drivers/net/sfc/efx/base/efx_check.h | 7 ++\n drivers/net/sfc/efx/base/efx_impl.h | 29 ++++++\n drivers/net/sfc/efx/base/efx_nic.c | 168 ++++++++++++++++++++++++++++++++++\n drivers/net/sfc/efx/base/efx_sram.c | 131 ++++++++++++++++++++++++++\n drivers/net/sfc/efx/base/siena_impl.h | 17 ++++\n drivers/net/sfc/efx/base/siena_nic.c | 132 ++++++++++++++++++++++++++\n drivers/net/sfc/efx/base/siena_sram.c | 104 +++++++++++++++++++++\n 10 files changed, 656 insertions(+)", "diff": "diff --git a/drivers/net/sfc/efx/base/ef10_impl.h b/drivers/net/sfc/efx/base/ef10_impl.h\nindex 15d12d2..5bebbe9 100644\n--- a/drivers/net/sfc/efx/base/ef10_impl.h\n+++ b/drivers/net/sfc/efx/base/ef10_impl.h\n@@ -192,6 +192,14 @@ extern\t__checkReturn\tefx_rc_t\n ef10_nic_init(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_DIAG\n+\n+extern\t__checkReturn\tefx_rc_t\n+ef10_nic_register_test(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n extern\t\t\tvoid\n ef10_nic_fini(\n \t__in\t\tefx_nic_t *enp);\ndiff --git a/drivers/net/sfc/efx/base/ef10_nic.c b/drivers/net/sfc/efx/base/ef10_nic.c\nindex 538e18c..0eb72a7 100644\n--- a/drivers/net/sfc/efx/base/ef10_nic.c\n+++ b/drivers/net/sfc/efx/base/ef10_nic.c\n@@ -1765,5 +1765,32 @@ ef10_nic_unprobe(\n \t(void) efx_mcdi_drv_attach(enp, B_FALSE);\n }\n \n+#if EFSYS_OPT_DIAG\n+\n+\t__checkReturn\tefx_rc_t\n+ef10_nic_register_test(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_rc_t rc;\n+\n+\t/* FIXME */\n+\t_NOTE(ARGUNUSED(enp))\n+\t_NOTE(CONSTANTCONDITION)\n+\tif (B_FALSE) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\t/* FIXME */\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n \n #endif\t/* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */\ndiff --git a/drivers/net/sfc/efx/base/efx.h b/drivers/net/sfc/efx/base/efx.h\nindex e61c865..4cabc79 100644\n--- a/drivers/net/sfc/efx/base/efx.h\n+++ b/drivers/net/sfc/efx/base/efx.h\n@@ -146,6 +146,14 @@ extern\t__checkReturn\tefx_rc_t\n efx_nic_reset(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_DIAG\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_register_test(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n extern\t\tvoid\n efx_nic_fini(\n \t__in\t\tefx_nic_t *enp);\n@@ -689,6 +697,31 @@ efx_nic_get_vi_pool(\n \n /* NVRAM */\n \n+#if EFSYS_OPT_DIAG\n+\n+typedef enum efx_pattern_type_t {\n+\tEFX_PATTERN_BYTE_INCREMENT = 0,\n+\tEFX_PATTERN_ALL_THE_SAME,\n+\tEFX_PATTERN_BIT_ALTERNATE,\n+\tEFX_PATTERN_BYTE_ALTERNATE,\n+\tEFX_PATTERN_BYTE_CHANGING,\n+\tEFX_PATTERN_BIT_SWEEP,\n+\tEFX_PATTERN_NTYPES\n+} efx_pattern_type_t;\n+\n+typedef\t\t\tvoid\n+(*efx_sram_pattern_fn_t)(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_sram_test(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_pattern_type_t type);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n extern\t__checkReturn\tefx_rc_t\n efx_sram_buf_tbl_set(\n \t__in\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/efx/base/efx_check.h b/drivers/net/sfc/efx/base/efx_check.h\nindex ef88645..feaccd0 100644\n--- a/drivers/net/sfc/efx/base/efx_check.h\n+++ b/drivers/net/sfc/efx/base/efx_check.h\n@@ -59,6 +59,13 @@\n # endif\n #endif /* EFSYS_OPT_DECODE_INTR_FATAL */\n \n+#if EFSYS_OPT_DIAG\n+/* Support diagnostic hardware tests */\n+# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)\n+# error \"DIAG requires SIENA or HUNTINGTON or MEDFORD\"\n+# endif\n+#endif /* EFSYS_OPT_DIAG */\n+\n #ifdef EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE\n # error \"FALCON_NIC_CFG_OVERRIDE is obsolete and is not supported.\"\n #endif\ndiff --git a/drivers/net/sfc/efx/base/efx_impl.h b/drivers/net/sfc/efx/base/efx_impl.h\nindex 97057e4..a7c6b29 100644\n--- a/drivers/net/sfc/efx/base/efx_impl.h\n+++ b/drivers/net/sfc/efx/base/efx_impl.h\n@@ -271,6 +271,9 @@ typedef struct efx_nic_ops_s {\n \tefx_rc_t\t(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);\n \tefx_rc_t\t(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,\n \t\t\t\t\tuint32_t *, size_t *);\n+#if EFSYS_OPT_DIAG\n+\tefx_rc_t\t(*eno_register_test)(efx_nic_t *);\n+#endif\t/* EFSYS_OPT_DIAG */\n \tvoid\t\t(*eno_fini)(efx_nic_t *);\n \tvoid\t\t(*eno_unprobe)(efx_nic_t *);\n } efx_nic_ops_t;\n@@ -829,6 +832,32 @@ extern\t\t\tvoid\n efx_phy_unprobe(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_DIAG\n+\n+extern\tefx_sram_pattern_fn_t\t__efx_sram_pattern_fns[];\n+\n+typedef struct efx_register_set_s {\n+\tunsigned int\t\taddress;\n+\tunsigned int\t\tstep;\n+\tunsigned int\t\trows;\n+\tefx_oword_t\t\tmask;\n+} efx_register_set_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_test_registers(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_register_set_t *rsp,\n+\t__in\t\tsize_t count);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_test_tables(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_register_set_t *rsp,\n+\t__in\t\tefx_pattern_type_t pattern,\n+\t__in\t\tsize_t count);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n #if EFSYS_OPT_MCDI\n \n extern\t__checkReturn\t\tefx_rc_t\ndiff --git a/drivers/net/sfc/efx/base/efx_nic.c b/drivers/net/sfc/efx/base/efx_nic.c\nindex 5cc2910..95ae8c6 100644\n--- a/drivers/net/sfc/efx/base/efx_nic.c\n+++ b/drivers/net/sfc/efx/base/efx_nic.c\n@@ -184,6 +184,9 @@ static const efx_nic_ops_t\t__efx_nic_siena_ops = {\n \tsiena_nic_init,\t\t\t/* eno_init */\n \tNULL,\t\t\t\t/* eno_get_vi_pool */\n \tNULL,\t\t\t\t/* eno_get_bar_region */\n+#if EFSYS_OPT_DIAG\n+\tsiena_nic_register_test,\t/* eno_register_test */\n+#endif\t/* EFSYS_OPT_DIAG */\n \tsiena_nic_fini,\t\t\t/* eno_fini */\n \tsiena_nic_unprobe,\t\t/* eno_unprobe */\n };\n@@ -200,6 +203,9 @@ static const efx_nic_ops_t\t__efx_nic_hunt_ops = {\n \tef10_nic_init,\t\t\t/* eno_init */\n \tef10_nic_get_vi_pool,\t\t/* eno_get_vi_pool */\n \tef10_nic_get_bar_region,\t/* eno_get_bar_region */\n+#if EFSYS_OPT_DIAG\n+\tef10_nic_register_test,\t\t/* eno_register_test */\n+#endif\t/* EFSYS_OPT_DIAG */\n \tef10_nic_fini,\t\t\t/* eno_fini */\n \tef10_nic_unprobe,\t\t/* eno_unprobe */\n };\n@@ -216,6 +222,9 @@ static const efx_nic_ops_t\t__efx_nic_medford_ops = {\n \tef10_nic_init,\t\t\t/* eno_init */\n \tef10_nic_get_vi_pool,\t\t/* eno_get_vi_pool */\n \tef10_nic_get_bar_region,\t/* eno_get_bar_region */\n+#if EFSYS_OPT_DIAG\n+\tef10_nic_register_test,\t\t/* eno_register_test */\n+#endif\t/* EFSYS_OPT_DIAG */\n \tef10_nic_fini,\t\t\t/* eno_fini */\n \tef10_nic_unprobe,\t\t/* eno_unprobe */\n };\n@@ -607,6 +616,165 @@ efx_nic_cfg_get(\n \treturn (&(enp->en_nic_cfg));\n }\n \n+#if EFSYS_OPT_DIAG\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_register_test(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));\n+\n+\tif ((rc = enop->eno_register_test(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_test_registers(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_register_set_t *rsp,\n+\t__in\t\tsize_t count)\n+{\n+\tunsigned int bit;\n+\tefx_oword_t original;\n+\tefx_oword_t reg;\n+\tefx_oword_t buf;\n+\tefx_rc_t rc;\n+\n+\twhile (count > 0) {\n+\t\t/* This function is only suitable for registers */\n+\t\tEFSYS_ASSERT(rsp->rows == 1);\n+\n+\t\t/* bit sweep on and off */\n+\t\tEFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,\n+\t\t\t B_TRUE);\n+\t\tfor (bit = 0; bit < 128; bit++) {\n+\t\t\t/* Is this bit in the mask? */\n+\t\t\tif (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Test this bit can be set in isolation */\n+\t\t\treg = original;\n+\t\t\tEFX_AND_OWORD(reg, rsp->mask);\n+\t\t\tEFX_SET_OWORD_BIT(reg, bit);\n+\n+\t\t\tEFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,\n+\t\t\t\t B_TRUE);\n+\t\t\tEFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,\n+\t\t\t\t B_TRUE);\n+\n+\t\t\tEFX_AND_OWORD(buf, rsp->mask);\n+\t\t\tif (memcmp(®, &buf, sizeof (reg))) {\n+\t\t\t\trc = EIO;\n+\t\t\t\tgoto fail1;\n+\t\t\t}\n+\n+\t\t\t/* Test this bit can be cleared in isolation */\n+\t\t\tEFX_OR_OWORD(reg, rsp->mask);\n+\t\t\tEFX_CLEAR_OWORD_BIT(reg, bit);\n+\n+\t\t\tEFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,\n+\t\t\t\t B_TRUE);\n+\t\t\tEFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,\n+\t\t\t\t B_TRUE);\n+\n+\t\t\tEFX_AND_OWORD(buf, rsp->mask);\n+\t\t\tif (memcmp(®, &buf, sizeof (reg))) {\n+\t\t\t\trc = EIO;\n+\t\t\t\tgoto fail2;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Restore the old value */\n+\t\tEFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,\n+\t\t\t B_TRUE);\n+\n+\t\t--count;\n+\t\t++rsp;\n+\t}\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\t/* Restore the old value */\n+\tEFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_test_tables(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_register_set_t *rsp,\n+\t__in\t\tefx_pattern_type_t pattern,\n+\t__in\t\tsize_t count)\n+{\n+\tefx_sram_pattern_fn_t func;\n+\tunsigned int index;\n+\tunsigned int address;\n+\tefx_oword_t reg;\n+\tefx_oword_t buf;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);\n+\tfunc = __efx_sram_pattern_fns[pattern];\n+\n+\twhile (count > 0) {\n+\t\t/* Write */\n+\t\taddress = rsp->address;\n+\t\tfor (index = 0; index < rsp->rows; ++index) {\n+\t\t\tfunc(2 * index + 0, B_FALSE, ®.eo_qword[0]);\n+\t\t\tfunc(2 * index + 1, B_FALSE, ®.eo_qword[1]);\n+\t\t\tEFX_AND_OWORD(reg, rsp->mask);\n+\t\t\tEFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);\n+\n+\t\t\taddress += rsp->step;\n+\t\t}\n+\n+\t\t/* Read */\n+\t\taddress = rsp->address;\n+\t\tfor (index = 0; index < rsp->rows; ++index) {\n+\t\t\tfunc(2 * index + 0, B_FALSE, ®.eo_qword[0]);\n+\t\t\tfunc(2 * index + 1, B_FALSE, ®.eo_qword[1]);\n+\t\t\tEFX_AND_OWORD(reg, rsp->mask);\n+\t\t\tEFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);\n+\t\t\tif (memcmp(®, &buf, sizeof (reg))) {\n+\t\t\t\trc = EIO;\n+\t\t\t\tgoto fail1;\n+\t\t\t}\n+\n+\t\t\taddress += rsp->step;\n+\t\t}\n+\n+\t\t++rsp;\n+\t\t--count;\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n \t__checkReturn\tefx_rc_t\n efx_nic_calculate_pcie_link_bandwidth(\n \t__in\t\tuint32_t pcie_link_width,\ndiff --git a/drivers/net/sfc/efx/base/efx_sram.c b/drivers/net/sfc/efx/base/efx_sram.c\nindex a55b06e..5f4edea 100644\n--- a/drivers/net/sfc/efx/base/efx_sram.c\n+++ b/drivers/net/sfc/efx/base/efx_sram.c\n@@ -198,3 +198,134 @@ efx_sram_buf_tbl_clear(\n }\n \n \n+#if EFSYS_OPT_DIAG\n+\n+static\t\t\tvoid\n+efx_sram_byte_increment_set(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp)\n+{\n+\tsize_t offset = row * FR_AZ_SRM_DBG_REG_STEP;\n+\tunsigned int index;\n+\n+\t_NOTE(ARGUNUSED(negate))\n+\n+\tfor (index = 0; index < sizeof (efx_qword_t); index++)\n+\t\teqp->eq_u8[index] = offset + index;\n+}\n+\n+static\t\t\tvoid\n+efx_sram_all_the_same_set(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp)\n+{\n+\t_NOTE(ARGUNUSED(row))\n+\n+\tif (negate)\n+\t\tEFX_SET_QWORD(*eqp);\n+\telse\n+\t\tEFX_ZERO_QWORD(*eqp);\n+}\n+\n+static\t\t\tvoid\n+efx_sram_bit_alternate_set(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp)\n+{\n+\t_NOTE(ARGUNUSED(row))\n+\n+\tEFX_POPULATE_QWORD_2(*eqp,\n+\t EFX_DWORD_0, (negate) ? 0x55555555 : 0xaaaaaaaa,\n+\t EFX_DWORD_1, (negate) ? 0x55555555 : 0xaaaaaaaa);\n+}\n+\n+static\t\t\tvoid\n+efx_sram_byte_alternate_set(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp)\n+{\n+\t_NOTE(ARGUNUSED(row))\n+\n+\tEFX_POPULATE_QWORD_2(*eqp,\n+\t EFX_DWORD_0, (negate) ? 0x00ff00ff : 0xff00ff00,\n+\t EFX_DWORD_1, (negate) ? 0x00ff00ff : 0xff00ff00);\n+}\n+\n+static\t\t\tvoid\n+efx_sram_byte_changing_set(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp)\n+{\n+\tsize_t offset = row * FR_AZ_SRM_DBG_REG_STEP;\n+\tunsigned int index;\n+\n+\tfor (index = 0; index < sizeof (efx_qword_t); index++) {\n+\t\tuint8_t byte;\n+\n+\t\tif (offset / 256 == 0)\n+\t\t\tbyte = (uint8_t)((offset % 257) % 256);\n+\t\telse\n+\t\t\tbyte = (uint8_t)(~((offset - 8) % 257) % 256);\n+\n+\t\teqp->eq_u8[index] = (negate) ? ~byte : byte;\n+\t}\n+}\n+\n+static\t\t\tvoid\n+efx_sram_bit_sweep_set(\n+\t__in\t\tsize_t row,\n+\t__in\t\tboolean_t negate,\n+\t__out\t\tefx_qword_t *eqp)\n+{\n+\tsize_t offset = row * FR_AZ_SRM_DBG_REG_STEP;\n+\n+\tif (negate) {\n+\t\tEFX_SET_QWORD(*eqp);\n+\t\tEFX_CLEAR_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64);\n+\t} else {\n+\t\tEFX_ZERO_QWORD(*eqp);\n+\t\tEFX_SET_QWORD_BIT(*eqp, (offset / sizeof (efx_qword_t)) % 64);\n+\t}\n+}\n+\n+efx_sram_pattern_fn_t\t__efx_sram_pattern_fns[] = {\n+\tefx_sram_byte_increment_set,\n+\tefx_sram_all_the_same_set,\n+\tefx_sram_bit_alternate_set,\n+\tefx_sram_byte_alternate_set,\n+\tefx_sram_byte_changing_set,\n+\tefx_sram_bit_sweep_set\n+};\n+\n+\t__checkReturn\tefx_rc_t\n+efx_sram_test(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_pattern_type_t type)\n+{\n+\tefx_sram_pattern_fn_t func;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));\n+\n+\t/* SRAM testing is only available on Siena. */\n+\tif (enp->en_family != EFX_FAMILY_SIENA)\n+\t\treturn (0);\n+\n+\t/* Select pattern generator */\n+\tEFSYS_ASSERT3U(type, <, EFX_PATTERN_NTYPES);\n+\tfunc = __efx_sram_pattern_fns[type];\n+\n+\treturn (siena_sram_test(enp, func));\n+}\n+\n+#endif\t/* EFSYS_OPT_DIAG */\ndiff --git a/drivers/net/sfc/efx/base/siena_impl.h b/drivers/net/sfc/efx/base/siena_impl.h\nindex 2c2a098..c316867 100644\n--- a/drivers/net/sfc/efx/base/siena_impl.h\n+++ b/drivers/net/sfc/efx/base/siena_impl.h\n@@ -54,6 +54,14 @@ extern\t__checkReturn\tefx_rc_t\n siena_nic_init(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_DIAG\n+\n+extern\t__checkReturn\tefx_rc_t\n+siena_nic_register_test(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n extern\t\t\tvoid\n siena_nic_fini(\n \t__in\t\tefx_nic_t *enp);\n@@ -68,6 +76,15 @@ extern\t\t\tvoid\n siena_sram_init(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_DIAG\n+\n+extern\t__checkReturn\tefx_rc_t\n+siena_sram_test(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_sram_pattern_fn_t func);\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n #if EFSYS_OPT_MCDI\n \n extern\t__checkReturn\tefx_rc_t\ndiff --git a/drivers/net/sfc/efx/base/siena_nic.c b/drivers/net/sfc/efx/base/siena_nic.c\nindex 7be16dc..2d079c2 100644\n--- a/drivers/net/sfc/efx/base/siena_nic.c\n+++ b/drivers/net/sfc/efx/base/siena_nic.c\n@@ -354,4 +354,136 @@ siena_nic_unprobe(\n \t(void) efx_mcdi_drv_attach(enp, B_FALSE);\n }\n \n+#if EFSYS_OPT_DIAG\n+\n+static efx_register_set_t __siena_registers[] = {\n+\t{ FR_AZ_ADR_REGION_REG_OFST, 0, 1 },\n+\t{ FR_CZ_USR_EV_CFG_OFST, 0, 1 },\n+\t{ FR_AZ_RX_CFG_REG_OFST, 0, 1 },\n+\t{ FR_AZ_TX_CFG_REG_OFST, 0, 1 },\n+\t{ FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },\n+\t{ FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },\n+\t{ FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },\n+\t{ FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },\n+\t{ FR_AZ_DP_CTRL_REG_OFST, 0, 1 },\n+\t{ FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},\n+\t{ FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},\n+\t{ FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},\n+\t{ FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}\n+};\n+\n+static const uint32_t __siena_register_masks[] = {\n+\t0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,\n+\t0x000103FF, 0x00000000, 0x00000000, 0x00000000,\n+\t0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,\n+\t0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,\n+\t0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,\n+\t0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000003, 0x00000000, 0x00000000, 0x00000000,\n+\t0x000003FF, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000FFF, 0x00000000, 0x00000000, 0x00000000,\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000\n+};\n+\n+static efx_register_set_t __siena_tables[] = {\n+\t{ FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,\n+\t FR_AZ_RX_FILTER_TBL0_ROWS },\n+\t{ FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,\n+\t FR_CZ_RX_MAC_FILTER_TBL0_ROWS },\n+\t{ FR_AZ_RX_DESC_PTR_TBL_OFST,\n+\t FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },\n+\t{ FR_AZ_TX_DESC_PTR_TBL_OFST,\n+\t FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },\n+\t{ FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },\n+\t{ FR_CZ_TX_FILTER_TBL0_OFST,\n+\t FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },\n+\t{ FR_CZ_TX_MAC_FILTER_TBL0_OFST,\n+\t FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }\n+};\n+\n+static const uint32_t __siena_table_masks[] = {\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,\n+\t0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,\n+\t0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,\n+\t0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,\n+\t0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,\n+\t0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,\n+};\n+\n+\t__checkReturn\tefx_rc_t\n+siena_nic_register_test(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_register_set_t *rsp;\n+\tconst uint32_t *dwordp;\n+\tunsigned int nitems;\n+\tunsigned int count;\n+\tefx_rc_t rc;\n+\n+\t/* Fill out the register mask entries */\n+\tEFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)\n+\t\t == EFX_ARRAY_SIZE(__siena_registers) * 4);\n+\n+\tnitems = EFX_ARRAY_SIZE(__siena_registers);\n+\tdwordp = __siena_register_masks;\n+\tfor (count = 0; count < nitems; ++count) {\n+\t\trsp = __siena_registers + count;\n+\t\trsp->mask.eo_u32[0] = *dwordp++;\n+\t\trsp->mask.eo_u32[1] = *dwordp++;\n+\t\trsp->mask.eo_u32[2] = *dwordp++;\n+\t\trsp->mask.eo_u32[3] = *dwordp++;\n+\t}\n+\n+\t/* Fill out the register table entries */\n+\tEFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)\n+\t\t == EFX_ARRAY_SIZE(__siena_tables) * 4);\n+\n+\tnitems = EFX_ARRAY_SIZE(__siena_tables);\n+\tdwordp = __siena_table_masks;\n+\tfor (count = 0; count < nitems; ++count) {\n+\t\trsp = __siena_tables + count;\n+\t\trsp->mask.eo_u32[0] = *dwordp++;\n+\t\trsp->mask.eo_u32[1] = *dwordp++;\n+\t\trsp->mask.eo_u32[2] = *dwordp++;\n+\t\trsp->mask.eo_u32[3] = *dwordp++;\n+\t}\n+\n+\tif ((rc = efx_nic_test_registers(enp, __siena_registers,\n+\t EFX_ARRAY_SIZE(__siena_registers))) != 0)\n+\t\tgoto fail1;\n+\n+\tif ((rc = efx_nic_test_tables(enp, __siena_tables,\n+\t EFX_PATTERN_BYTE_ALTERNATE,\n+\t EFX_ARRAY_SIZE(__siena_tables))) != 0)\n+\t\tgoto fail2;\n+\n+\tif ((rc = efx_nic_test_tables(enp, __siena_tables,\n+\t EFX_PATTERN_BYTE_CHANGING,\n+\t EFX_ARRAY_SIZE(__siena_tables))) != 0)\n+\t\tgoto fail3;\n+\n+\tif ((rc = efx_nic_test_tables(enp, __siena_tables,\n+\t EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)\n+\t\tgoto fail4;\n+\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n #endif\t/* EFSYS_OPT_SIENA */\ndiff --git a/drivers/net/sfc/efx/base/siena_sram.c b/drivers/net/sfc/efx/base/siena_sram.c\nindex 411ef9d..572c2e9 100644\n--- a/drivers/net/sfc/efx/base/siena_sram.c\n+++ b/drivers/net/sfc/efx/base/siena_sram.c\n@@ -71,4 +71,108 @@ siena_sram_init(\n \tEFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);\n }\n \n+#if EFSYS_OPT_DIAG\n+\n+\t__checkReturn\tefx_rc_t\n+siena_sram_test(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_sram_pattern_fn_t func)\n+{\n+\tefx_oword_t oword;\n+\tefx_qword_t qword;\n+\tefx_qword_t verify;\n+\tsize_t rows;\n+\tunsigned int wptr;\n+\tunsigned int rptr;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);\n+\n+\t/* Reconfigure into HALF buffer table mode */\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);\n+\n+\t/*\n+\t * Move the descriptor caches up to the top of SRAM, and test\n+\t * all of SRAM below them. We only miss out one row here.\n+\t */\n+\trows = SIENA_SRAM_ROWS - 1;\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);\n+\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);\n+\n+\t/*\n+\t * Write the pattern through BUF_HALF_TBL. Write\n+\t * in 64 entry batches, waiting 1us in between each batch\n+\t * to guarantee not to overflow the SRAM fifo\n+\t */\n+\tfor (wptr = 0, rptr = 0; wptr < rows; ++wptr) {\n+\t\tfunc(wptr, B_FALSE, &qword);\n+\t\tEFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);\n+\n+\t\tif ((wptr - rptr) < 64 && wptr < rows - 1)\n+\t\t\tcontinue;\n+\n+\t\tEFSYS_SPIN(1);\n+\n+\t\tfor (; rptr <= wptr; ++rptr) {\n+\t\t\tfunc(rptr, B_FALSE, &qword);\n+\t\t\tEFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,\n+\t\t\t &verify);\n+\n+\t\t\tif (!EFX_QWORD_IS_EQUAL(verify, qword)) {\n+\t\t\t\trc = EFAULT;\n+\t\t\t\tgoto fail1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* And do the same negated */\n+\tfor (wptr = 0, rptr = 0; wptr < rows; ++wptr) {\n+\t\tfunc(wptr, B_TRUE, &qword);\n+\t\tEFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);\n+\n+\t\tif ((wptr - rptr) < 64 && wptr < rows - 1)\n+\t\t\tcontinue;\n+\n+\t\tEFSYS_SPIN(1);\n+\n+\t\tfor (; rptr <= wptr; ++rptr) {\n+\t\t\tfunc(rptr, B_TRUE, &qword);\n+\t\t\tEFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,\n+\t\t\t &verify);\n+\n+\t\t\tif (!EFX_QWORD_IS_EQUAL(verify, qword)) {\n+\t\t\t\trc = EFAULT;\n+\t\t\t\tgoto fail2;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Restore back to FULL buffer table mode */\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);\n+\n+\t/*\n+\t * We don't need to reconfigure SRAM again because the API\n+\t * requires efx_nic_fini() to be called after an sram test.\n+\t */\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\t/* Restore back to FULL buffer table mode */\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_DIAG */\n+\n #endif\t/* EFSYS_OPT_SIENA */\n", "prefixes": [ "dpdk-dev", "12/56" ] }