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GET /api/patches/17024/?format=api
{ "id": 17024, "url": "https://patches.dpdk.org/api/patches/17024/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/3ce1da9662dcf59950f43643c14cc14e972f0429.1479309557.git.nelio.laranjeiro@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<3ce1da9662dcf59950f43643c14cc14e972f0429.1479309557.git.nelio.laranjeiro@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/3ce1da9662dcf59950f43643c14cc14e972f0429.1479309557.git.nelio.laranjeiro@6wind.com", "date": "2016-11-16T15:20:38", "name": "[dpdk-dev] eal: define generic vector types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6ba937bc0e766010d0ac4e85f51898a6ca4359ea", "submitter": { "id": 243, "url": "https://patches.dpdk.org/api/people/243/?format=api", "name": "Nélio Laranjeiro", "email": "nelio.laranjeiro@6wind.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/3ce1da9662dcf59950f43643c14cc14e972f0429.1479309557.git.nelio.laranjeiro@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/17024/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/17024/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 23C5F559A;\n\tWed, 16 Nov 2016 16:20:53 +0100 (CET)", "from mail-wm0-f47.google.com (mail-wm0-f47.google.com\n\t[74.125.82.47]) by dpdk.org (Postfix) with ESMTP id 3CC7D475E\n\tfor <dev@dpdk.org>; Wed, 16 Nov 2016 16:20:52 +0100 (CET)", "by mail-wm0-f47.google.com with SMTP id a197so246091203wmd.0\n\tfor <dev@dpdk.org>; Wed, 16 Nov 2016 07:20:52 -0800 (PST)", "from ping.vm.6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by smtp.gmail.com with ESMTPSA id\n\tq65sm10678589wmd.6.2016.11.16.07.20.50\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 16 Nov 2016 07:20:51 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id;\n\tbh=D4QNw0II/lVs/+JS7xkf5TYjs7eMSprdofIuuqDF9TE=;\n\tb=z8foeA1RNPHxnHSMOMfkl14FPb+3Jgx6hXo1/Bpc+GZU3nkNxbpbXn+GdRVxeoSnHB\n\teX+3TH6q3yeZe+lEmMtzKySBWM5lyJSGTHIeY4GI+cqvN/OwJxLUiXyr0nard/IM7OZg\n\tjO9hBt+YRxYWbqRPizGHvy2zXLrU4Vz80JGqyq2338p52e26t8arCax4A5Erevm11bjL\n\trLpNG6rh/ifIBuwo6Xv2lKjnAevm9FuNGF6ADzwNwRGuAZ/xTuk69s1OQcOl1WAoFNfK\n\t2ACuHN1jgQoTRgQusmn/fVGBwdQ1I+sdANQbk6KB/5YUjXPuVfLbL7KtshphUJJAbU3E\n\tmrfw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=D4QNw0II/lVs/+JS7xkf5TYjs7eMSprdofIuuqDF9TE=;\n\tb=YZLwj3ZfGHT0gElzoe6ISSDp0giFhfHNmEvTvq7FyzNEAIId/knws8jFV/iUkCGB+U\n\tiO2otasRLsEErAjavlEq2nWxAGKLW6AzaLfDh3knssO4so8IcR8jHqf6NCx5Lc2/k6tf\n\tM5rvQfHUuy/jChajdHUjbmjBUqWgxIgvq6GM+aV3yWRstgumHS+ElwyMaF9wVyY+cQYK\n\t3sD3/nljqlHz2nV0WRACOPNPmcin1iXEnTcrUWcPqQ4VeoKAAWSqC2o28SF3oeEZ78x4\n\t8Y79G9aysSsvfL86FiLu5ge42fC75fGEuk3EP/lAGGGKyze3YwiaoDVI2D9q8FPZg3L4\n\tasSw==", "X-Gm-Message-State": "ABUngvfukiPp8OxZX/69ESDoljgBOQ0T8SjrQl+eag1YrMAZEGm/5ifx/p2I9+TOnVcVewmh", "X-Received": "by 10.28.221.11 with SMTP id u11mr9845741wmg.91.1479309651755;\n\tWed, 16 Nov 2016 07:20:51 -0800 (PST)", "From": "Nelio Laranjeiro <nelio.laranjeiro@6wind.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas.monjalon@6wind.com>,\n\tJianbo Liu <jianbo.liu@linaro.org>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tZhigang Lu <zlu@ezchip.com>, \n\tLiming Sun <lsun@ezchip.com>, Chao Zhu <chaozhu@linux.vnet.ibm.com>, \n\tBruce Richardson <bruce.richardson@intel.com>,\n\tKonstantin Ananyev <konstantin.ananyev@intel.com>,\n\tAdrien Mazarguil <adrien.mazarguil@6wind.com>", "Date": "Wed, 16 Nov 2016 16:20:38 +0100", "Message-Id": "<3ce1da9662dcf59950f43643c14cc14e972f0429.1479309557.git.nelio.laranjeiro@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "Subject": "[dpdk-dev] [PATCH] eal: define generic vector types", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add common vector type definitions to all CPU architectures.\n\nSigned-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\n---\n lib/librte_eal/common/Makefile | 1 +\n lib/librte_eal/common/include/arch/arm/rte_vect.h | 1 +\n .../common/include/arch/ppc_64/rte_vect.h | 1 +\n lib/librte_eal/common/include/arch/tile/rte_vect.h | 38 +++++\n lib/librte_eal/common/include/arch/x86/rte_vect.h | 7 +-\n lib/librte_eal/common/include/generic/rte_vect.h | 185 +++++++++++++++++++++\n 6 files changed, 230 insertions(+), 3 deletions(-)\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_vect.h\n create mode 100644 lib/librte_eal/common/include/generic/rte_vect.h", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex dfd64aa..8af06b1 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -48,6 +48,7 @@ endif\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h\n+GENERIC_INC += rte_vect.h\n # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk\n ARCH_DIR ?= $(RTE_ARCH)\n ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_vect.h b/lib/librte_eal/common/include/arch/arm/rte_vect.h\nindex b86c2cf..4107c99 100644\n--- a/lib/librte_eal/common/include/arch/arm/rte_vect.h\n+++ b/lib/librte_eal/common/include/arch/arm/rte_vect.h\n@@ -34,6 +34,7 @@\n #define _RTE_VECT_ARM_H_\n \n #include <stdint.h>\n+#include \"generic/rte_vect.h\"\n #include \"arm_neon.h\"\n \n #ifdef __cplusplus\ndiff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h\nindex 05209e5..99586e5 100644\n--- a/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h\n@@ -34,6 +34,7 @@\n #define _RTE_VECT_PPC_64_H_\n \n #include <altivec.h>\n+#include \"generic/rte_vect.h\"\n \n #ifdef __cplusplus\n extern \"C\" {\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_vect.h b/lib/librte_eal/common/include/arch/tile/rte_vect.h\nnew file mode 100644\nindex 0000000..f1e1709\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_vect.h\n@@ -0,0 +1,38 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright 2016 6WIND S.A.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of 6WIND S.A. nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_VECT_TILE_H_\n+#define _RTE_VECT_TILE_H_\n+\n+#include \"generic/rte_vect.h\"\n+\n+#endif /* _RTE_VECT_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/x86/rte_vect.h b/lib/librte_eal/common/include/arch/x86/rte_vect.h\nindex 77f2e25..1b4b85d 100644\n--- a/lib/librte_eal/common/include/arch/x86/rte_vect.h\n+++ b/lib/librte_eal/common/include/arch/x86/rte_vect.h\n@@ -31,8 +31,8 @@\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n \n-#ifndef _RTE_VECT_H_\n-#define _RTE_VECT_H_\n+#ifndef _RTE_VECT_X86_H_\n+#define _RTE_VECT_X86_H_\n \n /**\n * @file\n@@ -41,6 +41,7 @@\n */\n \n #include <stdint.h>\n+#include \"generic/rte_vect.h\"\n \n #if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))\n \n@@ -133,4 +134,4 @@ __extension__ ({ \\\n }\n #endif\n \n-#endif /* _RTE_VECT_H_ */\n+#endif /* _RTE_VECT_X86_H_ */\ndiff --git a/lib/librte_eal/common/include/generic/rte_vect.h b/lib/librte_eal/common/include/generic/rte_vect.h\nnew file mode 100644\nindex 0000000..d7b9cd9\n--- /dev/null\n+++ b/lib/librte_eal/common/include/generic/rte_vect.h\n@@ -0,0 +1,185 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright 2016 6WIND S.A.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of 6WIND S.A. nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_VECT_H_\n+#define _RTE_VECT_H_\n+\n+#include <stdint.h>\n+\n+/* Unsigned vector types. */\n+\n+/*\n+ * 64 bits vector size to use with unsigned 8 bits elements.\n+ * a = (rte_v64u8_t){ a0, a1, a2, a3, a4, a5, a6, a7 }\n+ */\n+typedef uint8_t rte_v64u8_t __attribute__((vector_size(8), aligned(8)));\n+\n+/*\n+ * 64 bits vector size to use with unsigned 16 bits elements.\n+ * a = (rte_v64u16_t){ a0, a1, a2, a3 }\n+ */\n+typedef uint16_t rte_v64u16_t __attribute__((vector_size(8), aligned(8)));\n+\n+/*\n+ * 64 bits vector size to use with unsigned 32 bits elements.\n+ * a = (rte_v64u32_t){ a0, a1 }\n+ */\n+typedef uint32_t rte_v64u32_t __attribute__((vector_size(8), aligned(8)));\n+\n+/*\n+ * 128 bits vector size to use with unsigned 8 bits elements.\n+ * a = (rte_v128u8_t){ a00, a01, a02, a03, a04, a05, a06, a07,\n+ * a08, a09, a10, a11, a12, a13, a14, a15 }\n+ */\n+typedef uint8_t rte_v128u8_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 128 bits vector size to use with unsigned 16 bits elements.\n+ * a = (rte_v128u16_t){ a0, a1, a2, a3, a4, a5, a6, a7 }\n+ */\n+typedef uint16_t rte_v128u16_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 128 bits vector size to use with unsigned 32 bits elements.\n+ * a = (rte_v128u32_t){ a0, a1, a2, a3, a4 }\n+ */\n+typedef uint32_t rte_v128u32_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 128 bits vector size to use with unsigned 64 bits elements.\n+ * a = (rte_v128u64_t){ a0, a1 }\n+ */\n+typedef uint64_t rte_v128u64_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 256 bits vector size to use with unsigned 8 bits elements.\n+ * a = (rte_v256u8_t){ a00, a01, a02, a03, a04, a05, a06, a07,\n+ * a08, a09, a10, a11, a12, a13, a14, a15,\n+ * a16, a17, a18, a19, a20, a21, a22, a23,\n+ * a24, a25, a26, a27, a28, a29, a30, a31 }\n+ */\n+typedef uint8_t rte_v256u8_t __attribute__((vector_size(32), aligned(32)));\n+\n+/*\n+ * 256 bits vector size to use with unsigned 16 bits elements.\n+ * a = (rte_v256u16_t){ a00, a01, a02, a03, a04, a05, a06, a07,\n+ * a08, a09, a10, a11, a12, a13, a14, a15 }\n+ */\n+typedef uint16_t rte_v256u16_t __attribute__((vector_size(32), aligned(32)));\n+\n+/*\n+ * 256 bits vector size to use with unsigned 32 bits elements.\n+ * a = (rte_v256u32_t){ a0, a1, a2, a3, a4, a5, a6, a7 }\n+ */\n+typedef uint32_t rte_v256u32_t __attribute__((vector_size(32), aligned(32)));\n+\n+/*\n+ * 256 bits vector size to use with unsigned 64 bits elements.\n+ * a = (rte_v256u64_t){ a0, a1, a2, a3 }\n+ */\n+typedef uint64_t rte_v256u64_t __attribute__((vector_size(32), aligned(32)));\n+\n+\n+/* Signed vector types. */\n+\n+/*\n+ * 64 bits vector size to use with 8 bits elements.\n+ * a = (rte_v64s8_t){ a0, a1, a2, a3, a4, a5, a6, a7 }\n+ */\n+typedef int8_t rte_v64s8_t __attribute__((vector_size(8), aligned(8)));\n+\n+/*\n+ * 64 bits vector size to use with 16 bits elements.\n+ * a = (rte_v64s16_t){ a0, a1, a2, a3 }\n+ */\n+typedef int16_t rte_v64s16_t __attribute__((vector_size(8), aligned(8)));\n+\n+/*\n+ * 64 bits vector size to use with 32 bits elements.\n+ * a = (rte_v64s32_t){ a0, a1 }\n+ */\n+typedef int32_t rte_v64s32_t __attribute__((vector_size(8), aligned(8)));\n+\n+/*\n+ * 128 bits vector size to use with 8 bits elements.\n+ * a = (rte_v128s8_t){ a00, a01, a02, a03, a04, a05, a06, a07,\n+ * a08, a09, a10, a11, a12, a13, a14, a15 }\n+ */\n+typedef int8_t rte_v128s8_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 128 bits vector size to use with 16 bits elements.\n+ * a = (rte_v128s16_t){ a0, a1, a2, a3, a4, a5, a6, a7 }\n+ */\n+typedef int16_t rte_v128s16_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 128 bits vector size to use with 32 bits elements.\n+ * a = (rte_v128s32_t){ a0, a1, a2, a3 }\n+ */\n+typedef int32_t rte_v128s32_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 128 bits vector size to use with 64 bits elements.\n+ * a = (rte_v128s64_t){ a1, a2 }\n+ */\n+typedef int64_t rte_v128s64_t __attribute__((vector_size(16), aligned(16)));\n+\n+/*\n+ * 256 bits vector size to use with 8 bits elements.\n+ * a = (rte_v256s8_t){ a00, a01, a02, a03, a04, a05, a06, a07,\n+ * a08, a09, a10, a11, a12, a13, a14, a15,\n+ * a16, a17, a18, a19, a20, a21, a22, a23,\n+ * a24, a25, a26, a27, a28, a29, a30, a31 }\n+ */\n+typedef int8_t rte_v256s8_t __attribute__((vector_size(32), aligned(32)));\n+\n+/*\n+ * 256 bits vector size to use with 16 bits elements.\n+ * a = (rte_v256s16_t){ a00, a01, a02, a03, a04, a05, a06, a07,\n+ * a08, a09, a10, a11, a12, a13, a14, a15 }\n+ */\n+typedef int16_t rte_v256s16_t __attribute__((vector_size(32), aligned(32)));\n+\n+/*\n+ * 256 bits vector size to use with 32 bits elements.\n+ * a = (rte_v256s32_t){ a0, a1, a2, a3, a4, a5, a6, a7 }\n+ */\n+typedef int32_t rte_v256s32_t __attribute__((vector_size(32), aligned(32)));\n+\n+/*\n+ * 256 bits vector size to use with 64 bits elements.\n+ * a = (rte_v256s64_t){ a0, a1, a2, a3 }\n+ */\n+typedef int64_t rte_v256s64_t __attribute__((vector_size(32), aligned(32)));\n+\n+#endif /* _RTE_VECT_H_ */\n", "prefixes": [ "dpdk-dev" ] }