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{
    "id": 16617,
    "url": "https://patches.dpdk.org/api/patches/16617/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1476562089-21823-3-git-send-email-rasesh.mody@qlogic.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1476562089-21823-3-git-send-email-rasesh.mody@qlogic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1476562089-21823-3-git-send-email-rasesh.mody@qlogic.com",
    "date": "2016-10-15T20:07:39",
    "name": "[dpdk-dev,v3,02/32] qede/base: formatting changes",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "b504a735497b34745827197f393510e95fe563df",
    "submitter": {
        "id": 325,
        "url": "https://patches.dpdk.org/api/people/325/?format=api",
        "name": "Rasesh Mody",
        "email": "rasesh.mody@qlogic.com"
    },
    "delegate": {
        "id": 10,
        "url": "https://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1476562089-21823-3-git-send-email-rasesh.mody@qlogic.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/16617/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/16617/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 45A0D6CD8;\n\tSat, 15 Oct 2016 22:08:44 +0200 (CEST)",
            "from mx0b-0016ce01.pphosted.com (mx0a-0016ce01.pphosted.com\n\t[67.231.148.157]) by dpdk.org (Postfix) with ESMTP id BF2F56CD5\n\tfor <dev@dpdk.org>; Sat, 15 Oct 2016 22:08:41 +0200 (CEST)",
            "from pps.filterd (m0095336.ppops.net [127.0.0.1])\n\tby mx0a-0016ce01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id\n\tu9FK62EO014065; Sat, 15 Oct 2016 13:08:40 -0700",
            "from avcashub1.qlogic.com ([198.186.0.115])\n\tby mx0a-0016ce01.pphosted.com with ESMTP id 263jj4gfrf-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tSat, 15 Oct 2016 13:08:39 -0700",
            "from avluser05.qlc.com (10.1.113.115) by avcashub1.qlogic.org\n\t(10.1.4.190) with Microsoft SMTP Server (TLS) id 14.3.235.1;\n\tSat, 15 Oct 2016 13:08:38 -0700",
            "(from rmody@localhost)\tby avluser05.qlc.com (8.14.4/8.14.4/Submit)\n\tid u9FK8cID021950;\tSat, 15 Oct 2016 13:08:38 -0700"
        ],
        "X-Authentication-Warning": "avluser05.qlc.com: rmody set sender to\n\trasesh.mody@qlogic.com using -f",
        "From": "Rasesh Mody <rasesh.mody@qlogic.com>",
        "To": "<ferruh.yigit@intel.com>, <thomas.monjalon@6wind.com>,\n\t<bruce.richardson@intel.com>",
        "CC": "<dev@dpdk.org>, <Dept-EngDPDKDev@qlogic.com>, Rasesh Mody\n\t<rasesh.mody@qlogic.com>",
        "Date": "Sat, 15 Oct 2016 13:07:39 -0700",
        "Message-ID": "<1476562089-21823-3-git-send-email-rasesh.mody@qlogic.com>",
        "X-Mailer": "git-send-email 1.7.10.3",
        "In-Reply-To": "<1476562089-21823-1-git-send-email-rasesh.mody@qlogic.com>",
        "References": "<1476562089-21823-1-git-send-email-rasesh.mody@qlogic.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "disclaimer": "bypass",
        "X-Proofpoint-Virus-Version": "vendor=nai engine=5800 definitions=8319\n\tsignatures=670719",
        "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0\n\tpriorityscore=1501 malwarescore=0\n\tsuspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015\n\tlowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam\n\tadjust=0\n\treason=mlx scancount=1 engine=8.0.1-1609300000\n\tdefinitions=main-1610150355",
        "Subject": "[dpdk-dev] [PATCH v3 02/32] qede/base: formatting changes",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Fixes white spaces and tabs.\n\nSigned-off-by: Rasesh Mody <rasesh.mody@qlogic.com>\n---\n drivers/net/qede/base/common_hsi.h          |  252 ++---\n drivers/net/qede/base/ecore.h               |  414 +++----\n drivers/net/qede/base/ecore_chain.h         |   20 +-\n drivers/net/qede/base/ecore_cxt.c           |   16 +-\n drivers/net/qede/base/ecore_cxt_api.h       |   10 +-\n drivers/net/qede/base/ecore_dcbx.c          |    4 +-\n drivers/net/qede/base/ecore_dcbx_api.h      |   26 +-\n drivers/net/qede/base/ecore_dev.c           |  112 +-\n drivers/net/qede/base/ecore_dev_api.h       |   72 +-\n drivers/net/qede/base/ecore_gtt_reg_addr.h  |   20 +-\n drivers/net/qede/base/ecore_gtt_values.h    |   20 +-\n drivers/net/qede/base/ecore_hsi_common.h    |    6 +-\n drivers/net/qede/base/ecore_hsi_eth.h       |    8 +-\n drivers/net/qede/base/ecore_hw.c            |   14 +-\n drivers/net/qede/base/ecore_hw.h            |   28 +-\n drivers/net/qede/base/ecore_hw_defs.h       |    6 +-\n drivers/net/qede/base/ecore_init_fw_funcs.c |   12 +-\n drivers/net/qede/base/ecore_init_fw_funcs.h |   68 +-\n drivers/net/qede/base/ecore_init_ops.c      |    4 +-\n drivers/net/qede/base/ecore_int.c           |   14 +-\n drivers/net/qede/base/ecore_int.h           |    4 +-\n drivers/net/qede/base/ecore_iov_api.h       |   46 +-\n drivers/net/qede/base/ecore_iro.h           |   12 +-\n drivers/net/qede/base/ecore_iro_values.h    |   32 +-\n drivers/net/qede/base/ecore_l2.c            |   18 +-\n drivers/net/qede/base/ecore_l2.h            |    4 +-\n drivers/net/qede/base/ecore_l2_api.h        |   88 +-\n drivers/net/qede/base/ecore_mcp.c           |   28 +-\n drivers/net/qede/base/ecore_mcp.h           |    6 +-\n drivers/net/qede/base/ecore_mcp_api.h       |   16 +-\n drivers/net/qede/base/ecore_proto_if.h      |    4 +-\n drivers/net/qede/base/ecore_rt_defs.h       |  230 ++--\n drivers/net/qede/base/ecore_sp_api.h        |   10 +-\n drivers/net/qede/base/ecore_sp_commands.c   |   16 +-\n drivers/net/qede/base/ecore_sp_commands.h   |    8 +-\n drivers/net/qede/base/ecore_spq.c           |   60 +-\n drivers/net/qede/base/ecore_spq.h           |  136 +--\n drivers/net/qede/base/ecore_sriov.c         |  222 ++--\n drivers/net/qede/base/ecore_sriov.h         |   98 +-\n drivers/net/qede/base/ecore_status.h        |   18 +-\n drivers/net/qede/base/ecore_vf.c            |   18 +-\n drivers/net/qede/base/ecore_vf.h            |   34 +-\n drivers/net/qede/base/ecore_vf_api.h        |    4 +-\n drivers/net/qede/base/ecore_vfpf_if.h       |  270 ++---\n drivers/net/qede/base/eth_common.h          |   52 +-\n drivers/net/qede/base/mcp_public.h          |  194 ++--\n drivers/net/qede/base/nvm_cfg.h             | 1562 +++++++++++++--------------\n 47 files changed, 2158 insertions(+), 2158 deletions(-)",
    "diff": "diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h\nindex 295a41f..4574800 100644\n--- a/drivers/net/qede/base/common_hsi.h\n+++ b/drivers/net/qede/base/common_hsi.h\n@@ -9,9 +9,9 @@\n #ifndef __COMMON_HSI__\n #define __COMMON_HSI__\n \n-#define CORE_SPQE_PAGE_SIZE_BYTES                       4096\n+#define CORE_SPQE_PAGE_SIZE_BYTES\t\t\t4096\n \n-#define FW_MAJOR_VERSION\t8\n+#define FW_MAJOR_VERSION\t\t8\n #define FW_MINOR_VERSION\t7\n #define FW_REVISION_VERSION\t7\n #define FW_ENGINEERING_VERSION\t0\n@@ -21,68 +21,68 @@\n /***********************/\n \n /* PCI functions */\n-#define MAX_NUM_PORTS_K2\t(4)\n-#define MAX_NUM_PORTS_BB\t(2)\n-#define MAX_NUM_PORTS\t\t(MAX_NUM_PORTS_K2)\n+#define MAX_NUM_PORTS_K2\t\t(4)\n+#define MAX_NUM_PORTS_BB\t\t(2)\n+#define MAX_NUM_PORTS\t\t\t(MAX_NUM_PORTS_K2)\n \n-#define MAX_NUM_PFS_K2\t(16)\n-#define MAX_NUM_PFS_BB\t(8)\n-#define MAX_NUM_PFS\t(MAX_NUM_PFS_K2)\n-#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */\n+#define MAX_NUM_PFS_K2\t\t\t(16)\n+#define MAX_NUM_PFS_BB\t\t\t(8)\n+#define MAX_NUM_PFS\t\t\t\t(MAX_NUM_PFS_K2)\n+#define MAX_NUM_OF_PFS_IN_CHIP\t(16) /* On both engines */\n \n-#define MAX_NUM_VFS_K2\t(192)\n-#define MAX_NUM_VFS_BB\t(120)\n-#define MAX_NUM_VFS\t(MAX_NUM_VFS_K2)\n+#define MAX_NUM_VFS_K2\t\t\t(192)\n+#define MAX_NUM_VFS_BB\t\t\t(120)\n+#define MAX_NUM_VFS\t\t\t\t(MAX_NUM_VFS_K2)\n \n #define MAX_NUM_FUNCTIONS_BB\t(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)\n-#define MAX_NUM_FUNCTIONS\t(MAX_NUM_PFS + MAX_NUM_VFS)\n+#define MAX_NUM_FUNCTIONS\t\t(MAX_NUM_PFS + MAX_NUM_VFS)\n \n #define MAX_FUNCTION_NUMBER_BB\t(MAX_NUM_PFS + MAX_NUM_VFS_BB)\n-#define MAX_FUNCTION_NUMBER\t(MAX_NUM_PFS + MAX_NUM_VFS)\n+#define MAX_FUNCTION_NUMBER\t\t(MAX_NUM_PFS + MAX_NUM_VFS)\n \n-#define MAX_NUM_VPORTS_K2\t(208)\n-#define MAX_NUM_VPORTS_BB\t(160)\n-#define MAX_NUM_VPORTS\t\t(MAX_NUM_VPORTS_K2)\n+#define MAX_NUM_VPORTS_K2\t\t(208)\n+#define MAX_NUM_VPORTS_BB\t\t(160)\n+#define MAX_NUM_VPORTS\t\t\t(MAX_NUM_VPORTS_K2)\n \n #define MAX_NUM_L2_QUEUES_K2\t(320)\n #define MAX_NUM_L2_QUEUES_BB\t(256)\n-#define MAX_NUM_L2_QUEUES\t(MAX_NUM_L2_QUEUES_K2)\n+#define MAX_NUM_L2_QUEUES\t\t(MAX_NUM_L2_QUEUES_K2)\n \n /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */\n #define NUM_PHYS_TCS_4PORT_K2\t(4)\n-#define NUM_OF_PHYS_TCS\t\t(8)\n+#define NUM_OF_PHYS_TCS\t\t\t(8)\n \n-#define NUM_TCS_4PORT_K2\t(NUM_PHYS_TCS_4PORT_K2 + 1)\n-#define NUM_OF_TCS\t\t(NUM_OF_PHYS_TCS + 1)\n+#define NUM_TCS_4PORT_K2\t\t(NUM_PHYS_TCS_4PORT_K2 + 1)\n+#define NUM_OF_TCS\t\t\t\t(NUM_OF_PHYS_TCS + 1)\n \n-#define LB_TC\t\t\t(NUM_OF_PHYS_TCS)\n+#define LB_TC\t\t\t\t\t(NUM_OF_PHYS_TCS)\n \n /* Num of possible traffic priority values */\n-#define NUM_OF_PRIO\t\t(8)\n+#define NUM_OF_PRIO\t\t\t\t(8)\n \n-#define MAX_NUM_VOQS_K2\t\t(NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)\n-#define MAX_NUM_VOQS_BB\t\t(NUM_OF_TCS * MAX_NUM_PORTS_BB)\n-#define MAX_NUM_VOQS\t\t(MAX_NUM_VOQS_K2)\n-#define MAX_PHYS_VOQS\t\t(NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)\n+#define MAX_NUM_VOQS_K2\t\t\t(NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)\n+#define MAX_NUM_VOQS_BB         (NUM_OF_TCS * MAX_NUM_PORTS_BB)\n+#define MAX_NUM_VOQS\t\t\t(MAX_NUM_VOQS_K2)\n+#define MAX_PHYS_VOQS\t\t\t(NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)\n \n /* CIDs */\n-#define NUM_OF_CONNECTION_TYPES\t(8)\n-#define NUM_OF_LCIDS\t\t(320)\n-#define NUM_OF_LTIDS\t\t(320)\n+#define NUM_OF_CONNECTION_TYPES (8)\n+#define NUM_OF_LCIDS\t\t\t(320)\n+#define NUM_OF_LTIDS\t\t\t(320)\n \n /*****************/\n /* CDU CONSTANTS */\n /*****************/\n \n-#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT              (17)\n-#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK             (0x1ffff)\n+#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT\t\t(17)\n+#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK\t\t(0x1ffff)\n \n /*****************/\n /* DQ CONSTANTS  */\n /*****************/\n \n /* DEMS */\n-#define DQ_DEMS_LEGACY\t\t\t0\n+#define\tDQ_DEMS_LEGACY\t\t\t\t\t\t0\n \n /* XCM agg val selection */\n #define DQ_XCM_AGG_VAL_SEL_WORD2  0\n@@ -107,7 +107,7 @@\n \tDQ_XCM_AGG_VAL_SEL_WORD4\n #define DQ_XCM_CORE_SPQ_PROD_CMD \\\n \tDQ_XCM_AGG_VAL_SEL_WORD4\n-#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD            DQ_XCM_AGG_VAL_SEL_WORD5\n+#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD        DQ_XCM_AGG_VAL_SEL_WORD5\n \n /* XCM agg counter flag selection */\n #define DQ_XCM_AGG_FLG_SHIFT_BIT14  0\n@@ -140,22 +140,22 @@\n /*****************/\n \n /* number of TX queues in the QM */\n-#define MAX_QM_TX_QUEUES_K2\t512\n-#define MAX_QM_TX_QUEUES_BB\t448\n-#define MAX_QM_TX_QUEUES\tMAX_QM_TX_QUEUES_K2\n+#define MAX_QM_TX_QUEUES_K2\t\t\t512\n+#define MAX_QM_TX_QUEUES_BB\t\t\t448\n+#define MAX_QM_TX_QUEUES\t\t\tMAX_QM_TX_QUEUES_K2\n \n /* number of Other queues in the QM */\n-#define MAX_QM_OTHER_QUEUES_BB\t64\n-#define MAX_QM_OTHER_QUEUES_K2\t128\n-#define MAX_QM_OTHER_QUEUES\tMAX_QM_OTHER_QUEUES_K2\n+#define MAX_QM_OTHER_QUEUES_BB\t\t64\n+#define MAX_QM_OTHER_QUEUES_K2\t\t128\n+#define MAX_QM_OTHER_QUEUES\t\t\tMAX_QM_OTHER_QUEUES_K2\n \n /* number of queues in a PF queue group */\n-#define QM_PF_QUEUE_GROUP_SIZE\t8\n+#define QM_PF_QUEUE_GROUP_SIZE\t\t8\n \n /* base number of Tx PQs in the CM PQ representation.\n  * should be used when storing PQ IDs in CM PQ registers and context\n  */\n-#define CM_TX_PQ_BASE\t0x200\n+#define CM_TX_PQ_BASE               0x200\n \n /* QM registers data */\n #define QM_LINE_CRD_REG_WIDTH\t\t16\n@@ -164,7 +164,7 @@\n #define QM_BYTE_CRD_REG_SIGN_BIT\t(1 << (QM_BYTE_CRD_REG_WIDTH - 1))\n #define QM_WFQ_CRD_REG_WIDTH\t\t32\n #define QM_WFQ_CRD_REG_SIGN_BIT\t\t(1 << (QM_WFQ_CRD_REG_WIDTH - 1))\n-#define QM_RL_CRD_REG_WIDTH\t\t32\n+#define QM_RL_CRD_REG_WIDTH\t\t\t32\n #define QM_RL_CRD_REG_SIGN_BIT\t\t(1 << (QM_RL_CRD_REG_WIDTH - 1))\n \n /*****************/\n@@ -185,100 +185,100 @@\n /* IGU CONSTANTS */\n /*****************/\n \n-#define MAX_SB_PER_PATH_K2\t(368)\n-#define MAX_SB_PER_PATH_BB\t(288)\n+#define MAX_SB_PER_PATH_K2\t\t\t\t(368)\n+#define MAX_SB_PER_PATH_BB\t\t\t\t(288)\n #define MAX_TOT_SB_PER_PATH \\\n \tMAX_SB_PER_PATH_K2\n \n-#define MAX_SB_PER_PF_MIMD\t129\n-#define MAX_SB_PER_PF_SIMD\t64\n-#define MAX_SB_PER_VF\t\t64\n+#define MAX_SB_PER_PF_MIMD\t\t\t\t129\n+#define MAX_SB_PER_PF_SIMD\t\t\t\t64\n+#define MAX_SB_PER_VF\t\t\t\t\t64\n \n /* Memory addresses on the BAR for the IGU Sub Block */\n-#define IGU_MEM_BASE\t\t\t0x0000\n+#define IGU_MEM_BASE\t\t\t\t\t0x0000\n \n-#define IGU_MEM_MSIX_BASE\t\t0x0000\n-#define IGU_MEM_MSIX_UPPER\t\t0x0101\n-#define IGU_MEM_MSIX_RESERVED_UPPER\t0x01ff\n+#define IGU_MEM_MSIX_BASE\t\t\t\t0x0000\n+#define IGU_MEM_MSIX_UPPER\t\t\t\t0x0101\n+#define IGU_MEM_MSIX_RESERVED_UPPER\t\t\t0x01ff\n \n-#define IGU_MEM_PBA_MSIX_BASE\t\t0x0200\n-#define IGU_MEM_PBA_MSIX_UPPER\t\t0x0202\n-#define IGU_MEM_PBA_MSIX_RESERVED_UPPER\t0x03ff\n+#define IGU_MEM_PBA_MSIX_BASE\t\t\t\t0x0200\n+#define IGU_MEM_PBA_MSIX_UPPER\t\t\t\t0x0202\n+#define IGU_MEM_PBA_MSIX_RESERVED_UPPER\t\t\t0x03ff\n \n-#define IGU_CMD_INT_ACK_BASE\t\t0x0400\n+#define IGU_CMD_INT_ACK_BASE\t\t\t\t0x0400\n #define IGU_CMD_INT_ACK_UPPER\t\t(IGU_CMD_INT_ACK_BASE +\t\\\n \t\t\t\t\t MAX_TOT_SB_PER_PATH -\t\\\n \t\t\t\t\t 1)\n-#define IGU_CMD_INT_ACK_RESERVED_UPPER\t0x05ff\n+#define IGU_CMD_INT_ACK_RESERVED_UPPER\t\t\t0x05ff\n \n-#define IGU_CMD_ATTN_BIT_UPD_UPPER\t0x05f0\n-#define IGU_CMD_ATTN_BIT_SET_UPPER\t0x05f1\n-#define IGU_CMD_ATTN_BIT_CLR_UPPER\t0x05f2\n+#define IGU_CMD_ATTN_BIT_UPD_UPPER\t\t\t0x05f0\n+#define IGU_CMD_ATTN_BIT_SET_UPPER\t\t\t0x05f1\n+#define IGU_CMD_ATTN_BIT_CLR_UPPER\t\t\t0x05f2\n \n-#define IGU_REG_SISR_MDPC_WMASK_UPPER\t\t0x05f3\n-#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER\t0x05f4\n-#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER\t0x05f5\n-#define IGU_REG_SISR_MDPC_WOMASK_UPPER\t\t0x05f6\n+#define IGU_REG_SISR_MDPC_WMASK_UPPER\t\t\t0x05f3\n+#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER\t\t0x05f4\n+#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER\t\t0x05f5\n+#define IGU_REG_SISR_MDPC_WOMASK_UPPER\t\t\t0x05f6\n \n-#define IGU_CMD_PROD_UPD_BASE\t\t\t0x0600\n+#define IGU_CMD_PROD_UPD_BASE\t\t\t\t0x0600\n #define IGU_CMD_PROD_UPD_UPPER\t\t\t(IGU_CMD_PROD_UPD_BASE +\\\n \t\t\t\t\t\t MAX_TOT_SB_PER_PATH - \\\n \t\t\t\t\t\t 1)\n-#define IGU_CMD_PROD_UPD_RESERVED_UPPER\t\t0x07ff\n+#define IGU_CMD_PROD_UPD_RESERVED_UPPER\t\t\t0x07ff\n \n /*****************/\n /* PXP CONSTANTS */\n /*****************/\n \n /* PTT and GTT */\n-#define PXP_NUM_PF_WINDOWS\t\t12\n-#define PXP_PER_PF_ENTRY_SIZE\t\t8\n-#define PXP_NUM_GLOBAL_WINDOWS\t\t243\n-#define PXP_GLOBAL_ENTRY_SIZE\t\t4\n-#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH\t4\n-#define PXP_PF_WINDOW_ADMIN_START\t0\n-#define PXP_PF_WINDOW_ADMIN_LENGTH\t0x1000\n+#define PXP_NUM_PF_WINDOWS                                  12\n+#define PXP_PER_PF_ENTRY_SIZE                               8\n+#define PXP_NUM_GLOBAL_WINDOWS                              243\n+#define PXP_GLOBAL_ENTRY_SIZE                               4\n+#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH                     4\n+#define PXP_PF_WINDOW_ADMIN_START                           0\n+#define PXP_PF_WINDOW_ADMIN_LENGTH                          0x1000\n #define PXP_PF_WINDOW_ADMIN_END\t\t(PXP_PF_WINDOW_ADMIN_START + \\\n \t\t\t\t\t PXP_PF_WINDOW_ADMIN_LENGTH - 1)\n-#define PXP_PF_WINDOW_ADMIN_PER_PF_START\t0\n+#define PXP_PF_WINDOW_ADMIN_PER_PF_START                    0\n #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH\t(PXP_NUM_PF_WINDOWS * \\\n \t\t\t\t\t\t PXP_PER_PF_ENTRY_SIZE)\n #define PXP_PF_WINDOW_ADMIN_PER_PF_END\t(PXP_PF_WINDOW_ADMIN_PER_PF_START + \\\n-\t\t\t\t\t PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)\n-#define PXP_PF_WINDOW_ADMIN_GLOBAL_START\t0x200\n+\t PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)\n+#define PXP_PF_WINDOW_ADMIN_GLOBAL_START                    0x200\n #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH\t(PXP_NUM_GLOBAL_WINDOWS * \\\n \t\t\t\t\t\t PXP_GLOBAL_ENTRY_SIZE)\n-#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \\\n-\t\t(PXP_PF_WINDOW_ADMIN_GLOBAL_START + \\\n-\t\t PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)\n-#define PXP_PF_GLOBAL_PRETEND_ADDR\t0x1f0\n-#define PXP_PF_ME_OPAQUE_MASK_ADDR\t0xf4\n-#define PXP_PF_ME_OPAQUE_ADDR\t\t0x1f8\n-#define PXP_PF_ME_CONCRETE_ADDR\t\t0x1fc\n-\n-#define PXP_EXTERNAL_BAR_PF_WINDOW_START\t0x1000\n-#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM\t\tPXP_NUM_PF_WINDOWS\n-#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE\t0x1000\n-#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \\\n-\t(PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \\\n+#define PXP_PF_WINDOW_ADMIN_GLOBAL_END                      \\\n+\t(PXP_PF_WINDOW_ADMIN_GLOBAL_START +\t\t    \\\n+\t PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)\n+#define PXP_PF_GLOBAL_PRETEND_ADDR                          0x1f0\n+#define PXP_PF_ME_OPAQUE_MASK_ADDR                          0xf4\n+#define PXP_PF_ME_OPAQUE_ADDR                               0x1f8\n+#define PXP_PF_ME_CONCRETE_ADDR                             0x1fc\n+\n+#define PXP_EXTERNAL_BAR_PF_WINDOW_START                    0x1000\n+#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM                      PXP_NUM_PF_WINDOWS\n+#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE              0x1000\n+#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH                   \\\n+\t(PXP_EXTERNAL_BAR_PF_WINDOW_NUM *\t\t    \\\n \t PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)\n-#define PXP_EXTERNAL_BAR_PF_WINDOW_END \\\n-\t(PXP_EXTERNAL_BAR_PF_WINDOW_START + \\\n+#define PXP_EXTERNAL_BAR_PF_WINDOW_END                      \\\n+\t(PXP_EXTERNAL_BAR_PF_WINDOW_START +\t\t    \\\n \t PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)\n \n-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \\\n+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START                \\\n \t(PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)\n #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM\t\tPXP_NUM_GLOBAL_WINDOWS\n-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE\t0x1000\n-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \\\n-\t(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \\\n+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE          0x1000\n+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH               \\\n+\t(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM *\t\t    \\\n \t PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)\n-#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \\\n-\t(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \\\n+#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END                  \\\n+\t(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START +\t\t    \\\n \t PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)\n \n-#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN\t12\n-#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER\t1024\n+#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN          12\n+#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER         1024\n \n /* ILT Records */\n #define PXP_NUM_ILT_RECORDS_BB 7600\n@@ -301,10 +301,10 @@\n \n /* Async data KCQ CQE */\n struct async_data {\n-\t__le32\tcid;\n-\t__le16\titid;\n-\tu8\terror_code;\n-\tu8\tfw_debug_param;\n+\t__le32 cid;\n+\t__le16 itid;\n+\tu8 error_code;\n+\tu8 fw_debug_param;\n };\n \n struct regpair {\n@@ -359,12 +359,12 @@ struct event_ring_entry {\n \t__le16\t\t\treserved0;\n \t__le16\t\t\techo;\n \tu8\t\t\tfw_return_code;\n-\tu8\t\t\tflags;\n+\tu8 flags;\n #define EVENT_RING_ENTRY_ASYNC_MASK      0x1\n #define EVENT_RING_ENTRY_ASYNC_SHIFT     0\n #define EVENT_RING_ENTRY_RESERVED1_MASK  0x7F\n #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1\n-\tunion event_ring_data\tdata;\n+\tunion event_ring_data data;\n };\n \n /* Multi function mode */\n@@ -444,8 +444,8 @@ struct core_db_data {\n #define CORE_DB_DATA_RESERVED_SHIFT    5\n #define CORE_DB_DATA_AGG_VAL_SEL_MASK  0x3\n #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6\n-\tu8\tagg_flags;\n-\t__le16\tspq_prod;\n+\tu8 agg_flags;\n+\t__le16 spq_prod;\n };\n \n /* Enum of doorbell aggregative command selection */\n@@ -479,10 +479,10 @@ struct db_legacy_addr {\n \n /* Igu interrupt command */\n enum igu_int_cmd {\n-\tIGU_INT_ENABLE\t= 0,\n+\tIGU_INT_ENABLE = 0,\n \tIGU_INT_DISABLE = 1,\n-\tIGU_INT_NOP\t= 2,\n-\tIGU_INT_NOP2\t= 3,\n+\tIGU_INT_NOP = 2,\n+\tIGU_INT_NOP2 = 3,\n \tMAX_IGU_INT_CMD\n };\n \n@@ -508,8 +508,8 @@ struct igu_prod_cons_update {\n \n /* Igu segments access for default status block only */\n enum igu_seg_access {\n-\tIGU_SEG_ACCESS_REG\t= 0,\n-\tIGU_SEG_ACCESS_ATTN\t= 1,\n+\tIGU_SEG_ACCESS_REG = 0,\n+\tIGU_SEG_ACCESS_ATTN = 1,\n \tMAX_IGU_SEG_ACCESS\n };\n \n@@ -574,13 +574,13 @@ struct pxp_pretend_concrete_fid {\n \n union pxp_pretend_fid {\n \tstruct pxp_pretend_concrete_fid concrete_fid;\n-\t__le16\t\t\t\topaque_fid;\n+\t__le16 opaque_fid;\n };\n \n /* Pxp Pretend Command Register. */\n struct pxp_pretend_cmd {\n-\tunion pxp_pretend_fid\tfid;\n-\t__le16\t\t\tcontrol;\n+\tunion pxp_pretend_fid fid;\n+\t__le16 control;\n #define PXP_PRETEND_CMD_PATH_MASK              0x1\n #define PXP_PRETEND_CMD_PATH_SHIFT             0\n #define PXP_PRETEND_CMD_USE_PORT_MASK          0x1\n@@ -603,30 +603,30 @@ struct pxp_pretend_cmd {\n \n /* PTT Record in PXP Admin Window. */\n struct pxp_ptt_entry {\n-\t__le32\t\t\toffset;\n+\t__le32 offset;\n #define PXP_PTT_ENTRY_OFFSET_MASK     0x7FFFFF\n #define PXP_PTT_ENTRY_OFFSET_SHIFT    0\n #define PXP_PTT_ENTRY_RESERVED0_MASK  0x1FF\n #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23\n-\tstruct pxp_pretend_cmd\tpretend;\n+\tstruct pxp_pretend_cmd pretend;\n };\n \n /* RSS hash type */\n enum rss_hash_type {\n-\tRSS_HASH_TYPE_DEFAULT\t= 0,\n-\tRSS_HASH_TYPE_IPV4\t= 1,\n-\tRSS_HASH_TYPE_TCP_IPV4\t= 2,\n-\tRSS_HASH_TYPE_IPV6\t= 3,\n-\tRSS_HASH_TYPE_TCP_IPV6\t= 4,\n-\tRSS_HASH_TYPE_UDP_IPV4\t= 5,\n-\tRSS_HASH_TYPE_UDP_IPV6\t= 6,\n+\tRSS_HASH_TYPE_DEFAULT = 0,\n+\tRSS_HASH_TYPE_IPV4 = 1,\n+\tRSS_HASH_TYPE_TCP_IPV4 = 2,\n+\tRSS_HASH_TYPE_IPV6 = 3,\n+\tRSS_HASH_TYPE_TCP_IPV6 = 4,\n+\tRSS_HASH_TYPE_UDP_IPV4 = 5,\n+\tRSS_HASH_TYPE_UDP_IPV6 = 6,\n \tMAX_RSS_HASH_TYPE\n };\n \n /* status block structure */\n struct status_block {\n-\t__le16\tpi_array[PIS_PER_SB];\n-\t__le32\tsb_num;\n+\t__le16 pi_array[PIS_PER_SB];\n+\t__le32 sb_num;\n #define STATUS_BLOCK_SB_NUM_MASK      0x1FF\n #define STATUS_BLOCK_SB_NUM_SHIFT     0\n #define STATUS_BLOCK_ZERO_PAD_MASK    0x7F\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex db72f03..c83b22b 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -21,7 +21,7 @@\n #define VER_SIZE 16\n /* @DPDK ARRAY_DECL */\n #define ECORE_WFQ_UNIT\t100\n-#include \"../qede_logs.h\"\t/* @DPDK */\n+#include \"../qede_logs.h\" /* @DPDK */\n \n /* Constants */\n #define ECORE_WID_SIZE\t\t(1024)\n@@ -77,7 +77,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)\n {\n \tu32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |\n-\t    (cid * ECORE_PF_DEMS_SIZE);\n+\t\t      (cid * ECORE_PF_DEMS_SIZE);\n \n \treturn db_addr;\n }\n@@ -105,10 +105,10 @@ static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)\n \n #ifndef __EXTRACT__LINUX__\n enum DP_LEVEL {\n-\tECORE_LEVEL_VERBOSE = 0x0,\n-\tECORE_LEVEL_INFO = 0x1,\n-\tECORE_LEVEL_NOTICE = 0x2,\n-\tECORE_LEVEL_ERR = 0x3,\n+\tECORE_LEVEL_VERBOSE\t= 0x0,\n+\tECORE_LEVEL_INFO\t= 0x1,\n+\tECORE_LEVEL_NOTICE\t= 0x2,\n+\tECORE_LEVEL_ERR\t\t= 0x3,\n };\n \n #define ECORE_LOG_LEVEL_SHIFT\t(30)\n@@ -118,31 +118,31 @@ enum DP_LEVEL {\n \n enum DP_MODULE {\n #ifndef LINUX_REMOVE\n-\tECORE_MSG_DRV = 0x0001,\n-\tECORE_MSG_PROBE = 0x0002,\n-\tECORE_MSG_LINK = 0x0004,\n-\tECORE_MSG_TIMER = 0x0008,\n-\tECORE_MSG_IFDOWN = 0x0010,\n-\tECORE_MSG_IFUP = 0x0020,\n-\tECORE_MSG_RX_ERR = 0x0040,\n-\tECORE_MSG_TX_ERR = 0x0080,\n-\tECORE_MSG_TX_QUEUED = 0x0100,\n-\tECORE_MSG_INTR = 0x0200,\n-\tECORE_MSG_TX_DONE = 0x0400,\n-\tECORE_MSG_RX_STATUS = 0x0800,\n-\tECORE_MSG_PKTDATA = 0x1000,\n-\tECORE_MSG_HW = 0x2000,\n-\tECORE_MSG_WOL = 0x4000,\n+\tECORE_MSG_DRV\t\t= 0x0001,\n+\tECORE_MSG_PROBE\t\t= 0x0002,\n+\tECORE_MSG_LINK\t\t= 0x0004,\n+\tECORE_MSG_TIMER\t\t= 0x0008,\n+\tECORE_MSG_IFDOWN\t= 0x0010,\n+\tECORE_MSG_IFUP\t\t= 0x0020,\n+\tECORE_MSG_RX_ERR\t= 0x0040,\n+\tECORE_MSG_TX_ERR\t= 0x0080,\n+\tECORE_MSG_TX_QUEUED\t= 0x0100,\n+\tECORE_MSG_INTR\t\t= 0x0200,\n+\tECORE_MSG_TX_DONE\t= 0x0400,\n+\tECORE_MSG_RX_STATUS\t= 0x0800,\n+\tECORE_MSG_PKTDATA\t= 0x1000,\n+\tECORE_MSG_HW\t\t= 0x2000,\n+\tECORE_MSG_WOL\t\t= 0x4000,\n #endif\n-\tECORE_MSG_SPQ = 0x10000,\n-\tECORE_MSG_STATS = 0x20000,\n-\tECORE_MSG_DCB = 0x40000,\n-\tECORE_MSG_IOV = 0x80000,\n-\tECORE_MSG_SP = 0x100000,\n-\tECORE_MSG_STORAGE = 0x200000,\n-\tECORE_MSG_CXT = 0x800000,\n-\tECORE_MSG_ILT = 0x2000000,\n-\tECORE_MSG_DEBUG = 0x8000000,\n+\tECORE_MSG_SPQ\t\t= 0x10000,\n+\tECORE_MSG_STATS\t\t= 0x20000,\n+\tECORE_MSG_DCB\t\t= 0x40000,\n+\tECORE_MSG_IOV\t\t= 0x80000,\n+\tECORE_MSG_SP\t\t= 0x100000,\n+\tECORE_MSG_STORAGE\t= 0x200000,\n+\tECORE_MSG_CXT\t\t= 0x800000,\n+\tECORE_MSG_ILT\t\t= 0x2000000,\n+\tECORE_MSG_DEBUG         = 0x8000000,\n \t/* to be added...up to 0x8000000 */\n };\n #endif\n@@ -166,8 +166,8 @@ struct ecore_mcp_info;\n struct ecore_dcbx_info;\n \n struct ecore_rt_data {\n-\tu32 *init_val;\n-\tbool *b_valid;\n+\tu32\t*init_val;\n+\tbool\t*b_valid;\n };\n \n enum ecore_tunn_mode {\n@@ -188,31 +188,31 @@ enum ecore_tunn_clss {\n \n struct ecore_tunn_start_params {\n \tunsigned long tunn_mode;\n-\tu16 vxlan_udp_port;\n-\tu16 geneve_udp_port;\n-\tu8 update_vxlan_udp_port;\n-\tu8 update_geneve_udp_port;\n-\tu8 tunn_clss_vxlan;\n-\tu8 tunn_clss_l2geneve;\n-\tu8 tunn_clss_ipgeneve;\n-\tu8 tunn_clss_l2gre;\n-\tu8 tunn_clss_ipgre;\n+\tu16\tvxlan_udp_port;\n+\tu16\tgeneve_udp_port;\n+\tu8\tupdate_vxlan_udp_port;\n+\tu8\tupdate_geneve_udp_port;\n+\tu8\ttunn_clss_vxlan;\n+\tu8\ttunn_clss_l2geneve;\n+\tu8\ttunn_clss_ipgeneve;\n+\tu8\ttunn_clss_l2gre;\n+\tu8\ttunn_clss_ipgre;\n };\n \n struct ecore_tunn_update_params {\n \tunsigned long tunn_mode_update_mask;\n \tunsigned long tunn_mode;\n-\tu16 vxlan_udp_port;\n-\tu16 geneve_udp_port;\n-\tu8 update_rx_pf_clss;\n-\tu8 update_tx_pf_clss;\n-\tu8 update_vxlan_udp_port;\n-\tu8 update_geneve_udp_port;\n-\tu8 tunn_clss_vxlan;\n-\tu8 tunn_clss_l2geneve;\n-\tu8 tunn_clss_ipgeneve;\n-\tu8 tunn_clss_l2gre;\n-\tu8 tunn_clss_ipgre;\n+\tu16\tvxlan_udp_port;\n+\tu16\tgeneve_udp_port;\n+\tu8\tupdate_rx_pf_clss;\n+\tu8\tupdate_tx_pf_clss;\n+\tu8\tupdate_vxlan_udp_port;\n+\tu8\tupdate_geneve_udp_port;\n+\tu8\ttunn_clss_vxlan;\n+\tu8\ttunn_clss_l2geneve;\n+\tu8\ttunn_clss_ipgeneve;\n+\tu8\ttunn_clss_l2gre;\n+\tu8\ttunn_clss_ipgre;\n };\n \n struct ecore_hw_sriov_info {\n@@ -244,7 +244,7 @@ struct ecore_hw_sriov_info {\n  */\n enum ecore_pci_personality {\n \tECORE_PCI_ETH,\n-\tECORE_PCI_DEFAULT\t/* default in shmem */\n+\tECORE_PCI_DEFAULT /* default in shmem */\n };\n \n /* All VFs are symmetric, all counters are PF + all VFs */\n@@ -322,11 +322,11 @@ struct ecore_hw_info {\n \tu32 resc_num[ECORE_MAX_RESC];\n \tu32 feat_num[ECORE_MAX_FEATURES];\n \n-#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])\n-#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])\n-#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \\\n+\t#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])\n+\t#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])\n+\t#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \\\n \t\t\t\t\t RESC_NUM(_p_hwfn, resc))\n-#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])\n+\t#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])\n \n \tu8 num_tc;\n \tu8 ooo_tc;\n@@ -346,18 +346,18 @@ struct ecore_hw_info {\n \tu8 max_chains_per_vf;\n \n \tu32 port_mode;\n-\tu32 hw_mode;\n+\tu32\thw_mode;\n \tunsigned long device_capabilities;\n };\n \n struct ecore_hw_cid_data {\n-\tu32 cid;\n-\tbool b_cid_allocated;\n-\tu8 vfid;\t\t/* 1-based; 0 signals this is for a PF */\n+\tu32\tcid;\n+\tbool\tb_cid_allocated;\n+\tu8\tvfid; /* 1-based; 0 signals this is for a PF */\n \n \t/* Additional identifiers */\n-\tu16 opaque_fid;\n-\tu8 vport_id;\n+\tu16\topaque_fid;\n+\tu8\tvport_id;\n };\n \n /* maximun size of read/write commands (HW limit) */\n@@ -365,7 +365,7 @@ struct ecore_hw_cid_data {\n \n struct ecore_dmae_info {\n \t/* Mutex for synchronizing access to functions */\n-\tosal_mutex_t mutex;\n+\tosal_mutex_t\tmutex;\n \n \tu8 channel;\n \n@@ -389,33 +389,33 @@ struct ecore_dmae_info {\n };\n \n struct ecore_wfq_data {\n-\tu32 default_min_speed;\t/* When wfq feature is not configured */\n-\tu32 min_speed;\t\t/* when feature is configured for any 1 vport */\n+\tu32 default_min_speed; /* When wfq feature is not configured */\n+\tu32 min_speed; /* when feature is configured for any 1 vport */\n \tbool configured;\n };\n \n struct ecore_qm_info {\n-\tstruct init_qm_pq_params *qm_pq_params;\n+\tstruct init_qm_pq_params    *qm_pq_params;\n \tstruct init_qm_vport_params *qm_vport_params;\n-\tstruct init_qm_port_params *qm_port_params;\n-\tu16 start_pq;\n-\tu8 start_vport;\n-\tu8 pure_lb_pq;\n-\tu8 offload_pq;\n-\tu8 pure_ack_pq;\n-\tu8 ooo_pq;\n-\tu8 vf_queues_offset;\n-\tu16 num_pqs;\n-\tu16 num_vf_pqs;\n-\tu8 num_vports;\n-\tu8 max_phys_tcs_per_port;\n-\tbool pf_rl_en;\n-\tbool pf_wfq_en;\n-\tbool vport_rl_en;\n-\tbool vport_wfq_en;\n-\tu8 pf_wfq;\n-\tu32 pf_rl;\n-\tstruct ecore_wfq_data *wfq_data;\n+\tstruct init_qm_port_params  *qm_port_params;\n+\tu16\t\t\tstart_pq;\n+\tu8\t\t\tstart_vport;\n+\tu8\t\t\tpure_lb_pq;\n+\tu8\t\t\toffload_pq;\n+\tu8\t\t\tpure_ack_pq;\n+\tu8\t\t\tooo_pq;\n+\tu8\t\t\tvf_queues_offset;\n+\tu16\t\t\tnum_pqs;\n+\tu16\t\t\tnum_vf_pqs;\n+\tu8\t\t\tnum_vports;\n+\tu8\t\t\tmax_phys_tcs_per_port;\n+\tbool\t\t\tpf_rl_en;\n+\tbool\t\t\tpf_wfq_en;\n+\tbool\t\t\tvport_rl_en;\n+\tbool\t\t\tvport_wfq_en;\n+\tu8\t\t\tpf_wfq;\n+\tu32\t\t\tpf_rl;\n+\tstruct ecore_wfq_data\t*wfq_data;\n };\n \n struct storm_stats {\n@@ -437,106 +437,106 @@ struct ecore_fw_data {\n };\n \n struct ecore_hwfn {\n-\tstruct ecore_dev *p_dev;\n-\tu8 my_id;\t\t/* ID inside the PF */\n+\tstruct ecore_dev\t\t*p_dev;\n+\tu8\t\t\t\tmy_id;\t\t/* ID inside the PF */\n #define IS_LEAD_HWFN(edev)\t\t(!((edev)->my_id))\n-\tu8 rel_pf_id;\t\t/* Relative to engine */\n-\tu8 abs_pf_id;\n-#define ECORE_PATH_ID(_p_hwfn) \\\n+\tu8\t\t\t\trel_pf_id;\t/* Relative to engine*/\n+\tu8\t\t\t\tabs_pf_id;\n+\t#define ECORE_PATH_ID(_p_hwfn) \\\n \t\t(ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))\n-\tu8 port_id;\n-\tbool b_active;\n+\tu8\t\t\t\tport_id;\n+\tbool\t\t\t\tb_active;\n \n-\tu32 dp_module;\n-\tu8 dp_level;\n-\tchar name[NAME_SIZE];\n-\tvoid *dp_ctx;\n+\tu32\t\t\t\tdp_module;\n+\tu8\t\t\t\tdp_level;\n+\tchar\t\t\t\tname[NAME_SIZE];\n+\tvoid                            *dp_ctx;\n \n-\tbool first_on_engine;\n-\tbool hw_init_done;\n+\tbool\t\t\t\tfirst_on_engine;\n+\tbool\t\t\t\thw_init_done;\n \n-\tu8 num_funcs_on_engine;\n+\tu8\t\t\t\tnum_funcs_on_engine;\n \n \t/* BAR access */\n-\tvoid OSAL_IOMEM *regview;\n-\tvoid OSAL_IOMEM *doorbells;\n-\tu64 db_phys_addr;\n-\tunsigned long db_size;\n+\tvoid OSAL_IOMEM\t\t\t*regview;\n+\tvoid OSAL_IOMEM\t\t\t*doorbells;\n+\tu64\t\t\t\tdb_phys_addr;\n+\tunsigned long\t\t\tdb_size;\n \n \t/* PTT pool */\n-\tstruct ecore_ptt_pool *p_ptt_pool;\n+\tstruct ecore_ptt_pool\t\t*p_ptt_pool;\n \n \t/* HW info */\n-\tstruct ecore_hw_info hw_info;\n+\tstruct ecore_hw_info\t\thw_info;\n \n \t/* rt_array (for init-tool) */\n-\tstruct ecore_rt_data rt_data;\n+\tstruct ecore_rt_data\t\trt_data;\n \n \t/* SPQ */\n-\tstruct ecore_spq *p_spq;\n+\tstruct ecore_spq\t\t*p_spq;\n \n \t/* EQ */\n-\tstruct ecore_eq *p_eq;\n+\tstruct ecore_eq\t\t\t*p_eq;\n \n-\t/* Consolidate Q */\n-\tstruct ecore_consq *p_consq;\n+\t/* Consolidate Q*/\n+\tstruct ecore_consq\t\t*p_consq;\n \n \t/* Slow-Path definitions */\n-\tosal_dpc_t sp_dpc;\n-\tbool b_sp_dpc_enabled;\n+\tosal_dpc_t\t\t\tsp_dpc;\n+\tbool\t\t\t\tb_sp_dpc_enabled;\n \n-\tstruct ecore_ptt *p_main_ptt;\n-\tstruct ecore_ptt *p_dpc_ptt;\n+\tstruct ecore_ptt\t\t*p_main_ptt;\n+\tstruct ecore_ptt\t\t*p_dpc_ptt;\n \n-\tstruct ecore_sb_sp_info *p_sp_sb;\n-\tstruct ecore_sb_attn_info *p_sb_attn;\n+\tstruct ecore_sb_sp_info\t\t*p_sp_sb;\n+\tstruct ecore_sb_attn_info\t*p_sb_attn;\n \n \t/* Protocol related */\n-\tstruct ecore_ooo_info *p_ooo_info;\n-\tstruct ecore_pf_params pf_params;\n+\tstruct ecore_ooo_info\t\t*p_ooo_info;\n+\tstruct ecore_pf_params\t\tpf_params;\n \n \t/* Array of sb_info of all status blocks */\n-\tstruct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];\n-\tu16 num_sbs;\n+\tstruct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];\n+\tu16                             num_sbs;\n \n-\tstruct ecore_cxt_mngr *p_cxt_mngr;\n+\tstruct ecore_cxt_mngr\t\t*p_cxt_mngr;\n \n-\t/* Flag indicating whether interrupts are enabled or not */\n-\tbool b_int_enabled;\n-\tbool b_int_requested;\n+\t/* Flag indicating whether interrupts are enabled or not*/\n+\tbool\t\t\t\tb_int_enabled;\n+\tbool\t\t\t\tb_int_requested;\n \n \t/* True if the driver requests for the link */\n-\tbool b_drv_link_init;\n+\tbool\t\t\t\tb_drv_link_init;\n \n-\tstruct ecore_vf_iov *vf_iov_info;\n-\tstruct ecore_pf_iov *pf_iov_info;\n-\tstruct ecore_mcp_info *mcp_info;\n-\tstruct ecore_dcbx_info *p_dcbx_info;\n+\tstruct ecore_vf_iov\t\t*vf_iov_info;\n+\tstruct ecore_pf_iov\t\t*pf_iov_info;\n+\tstruct ecore_mcp_info\t\t*mcp_info;\n+\tstruct ecore_dcbx_info\t\t*p_dcbx_info;\n \n-\tstruct ecore_hw_cid_data *p_tx_cids;\n-\tstruct ecore_hw_cid_data *p_rx_cids;\n+\tstruct ecore_hw_cid_data\t*p_tx_cids;\n+\tstruct ecore_hw_cid_data\t*p_rx_cids;\n \n-\tstruct ecore_dmae_info dmae_info;\n+\tstruct ecore_dmae_info\t\tdmae_info;\n \n \t/* QM init */\n-\tstruct ecore_qm_info qm_info;\n+\tstruct ecore_qm_info\t\tqm_info;\n \n \t/* Buffer for unzipping firmware data */\n #ifdef CONFIG_ECORE_ZIPPED_FW\n \tvoid *unzip_buf;\n #endif\n \n-\tstruct dbg_tools_data dbg_info;\n+\tstruct dbg_tools_data\t\tdbg_info;\n \n-\tstruct z_stream_s *stream;\n+\tstruct z_stream_s\t\t*stream;\n \n \t/* PWM region specific data */\n-\tu32 dpi_size;\n-\tu32 dpi_count;\n-\tu32 dpi_start_offset;\t/* this is used to\n-\t\t\t\t * calculate th\n-\t\t\t\t * doorbell address\n-\t\t\t\t */\n+\tu32\t\t\t\tdpi_size;\n+\tu32\t\t\t\tdpi_count;\n+\tu32\t\t\t\tdpi_start_offset; /* this is used to\n+\t\t\t\t\t\t\t   * calculate th\n+\t\t\t\t\t\t\t   * doorbell address\n+\t\t\t\t\t\t\t   */\n };\n \n #ifndef __EXTRACT__LINUX__\n@@ -548,12 +548,12 @@ enum ecore_mf_mode {\n #endif\n \n struct ecore_dev {\n-\tu32 dp_module;\n-\tu8 dp_level;\n-\tchar name[NAME_SIZE];\n-\tvoid *dp_ctx;\n+\tu32\t\t\t\tdp_module;\n+\tu8\t\t\t\tdp_level;\n+\tchar\t\t\t\tname[NAME_SIZE];\n+\tvoid                            *dp_ctx;\n \n-\tu8 type;\n+\tu8\t\t\t\ttype;\n #define ECORE_DEV_TYPE_BB\t(0 << 0)\n #define ECORE_DEV_TYPE_AH\t(1 << 0)\n /* Translate type/revision combo into the proper conditions */\n@@ -571,112 +571,112 @@ struct ecore_dev {\n \tu16 vendor_id;\n \tu16 device_id;\n \n-\tu16 chip_num;\n-#define CHIP_NUM_MASK\t\t\t0xffff\n-#define CHIP_NUM_SHIFT\t\t\t16\n+\tu16\t\t\t\tchip_num;\n+\t#define CHIP_NUM_MASK\t\t\t0xffff\n+\t#define CHIP_NUM_SHIFT\t\t\t16\n \n-\tu16 chip_rev;\n-#define CHIP_REV_MASK\t\t\t0xf\n-#define CHIP_REV_SHIFT\t\t\t12\n+\tu16\t\t\t\tchip_rev;\n+\t#define CHIP_REV_MASK\t\t\t0xf\n+\t#define CHIP_REV_SHIFT\t\t\t12\n #ifndef ASIC_ONLY\n-#define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)\n-#define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)\n-#define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)\n-#define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \\\n+\t#define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)\n+\t#define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)\n+\t#define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)\n+\t#define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \\\n \t\t\t\t\t  CHIP_REV_IS_EMUL_B0(_p_dev))\n-#define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)\n-#define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)\n-#define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \\\n+\t#define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)\n+\t#define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)\n+\t#define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \\\n \t\t\t\t\t  CHIP_REV_IS_FPGA_B0(_p_dev))\n-#define CHIP_REV_IS_SLOW(_p_dev) \\\n+\t#define CHIP_REV_IS_SLOW(_p_dev) \\\n \t\t(CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))\n-#define CHIP_REV_IS_A0(_p_dev) \\\n+\t#define CHIP_REV_IS_A0(_p_dev) \\\n \t\t(CHIP_REV_IS_EMUL_A0(_p_dev) || \\\n \t\t CHIP_REV_IS_FPGA_A0(_p_dev) || \\\n \t\t !(_p_dev)->chip_rev)\n-#define CHIP_REV_IS_B0(_p_dev) \\\n+\t#define CHIP_REV_IS_B0(_p_dev) \\\n \t\t(CHIP_REV_IS_EMUL_B0(_p_dev) || \\\n \t\t CHIP_REV_IS_FPGA_B0(_p_dev) || \\\n \t\t (_p_dev)->chip_rev == 1)\n #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))\n #else\n-#define CHIP_REV_IS_A0(_p_dev)\t(!(_p_dev)->chip_rev)\n-#define CHIP_REV_IS_B0(_p_dev)\t((_p_dev)->chip_rev == 1)\n+\t#define CHIP_REV_IS_A0(_p_dev)\t(!(_p_dev)->chip_rev)\n+\t#define CHIP_REV_IS_B0(_p_dev)\t((_p_dev)->chip_rev == 1)\n #endif\n \n-\tu16 chip_metal;\n-#define CHIP_METAL_MASK\t\t\t0xff\n-#define CHIP_METAL_SHIFT\t\t4\n+\tu16\t\t\t\tchip_metal;\n+\t#define CHIP_METAL_MASK\t\t\t0xff\n+\t#define CHIP_METAL_SHIFT\t\t4\n \n-\tu16 chip_bond_id;\n-#define CHIP_BOND_ID_MASK\t\t0xf\n-#define CHIP_BOND_ID_SHIFT\t\t0\n+\tu16\t\t\t\tchip_bond_id;\n+\t#define CHIP_BOND_ID_MASK\t\t0xf\n+\t#define CHIP_BOND_ID_SHIFT\t\t0\n \n-\tu8 num_engines;\n-\tu8 num_ports_in_engines;\n-\tu8 num_funcs_in_port;\n+\tu8\t\t\t\tnum_engines;\n+\tu8\t\t\t\tnum_ports_in_engines;\n+\tu8\t\t\t\tnum_funcs_in_port;\n \n-\tu8 path_id;\n-\tenum ecore_mf_mode mf_mode;\n-#define IS_MF_DEFAULT(_p_hwfn) \\\n-\t\t(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)\n+\tu8\t\t\t\tpath_id;\n+\tenum ecore_mf_mode\t\tmf_mode;\n+\t#define IS_MF_DEFAULT(_p_hwfn)\t\\\n+\t\t\t(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)\n #define IS_MF_SI(_p_hwfn)\t(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)\n #define IS_MF_SD(_p_hwfn)\t(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)\n \n-\tint pcie_width;\n-\tint pcie_speed;\n+\tint\t\t\t\tpcie_width;\n+\tint\t\t\t\tpcie_speed;\n \tu8 ver_str[VER_SIZE];\n \t/* Add MF related configuration */\n-\tu8 mcp_rev;\n-\tu8 boot_mode;\n+\tu8\t\t\t\tmcp_rev;\n+\tu8\t\t\t\tboot_mode;\n \n-\tu8 wol;\n+\tu8\t\t\t\twol;\n \n-\tu32 int_mode;\n-\tenum ecore_coalescing_mode int_coalescing_mode;\n+\tu32\t\t\t\tint_mode;\n+\tenum ecore_coalescing_mode\tint_coalescing_mode;\n \tu8 rx_coalesce_usecs;\n \tu8 tx_coalesce_usecs;\n \n \t/* Start Bar offset of first hwfn */\n-\tvoid OSAL_IOMEM *regview;\n-\tvoid OSAL_IOMEM *doorbells;\n-\tu64 db_phys_addr;\n-\tunsigned long db_size;\n+\tvoid OSAL_IOMEM\t\t\t*regview;\n+\tvoid OSAL_IOMEM\t\t\t*doorbells;\n+\tu64\t\t\t\tdb_phys_addr;\n+\tunsigned long\t\t\tdb_size;\n \n \t/* PCI */\n-\tu8 cache_shift;\n+\tu8\t\t\t\tcache_shift;\n \n \t/* Init */\n-\tconst struct iro *iro_arr;\n-#define IRO (p_hwfn->p_dev->iro_arr)\n+\tconst struct iro\t\t*iro_arr;\n+\t#define IRO (p_hwfn->p_dev->iro_arr)\n \n \t/* HW functions */\n-\tu8 num_hwfns;\n-\tstruct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];\n+\tu8\t\t\t\tnum_hwfns;\n+\tstruct ecore_hwfn\t\thwfns[MAX_HWFNS_PER_DEVICE];\n \n \t/* SRIOV */\n \tstruct ecore_hw_sriov_info sriov_info;\n-\tunsigned long tunn_mode;\n+\tunsigned long\t\t\ttunn_mode;\n #define IS_ECORE_SRIOV(edev)\t\t(!!((edev)->sriov_info.total_vfs))\n-\tbool b_is_vf;\n+\tbool\t\t\t\tb_is_vf;\n \n-\tu32 drv_type;\n+\tu32\t\t\t\tdrv_type;\n \n-\tstruct ecore_eth_stats *reset_stats;\n-\tstruct ecore_fw_data *fw_data;\n+\tstruct ecore_eth_stats\t\t*reset_stats;\n+\tstruct ecore_fw_data\t\t*fw_data;\n \n-\tu32 mcp_nvm_resp;\n+\tu32\t\t\t\tmcp_nvm_resp;\n \n \t/* Recovery */\n-\tbool recov_in_prog;\n+\tbool\t\t\t\trecov_in_prog;\n \n #ifndef ASIC_ONLY\n-\tbool b_is_emul_full;\n+\tbool\t\t\t\tb_is_emul_full;\n #endif\n \n-\tvoid *firmware;\n+\tvoid\t\t\t\t*firmware;\n \n-\tu64 fw_len;\n+\tu64\t\t\t\tfw_len;\n \n };\n \n@@ -707,10 +707,10 @@ struct ecore_dev {\n  * @return OSAL_INLINE u8\n  */\n static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,\n-\t\t\t\t\t       u32 concrete_fid)\n+\t\t\t\t\t  u32 concrete_fid)\n {\n-\tu8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);\n-\tu8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);\n+\tu8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);\n+\tu8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);\n \tu8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);\n \tu8 sw_fid;\n \ndiff --git a/drivers/net/qede/base/ecore_chain.h b/drivers/net/qede/base/ecore_chain.h\nindex c573449..bc18c41 100644\n--- a/drivers/net/qede/base/ecore_chain.h\n+++ b/drivers/net/qede/base/ecore_chain.h\n@@ -129,7 +129,7 @@ struct ecore_chain {\n \t   (1 + ((sizeof(struct ecore_chain_next) - 1) /\t\t\\\n \t   (elem_size))) : 0)\n \n-#define USABLE_ELEMS_PER_PAGE(elem_size, mode)\t\t\t\\\n+#define USABLE_ELEMS_PER_PAGE(elem_size, mode)\t\t\\\n \t((u32)(ELEMS_PER_PAGE(elem_size) -\t\t\t\\\n \tUNUSABLE_ELEMS_PER_PAGE(elem_size, mode)))\n \n@@ -183,7 +183,7 @@ static OSAL_INLINE u16 ecore_chain_get_elem_left(struct ecore_chain *p_chain)\n \t\t     (u32)p_chain->u.chain16.cons_idx);\n \tif (p_chain->mode == ECORE_CHAIN_MODE_NEXT_PTR)\n \t\tused -= p_chain->u.chain16.prod_idx / p_chain->elem_per_page -\n-\t\t    p_chain->u.chain16.cons_idx / p_chain->elem_per_page;\n+\t\t\tp_chain->u.chain16.cons_idx / p_chain->elem_per_page;\n \n \treturn (u16)(p_chain->capacity - used);\n }\n@@ -196,11 +196,11 @@ ecore_chain_get_elem_left_u32(struct ecore_chain *p_chain)\n \tOSAL_ASSERT(is_chain_u32(p_chain));\n \n \tused = (u32)(((u64)ECORE_U32_MAX + 1 +\n-\t\t       (u64)(p_chain->u.chain32.prod_idx)) -\n-\t\t      (u64)p_chain->u.chain32.cons_idx);\n+\t\t      (u64)(p_chain->u.chain32.prod_idx)) -\n+\t\t     (u64)p_chain->u.chain32.cons_idx);\n \tif (p_chain->mode == ECORE_CHAIN_MODE_NEXT_PTR)\n \t\tused -= p_chain->u.chain32.prod_idx / p_chain->elem_per_page -\n-\t\t    p_chain->u.chain32.cons_idx / p_chain->elem_per_page;\n+\t\t\tp_chain->u.chain32.cons_idx / p_chain->elem_per_page;\n \n \treturn p_chain->capacity - used;\n }\n@@ -518,14 +518,14 @@ static OSAL_INLINE void ecore_chain_reset(struct ecore_chain *p_chain)\n \tswitch (p_chain->intended_use) {\n \tcase ECORE_CHAIN_USE_TO_CONSUME_PRODUCE:\n \tcase ECORE_CHAIN_USE_TO_PRODUCE:\n-\t\t/* Do nothing */\n-\t\tbreak;\n+\t\t\t/* Do nothing */\n+\t\t\tbreak;\n \n \tcase ECORE_CHAIN_USE_TO_CONSUME:\n-\t\t/* produce empty elements */\n-\t\tfor (i = 0; i < p_chain->capacity; i++)\n+\t\t\t/* produce empty elements */\n+\t\t\tfor (i = 0; i < p_chain->capacity; i++)\n \t\t\tecore_chain_recycle_consumed(p_chain);\n-\t\tbreak;\n+\t\t\tbreak;\n \t}\n }\n \ndiff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c\nindex 1201c1a..415d1c8 100644\n--- a/drivers/net/qede/base/ecore_cxt.c\n+++ b/drivers/net/qede/base/ecore_cxt.c\n@@ -807,8 +807,8 @@ static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)\n \t\tif (!ilt_clients[i].active)\n \t\t\tcontinue;\n \t\telse\n-\t\t\tsize += (ilt_clients[i].last.val -\n-\t\t\t\tilt_clients[i].first.val + 1);\n+\t\tsize += (ilt_clients[i].last.val -\n+\t\t\t ilt_clients[i].first.val + 1);\n \n \treturn size;\n }\n@@ -1027,8 +1027,8 @@ enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)\n \t\tp_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;\n \n \t/* Initialize task sizes */\n-\tp_mngr->task_type_size[0] = 512;\t/* @DPDK */\n-\tp_mngr->task_type_size[1] = 128;\t/* @DPDK */\n+\tp_mngr->task_type_size[0] = 512; /* @DPDK */\n+\tp_mngr->task_type_size[1] = 128; /* @DPDK */\n \n \tp_mngr->vf_count = p_hwfn->p_dev->sriov_info.total_vfs;\n \t/* Set the cxt mangr pointer priori to further allocations */\n@@ -1383,11 +1383,11 @@ static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)\n \tu32 blk_factor;\n \n \t/* For simplicty  we set the 'block' to be an ILT page */\n-\tSTORE_RT_REG(p_hwfn,\n-\t\t     PSWRQ2_REG_VF_BASE_RT_OFFSET,\n+\t\tSTORE_RT_REG(p_hwfn,\n+\t\t\t     PSWRQ2_REG_VF_BASE_RT_OFFSET,\n \t\t     p_hwfn->hw_info.first_vf_in_pf);\n-\tSTORE_RT_REG(p_hwfn,\n-\t\t     PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,\n+\t\tSTORE_RT_REG(p_hwfn,\n+\t\t\t     PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,\n \t\t     p_hwfn->hw_info.first_vf_in_pf +\n \t\t     p_hwfn->p_dev->sriov_info.total_vfs);\n \ndiff --git a/drivers/net/qede/base/ecore_cxt_api.h b/drivers/net/qede/base/ecore_cxt_api.h\nindex d98dddb..90aff3e 100644\n--- a/drivers/net/qede/base/ecore_cxt_api.h\n+++ b/drivers/net/qede/base/ecore_cxt_api.h\n@@ -12,9 +12,9 @@\n struct ecore_hwfn;\n \n struct ecore_cxt_info {\n-\tvoid *p_cxt;\n-\tu32 iid;\n-\tenum protocol_type type;\n+\tvoid\t\t\t*p_cxt;\n+\tu32\t\t\tiid;\n+\tenum protocol_type\ttype;\n };\n \n #define MAX_TID_BLOCKS\t\t\t512\n@@ -22,7 +22,7 @@ struct ecore_tid_mem {\n \tu32 tid_size;\n \tu32 num_tids_per_block;\n \tu32 waste;\n-\tu8 *blocks[MAX_TID_BLOCKS];\t/* 4K */\n+\tu8 *blocks[MAX_TID_BLOCKS]; /* 4K */\n };\n \n static OSAL_INLINE void *get_task_mem(struct ecore_tid_mem *info, u32 tid)\n@@ -49,7 +49,7 @@ static OSAL_INLINE void *get_task_mem(struct ecore_tid_mem *info, u32 tid)\n *\n * @return enum _ecore_status_t\n */\n-enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,\n+enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn  *p_hwfn,\n \t\t\t\t\t   enum protocol_type type,\n \t\t\t\t\t   u32 *p_cid);\n \ndiff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c\nindex 6a966cb..18843c4 100644\n--- a/drivers/net/qede/base/ecore_dcbx.c\n+++ b/drivers/net/qede/base/ecore_dcbx.c\n@@ -116,8 +116,8 @@ ecore_dcbx_set_pf_tcs(struct ecore_hw_info *p_info,\n \t\tif (personality == ECORE_PCI_ETH)\n \t\t\tp_info->non_offload_tc = tc;\n \t\telse\n-\t\t\tp_info->offload_tc = tc;\n-\t}\n+\t\tp_info->offload_tc = tc;\n+}\n }\n \n void\ndiff --git a/drivers/net/qede/base/ecore_dcbx_api.h b/drivers/net/qede/base/ecore_dcbx_api.h\nindex 7767d48..7cd8ee0 100644\n--- a/drivers/net/qede/base/ecore_dcbx_api.h\n+++ b/drivers/net/qede/base/ecore_dcbx_api.h\n@@ -53,10 +53,10 @@ enum dcbx_protocol_type {\n struct ecore_dcbx_lldp_remote {\n \tu32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];\n \tu32 peer_port_id[LLDP_PORT_ID_STAT_LEN];\n-\tbool enable_rx;\n-\tbool enable_tx;\n-\tu32 tx_interval;\n-\tu32 max_credit;\n+\tbool\tenable_rx;\n+\tbool\tenable_tx;\n+\tu32     tx_interval;\n+\tu32     max_credit;\n };\n \n struct ecore_dcbx_lldp_local {\n@@ -65,17 +65,17 @@ struct ecore_dcbx_lldp_local {\n };\n \n struct ecore_dcbx_app_prio {\n-\tu8 eth;\n+\tu8\teth;\n };\n \n struct ecore_dcbx_params {\n \tu32 app_bitmap[DCBX_MAX_APP_PROTOCOL];\n-\tu16 num_app_entries;\n-\tbool app_willing;\n-\tbool app_valid;\n-\tbool ets_willing;\n-\tbool ets_enabled;\n-\tbool valid;\t\t/* Indicate validity of params */\n+\tu16\tnum_app_entries;\n+\tbool\tapp_willing;\n+\tbool\tapp_valid;\n+\tbool\tets_willing;\n+\tbool\tets_enabled;\n+\tbool\tvalid;          /* Indicate validity of params */\n \tu32 ets_pri_tc_tbl[1];\n \tu32 ets_tc_bw_tbl[2];\n \tu32 ets_tc_tsa_tbl[2];\n@@ -83,7 +83,7 @@ struct ecore_dcbx_params {\n \tbool pfc_enabled;\n \tu32 pfc_bitmap;\n \tu8 max_pfc_tc;\n-\tu8 max_ets_tc;\n+\tu8\tmax_ets_tc;\n };\n \n struct ecore_dcbx_admin_params {\n@@ -129,7 +129,7 @@ struct ecore_dcbx_results {\n \n struct ecore_dcbx_app_metadata {\n \tenum dcbx_protocol_type id;\n-\tconst char *name;\t/* @DPDK */\n+\tconst char *name; /* @DPDK */\n \tenum ecore_pci_personality personality;\n };\n \ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 89faa35..46d3e80 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -64,11 +64,11 @@ static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)\n \t\t\treturn BAR_ID_0 ? 256 * 1024 : 512 * 1024;\n \t\t}\n \n-\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\tDP_NOTICE(p_hwfn, false,\n \t\t\t  \"BAR size not configured. Assuming BAR\"\n \t\t\t  \" size of 512kB for GRC and 512kB for DB\\n\");\n-\t\treturn 512 * 1024;\n-\t}\n+\t\t\treturn 512 * 1024;\n+\t\t}\n \n \treturn 1 << (val + 15);\n }\n@@ -305,7 +305,7 @@ static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,\n \n \treturn ECORE_SUCCESS;\n \n-alloc_err:\n+ alloc_err:\n \tDP_NOTICE(p_hwfn, false, \"Failed to allocate memory for QM params\\n\");\n \tecore_qm_info_free(p_hwfn);\n \treturn ECORE_NOMEM;\n@@ -494,9 +494,9 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)\n \n \treturn ECORE_SUCCESS;\n \n-alloc_no_mem:\n+ alloc_no_mem:\n \trc = ECORE_NOMEM;\n-alloc_err:\n+ alloc_err:\n \tecore_resc_free(p_dev);\n \treturn rc;\n }\n@@ -557,11 +557,11 @@ enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,\n \tcommand |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;\n \tcommand |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;\n \n-\t/* Make sure notification is not set before initiating final cleanup */\n+/* Make sure notification is not set before initiating final cleanup */\n \tif (REG_RD(p_hwfn, addr)) {\n \t\tDP_NOTICE(p_hwfn, false,\n \t\t\t  \"Unexpected; Found final cleanup notification \"\n-\t\t\t  \"before initiating final cleanup\\n\");\n+\t\t\t  \" before initiating final cleanup\\n\");\n \t\tREG_WR(p_hwfn, addr, 0);\n \t}\n \n@@ -666,7 +666,7 @@ static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)\n #ifndef ASIC_ONLY\n /* MFW-replacement initializations for non-ASIC */\n static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,\n-\t\t\t       struct ecore_ptt *p_ptt)\n+\t\t\t\t\t       struct ecore_ptt *p_ptt)\n {\n \tu32 pl_hv = 1;\n \tint i;\n@@ -907,7 +907,7 @@ static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,\n \t}\n \n \tecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,\n-\t\t\t\tport);\n+\t\t\t port);\n \tecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);\n \tecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);\n \tecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);\n@@ -935,10 +935,10 @@ static void ecore_link_init(struct ecore_hwfn *p_hwfn,\n \t/* Reset of XMAC */\n \t/* FIXME: move to common start */\n \tecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),\n-\t\tMISC_REG_RESET_REG_2_XMAC_BIT);\t/* Clear */\n+\t\t MISC_REG_RESET_REG_2_XMAC_BIT);\t/* Clear */\n \tOSAL_MSLEEP(1);\n \tecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),\n-\t\tMISC_REG_RESET_REG_2_XMAC_BIT);\t/* Set */\n+\t\t MISC_REG_RESET_REG_2_XMAC_BIT);\t/* Set */\n \n \tecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);\n \n@@ -1078,7 +1078,7 @@ ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,\n \tp_hwfn->dpi_start_offset = norm_regsize; /* this is later used to\n \t\t\t\t\t\t  * calculate the doorbell\n \t\t\t\t\t\t  * address\n-\t\t\t\t\t\t  */\n+\t\t */\n \n \t/* Update registers */\n \t/* DEMS size is configured log2 of DWORDs, hence the division by 4 */\n@@ -1319,7 +1319,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\tecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);\n \n \t\tDP_VERBOSE(p_hwfn, ECORE_MSG_SP,\n-\t\t\t   \"Load request was sent.Resp:0x%x, Load code: 0x%x\\n\",\n+\t\t\t   \"Load request was sent. Resp:0x%x, Load code: 0x%x\\n\",\n \t\t\t   rc, load_code);\n \n \t\t/* Only relevant for recovery:\n@@ -1411,8 +1411,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \n #define ECORE_HW_STOP_RETRY_LIMIT\t(10)\n static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,\n-\t\t\t\t\t     struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t     struct ecore_ptt *p_ptt)\n+\t\t\t\t struct ecore_hwfn *p_hwfn,\n+\t\t\t\t struct ecore_ptt *p_ptt)\n {\n \tint i;\n \n@@ -1436,9 +1436,9 @@ static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,\n \t\t\t  \"Timers linear scans are not over\"\n \t\t\t  \" [Connection %02x Tasks %02x]\\n\",\n \t\t\t  (u8)ecore_rd(p_hwfn, p_ptt,\n-\t\t\t\t       TM_REG_PF_SCAN_ACTIVE_CONN),\n+\t\t\t\t\tTM_REG_PF_SCAN_ACTIVE_CONN),\n \t\t\t  (u8)ecore_rd(p_hwfn, p_ptt,\n-\t\t\t\t       TM_REG_PF_SCAN_ACTIVE_TASK));\n+\t\t\t\t\tTM_REG_PF_SCAN_ACTIVE_TASK));\n }\n \n void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)\n@@ -1679,7 +1679,7 @@ static void get_function_id(struct ecore_hwfn *p_hwfn)\n {\n \t/* ME Register */\n \tp_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,\n-\t\t\t\t\t\t PXP_PF_ME_OPAQUE_ADDR);\n+\t\t\t\t\t\t  PXP_PF_ME_OPAQUE_ADDR);\n \n \tp_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);\n \n@@ -1725,7 +1725,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)\n \tstruct ecore_sb_cnt_info sb_cnt_info;\n \tbool b_ah = ECORE_IS_AH(p_hwfn->p_dev);\n \n-\tOSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));\n+\t\tOSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));\n \n #ifdef CONFIG_ECORE_SRIOV\n \tmax_vf_vlan_filters = ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS;\n@@ -1733,19 +1733,19 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)\n \tmax_vf_vlan_filters = 0;\n #endif\n \n-\tecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);\n+\t\tecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);\n \tresc_num[ECORE_SB] = OSAL_MIN_T(u32,\n \t\t\t\t\t(MAX_SB_PER_PATH_BB / num_funcs),\n \t\t\t\t\tsb_cnt_info.sb_cnt);\n \n \tresc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 :\n-\t\t\t\t    MAX_NUM_L2_QUEUES_BB) / num_funcs;\n+\t\t\t\t MAX_NUM_L2_QUEUES_BB) / num_funcs;\n \tresc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 :\n \t\t\t\t MAX_NUM_VPORTS_BB) / num_funcs;\n \tresc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :\n-\t\t\t\t   ETH_RSS_ENGINE_NUM_BB) / num_funcs;\n+\t\t\t\t ETH_RSS_ENGINE_NUM_BB) / num_funcs;\n \tresc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 :\n-\t\t\t      MAX_QM_TX_QUEUES_BB) / num_funcs;\n+\t\t\t\t MAX_QM_TX_QUEUES_BB) / num_funcs;\n \tresc_num[ECORE_RL] = 8;\n \tresc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;\n \tresc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS -\n@@ -1754,7 +1754,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)\n \n \t/* TODO - there will be a problem in AH - there are only 11k lines */\n \tresc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :\n-\t\t\t       PXP_NUM_ILT_RECORDS_BB) / num_funcs;\n+\t\t\t\t PXP_NUM_ILT_RECORDS_BB) / num_funcs;\n \n #ifndef ASIC_ONLY\n \tif (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {\n@@ -1840,7 +1840,7 @@ static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,\n \t\treturn ECORE_INVAL;\n \t}\n \n-\t/* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */\n+/* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */\n \tnvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);\n \n \taddr = MCP_REG_SCRATCH + nvm_cfg1_offset +\n@@ -2003,8 +2003,8 @@ static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,\n \t\tif (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) {\n \t\t\tnum_funcs = 0;\n \t\t\tmask = 0xaaaa;\n-\t\t} else {\n-\t\t\tnum_funcs = 1;\n+\t\t\t} else {\n+\t\t\t\tnum_funcs = 1;\n \t\t\tmask = 0x5554;\n \t\t}\n \n@@ -2070,12 +2070,12 @@ static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,\n \n \tp_hwfn->p_dev->num_ports_in_engines = 0;\n \n-\tfor (i = 0; i < MAX_NUM_PORTS_K2; i++) {\n-\t\tport = ecore_rd(p_hwfn, p_ptt,\n-\t\t\t\tCNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));\n-\t\tif (port & 1)\n-\t\t\tp_hwfn->p_dev->num_ports_in_engines++;\n-\t}\n+\t\tfor (i = 0; i < MAX_NUM_PORTS_K2; i++) {\n+\t\t\tport = ecore_rd(p_hwfn, p_ptt,\n+\t\t\t\t\tCNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));\n+\t\t\tif (port & 1)\n+\t\t\t\tp_hwfn->p_dev->num_ports_in_engines++;\n+\t\t}\n }\n \n static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,\n@@ -2095,8 +2095,8 @@ ecore_get_hw_info(struct ecore_hwfn *p_hwfn,\n \tenum _ecore_status_t rc;\n \n \trc = ecore_iov_hw_info(p_hwfn, p_hwfn->p_main_ptt);\n-\tif (rc)\n-\t\treturn rc;\n+\t\tif (rc)\n+\t\t\treturn rc;\n \n \t/* TODO In get_hw_info, amoungst others:\n \t * Get MCP FW revision and determine according to it the supported\n@@ -2178,7 +2178,7 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)\n \tp_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t\t\t MISCS_REG_CHIP_NUM);\n \tp_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t\tMISCS_REG_CHIP_REV);\n+\t\t\t\t\t MISCS_REG_CHIP_REV);\n \n \tMASK_FIELD(CHIP_REV, p_dev->chip_rev);\n \n@@ -2214,7 +2214,7 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)\n \t\t\t\t       MISCS_REG_CHIP_TEST_REG) >> 4;\n \tMASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);\n \tp_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t\t  MISCS_REG_CHIP_METAL);\n+\t\t\t\t\t   MISCS_REG_CHIP_METAL);\n \tMASK_FIELD(CHIP_METAL, p_dev->chip_metal);\n \tDP_INFO(p_dev->hwfns,\n \t\t\"Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x\"\n@@ -2344,11 +2344,11 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,\n #endif\n \n \treturn rc;\n-err2:\n+ err2:\n \tecore_mcp_free(p_hwfn);\n-err1:\n+ err1:\n \tecore_hw_hwfn_free(p_hwfn);\n-err0:\n+ err0:\n \treturn rc;\n }\n \n@@ -2361,7 +2361,7 @@ enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality)\n \t\treturn ecore_vf_hw_prepare(p_dev);\n \n \t/* Store the precompiled init data ptrs */\n-\tecore_init_iro_array(p_dev);\n+\t\tecore_init_iro_array(p_dev);\n \n \t/* Initialize the first hwfn - will learn number of hwfns */\n \trc = ecore_hw_prepare_single(p_hwfn,\n@@ -2490,7 +2490,7 @@ static void ecore_chain_free_pbl(struct ecore_dev *p_dev,\n \tpbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;\n \tOSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,\n \t\t\t       p_chain->pbl.p_phys_table, pbl_size);\n-out:\n+ out:\n \tOSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);\n }\n \n@@ -2692,7 +2692,7 @@ enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,\n \n \treturn ECORE_SUCCESS;\n \n-nomem:\n+ nomem:\n \tecore_chain_free(p_dev, p_chain);\n \treturn rc;\n }\n@@ -2848,7 +2848,7 @@ void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,\n }\n \n enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t\t    struct ecore_ptt *p_ptt,\n+\t\t\t      struct ecore_ptt *p_ptt,\n \t\t\t\t\t\t    u16 filter)\n {\n \tu32 high, low, en;\n@@ -2887,7 +2887,7 @@ enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,\n \t\treturn ECORE_INVAL;\n \t}\n \n-\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n \t\t   \"ETH type: %x is added at %d\\n\", filter, i);\n \n \treturn ECORE_SUCCESS;\n@@ -2952,7 +2952,7 @@ void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,\n }\n \n enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t  struct ecore_ptt *p_ptt)\n+\t\t\t\t  struct ecore_ptt *p_ptt)\n {\n \tu32 reg_tbl[] = {\n \t\tBRB_REG_HEADER_SIZE,\n@@ -3032,8 +3032,8 @@ enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,\n \t\t\t}\n \t\t}\n \t}\n-\treturn ECORE_SUCCESS;\n-}\n+\t\treturn ECORE_SUCCESS;\n+\t}\n \n static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t       struct ecore_ptt *p_ptt,\n@@ -3089,7 +3089,7 @@ enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,\n \t\tgoto out;\n \n \tp_hwfn->p_dev->rx_coalesce_usecs = coalesce;\n-out:\n+ out:\n \treturn rc;\n }\n \n@@ -3119,7 +3119,7 @@ enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,\n \t\tgoto out;\n \n \tp_hwfn->p_dev->tx_coalesce_usecs = coalesce;\n-out:\n+ out:\n \treturn rc;\n }\n \n@@ -3305,16 +3305,16 @@ static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,\n \t\tif (p_hwfn->qm_info.wfq_data[i].configured) {\n \t\t\tu32 rate = p_hwfn->qm_info.wfq_data[i].min_speed;\n \n-\t\t\tuse_wfq = true;\n-\t\t\trc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);\n+\t\tuse_wfq = true;\n+\t\trc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);\n \t\t\tif (rc == ECORE_INVAL) {\n-\t\t\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\tDP_NOTICE(p_hwfn, false,\n \t\t\t\t\t  \"Validation failed while\"\n \t\t\t\t\t  \" configuring min rate\\n\");\n-\t\t\t\tbreak;\n-\t\t\t}\n+\t\t\tbreak;\n \t\t}\n \t}\n+\t}\n \n \tif (rc == ECORE_SUCCESS && use_wfq)\n \t\tecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);\ndiff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h\nindex 535b82b..1b78c32 100644\n--- a/drivers/net/qede/base/ecore_dev_api.h\n+++ b/drivers/net/qede/base/ecore_dev_api.h\n@@ -270,22 +270,22 @@ enum ecore_dmae_address_type_t {\n #define ECORE_DMAE_FLAG_COMPLETION_DST\t0x00000008\n \n struct ecore_dmae_params {\n-\tu32 flags;\t\t/* consists of ECORE_DMAE_FLAG_* values */\n+\tu32 flags; /* consists of ECORE_DMAE_FLAG_* values */\n \tu8 src_vfid;\n \tu8 dst_vfid;\n };\n \n /**\n-* @brief ecore_dmae_host2grc - copy data from source addr to\n-* dmae registers using the given ptt\n-*\n-* @param p_hwfn\n-* @param p_ptt\n-* @param source_addr\n-* @param grc_addr (dmae_data_offset)\n-* @param size_in_dwords\n-* @param flags (one of the flags defined above)\n-*/\n+ * @brief ecore_dmae_host2grc - copy data from source addr to\n+ * dmae registers using the given ptt\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ * @param source_addr\n+ * @param grc_addr (dmae_data_offset)\n+ * @param size_in_dwords\n+ * @param flags (one of the flags defined above)\n+ */\n enum _ecore_status_t\n ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,\n \t\t    struct ecore_ptt *p_ptt,\n@@ -293,15 +293,15 @@ ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,\n \t\t    u32 grc_addr, u32 size_in_dwords, u32 flags);\n \n /**\n-* @brief ecore_dmae_grc2host - Read data from dmae data offset\n-* to source address using the given ptt\n-*\n-* @param p_ptt\n-* @param grc_addr (dmae_data_offset)\n-* @param dest_addr\n-* @param size_in_dwords\n-* @param flags - one of the flags defined above\n-*/\n+ * @brief ecore_dmae_grc2host - Read data from dmae data offset\n+ * to source address using the given ptt\n+ *\n+ * @param p_ptt\n+ * @param grc_addr (dmae_data_offset)\n+ * @param dest_addr\n+ * @param size_in_dwords\n+ * @param flags - one of the flags defined above\n+ */\n enum _ecore_status_t\n ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,\n \t\t    struct ecore_ptt *p_ptt,\n@@ -309,16 +309,16 @@ ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,\n \t\t    dma_addr_t dest_addr, u32 size_in_dwords, u32 flags);\n \n /**\n-* @brief ecore_dmae_host2host - copy data from to source address\n-* to a destination address (for SRIOV) using the given ptt\n-*\n-* @param p_hwfn\n-* @param p_ptt\n-* @param source_addr\n-* @param dest_addr\n-* @param size_in_dwords\n-* @param params\n-*/\n+ * @brief ecore_dmae_host2host - copy data from to source address\n+ * to a destination address (for SRIOV) using the given ptt\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ * @param source_addr\n+ * @param dest_addr\n+ * @param size_in_dwords\n+ * @param params\n+ */\n enum _ecore_status_t\n ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,\n \t\t     struct ecore_ptt *p_ptt,\n@@ -398,8 +398,8 @@ enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,\n  * @param p_filter - MAC to add\n  */\n enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t      struct ecore_ptt *p_ptt,\n-\t\t\t\t\t      u8 *p_filter);\n+\t\t\t\t\t  struct ecore_ptt *p_ptt,\n+\t\t\t\t\t  u8 *p_filter);\n \n /**\n  * @brief ecore_llh_remove_mac_filter - removes a MAC filtre from llh\n@@ -419,7 +419,7 @@ void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,\n  * @param filter - ethertype to add\n  */\n enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t\t    struct ecore_ptt *p_ptt,\n+\t\t\t      struct ecore_ptt *p_ptt,\n \t\t\t\t\t\t    u16 filter);\n \n /**\n@@ -439,9 +439,9 @@ void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,\n  * @param p_ptt\n  */\n void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t struct ecore_ptt *p_ptt);\n+\t\t\t     struct ecore_ptt *p_ptt);\n \n- /**\n+/**\n *@brief Cleanup of previous driver remains prior to load\n  *\n  * @param p_hwfn\n@@ -461,7 +461,7 @@ enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,\n  * @param p_hwfn\n  * @param p_ptt\n  *\n- *  @return enum _ecore_status_t\n+ * @return enum _ecore_status_t\n  */\n enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t  struct ecore_ptt *p_ptt);\ndiff --git a/drivers/net/qede/base/ecore_gtt_reg_addr.h b/drivers/net/qede/base/ecore_gtt_reg_addr.h\nindex cc49fc7..0eba1aa 100644\n--- a/drivers/net/qede/base/ecore_gtt_reg_addr.h\n+++ b/drivers/net/qede/base/ecore_gtt_reg_addr.h\n@@ -10,33 +10,33 @@\n #define GTT_REG_ADDR_H\n \n /* Win 2 */\n-#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL\n+#define GTT_BAR0_MAP_REG_IGU_CMD                                      0x00f000UL\n \n /* Win 3 */\n-#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL\n+#define GTT_BAR0_MAP_REG_TSDM_RAM                                     0x010000UL\n \n /* Win 4 */\n-#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL\n+#define GTT_BAR0_MAP_REG_MSDM_RAM                                     0x011000UL\n \n /* Win 5 */\n-#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL\n+#define GTT_BAR0_MAP_REG_MSDM_RAM_1024                                0x012000UL\n \n /* Win 6 */\n-#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL\n+#define GTT_BAR0_MAP_REG_USDM_RAM                                     0x013000UL\n \n /* Win 7 */\n-#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL\n+#define GTT_BAR0_MAP_REG_USDM_RAM_1024                                0x014000UL\n \n /* Win 8 */\n-#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL\n+#define GTT_BAR0_MAP_REG_USDM_RAM_2048                                0x015000UL\n \n /* Win 9 */\n-#define GTT_BAR0_MAP_REG_XSDM_RAM  0x016000UL\n+#define GTT_BAR0_MAP_REG_XSDM_RAM                                     0x016000UL\n \n /* Win 10 */\n-#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL\n+#define GTT_BAR0_MAP_REG_YSDM_RAM                                     0x017000UL\n \n /* Win 11 */\n-#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL\n+#define GTT_BAR0_MAP_REG_PSDM_RAM                                     0x018000UL\n \n #endif\ndiff --git a/drivers/net/qede/base/ecore_gtt_values.h b/drivers/net/qede/base/ecore_gtt_values.h\nindex f2efe24..2ddc5f1 100644\n--- a/drivers/net/qede/base/ecore_gtt_values.h\n+++ b/drivers/net/qede/base/ecore_gtt_values.h\n@@ -11,16 +11,16 @@\n static u32 pxp_global_win[] = {\n \t0,\n \t0,\n-\t0x1c02,\t\t\t/* win 2: addr=0x1c02000, size=4096 bytes */\n-\t0x1c80,\t\t\t/* win 3: addr=0x1c80000, size=4096 bytes */\n-\t0x1d00,\t\t\t/* win 4: addr=0x1d00000, size=4096 bytes */\n-\t0x1d01,\t\t\t/* win 5: addr=0x1d01000, size=4096 bytes */\n-\t0x1d80,\t\t\t/* win 6: addr=0x1d80000, size=4096 bytes */\n-\t0x1d81,\t\t\t/* win 7: addr=0x1d81000, size=4096 bytes */\n-\t0x1d82,\t\t\t/* win 8: addr=0x1d82000, size=4096 bytes */\n-\t0x1e00,\t\t\t/* win 9: addr=0x1e00000, size=4096 bytes */\n-\t0x1e80,\t\t\t/* win 10: addr=0x1e80000, size=4096 bytes */\n-\t0x1f00,\t\t\t/* win 11: addr=0x1f00000, size=4096 bytes */\n+\t0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */\n+\t0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */\n+\t0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */\n+\t0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */\n+\t0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */\n+\t0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */\n+\t0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */\n+\t0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */\n+\t0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */\n+\t0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */\n \t0,\n \t0,\n \t0,\ndiff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h\nindex 9cd55c4..877de8b 100644\n--- a/drivers/net/qede/base/ecore_hsi_common.h\n+++ b/drivers/net/qede/base/ecore_hsi_common.h\n@@ -953,7 +953,7 @@ enum malicious_vf_error_id {\n \tVF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,\n \tVF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,\n \tETH_PACKET_TOO_SMALL\n-\t    /* TX packet is shorter then reported on BDs or from minimal size */\n+/* TX packet is shorter then reported on BDs or from minimal size */\n \t    ,\n \tETH_ILLEGAL_VLAN_MODE\n \t    /* Tx packet with marked as insert VLAN when its illegal */,\n@@ -1060,7 +1060,7 @@ struct pf_start_ramrod_data {\n \tu8 allow_npar_tx_switching;\n \tu8 inner_to_outer_pri_map[8];\n \tu8 pri_map_valid\n-\t    /* If inner_to_outer_pri_map is initialize then set pri_map_valid */\n+/* If inner_to_outer_pri_map is initialize then set pri_map_valid */\n \t  ;\n \t__le32 outer_tag;\n \tu8 reserved0[4];\n@@ -1244,7 +1244,7 @@ enum tunnel_clss {\n \tTUNNEL_CLSS_MAC_VNI\n \t    ,\n \tTUNNEL_CLSS_INNER_MAC_VLAN\n-\t    /* Use MAC and VLAN from last L2 header for vport classification */\n+/* Use MAC and VLAN from last L2 header for vport classification */\n \t    ,\n \tTUNNEL_CLSS_INNER_MAC_VNI\n \t    ,\ndiff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h\nindex 80f4165..78cc55d 100644\n--- a/drivers/net/qede/base/ecore_hsi_eth.h\n+++ b/drivers/net/qede/base/ecore_hsi_eth.h\n@@ -872,7 +872,7 @@ struct eth_vport_tpa_param {\n \tu8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;\n \tu8 tpa_pkt_split_flg;\n \tu8 tpa_hdr_data_split_flg\n-\t    /* If set, put header of first TPA segment on bd and data on SGE */\n+/* If set, put header of first TPA segment on bd and data on SGE */\n \t   ;\n \tu8 tpa_gro_consistent_flg\n \t    /* If set, GRO data consistent will checked for TPA continue */;\n@@ -882,10 +882,10 @@ struct eth_vport_tpa_param {\n \t__le16 tpa_min_size_to_start\n \t    /* minimum TCP payload size for a packet to start aggregation */;\n \t__le16 tpa_min_size_to_cont\n-\t    /* minimum TCP payload size for a packet to continue aggregation */\n+/* minimum TCP payload size for a packet to continue aggregation */\n \t   ;\n \tu8 max_buff_num\n-\t    /* maximal number of buffers that can be used for one aggregation */\n+/* maximal number of buffers that can be used for one aggregation */\n \t   ;\n \tu8 reserved;\n };\n@@ -1124,7 +1124,7 @@ struct vport_start_ramrod_data {\n \tu8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */\n \t   ;\n \tu8 silent_vlan_removal_en;\n-\t/* If enable then innerVlan will be striped and not written to cqe */\n+/* If enable then innerVlan will be striped and not written to cqe */\n \tu8 untagged;\n \tstruct eth_tx_err_vals tx_err_behav\n \t    /* Desired behavior per TX error type */;\ndiff --git a/drivers/net/qede/base/ecore_hw.c b/drivers/net/qede/base/ecore_hw.c\nindex 5403b94..e9b96d5 100644\n--- a/drivers/net/qede/base/ecore_hw.c\n+++ b/drivers/net/qede/base/ecore_hw.c\n@@ -108,15 +108,15 @@ struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)\n \t}\n \n \tp_ptt = OSAL_LIST_FIRST_ENTRY(&p_hwfn->p_ptt_pool->free_list,\n-\t\t\t\t      struct ecore_ptt, list_entry);\n-\tOSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,\n-\t\t\t       &p_hwfn->p_ptt_pool->free_list);\n-\tOSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);\n+\t\t\t\t\t\tstruct ecore_ptt, list_entry);\n+\t\t\tOSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,\n+\t\t\t\t\t       &p_hwfn->p_ptt_pool->free_list);\n+\t\t\tOSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);\n \n \tDP_VERBOSE(p_hwfn, ECORE_MSG_HW, \"allocated ptt %d\\n\", p_ptt->idx);\n \n-\treturn p_ptt;\n-}\n+\t\t\treturn p_ptt;\n+\t\t}\n \n void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)\n {\n@@ -298,7 +298,7 @@ void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,\n \tSET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);\n \tSET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);\n \n-\t/* Every pretend undos prev pretends, including previous port pretend */\n+/* Every pretend undos prev pretends, including previous port pretend */\n \tSET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);\n \tSET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);\n \tSET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);\ndiff --git a/drivers/net/qede/base/ecore_hw.h b/drivers/net/qede/base/ecore_hw.h\nindex 8949944..9603c99 100644\n--- a/drivers/net/qede/base/ecore_hw.h\n+++ b/drivers/net/qede/base/ecore_hw.h\n@@ -115,7 +115,7 @@ u32 ecore_ptt_get_hw_addr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);\n  *\n  * @return u32\n  */\n-u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt);\n+u32 ecore_ptt_get_bar_addr(struct ecore_ptt\t*p_ptt);\n \n /**\n  * @brief ecore_ptt_set_win - Set PTT Window's GRC BAR address\n@@ -124,7 +124,7 @@ u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt);\n  * @param new_hw_addr\n  * @param p_ptt\n  */\n-void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,\n+void ecore_ptt_set_win(struct ecore_hwfn\t*p_hwfn,\n \t\t       struct ecore_ptt *p_ptt, u32 new_hw_addr);\n \n /**\n@@ -135,8 +135,8 @@ void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,\n  *\n  * @return struct ecore_ptt *\n  */\n-struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t enum reserved_ptts ptt_idx);\n+struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn\t*p_hwfn,\n+\t\t\t\t\t enum reserved_ptts\tptt_idx);\n \n /**\n  * @brief ecore_wr - Write value to BAR using the given ptt\n@@ -146,7 +146,7 @@ struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,\n  * @param val\n  * @param hw_addr\n  */\n-void ecore_wr(struct ecore_hwfn *p_hwfn,\n+void ecore_wr(struct ecore_hwfn\t*p_hwfn,\n \t      struct ecore_ptt *p_ptt, u32 hw_addr, u32 val);\n \n /**\n@@ -169,8 +169,8 @@ u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr);\n  * @param hw_addr\n  * @param n\n  */\n-void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,\n-\t\t       struct ecore_ptt *p_ptt,\n+void ecore_memcpy_from(struct ecore_hwfn\t*p_hwfn,\n+\t\t       struct ecore_ptt\t\t*p_ptt,\n \t\t       void *dest, u32 hw_addr, osal_size_t n);\n \n /**\n@@ -183,8 +183,8 @@ void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,\n  * @param src\n  * @param n\n  */\n-void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,\n-\t\t     struct ecore_ptt *p_ptt,\n+void ecore_memcpy_to(struct ecore_hwfn\t*p_hwfn,\n+\t\t     struct ecore_ptt\t*p_ptt,\n \t\t     u32 hw_addr, void *src, osal_size_t n);\n /**\n  * @brief ecore_fid_pretend - pretend to another function when\n@@ -197,7 +197,7 @@ void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,\n  * @param fid - fid field of pxp_pretend structure. Can contain\n  *            either pf / vf, port/path fields are don't care.\n  */\n-void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,\n+void ecore_fid_pretend(struct ecore_hwfn\t*p_hwfn,\n \t\t       struct ecore_ptt *p_ptt, u16 fid);\n \n /**\n@@ -208,7 +208,7 @@ void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,\n  * @param p_ptt\n  * @param port_id - the port to pretend to\n  */\n-void ecore_port_pretend(struct ecore_hwfn *p_hwfn,\n+void ecore_port_pretend(struct ecore_hwfn\t*p_hwfn,\n \t\t\tstruct ecore_ptt *p_ptt, u8 port_id);\n \n /**\n@@ -235,7 +235,7 @@ u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid);\n * which is part of p_hwfn.\n * @param p_hwfn\n */\n-enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn);\n+enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn\t*p_hwfn);\n \n /**\n * @brief ecore_dmae_info_free - Free the dmae_info structure\n@@ -243,7 +243,7 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn);\n *\n * @param p_hwfn\n */\n-void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn);\n+void ecore_dmae_info_free(struct ecore_hwfn\t*p_hwfn);\n \n union ecore_qm_pq_params {\n \tstruct {\n@@ -257,7 +257,7 @@ union ecore_qm_pq_params {\n \t} eth;\n };\n \n-u16 ecore_get_qm_pq(struct ecore_hwfn *p_hwfn,\n+u16 ecore_get_qm_pq(struct ecore_hwfn\t*p_hwfn,\n \t\t    enum protocol_type proto, union ecore_qm_pq_params *params);\n \n enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,\ndiff --git a/drivers/net/qede/base/ecore_hw_defs.h b/drivers/net/qede/base/ecore_hw_defs.h\nindex fa518ce..19816ff 100644\n--- a/drivers/net/qede/base/ecore_hw_defs.h\n+++ b/drivers/net/qede/base/ecore_hw_defs.h\n@@ -36,13 +36,13 @@ enum igu_ctrl_cmd {\n  */\n struct igu_ctrl_reg {\n \tu32 ctrl_data;\n-#define IGU_CTRL_REG_FID_MASK\t\t0xFFFF\t/* Opaque_FID     */\n+#define IGU_CTRL_REG_FID_MASK\t\t0xFFFF /* Opaque_FID\t */\n #define IGU_CTRL_REG_FID_SHIFT\t\t0\n-#define IGU_CTRL_REG_PXP_ADDR_MASK\t0xFFF\t/* Command address */\n+#define IGU_CTRL_REG_PXP_ADDR_MASK\t0xFFF /* Command address */\n #define IGU_CTRL_REG_PXP_ADDR_SHIFT\t16\n #define IGU_CTRL_REG_RESERVED_MASK\t0x1\n #define IGU_CTRL_REG_RESERVED_SHIFT\t28\n-#define IGU_CTRL_REG_TYPE_MASK\t\t0x1\t/* use enum igu_ctrl_cmd */\n+#define IGU_CTRL_REG_TYPE_MASK\t\t0x1 /* use enum igu_ctrl_cmd */\n #define IGU_CTRL_REG_TYPE_SHIFT\t\t31\n };\n \ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c\nindex 5440731..0844194 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.c\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.c\n@@ -206,7 +206,7 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\tfor (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {\n \t\t\t\tif (((port_params[port_id].active_phys_tcs >>\n \t\t\t\t\t\ttc) & 0x1) == 1)\n-\t\t\t\tnum_tcs_in_port++;\n+\t\t\t\t\tnum_tcs_in_port++;\n \t\t\t}\n \t\t\tphys_lines_per_tc = phys_lines / num_tcs_in_port;\n \t\t\t/* init registers per active TC */\n@@ -293,9 +293,9 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\t     tc < NUM_OF_PHYS_TCS;\n \t\t\t     tc++) {\n \t\t\t\tif (((port_params[port_id].active_phys_tcs >>\n-\t\t\t\t\t\t\t tc) & 0x1) == 1) {\n+\t\t\t\t\t\t\ttc) & 0x1) == 1) {\n \t\t\t\t\tvoq = PHYS_VOQ(port_id, tc,\n-\t\t\t\t\t\t\tmax_phys_tcs_per_port);\n+\t\t\t\t\t\t       max_phys_tcs_per_port);\n \t\t\t\t\tSTORE_RT_REG(p_hwfn,\n \t\t\t\t\t     PBF_BTB_GUARANTEED_RT_OFFSET(voq),\n \t\t\t\t\t     phys_blocks);\n@@ -412,7 +412,7 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\t\tu32 curr_mask =\n \t\t\t\t    is_first_pf ? 0 : ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t\t\t       QM_REG_MAXPQSIZETXSEL_0\n-\t\t\t\t\t\t\t       + i * 4);\n+\t\t\t\t\t\t\t\t+ i * 4);\n \t\t\t\tSTORE_RT_REG(p_hwfn,\n \t\t\t\t\t     QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET +\n \t\t\t\t\t     i, curr_mask | tx_pq_vf_mask[i]);\n@@ -518,8 +518,8 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\t\t    vport_params[i].first_tx_pq_id[tc];\n \t\t\t\tif (vport_pq_id != QM_INVALID_PQ_ID) {\n \t\t\t\t\tSTORE_RT_REG(p_hwfn,\n-\t\t\t\t\t\t     QM_REG_WFQVPCRD_RT_OFFSET +\n-\t\t\t\t\t\t     vport_pq_id,\n+\t\t\t\t\t\t  QM_REG_WFQVPCRD_RT_OFFSET +\n+\t\t\t\t\t\t  vport_pq_id,\n \t\t\t\t\t\t     QM_WFQ_CRD_REG_SIGN_BIT);\n \t\t\t\t\tSTORE_RT_REG(p_hwfn,\n \t\t\t\t\t\tQM_REG_WFQVPWEIGHT_RT_OFFSET\ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h\nindex 5280cd7..0c8d1fb 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.h\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.h\n@@ -26,8 +26,8 @@ struct init_qm_pq_params;\n  * @return The required host memory size in 4KB units.\n  */\n u32 ecore_qm_pf_mem_size(u8 pf_id,\n-\t\t\t u32 num_pf_cids,\n-\t\t\t u32 num_vf_cids,\n+\t\t\t\t\t\t u32 num_pf_cids,\n+\t\t\t\t\t\t u32 num_vf_cids,\n \t\t\t u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);\n /**\n  * @brief ecore_qm_common_rt_init -\n@@ -45,33 +45,33 @@ u32 ecore_qm_pf_mem_size(u8 pf_id,\n  * @return 0 on success, -1 on error.\n  */\n int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,\n-\t\t\t    u8 max_ports_per_engine,\n-\t\t\t    u8 max_phys_tcs_per_port,\n-\t\t\t    bool pf_rl_en,\n-\t\t\t    bool pf_wfq_en,\n-\t\t\t    bool vport_rl_en,\n-\t\t\t    bool vport_wfq_en,\n+\t\t\t u8 max_ports_per_engine,\n+\t\t\t u8 max_phys_tcs_per_port,\n+\t\t\t bool pf_rl_en,\n+\t\t\t bool pf_wfq_en,\n+\t\t\t bool vport_rl_en,\n+\t\t\t bool vport_wfq_en,\n \t\t\t    struct init_qm_port_params\n \t\t\t    port_params[MAX_NUM_PORTS]);\n \n int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,\n-\t\t\tstruct ecore_ptt *p_ptt,\n-\t\t\tu8 port_id,\n-\t\t\tu8 pf_id,\n-\t\t\tu8 max_phys_tcs_per_port,\n-\t\t\tbool is_first_pf,\n-\t\t\tu32 num_pf_cids,\n-\t\t\tu32 num_vf_cids,\n-\t\t\tu32 num_tids,\n-\t\t\tu16 start_pq,\n-\t\t\tu16 num_pf_pqs,\n-\t\t\tu16 num_vf_pqs,\n-\t\t\tu8 start_vport,\n-\t\t\tu8 num_vports,\n-\t\t\tu16 pf_wfq,\n-\t\t\tu32 pf_rl,\n-\t\t\tstruct init_qm_pq_params *pq_params,\n-\t\t\tstruct init_qm_vport_params *vport_params);\n+\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\tu8 port_id,\n+\t\t\t\tu8 pf_id,\n+\t\t\t\tu8 max_phys_tcs_per_port,\n+\t\t\t\tbool is_first_pf,\n+\t\t\t\tu32 num_pf_cids,\n+\t\t\t\tu32 num_vf_cids,\n+\t\t\t\tu32 num_tids,\n+\t\t\t\tu16 start_pq,\n+\t\t\t\tu16 num_pf_pqs,\n+\t\t\t\tu16 num_vf_pqs,\n+\t\t\t\tu8 start_vport,\n+\t\t\t\tu8 num_vports,\n+\t\t\t\tu16 pf_wfq,\n+\t\t\t\tu32 pf_rl,\n+\t\t\t\tstruct init_qm_pq_params *pq_params,\n+\t\t\t\tstruct init_qm_vport_params *vport_params);\n /**\n  * @brief ecore_init_pf_wfq  Initializes the WFQ weight of the specified PF\n  *\n@@ -109,7 +109,7 @@ int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,\n  * @return 0 on success, -1 on error.\n  */\n int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,\n-\t\t\t struct ecore_ptt *p_ptt,\n+\t\t\t\t\t\t struct ecore_ptt *p_ptt,\n \t\t\t u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);\n /**\n  * @brief ecore_init_vport_rl  Initializes the rate limit of the specified VPORT\n@@ -137,8 +137,8 @@ int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,\n  * waiting for QM command done.\n  */\n bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,\n-\t\t\t    struct ecore_ptt *p_ptt,\n-\t\t\t    bool is_release_cmd,\n+\t\t\t\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\t\t\t\tbool is_release_cmd,\n \t\t\t    bool is_tx_pq, u16 start_pq, u16 num_pqs);\n /**\n  * @brief ecore_init_nig_ets - initializes the NIG ETS arbiter\n@@ -152,7 +152,7 @@ bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,\n  *\t\t  requirements are ignored when is_lb is cleared.\n  */\n void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,\n-\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\t\t\tstruct ecore_ptt *p_ptt,\n \t\t\tstruct init_ets_req *req, bool is_lb);\n /**\n  * @brief ecore_init_nig_lb_rl - initializes the NIG LB RLs\n@@ -163,8 +163,8 @@ void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,\n  * @param req\t- the NIG LB RLs initialization requirements.\n  */\n void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,\n-\t\t\t  struct ecore_ptt *p_ptt,\n-\t\t\t  struct init_nig_lb_rl_req *req);\n+\t\t\t\t  struct ecore_ptt *p_ptt,\n+\t\t\t\t  struct init_nig_lb_rl_req *req);\n /**\n  * @brief ecore_init_nig_pri_tc_map - initializes the NIG priority to TC map.\n  *\n@@ -174,8 +174,8 @@ void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,\n  * @param req\t- required mapping from prioirties to TCs.\n  */\n void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,\n-\t\t\t       struct ecore_ptt *p_ptt,\n-\t\t\t       struct init_nig_pri_tc_map_req *req);\n+\t\t\t\t\t   struct ecore_ptt *p_ptt,\n+\t\t\t\t\t   struct init_nig_pri_tc_map_req *req);\n /**\n  * @brief ecore_init_prs_ets - initializes the PRS Rx ETS arbiter\n  *\n@@ -227,7 +227,7 @@ void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,\n /**\n  * @brief ecore_set_vxlan_enable - enable or disable VXLAN tunnel in HW\n  *\n- * @param p_ptt        - ptt window used for writing the registers.\n+ * @param p_ptt\t- ptt window used for writing the registers.\n  * @param vxlan_enable - vxlan enable flag.\n  */\n void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,\ndiff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c\nindex e6e4c36..71bad30 100644\n--- a/drivers/net/qede/base/ecore_init_ops.c\n+++ b/drivers/net/qede/base/ecore_init_ops.c\n@@ -251,9 +251,9 @@ static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t\t   b_can_dmae);\n \t\t\t\tif (rc)\n \t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tbreak;\n \t\t}\n+\t\tbreak;\n+\t}\n \tcase INIT_ARR_STANDARD:\n \t\tsize = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);\n \t\trc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,\ndiff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c\nindex bed9ea3..e4c002a 100644\n--- a/drivers/net/qede/base/ecore_int.c\n+++ b/drivers/net/qede/base/ecore_int.c\n@@ -100,7 +100,7 @@ static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)\n #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT\t(0)\n #define ECORE_PSWHST_ATTENTION_VF_DISABLED\t\t(0x1)\n #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS\t\t(0x1)\n-#define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK\t(0x1)\n+#define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK\t\t(0x1)\n #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT\t(0)\n #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK\t(0x1e)\n #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT\t(1)\n@@ -1138,7 +1138,7 @@ void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)\n \t\treturn;\n \t}\n \n-\t/* Check the validity of the DPC ptt. If not ack interrupts and fail */\n+/* Check the validity of the DPC ptt. If not ack interrupts and fail */\n \tif (!p_hwfn->p_dpc_ptt) {\n \t\tDP_NOTICE(p_hwfn->p_dev, true, \"Failed to allocate PTT\\n\");\n \t\tecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);\n@@ -1676,7 +1676,7 @@ static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,\n \n enum _ecore_status_t\n ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n-\t\t     enum ecore_int_mode int_mode)\n+\t\t\t  enum ecore_int_mode int_mode)\n {\n \tenum _ecore_status_t rc = ECORE_SUCCESS;\n \tu32 tmp;\n@@ -2102,10 +2102,10 @@ u16 ecore_int_queue_id_from_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)\n \t\treturn sb_id - p_info->igu_base_sb_iov + p_info->igu_sb_cnt;\n \t}\n \n-\tDP_NOTICE(p_hwfn, true, \"SB %d not in range for function\\n\",\n-\t\t  sb_id);\n-\treturn 0;\n-}\n+\t\tDP_NOTICE(p_hwfn, true, \"SB %d not in range for function\\n\",\n+\t\t\t  sb_id);\n+\t\treturn 0;\n+\t}\n \n void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)\n {\ndiff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h\nindex 17c9521..eeec8ca 100644\n--- a/drivers/net/qede/base/ecore_int.h\n+++ b/drivers/net/qede/base/ecore_int.h\n@@ -169,8 +169,8 @@ void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,\n *\n * @return enum _ecore_status_t\n */\n-enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t     struct ecore_ptt *p_ptt);\n+enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn\t*p_hwfn,\n+\t\t\t\t     struct ecore_ptt\t*p_ptt);\n \n /**\n * @brief ecore_int_free\ndiff --git a/drivers/net/qede/base/ecore_iov_api.h b/drivers/net/qede/base/ecore_iov_api.h\nindex b34a9c6..5ad4ec6 100644\n--- a/drivers/net/qede/base/ecore_iov_api.h\n+++ b/drivers/net/qede/base/ecore_iov_api.h\n@@ -21,22 +21,22 @@\n #define IS_PF_SRIOV(p_hwfn)\t(0)\n #endif\n #define IS_PF_SRIOV_ALLOC(p_hwfn)\t(!!((p_hwfn)->pf_iov_info))\n-#define IS_PF_PDA(p_hwfn)\t0\t/* @@TBD Michalk */\n+#define IS_PF_PDA(p_hwfn)\t0 /* @@TBD Michalk */\n \n /* @@@ TBD MichalK - what should this number be*/\n #define ECORE_MAX_VF_CHAINS_PER_PF 16\n \n /* vport update extended feature tlvs flags */\n enum ecore_iov_vport_update_flag {\n-\tECORE_IOV_VP_UPDATE_ACTIVATE = 0,\n-\tECORE_IOV_VP_UPDATE_VLAN_STRIP = 1,\n-\tECORE_IOV_VP_UPDATE_TX_SWITCH = 2,\n-\tECORE_IOV_VP_UPDATE_MCAST = 3,\n-\tECORE_IOV_VP_UPDATE_ACCEPT_PARAM = 4,\n-\tECORE_IOV_VP_UPDATE_RSS = 5,\n-\tECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN = 6,\n-\tECORE_IOV_VP_UPDATE_SGE_TPA = 7,\n-\tECORE_IOV_VP_UPDATE_MAX = 8,\n+\tECORE_IOV_VP_UPDATE_ACTIVATE\t\t= 0,\n+\tECORE_IOV_VP_UPDATE_VLAN_STRIP\t\t= 1,\n+\tECORE_IOV_VP_UPDATE_TX_SWITCH\t\t= 2,\n+\tECORE_IOV_VP_UPDATE_MCAST\t\t= 3,\n+\tECORE_IOV_VP_UPDATE_ACCEPT_PARAM\t= 4,\n+\tECORE_IOV_VP_UPDATE_RSS\t\t\t= 5,\n+\tECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN\t= 6,\n+\tECORE_IOV_VP_UPDATE_SGE_TPA\t\t= 7,\n+\tECORE_IOV_VP_UPDATE_MAX\t\t\t= 8,\n };\n \n struct ecore_mcp_link_params;\n@@ -67,21 +67,21 @@ struct ecore_public_vf_info {\n #ifdef CONFIG_ECORE_SW_CHANNEL\n /* This is SW channel related only... */\n enum mbx_state {\n-\tVF_PF_UNKNOWN_STATE = 0,\n-\tVF_PF_WAIT_FOR_START_REQUEST = 1,\n-\tVF_PF_WAIT_FOR_NEXT_CHUNK_OF_REQUEST = 2,\n-\tVF_PF_REQUEST_IN_PROCESSING = 3,\n-\tVF_PF_RESPONSE_READY = 4,\n+\tVF_PF_UNKNOWN_STATE\t\t\t= 0,\n+\tVF_PF_WAIT_FOR_START_REQUEST\t\t= 1,\n+\tVF_PF_WAIT_FOR_NEXT_CHUNK_OF_REQUEST\t= 2,\n+\tVF_PF_REQUEST_IN_PROCESSING\t\t= 3,\n+\tVF_PF_RESPONSE_READY\t\t\t= 4,\n };\n \n struct ecore_iov_sw_mbx {\n-\tenum mbx_state mbx_state;\n+\tenum mbx_state\t\tmbx_state;\n \n-\tu32 request_size;\n-\tu32 request_offset;\n+\tu32\t\t\trequest_size;\n+\tu32\t\t\trequest_offset;\n \n-\tu32 response_size;\n-\tu32 response_offset;\n+\tu32\t\t\tresponse_size;\n+\tu32\t\t\tresponse_offset;\n };\n \n /**\n@@ -93,7 +93,7 @@ struct ecore_iov_sw_mbx {\n  * @return struct ecore_iov_sw_mbx*\n  */\n struct ecore_iov_sw_mbx *ecore_iov_get_vf_sw_mbx(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t\t u16 rel_vf_id);\n+\t\t\tu16 rel_vf_id);\n #endif\n \n #ifdef CONFIG_ECORE_SRIOV\n@@ -457,9 +457,9 @@ void ecore_iov_get_vf_req_virt_mbx_params(struct ecore_hwfn *p_hwfn,\n  * @param p_reply_virt_size\n  */\n void ecore_iov_get_vf_reply_virt_mbx_params(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t    u16 rel_vf_id,\n+\t\t\t\t\t    u16\trel_vf_id,\n \t\t\t\t\t    void **pp_reply_virt_addr,\n-\t\t\t\t\t    u16 *p_reply_virt_size);\n+\t\t\t\t\t    u16\t*p_reply_virt_size);\n \n /**\n  * @brief Validate if the given length is a valid vfpf message\ndiff --git a/drivers/net/qede/base/ecore_iro.h b/drivers/net/qede/base/ecore_iro.h\nindex dd53ea9..7cabdf7 100644\n--- a/drivers/net/qede/base/ecore_iro.h\n+++ b/drivers/net/qede/base/ecore_iro.h\n@@ -10,24 +10,24 @@\n #define __IRO_H__\n \n /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */\n-#define YSTORM_FLOW_CONTROL_MODE_OFFSET\t\t(IRO[0].base)\n-#define YSTORM_FLOW_CONTROL_MODE_SIZE\t\t(IRO[0].size)\n+#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)\n+#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)\n /* Tstorm port statistics */\n #define TSTORM_PORT_STAT_OFFSET(port_id) \\\n (IRO[1].base + ((port_id) * IRO[1].m1))\n-#define TSTORM_PORT_STAT_SIZE\t\t\t(IRO[1].size)\n+#define TSTORM_PORT_STAT_SIZE (IRO[1].size)\n /* Ustorm VF-PF Channel ready flag */\n #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \\\n (IRO[3].base + ((vf_id) * IRO[3].m1))\n-#define USTORM_VF_PF_CHANNEL_READY_SIZE\t\t(IRO[3].size)\n+#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)\n /* Ustorm Final flr cleanup ack */\n #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \\\n (IRO[4].base + ((pf_id) * IRO[4].m1))\n-#define USTORM_FLR_FINAL_ACK_SIZE\t\t(IRO[4].size)\n+#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)\n /* Ustorm Event ring consumer */\n #define USTORM_EQE_CONS_OFFSET(pf_id) \\\n (IRO[5].base + ((pf_id) * IRO[5].m1))\n-#define USTORM_EQE_CONS_SIZE\t\t\t(IRO[5].size)\n+#define USTORM_EQE_CONS_SIZE (IRO[5].size)\n /* Ustorm Common Queue ring consumer */\n #define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \\\n (IRO[6].base + ((global_queue_id) * IRO[6].m1))\ndiff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h\nindex c818b58..548ad14 100644\n--- a/drivers/net/qede/base/ecore_iro_values.h\n+++ b/drivers/net/qede/base/ecore_iro_values.h\n@@ -10,49 +10,49 @@\n #define __IRO_VALUES_H__\n \n static const struct iro iro_arr[44] = {\n-\t{0x0, 0x0, 0x0, 0x0, 0x8},\n+\t{      0x0,      0x0,      0x0,      0x0,      0x8},\n \t{0x4db0, 0x60, 0x0, 0x0, 0x60},\n \t{0x6418, 0x20, 0x0, 0x0, 0x20},\n \t{0x500, 0x8, 0x0, 0x0, 0x4},\n \t{0x480, 0x8, 0x0, 0x0, 0x4},\n-\t{0x0, 0x8, 0x0, 0x0, 0x2},\n+\t{      0x0,      0x8,      0x0,      0x0,      0x2},\n \t{0x80, 0x8, 0x0, 0x0, 0x2},\n \t{0x4938, 0x0, 0x0, 0x0, 0x78},\n-\t{0x3df0, 0x0, 0x0, 0x0, 0x78},\n-\t{0x29b0, 0x0, 0x0, 0x0, 0x78},\n+\t{   0x3df0,      0x0,      0x0,      0x0,     0x78},\n+\t{   0x29b0,      0x0,      0x0,      0x0,     0x78},\n \t{0x4d38, 0x0, 0x0, 0x0, 0x78},\n \t{0x56c8, 0x0, 0x0, 0x0, 0x78},\n-\t{0x7e48, 0x0, 0x0, 0x0, 0x78},\n-\t{0xa28, 0x8, 0x0, 0x0, 0x8},\n+\t{   0x7e48,      0x0,      0x0,      0x0,     0x78},\n+\t{    0xa28,      0x8,      0x0,      0x0,      0x8},\n \t{0x61f8, 0x10, 0x0, 0x0, 0x10},\n \t{0xb500, 0x30, 0x0, 0x0, 0x30},\n-\t{0x95b8, 0x30, 0x0, 0x0, 0x30},\n+\t{   0x95b8,     0x30,      0x0,      0x0,     0x30},\n \t{0x5898, 0x40, 0x0, 0x0, 0x40},\n \t{0x1f8, 0x10, 0x0, 0x0, 0x8},\n \t{0xa228, 0x0, 0x0, 0x0, 0x4},\n-\t{0x8050, 0x40, 0x0, 0x0, 0x30},\n+\t{   0x8050,     0x40,      0x0,      0x0,     0x30},\n \t{0xcf8, 0x8, 0x0, 0x0, 0x8},\n-\t{0x2b48, 0x80, 0x0, 0x0, 0x38},\n+\t{   0x2b48,     0x80,      0x0,      0x0,     0x38},\n \t{0xadf0, 0x0, 0x0, 0x0, 0xf0},\n \t{0xaee0, 0x8, 0x0, 0x0, 0x8},\n \t{0x80, 0x8, 0x0, 0x0, 0x8},\n-\t{0xac0, 0x8, 0x0, 0x0, 0x8},\n-\t{0x2578, 0x8, 0x0, 0x0, 0x8},\n-\t{0x24f8, 0x8, 0x0, 0x0, 0x8},\n-\t{0x0, 0x8, 0x0, 0x0, 0x8},\n-\t{0x200, 0x10, 0x8, 0x0, 0x8},\n+\t{    0xac0,      0x8,      0x0,      0x0,      0x8},\n+\t{   0x2578,      0x8,      0x0,      0x0,      0x8},\n+\t{   0x24f8,      0x8,      0x0,      0x0,      0x8},\n+\t{      0x0,      0x8,      0x0,      0x0,      0x8},\n+\t{    0x200,     0x10,      0x8,      0x0,      0x8},\n \t{0x17f8, 0x8, 0x0, 0x0, 0x2},\n \t{0x19f8, 0x10, 0x8, 0x0, 0x2},\n \t{0xd988, 0x38, 0x0, 0x0, 0x24},\n \t{0x11040, 0x10, 0x0, 0x0, 0x8},\n \t{0x11670, 0x38, 0x0, 0x0, 0x18},\n \t{0xaeb8, 0x30, 0x0, 0x0, 0x10},\n-\t{0x86f8, 0x28, 0x0, 0x0, 0x18},\n+\t{   0x86f8,     0x28,      0x0,      0x0,     0x18},\n \t{0xebf8, 0x10, 0x0, 0x0, 0x10},\n \t{0xde08, 0x40, 0x0, 0x0, 0x30},\n \t{0x121a0, 0x38, 0x0, 0x0, 0x8},\n \t{0xf060, 0x20, 0x0, 0x0, 0x20},\n-\t{0x2b80, 0x80, 0x0, 0x0, 0x10},\n+\t{   0x2b80,     0x80,      0x0,      0x0,     0x10},\n \t{0x50a0, 0x10, 0x0, 0x0, 0x10},\n };\n \ndiff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c\nindex 9e6ef5a..b31523b 100644\n--- a/drivers/net/qede/base/ecore_l2.c\n+++ b/drivers/net/qede/base/ecore_l2.c\n@@ -234,7 +234,7 @@ ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,\n \n \t\tSET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,\n \t\t\t  !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||\n-\t\t\t    !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));\n+\t\t\t   !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));\n \n \t\tSET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,\n \t\t\t  !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));\n@@ -429,7 +429,7 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,\n \n \trc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);\n \tif (rc != ECORE_SUCCESS) {\n-\t\t/* Return spq entry which is taken in ecore_sp_init_request() */\n+\t\t/* Return spq entry which is taken in ecore_sp_init_request()*/\n \t\tecore_spq_return_entry(p_hwfn, p_ent);\n \t\treturn rc;\n \t}\n@@ -632,7 +632,7 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t dma_addr_t bd_chain_phys_addr,\n \t\t\t\t\t\t dma_addr_t cqe_pbl_addr,\n \t\t\t\t\t\t u16 cqe_pbl_size,\n-\t\t\t\t\t\t void OSAL_IOMEM * *pp_prod)\n+\t\t\t\t\t\t void OSAL_IOMEM **pp_prod)\n {\n \tstruct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];\n \tu8 abs_stats_id = 0;\n@@ -788,7 +788,7 @@ ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,\n \t * In addition, VFs require the answer to come as eqe to PF.\n \t */\n \tp_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==\n-\t\t\t\t\t  p_hwfn->hw_info.opaque_fid) &&\n+\t\t\t\t\t p_hwfn->hw_info.opaque_fid) &&\n \t\t\t\t      !eq_completion_only) || cqe_completion;\n \tp_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==\n \t\t\t\t\t p_hwfn->hw_info.opaque_fid) ||\n@@ -876,7 +876,7 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t u8 sb_index,\n \t\t\t\t\t\t dma_addr_t pbl_addr,\n \t\t\t\t\t\t u16 pbl_size,\n-\t\t\t\t\t\t void OSAL_IOMEM * *pp_doorbell)\n+\t\t\t\t\t\t void OSAL_IOMEM **pp_doorbell)\n {\n \tstruct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];\n \tunion ecore_qm_pq_params pq_params;\n@@ -1274,7 +1274,7 @@ ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,\n \tu8 abs_vport_id = 0;\n \tint i;\n \n-\trc = ecore_fw_vport(p_hwfn,\n+\t\trc = ecore_fw_vport(p_hwfn,\n \t\t\t    (p_filter_cmd->opcode == ECORE_FILTER_ADD) ?\n \t\t\t    p_filter_cmd->vport_to_add_to :\n \t\t\t    p_filter_cmd->vport_to_remove_from, &abs_vport_id);\n@@ -1306,9 +1306,9 @@ ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,\n \t\t    ETH_MULTICAST_MAC_BINS_IN_REGS);\n \n \tif (p_filter_cmd->opcode == ECORE_FILTER_ADD) {\n-\t\t/* filter ADD op is explicit set op and it removes\n-\t\t *  any existing filters for the vport.\n-\t\t */\n+\t/* filter ADD op is explicit set op and it removes\n+\t*  any existing filters for the vport.\n+\t*/\n \t\tfor (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {\n \t\t\tu32 bit;\n \ndiff --git a/drivers/net/qede/base/ecore_l2.h b/drivers/net/qede/base/ecore_l2.h\nindex b0850ca..5594a08 100644\n--- a/drivers/net/qede/base/ecore_l2.h\n+++ b/drivers/net/qede/base/ecore_l2.h\n@@ -103,7 +103,7 @@ ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,\n  * @return enum _ecore_status_t\n  */\n enum _ecore_status_t\n-ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,\n+ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn\t*p_hwfn,\n \t\t\t      u16 opaque_fid,\n \t\t\t      u32 cid,\n \t\t\t      u16 rx_queue_id,\n@@ -134,7 +134,7 @@ ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,\n  * @return enum _ecore_status_t\n  */\n enum _ecore_status_t\n-ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,\n+ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn\t*p_hwfn,\n \t\t\t      u16 opaque_fid,\n \t\t\t      u16 tx_queue_id,\n \t\t\t      u32 cid,\ndiff --git a/drivers/net/qede/base/ecore_l2_api.h b/drivers/net/qede/base/ecore_l2_api.h\nindex b41dd7f..ab9aca0 100644\n--- a/drivers/net/qede/base/ecore_l2_api.h\n+++ b/drivers/net/qede/base/ecore_l2_api.h\n@@ -14,17 +14,17 @@\n \n #ifndef __EXTRACT__LINUX__\n enum ecore_rss_caps {\n-\tECORE_RSS_IPV4 = 0x1,\n-\tECORE_RSS_IPV6 = 0x2,\n-\tECORE_RSS_IPV4_TCP = 0x4,\n-\tECORE_RSS_IPV6_TCP = 0x8,\n-\tECORE_RSS_IPV4_UDP = 0x10,\n-\tECORE_RSS_IPV6_UDP = 0x20,\n+\tECORE_RSS_IPV4\t\t= 0x1,\n+\tECORE_RSS_IPV6\t\t= 0x2,\n+\tECORE_RSS_IPV4_TCP\t= 0x4,\n+\tECORE_RSS_IPV6_TCP\t= 0x8,\n+\tECORE_RSS_IPV4_UDP\t= 0x10,\n+\tECORE_RSS_IPV6_UDP\t= 0x20,\n };\n \n /* Should be the same as ETH_RSS_IND_TABLE_ENTRIES_NUM */\n #define ECORE_RSS_IND_TABLE_SIZE 128\n-#define ECORE_RSS_KEY_SIZE 10\t/* size in 32b chunks */\n+#define ECORE_RSS_KEY_SIZE 10 /* size in 32b chunks */\n #endif\n \n struct ecore_rss_params {\n@@ -35,7 +35,7 @@ struct ecore_rss_params {\n \tu8 update_rss_ind_table;\n \tu8 update_rss_key;\n \tu8 rss_caps;\n-\tu8 rss_table_size_log;\t/* The table size is 2 ^ rss_table_size_log */\n+\tu8 rss_table_size_log; /* The table size is 2 ^ rss_table_size_log */\n \tu16 rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];\n \tu32 rss_key[ECORE_RSS_KEY_SIZE];\n };\n@@ -63,8 +63,8 @@ enum ecore_filter_opcode {\n \tECORE_FILTER_ADD,\n \tECORE_FILTER_REMOVE,\n \tECORE_FILTER_MOVE,\n-\tECORE_FILTER_REPLACE,\t/* Delete all MACs and add new one instead */\n-\tECORE_FILTER_FLUSH,\t/* Removes all filters */\n+\tECORE_FILTER_REPLACE, /* Delete all MACs and add new one instead */\n+\tECORE_FILTER_FLUSH, /* Removes all filters */\n };\n \n enum ecore_filter_ucast_type {\n@@ -97,7 +97,7 @@ struct ecore_filter_mcast {\n \tenum ecore_filter_opcode opcode;\n \tu8 vport_to_add_to;\n \tu8 vport_to_remove_from;\n-\tu8 num_mc_addrs;\n+\tu8\tnum_mc_addrs;\n #define ECORE_MAX_MC_ADDRS\t64\n \tunsigned char mac[ECORE_MAX_MC_ADDRS][ETH_ALEN];\n };\n@@ -138,12 +138,12 @@ ecore_filter_mcast_cmd(struct ecore_dev *p_dev,\n /* Set \"accept\" filters */\n enum _ecore_status_t\n ecore_filter_accept_cmd(struct ecore_dev *p_dev,\n-\t\t\tu8 vport,\n-\t\t\tstruct ecore_filter_accept_flags accept_flags,\n-\t\t\tu8 update_accept_any_vlan,\n-\t\t\tu8 accept_any_vlan,\n-\t\t\tenum spq_mode comp_mode,\n-\t\t\tstruct ecore_spq_comp_cb *p_comp_data);\n+\tu8\t\t\t\t vport,\n+\tstruct ecore_filter_accept_flags accept_flags,\n+\tu8\t\t\t\t update_accept_any_vlan,\n+\tu8\t\t\t\t accept_any_vlan,\n+\tenum spq_mode\t\t\t comp_mode,\n+\tstruct ecore_spq_comp_cb\t *p_comp_data);\n \n /**\n  * @brief ecore_sp_eth_rx_queue_start - RX Queue Start Ramrod\n@@ -156,11 +156,11 @@ ecore_filter_accept_cmd(struct ecore_dev *p_dev,\n  * @param rx_queue_id\t\tRX Queue ID: Zero based, per VPort, allocated\n  *\t\t\t\tby assignment (=rssId)\n  * @param vport_id\t\tVPort ID\n- * @param u8 stats_id           VPort ID which the queue stats\n+ * @param u8 stats_id\t\t VPort ID which the queue stats\n  *\t\t\t\twill be added to\n  * @param sb\t\t\tStatus Block of the Function Event Ring\n  * @param sb_index\t\tIndex into the status block of the\n- *\t\t\tFunction Event Ring\n+ *\t\t\t\tFunction Event Ring\n  * @param bd_max_bytes\t\tMaximum bytes that can be placed on a BD\n  * @param bd_chain_phys_addr\tPhysical address of BDs for receive.\n  * @param cqe_pbl_addr\t\tPhysical address of the CQE PBL Table.\n@@ -182,7 +182,7 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t dma_addr_t bd_chain_phys_addr,\n \t\t\t\t\t\t dma_addr_t cqe_pbl_addr,\n \t\t\t\t\t\t u16 cqe_pbl_size,\n-\t\t\t\t\t\t void OSAL_IOMEM * *pp_prod);\n+\t\t\t\t\t\t void OSAL_IOMEM **pp_prod);\n \n /**\n  * @brief ecore_sp_eth_rx_queue_stop -\n@@ -224,7 +224,7 @@ ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,\n  * @param pbl_addr\t\taddress of the pbl array\n  * @param pbl_size\t\tnumber of entries in pbl\n  * @param pp_doorbell\t\tPointer to place doorbell pointer (May be NULL).\n- *\t\t\tThis address should be used with the\n+ *\t\t\t\tThis address should be used with the\n  *\t\t\t\tDIRECT_REG_WR macro.\n  *\n  * @return enum _ecore_status_t\n@@ -255,7 +255,7 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,\n enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\tu16 tx_queue_id);\n \n-enum ecore_tpa_mode {\n+enum ecore_tpa_mode\t{\n \tECORE_TPA_MODE_NONE,\n \tECORE_TPA_MODE_RSC,\n \tECORE_TPA_MODE_GRO,\n@@ -293,28 +293,28 @@ ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,\n \t\t     struct ecore_sp_vport_start_params *p_params);\n \n struct ecore_sp_vport_update_params {\n-\tu16 opaque_fid;\n-\tu8 vport_id;\n-\tu8 update_vport_active_rx_flg;\n-\tu8 vport_active_rx_flg;\n-\tu8 update_vport_active_tx_flg;\n-\tu8 vport_active_tx_flg;\n-\tu8 update_inner_vlan_removal_flg;\n-\tu8 inner_vlan_removal_flg;\n-\tu8 silent_vlan_removal_flg;\n-\tu8 update_default_vlan_enable_flg;\n-\tu8 default_vlan_enable_flg;\n-\tu8 update_default_vlan_flg;\n-\tu16 default_vlan;\n-\tu8 update_tx_switching_flg;\n-\tu8 tx_switching_flg;\n-\tu8 update_approx_mcast_flg;\n-\tu8 update_anti_spoofing_en_flg;\n-\tu8 anti_spoofing_en;\n-\tu8 update_accept_any_vlan_flg;\n-\tu8 accept_any_vlan;\n-\tunsigned long bins[8];\n-\tstruct ecore_rss_params *rss_params;\n+\tu16\t\t\topaque_fid;\n+\tu8\t\t\tvport_id;\n+\tu8\t\t\tupdate_vport_active_rx_flg;\n+\tu8\t\t\tvport_active_rx_flg;\n+\tu8\t\t\tupdate_vport_active_tx_flg;\n+\tu8\t\t\tvport_active_tx_flg;\n+\tu8\t\t\tupdate_inner_vlan_removal_flg;\n+\tu8\t\t\tinner_vlan_removal_flg;\n+\tu8\t\t\tsilent_vlan_removal_flg;\n+\tu8\t\t\tupdate_default_vlan_enable_flg;\n+\tu8\t\t\tdefault_vlan_enable_flg;\n+\tu8\t\t\tupdate_default_vlan_flg;\n+\tu16\t\t\tdefault_vlan;\n+\tu8\t\t\tupdate_tx_switching_flg;\n+\tu8\t\t\ttx_switching_flg;\n+\tu8\t\t\tupdate_approx_mcast_flg;\n+\tu8\t\t\tupdate_anti_spoofing_en_flg;\n+\tu8\t\t\tanti_spoofing_en;\n+\tu8\t\t\tupdate_accept_any_vlan_flg;\n+\tu8\t\t\taccept_any_vlan;\n+\tunsigned long\t\tbins[8];\n+\tstruct ecore_rss_params\t*rss_params;\n \tstruct ecore_filter_accept_flags accept_flags;\n \tstruct ecore_sge_tpa_params *sge_tpa_params;\n };\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 9dd2eed..2823113 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -333,7 +333,7 @@ enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,\n }\n \n enum _ecore_status_t ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t     struct ecore_ptt *p_ptt,\n+\t\t\tstruct ecore_ptt *p_ptt,\n \t\t\t\t\t     u32 cmd, u32 param,\n \t\t\t\t\t     union drv_union_data *p_union_data,\n \t\t\t\t\t     u32 *o_mcp_resp,\n@@ -354,18 +354,18 @@ enum _ecore_status_t ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,\n \tOSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);\n \n \tif (p_union_data != OSAL_NULL) {\n-\t\tunion_data_addr = p_hwfn->mcp_info->drv_mb_addr +\n-\t\t    OFFSETOF(struct public_drv_mb, union_data);\n+\tunion_data_addr = p_hwfn->mcp_info->drv_mb_addr +\n+\t\t\t  OFFSETOF(struct public_drv_mb, union_data);\n \t\tecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, p_union_data,\n \t\t\t\tsizeof(*p_union_data));\n-\t}\n+}\n \n \trc = ecore_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, o_mcp_resp,\n \t\t\t      o_mcp_param);\n \n \tOSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);\n \n-\treturn rc;\n+\t\treturn rc;\n }\n \n enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,\n@@ -577,7 +577,7 @@ static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,\n \n \tDP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),\n \t\t   \"Received transceiver state update [0x%08x] from mfw\"\n-\t\t   \"[Addr 0x%x]\\n\",\n+\t\t   \" [Addr 0x%x]\\n\",\n \t\t   transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +\n \t\t\t\t\t    OFFSETOF(struct public_port,\n \t\t\t\t\t\t     transceiver_data)));\n@@ -661,18 +661,18 @@ static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,\n \tif (p_hwfn->mcp_info->func_info.bandwidth_max && p_link->speed) {\n \t\tu8 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;\n \n-\t\t__ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,\n-\t\t\t\t\t\t   p_link, max_bw);\n+\t__ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,\n+\t\t\t\t\t   p_link, max_bw);\n \t}\n \n \tif (p_hwfn->mcp_info->func_info.bandwidth_min && p_link->speed) {\n \t\tu8 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;\n \n-\t\t__ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,\n-\t\t\t\t\t\t   p_link, min_bw);\n+\t__ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,\n+\t\t\t\t\t   p_link, min_bw);\n \n-\t\tecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,\n-\t\t\t\t\t\t      p_link->min_pf_rate);\n+\tecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,\n+\t\t\t\t\t      p_link->min_pf_rate);\n \t}\n \n \tp_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);\n@@ -1090,8 +1090,8 @@ enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev,\n \n \t\tDP_VERBOSE(p_dev, ECORE_MSG_IOV,\n \t\t\t   \"VF requested MFW vers prior to ACQUIRE\\n\");\n-\t\treturn ECORE_INVAL;\n-\t}\n+\t\t\treturn ECORE_INVAL;\n+\t\t}\n \n \tglobal_offsize = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t  SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->\ndiff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h\nindex 448c30b..7af4349 100644\n--- a/drivers/net/qede/base/ecore_mcp.h\n+++ b/drivers/net/qede/base/ecore_mcp.h\n@@ -38,10 +38,10 @@ struct ecore_mcp_info {\n \tu32 port_addr;\t\t/* Address of the port configuration (link) */\n \tu16 drv_mb_seq;\t\t/* Current driver mailbox sequence */\n \tu16 drv_pulse_seq;\t/* Current driver pulse sequence */\n-\tstruct ecore_mcp_link_params link_input;\n-\tstruct ecore_mcp_link_state link_output;\n+\tstruct ecore_mcp_link_params       link_input;\n+\tstruct ecore_mcp_link_state\t   link_output;\n \tstruct ecore_mcp_link_capabilities link_capabilities;\n-\tstruct ecore_mcp_function_info func_info;\n+\tstruct ecore_mcp_function_info\t   func_info;\n \n \tu8 *mfw_mb_cur;\n \tu8 *mfw_mb_shadow;\ndiff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h\nindex 7360b35..530c0ec 100644\n--- a/drivers/net/qede/base/ecore_mcp_api.h\n+++ b/drivers/net/qede/base/ecore_mcp_api.h\n@@ -13,8 +13,8 @@\n \n struct ecore_mcp_link_speed_params {\n \tbool autoneg;\n-\tu32 advertised_speeds;\t/* bitmask of DRV_SPEED_CAPABILITY */\n-\tu32 forced_speed;\t/* In Mb/s */\n+\tu32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */\n+\tu32 forced_speed; /* In Mb/s */\n };\n \n struct ecore_mcp_link_pause_params {\n@@ -26,7 +26,7 @@ struct ecore_mcp_link_pause_params {\n struct ecore_mcp_link_params {\n \tstruct ecore_mcp_link_speed_params speed;\n \tstruct ecore_mcp_link_pause_params pause;\n-\tu32 loopback_mode;\t/* in PMM_LOOPBACK values */\n+\tu32 loopback_mode; /* in PMM_LOOPBACK values */\n };\n \n struct ecore_mcp_link_capabilities {\n@@ -36,9 +36,9 @@ struct ecore_mcp_link_capabilities {\n struct ecore_mcp_link_state {\n \tbool link_up;\n \n-\tu32 line_speed;\t\t/* In Mb/s */\n-\tu32 min_pf_rate;\t/* In Mb/s */\n-\tu32 speed;\t\t/* In Mb/s */\n+\tu32 line_speed; /* In Mb/s */\n+\tu32 min_pf_rate; /* In Mb/s */\n+\tu32 speed; /* In Mb/s */\n \tbool full_duplex;\n \n \tbool an;\n@@ -237,7 +237,7 @@ enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev,\n  *      ECORE_BUSY - Operation failed\n  */\n enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,\n-\t\t\t\t\t      u32 *media_type);\n+\t\t\t\t\t   u32 *media_type);\n \n /**\n  * @brief - Sends a command to the MCP mailbox.\n@@ -542,7 +542,7 @@ enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,\n  * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.\n  */\n enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,\n-\t\t\t\t\tu8 *p_buf, u32 len);\n+\t\t\t   u8 *p_buf, u32 len);\n \n /**\n  * @brief Read from sfp\ndiff --git a/drivers/net/qede/base/ecore_proto_if.h b/drivers/net/qede/base/ecore_proto_if.h\nindex 2fecbc8..bcbd9f0 100644\n--- a/drivers/net/qede/base/ecore_proto_if.h\n+++ b/drivers/net/qede/base/ecore_proto_if.h\n@@ -18,11 +18,11 @@ struct ecore_eth_pf_params {\n \t * and these parameters need to be passed as arguments\n \t * to update_pf_params routine invoked before slowpath start\n \t */\n-\tu16 num_cons;\n+\tu16\tnum_cons;\n };\n \n struct ecore_pf_params {\n-\tstruct ecore_eth_pf_params eth_pf_params;\n+\tstruct ecore_eth_pf_params\teth_pf_params;\n };\n \n #endif\ndiff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h\nindex 1f5139e..cc8a8ed 100644\n--- a/drivers/net/qede/base/ecore_rt_defs.h\n+++ b/drivers/net/qede/base/ecore_rt_defs.h\n@@ -10,93 +10,93 @@\n #define __RT_DEFS_H__\n \n /* Runtime array offsets */\n-#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET\t0\n-#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET\t1\n-#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET\t2\n-#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET\t3\n-#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET\t4\n-#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET\t5\n-#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET\t6\n-#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET\t7\n-#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET\t8\n-#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET\t9\n-#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET\t10\n-#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET\t11\n-#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET\t12\n-#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET\t13\n-#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET\t14\n-#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET\t15\n-#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET\t\t16\n-#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET\t\t17\n-#define IGU_REG_PF_CONFIGURATION_RT_OFFSET\t\t18\n-#define IGU_REG_VF_CONFIGURATION_RT_OFFSET\t\t19\n-#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET\t\t20\n-#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET\t\t21\n-#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET\t\t22\n-#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET\t\t23\n-#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET\t\t24\n-#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET\t\t761\n-#define CAU_REG_SB_VAR_MEMORY_RT_SIZE\t\t736\n-#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET\t\t761\n-#define CAU_REG_SB_VAR_MEMORY_RT_SIZE\t\t736\n-#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET\t1497\n-#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE\t\t736\n-#define CAU_REG_PI_MEMORY_RT_OFFSET\t\t2233\n-#define CAU_REG_PI_MEMORY_RT_SIZE\t\t4416\n-#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET\t\t6649\n-#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET\t\t6650\n-#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET\t\t6651\n-#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET\t6652\n-#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET\t6653\n-#define PRS_REG_SEARCH_TCP_RT_OFFSET\t\t6654\n-#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET\t\t6659\n-#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET\t\t6660\n-#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET\t\t6661\n-#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET\t\t6662\n-#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET\t\t6663\n-#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET\t6664\n-#define SRC_REG_FIRSTFREE_RT_OFFSET\t\t6665\n-#define SRC_REG_FIRSTFREE_RT_SIZE\t\t2\n-#define SRC_REG_LASTFREE_RT_OFFSET\t\t6667\n-#define SRC_REG_LASTFREE_RT_SIZE\t\t2\n-#define SRC_REG_COUNTFREE_RT_OFFSET\t\t6669\n-#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET\t\t6670\n-#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET\t6671\n-#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET\t6672\n-#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET\t\t6673\n-#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET\t\t6674\n-#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET\t\t6675\n-#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET\t6676\n-#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET\t\t6677\n-#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET\t6678\n-#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET\t\t6679\n-#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET\t6680\n-#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET\t\t6681\n-#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET\t\t6682\n-#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET\t\t6683\n-#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET\t\t6684\n-#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET\t\t6685\n-#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET\t\t6686\n-#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET\t\t6687\n-#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET\t\t6688\n-#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET\t\t6689\n-#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET\t6690\n-#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET\t6691\n-#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET\t\t6692\n-#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET\t\t6693\n-#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET\t\t6694\n-#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET\t\t6695\n-#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET\t6696\n-#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET\t6697\n-#define PSWRQ2_REG_VF_BASE_RT_OFFSET\t\t6698\n-#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET\t6699\n-#define PSWRQ2_REG_WR_MBS0_RT_OFFSET\t\t6700\n-#define PSWRQ2_REG_RD_MBS0_RT_OFFSET\t\t6701\n-#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET\t\t6702\n-#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET\t\t6703\n-#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET\t\t6704\n-#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE\t\t22000\n-#define PGLUE_REG_B_VF_BASE_RT_OFFSET\t\t28704\n+#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                            0\n+#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                            1\n+#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                            2\n+#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                            3\n+#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                            4\n+#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                            5\n+#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                            6\n+#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                            7\n+#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                            8\n+#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                            9\n+#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                            10\n+#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                            11\n+#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                            12\n+#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                            13\n+#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                            14\n+#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                            15\n+#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                              16\n+#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET                           17\n+#define IGU_REG_PF_CONFIGURATION_RT_OFFSET                          18\n+#define IGU_REG_VF_CONFIGURATION_RT_OFFSET                          19\n+#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                           20\n+#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                           21\n+#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                        22\n+#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                       23\n+#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                         24\n+#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                             761\n+#define CAU_REG_SB_VAR_MEMORY_RT_SIZE                               736\n+#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                             761\n+#define CAU_REG_SB_VAR_MEMORY_RT_SIZE                               736\n+#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                            1497\n+#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                              736\n+#define CAU_REG_PI_MEMORY_RT_OFFSET                                 2233\n+#define CAU_REG_PI_MEMORY_RT_SIZE                                   4416\n+#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET                6649\n+#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET                  6650\n+#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET                  6651\n+#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                     6652\n+#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                     6653\n+#define PRS_REG_SEARCH_TCP_RT_OFFSET                                6654\n+#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                           6659\n+#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET                 6660\n+#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET       6661\n+#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET                  6662\n+#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET                           6663\n+#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                     6664\n+#define SRC_REG_FIRSTFREE_RT_OFFSET                                 6665\n+#define SRC_REG_FIRSTFREE_RT_SIZE                                   2\n+#define SRC_REG_LASTFREE_RT_OFFSET                                  6667\n+#define SRC_REG_LASTFREE_RT_SIZE                                    2\n+#define SRC_REG_COUNTFREE_RT_OFFSET                                 6669\n+#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                          6670\n+#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                            6671\n+#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                            6672\n+#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                              6673\n+#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                              6674\n+#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                             6675\n+#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET                            6676\n+#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                           6677\n+#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                            6678\n+#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                           6679\n+#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                            6680\n+#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                          6681\n+#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                           6682\n+#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                         6683\n+#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                          6684\n+#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                         6685\n+#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                          6686\n+#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                         6687\n+#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                          6688\n+#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET                 6689\n+#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET               6690\n+#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET               6691\n+#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                           6692\n+#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                         6693\n+#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                         6694\n+#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                       6695\n+#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                     6696\n+#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                     6697\n+#define PSWRQ2_REG_VF_BASE_RT_OFFSET                                6698\n+#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                            6699\n+#define PSWRQ2_REG_WR_MBS0_RT_OFFSET                                6700\n+#define PSWRQ2_REG_RD_MBS0_RT_OFFSET                                6701\n+#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                          6702\n+#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                          6703\n+#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                             6704\n+#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                               22000\n+#define PGLUE_REG_B_VF_BASE_RT_OFFSET                               28704\n #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET\t\t28705\n #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET\t\t28706\n #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET\t\t28707\n@@ -107,9 +107,9 @@\n #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET\t\t28712\n #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET\t\t28713\n #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET\t28714\n-#define TM_REG_CONFIG_CONN_MEM_RT_SIZE\t\t416\n+#define TM_REG_CONFIG_CONN_MEM_RT_SIZE                              416\n #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET\t29130\n-#define TM_REG_CONFIG_TASK_MEM_RT_SIZE\t\t512\n+#define TM_REG_CONFIG_TASK_MEM_RT_SIZE                              512\n #define QM_REG_MAXPQSIZE_0_RT_OFFSET\t\t29642\n #define QM_REG_MAXPQSIZE_1_RT_OFFSET\t\t29643\n #define QM_REG_MAXPQSIZE_2_RT_OFFSET\t\t29644\n@@ -178,11 +178,11 @@\n #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET\t\t29707\n #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET\t\t29708\n #define QM_REG_BASEADDROTHERPQ_RT_OFFSET\t29709\n-#define QM_REG_BASEADDROTHERPQ_RT_SIZE\t\t128\n+#define QM_REG_BASEADDROTHERPQ_RT_SIZE                              128\n #define QM_REG_VOQCRDLINE_RT_OFFSET\t\t29837\n-#define QM_REG_VOQCRDLINE_RT_SIZE\t\t20\n+#define QM_REG_VOQCRDLINE_RT_SIZE                                   20\n #define QM_REG_VOQINITCRDLINE_RT_OFFSET\t\t29857\n-#define QM_REG_VOQINITCRDLINE_RT_SIZE\t\t20\n+#define QM_REG_VOQINITCRDLINE_RT_SIZE                               20\n #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET\t\t29877\n #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET\t\t29878\n #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET\t\t29879\n@@ -303,42 +303,42 @@\n #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET\t\t29994\n #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET\t\t29995\n #define QM_REG_RLGLBLINCVAL_RT_OFFSET\t\t29996\n-#define QM_REG_RLGLBLINCVAL_RT_SIZE\t\t256\n+#define QM_REG_RLGLBLINCVAL_RT_SIZE                                 256\n #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET\t\t30252\n-#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE\t\t256\n+#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                             256\n #define QM_REG_RLGLBLCRD_RT_OFFSET\t\t30508\n-#define QM_REG_RLGLBLCRD_RT_SIZE\t\t256\n+#define QM_REG_RLGLBLCRD_RT_SIZE                                    256\n #define QM_REG_RLGLBLENABLE_RT_OFFSET\t\t30764\n #define QM_REG_RLPFPERIOD_RT_OFFSET\t\t30765\n #define QM_REG_RLPFPERIODTIMER_RT_OFFSET\t30766\n #define QM_REG_RLPFINCVAL_RT_OFFSET\t\t30767\n-#define QM_REG_RLPFINCVAL_RT_SIZE\t\t16\n+#define QM_REG_RLPFINCVAL_RT_SIZE                                   16\n #define QM_REG_RLPFUPPERBOUND_RT_OFFSET\t\t30783\n-#define QM_REG_RLPFUPPERBOUND_RT_SIZE\t\t16\n+#define QM_REG_RLPFUPPERBOUND_RT_SIZE                               16\n #define QM_REG_RLPFCRD_RT_OFFSET\t\t30799\n-#define QM_REG_RLPFCRD_RT_SIZE\t\t\t16\n+#define QM_REG_RLPFCRD_RT_SIZE                                      16\n #define QM_REG_RLPFENABLE_RT_OFFSET\t\t30815\n #define QM_REG_RLPFVOQENABLE_RT_OFFSET\t\t30816\n #define QM_REG_WFQPFWEIGHT_RT_OFFSET\t\t30817\n-#define QM_REG_WFQPFWEIGHT_RT_SIZE\t\t16\n+#define QM_REG_WFQPFWEIGHT_RT_SIZE                                  16\n #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET\t30833\n-#define QM_REG_WFQPFUPPERBOUND_RT_SIZE\t\t16\n+#define QM_REG_WFQPFUPPERBOUND_RT_SIZE                              16\n #define QM_REG_WFQPFCRD_RT_OFFSET\t\t30849\n-#define QM_REG_WFQPFCRD_RT_SIZE\t\t\t160\n+#define QM_REG_WFQPFCRD_RT_SIZE                                     160\n #define QM_REG_WFQPFENABLE_RT_OFFSET\t\t31009\n #define QM_REG_WFQVPENABLE_RT_OFFSET\t\t31010\n #define QM_REG_BASEADDRTXPQ_RT_OFFSET\t\t31011\n-#define QM_REG_BASEADDRTXPQ_RT_SIZE\t\t512\n+#define QM_REG_BASEADDRTXPQ_RT_SIZE                                 512\n #define QM_REG_TXPQMAP_RT_OFFSET\t\t31523\n-#define QM_REG_TXPQMAP_RT_SIZE\t\t\t512\n+#define QM_REG_TXPQMAP_RT_SIZE                                      512\n #define QM_REG_WFQVPWEIGHT_RT_OFFSET\t\t32035\n-#define QM_REG_WFQVPWEIGHT_RT_SIZE\t\t512\n+#define QM_REG_WFQVPWEIGHT_RT_SIZE                                  512\n #define QM_REG_WFQVPCRD_RT_OFFSET\t\t32547\n-#define QM_REG_WFQVPCRD_RT_SIZE\t\t\t512\n+#define QM_REG_WFQVPCRD_RT_SIZE                                     512\n #define QM_REG_WFQVPMAP_RT_OFFSET\t\t33059\n-#define QM_REG_WFQVPMAP_RT_SIZE\t\t\t512\n+#define QM_REG_WFQVPMAP_RT_SIZE                                     512\n #define QM_REG_WFQPFCRD_MSB_RT_OFFSET\t\t33571\n-#define QM_REG_WFQPFCRD_MSB_RT_SIZE\t\t160\n+#define QM_REG_WFQPFCRD_MSB_RT_SIZE                                 160\n #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET\t\t33731\n #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET\t33732\n #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET\t33733\n@@ -347,22 +347,22 @@\n #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET\t\t33736\n #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET\t\t33737\n #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET\t\t33738\n-#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE\t\t4\n+#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                             4\n #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET\t\t33742\n-#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE\t\t4\n+#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE                        4\n #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET\t\t33746\n-#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE\t\t4\n+#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                          4\n #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET\t\t33750\n #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET\t33751\n-#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE\t\t32\n+#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                       32\n #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET\t\t33783\n-#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE\t\t16\n+#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                          16\n #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET\t\t33799\n-#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE\t\t16\n+#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                        16\n #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET\t\t33815\n-#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE\t16\n+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE               16\n #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET\t\t33831\n-#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE\t16\n+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                     16\n #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET\t\t33847\n #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET\t\t33848\n #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET\t\t33849\ndiff --git a/drivers/net/qede/base/ecore_sp_api.h b/drivers/net/qede/base/ecore_sp_api.h\nindex e80f5ef..71e2359 100644\n--- a/drivers/net/qede/base/ecore_sp_api.h\n+++ b/drivers/net/qede/base/ecore_sp_api.h\n@@ -12,9 +12,9 @@\n #include \"ecore_status.h\"\n \n enum spq_mode {\n-\tECORE_SPQ_MODE_BLOCK,\t/* Client will poll a designated mem. address */\n-\tECORE_SPQ_MODE_CB,\t/* Client supplies a callback */\n-\tECORE_SPQ_MODE_EBLOCK,\t/* ECORE should block until completion */\n+\tECORE_SPQ_MODE_BLOCK, /* Client will poll a designated mem. address */\n+\tECORE_SPQ_MODE_CB,  /* Client supplies a callback */\n+\tECORE_SPQ_MODE_EBLOCK,  /* ECORE should block until completion */\n };\n \n struct ecore_hwfn;\n@@ -22,9 +22,9 @@ union event_ring_data;\n struct eth_slow_path_rx_cqe;\n \n struct ecore_spq_comp_cb {\n-\tvoid (*function)(struct ecore_hwfn *,\n+\tvoid\t(*function)(struct ecore_hwfn *,\n \t\t\t void *, union event_ring_data *, u8 fw_return_code);\n-\tvoid *cookie;\n+\tvoid\t*cookie;\n };\n \n /**\ndiff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c\nindex e9ac898..7ba43e8 100644\n--- a/drivers/net/qede/base/ecore_sp_commands.c\n+++ b/drivers/net/qede/base/ecore_sp_commands.c\n@@ -391,7 +391,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,\n \t\tbreak;\n \tdefault:\n \t\tDP_NOTICE(p_hwfn, true, \"Unknown personality %d\\n\",\n-\t\t\t  p_hwfn->hw_info.personality);\n+\t\t\t p_hwfn->hw_info.personality);\n \t\tp_ramrod->personality = PERSONALITY_ETH;\n \t}\n \n@@ -467,16 +467,16 @@ ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,\n \trc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);\n \n \tif ((rc == ECORE_SUCCESS) && p_tunn) {\n-\t\tif (p_tunn->update_vxlan_udp_port)\n-\t\t\tecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t\t\t  p_tunn->vxlan_udp_port);\n-\t\tif (p_tunn->update_geneve_udp_port)\n-\t\t\tecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t\t\t   p_tunn->geneve_udp_port);\n+\tif (p_tunn->update_vxlan_udp_port)\n+\t\tecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t  p_tunn->vxlan_udp_port);\n+\tif (p_tunn->update_geneve_udp_port)\n+\t\tecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t   p_tunn->geneve_udp_port);\n \n \t\tecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t\t       p_tunn->tunn_mode);\n-\t\tp_hwfn->p_dev->tunn_mode = p_tunn->tunn_mode;\n+\tp_hwfn->p_dev->tunn_mode = p_tunn->tunn_mode;\n \t}\n \n \treturn rc;\ndiff --git a/drivers/net/qede/base/ecore_sp_commands.h b/drivers/net/qede/base/ecore_sp_commands.h\nindex e281ab0..22c7462 100644\n--- a/drivers/net/qede/base/ecore_sp_commands.h\n+++ b/drivers/net/qede/base/ecore_sp_commands.h\n@@ -21,12 +21,12 @@ struct ecore_sp_init_data {\n \t * e.g., in IOV scenarios. CID might defer between SPQ and\n \t * other elements.\n \t */\n-\tu32 cid;\n-\tu16 opaque_fid;\n+\tu32\t\t\t\tcid;\n+\tu16\t\t\t\topaque_fid;\n \n \t/* Information regarding operation upon sending & completion */\n-\tenum spq_mode comp_mode;\n-\tstruct ecore_spq_comp_cb *p_comp_data;\n+\tenum spq_mode\t\t\tcomp_mode;\n+\tstruct ecore_spq_comp_cb\t*p_comp_data;\n \n };\n \ndiff --git a/drivers/net/qede/base/ecore_spq.c b/drivers/net/qede/base/ecore_spq.c\nindex b263693..1839659 100644\n--- a/drivers/net/qede/base/ecore_spq.c\n+++ b/drivers/net/qede/base/ecore_spq.c\n@@ -49,7 +49,7 @@ static void ecore_spq_blocking_cb(struct ecore_hwfn *p_hwfn,\n }\n \n static enum _ecore_status_t ecore_spq_block(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t    struct ecore_spq_entry *p_ent,\n+\t\t\t\t\t      struct ecore_spq_entry *p_ent,\n \t\t\t\t\t    u8 *p_fw_ret)\n {\n \tint sleep_count = SPQ_BLOCK_SLEEP_LENGTH;\n@@ -83,7 +83,7 @@ static enum _ecore_status_t ecore_spq_block(struct ecore_hwfn *p_hwfn,\n \t\tif (comp_done->done == 1) {\n \t\t\tif (p_fw_ret)\n \t\t\t\t*p_fw_ret = comp_done->fw_return_code;\n-\t\t\treturn ECORE_SUCCESS;\n+\t\treturn ECORE_SUCCESS;\n \t\t}\n \t\tOSAL_MSLEEP(5);\n \t\tsleep_count--;\n@@ -310,9 +310,9 @@ enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn,\n \t\t\t   p_eqe->protocol_id,\t/* Event Protocol ID */\n \t\t\t   p_eqe->reserved0,\t/* Reserved */\n \t\t\t   OSAL_LE16_TO_CPU(p_eqe->echo),\n-\t\t\t   p_eqe->fw_return_code,\t/* FW return code for SP\n-\t\t\t\t\t\t\t * ramrods\n-\t\t\t\t\t\t\t */\n+\t\t\t   p_eqe->fw_return_code,    /* FW return code for SP\n+\t\t\t\t\t\t      * ramrods\n+\t\t\t\t\t\t      */\n \t\t\t   p_eqe->flags);\n \n \t\tif (GET_FIELD(p_eqe->flags, EVENT_RING_ENTRY_ASYNC)) {\n@@ -345,7 +345,7 @@ struct ecore_eq *ecore_eq_alloc(struct ecore_hwfn *p_hwfn, u16 num_elem)\n \t\treturn OSAL_NULL;\n \t}\n \n-\t/* Allocate and initialize EQ chain */\n+\t/* Allocate and initialize EQ chain*/\n \tif (ecore_chain_alloc(p_hwfn->p_dev,\n \t\t\t      ECORE_CHAIN_USE_TO_PRODUCE,\n \t\t\t      ECORE_CHAIN_MODE_PBL,\n@@ -609,18 +609,18 @@ ecore_spq_add_entry(struct ecore_hwfn *p_hwfn,\n \t\t\treturn ECORE_SUCCESS;\n \t\t}\n \n-\t\tstruct ecore_spq_entry *p_en2;\n+\t\t\tstruct ecore_spq_entry *p_en2;\n \n-\t\tp_en2 = OSAL_LIST_FIRST_ENTRY(&p_spq->free_pool,\n-\t\t\t\t\t      struct ecore_spq_entry,\n-\t\t\t\t\t      list);\n-\t\tOSAL_LIST_REMOVE_ENTRY(&p_en2->list, &p_spq->free_pool);\n+\t\t\tp_en2 = OSAL_LIST_FIRST_ENTRY(&p_spq->free_pool,\n+\t\t\t\t\t\t     struct ecore_spq_entry,\n+\t\t\t\t\t\t     list);\n+\t\t\tOSAL_LIST_REMOVE_ENTRY(&p_en2->list, &p_spq->free_pool);\n \n-\t\t/* Copy the ring element physical pointer to the new\n-\t\t * entry, since we are about to override the entire ring\n-\t\t * entry and don't want to lose the pointer.\n-\t\t */\n-\t\tp_ent->elem.data_ptr = p_en2->elem.data_ptr;\n+\t\t\t/* Copy the ring element physical pointer to the new\n+\t\t\t * entry, since we are about to override the entire ring\n+\t\t\t * entry and don't want to lose the pointer.\n+\t\t\t */\n+\t\t\tp_ent->elem.data_ptr = p_en2->elem.data_ptr;\n \n \t\t/* Setting the cookie to the comp_done of the\n \t\t * new element.\n@@ -628,12 +628,12 @@ ecore_spq_add_entry(struct ecore_hwfn *p_hwfn,\n \t\tif (p_ent->comp_cb.cookie == &p_ent->comp_done)\n \t\t\tp_ent->comp_cb.cookie = &p_en2->comp_done;\n \n-\t\t*p_en2 = *p_ent;\n+\t\t\t*p_en2 = *p_ent;\n \n-\t\tOSAL_FREE(p_hwfn->p_dev, p_ent);\n+\t\t\t\tOSAL_FREE(p_hwfn->p_dev, p_ent);\n \n-\t\tp_ent = p_en2;\n-\t}\n+\t\t\tp_ent = p_en2;\n+\t\t}\n \n \t/* entry is to be placed in 'pending' queue */\n \tswitch (priority) {\n@@ -682,18 +682,18 @@ static enum _ecore_status_t ecore_spq_post_list(struct ecore_hwfn *p_hwfn,\n \t       !OSAL_LIST_IS_EMPTY(head)) {\n \t\tstruct ecore_spq_entry *p_ent =\n \t\t    OSAL_LIST_FIRST_ENTRY(head, struct ecore_spq_entry, list);\n-\t\tOSAL_LIST_REMOVE_ENTRY(&p_ent->list, head);\n+\t\t\tOSAL_LIST_REMOVE_ENTRY(&p_ent->list, head);\n \t\tOSAL_LIST_PUSH_TAIL(&p_ent->list, &p_spq->completion_pending);\n-\t\tp_spq->comp_sent_count++;\n-\n-\t\trc = ecore_spq_hw_post(p_hwfn, p_spq, p_ent);\n-\t\tif (rc) {\n-\t\t\tOSAL_LIST_REMOVE_ENTRY(&p_ent->list,\n-\t\t\t\t\t       &p_spq->completion_pending);\n-\t\t\t__ecore_spq_return_entry(p_hwfn, p_ent);\n-\t\t\treturn rc;\n+\t\t\tp_spq->comp_sent_count++;\n+\n+\t\t\trc = ecore_spq_hw_post(p_hwfn, p_spq, p_ent);\n+\t\t\tif (rc) {\n+\t\t\t\tOSAL_LIST_REMOVE_ENTRY(&p_ent->list,\n+\t\t\t\t\t\t    &p_spq->completion_pending);\n+\t\t\t\t__ecore_spq_return_entry(p_hwfn, p_ent);\n+\t\t\t\treturn rc;\n+\t\t\t}\n \t\t}\n-\t}\n \n \treturn ECORE_SUCCESS;\n }\ndiff --git a/drivers/net/qede/base/ecore_spq.h b/drivers/net/qede/base/ecore_spq.h\nindex 5c16865..74484ab 100644\n--- a/drivers/net/qede/base/ecore_spq.h\n+++ b/drivers/net/qede/base/ecore_spq.h\n@@ -16,24 +16,24 @@\n #include \"ecore_sp_api.h\"\n \n union ramrod_data {\n-\tstruct pf_start_ramrod_data pf_start;\n-\tstruct pf_update_ramrod_data pf_update;\n-\tstruct rx_queue_start_ramrod_data rx_queue_start;\n-\tstruct rx_queue_update_ramrod_data rx_queue_update;\n-\tstruct rx_queue_stop_ramrod_data rx_queue_stop;\n-\tstruct tx_queue_start_ramrod_data tx_queue_start;\n-\tstruct tx_queue_stop_ramrod_data tx_queue_stop;\n-\tstruct vport_start_ramrod_data vport_start;\n-\tstruct vport_stop_ramrod_data vport_stop;\n-\tstruct vport_update_ramrod_data vport_update;\n-\tstruct core_rx_start_ramrod_data core_rx_queue_start;\n-\tstruct core_rx_stop_ramrod_data core_rx_queue_stop;\n-\tstruct core_tx_start_ramrod_data core_tx_queue_start;\n-\tstruct core_tx_stop_ramrod_data core_tx_queue_stop;\n-\tstruct vport_filter_update_ramrod_data vport_filter_update;\n-\n-\tstruct vf_start_ramrod_data vf_start;\n-\tstruct vf_stop_ramrod_data vf_stop;\n+\tstruct pf_start_ramrod_data\t\t\tpf_start;\n+\tstruct pf_update_ramrod_data\t\t\tpf_update;\n+\tstruct rx_queue_start_ramrod_data\t\trx_queue_start;\n+\tstruct rx_queue_update_ramrod_data\t\trx_queue_update;\n+\tstruct rx_queue_stop_ramrod_data\t\trx_queue_stop;\n+\tstruct tx_queue_start_ramrod_data\t\ttx_queue_start;\n+\tstruct tx_queue_stop_ramrod_data\t\ttx_queue_stop;\n+\tstruct vport_start_ramrod_data\t\t\tvport_start;\n+\tstruct vport_stop_ramrod_data\t\t\tvport_stop;\n+\tstruct vport_update_ramrod_data\t\t\tvport_update;\n+\tstruct core_rx_start_ramrod_data\t\tcore_rx_queue_start;\n+\tstruct core_rx_stop_ramrod_data\t\t\tcore_rx_queue_stop;\n+\tstruct core_tx_start_ramrod_data\t\tcore_tx_queue_start;\n+\tstruct core_tx_stop_ramrod_data\t\t\tcore_tx_queue_stop;\n+\tstruct vport_filter_update_ramrod_data\t\tvport_filter_update;\n+\n+\tstruct vf_start_ramrod_data\t\t\tvf_start;\n+\tstruct vf_stop_ramrod_data\t\t\tvf_stop;\n };\n \n #define EQ_MAX_CREDIT\t0xffffffff\n@@ -45,83 +45,83 @@ enum spq_priority {\n \n union ecore_spq_req_comp {\n \tstruct ecore_spq_comp_cb cb;\n-\tu64 *done_addr;\n+\tu64\t\t\t *done_addr;\n };\n \n /* SPQ_MODE_EBLOCK */\n struct ecore_spq_comp_done {\n \tu64 done;\n-\tu8 fw_return_code;\n+\tu8  fw_return_code;\n };\n \n struct ecore_spq_entry {\n-\tosal_list_entry_t list;\n+\tosal_list_entry_t\t\tlist;\n \n-\tu8 flags;\n+\tu8\t\t\t\tflags;\n \n \t/* HSI slow path element */\n-\tstruct slow_path_element elem;\n+\tstruct slow_path_element\telem;\n \n-\tunion ramrod_data ramrod;\n+\tunion ramrod_data\t\tramrod;\n \n-\tenum spq_priority priority;\n+\tenum spq_priority\t\tpriority;\n \n \t/* pending queue for this entry */\n-\tosal_list_t *queue;\n+\tosal_list_t\t\t\t*queue;\n \n-\tenum spq_mode comp_mode;\n-\tstruct ecore_spq_comp_cb comp_cb;\n-\tstruct ecore_spq_comp_done comp_done;\t/* SPQ_MODE_EBLOCK */\n+\tenum spq_mode\t\t\tcomp_mode;\n+\tstruct ecore_spq_comp_cb\tcomp_cb;\n+\tstruct ecore_spq_comp_done\tcomp_done; /* SPQ_MODE_EBLOCK */\n };\n \n struct ecore_eq {\n-\tstruct ecore_chain chain;\n-\tu8 eq_sb_index;\t\t/* index within the SB */\n-\t__le16 *p_fw_cons;\t/* ptr to index value */\n+\tstruct ecore_chain\tchain;\n+\tu8\t\t\teq_sb_index;\t/* index within the SB */\n+\t__le16\t\t\t*p_fw_cons;\t/* ptr to index value */\n };\n \n struct ecore_consq {\n-\tstruct ecore_chain chain;\n+\tstruct ecore_chain\tchain;\n };\n \n struct ecore_spq {\n-\tosal_spinlock_t lock;\n+\tosal_spinlock_t\t\t\tlock;\n \n-\tosal_list_t unlimited_pending;\n-\tosal_list_t pending;\n-\tosal_list_t completion_pending;\n-\tosal_list_t free_pool;\n+\tosal_list_t\t\t\tunlimited_pending;\n+\tosal_list_t\t\t\tpending;\n+\tosal_list_t\t\t\tcompletion_pending;\n+\tosal_list_t\t\t\tfree_pool;\n \n-\tstruct ecore_chain chain;\n+\tstruct ecore_chain\t\tchain;\n \n \t/* allocated dma-able memory for spq entries (+ramrod data) */\n-\tdma_addr_t p_phys;\n-\tstruct ecore_spq_entry *p_virt;\n+\tdma_addr_t\t\t\tp_phys;\n+\tstruct ecore_spq_entry\t\t*p_virt;\n \n \t/* Bitmap for handling out-of-order completions */\n-#define SPQ_RING_SIZE\t\t\t\t\t\t\\\n+#define SPQ_RING_SIZE\t\t\\\n \t(CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element))\n #define SPQ_COMP_BMAP_SIZE\t\t\t\t\t\\\n (SPQ_RING_SIZE / (sizeof(unsigned long) * 8 /* BITS_PER_LONG */))\n-\tunsigned long p_comp_bitmap[SPQ_COMP_BMAP_SIZE];\n-\tu8 comp_bitmap_idx;\n-#define SPQ_COMP_BMAP_SET_BIT(p_spq, idx)\t\t\t\\\n-(OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n+\tunsigned long\t\t\tp_comp_bitmap[SPQ_COMP_BMAP_SIZE];\n+\tu8\t\t\t\tcomp_bitmap_idx;\n+#define SPQ_COMP_BMAP_SET_BIT(p_spq, idx)\t\t\t\t\\\n+\t(OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n \n-#define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx)\t\t\t\\\n-(OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n+#define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx)\t\t\t\t\\\n+\t(OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n \n-#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx)\t\t\t\\\n-(OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n+#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx)\t\\\n+\t(OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n \n \t/* Statistics */\n-\tu32 unlimited_pending_count;\n-\tu32 normal_count;\n-\tu32 high_count;\n-\tu32 comp_sent_count;\n-\tu32 comp_count;\n+\tu32\t\t\t\tunlimited_pending_count;\n+\tu32\t\t\t\tnormal_count;\n+\tu32\t\t\t\thigh_count;\n+\tu32\t\t\t\tcomp_sent_count;\n+\tu32\t\t\t\tcomp_count;\n \n-\tu32 cid;\n+\tu32\t\t\t\tcid;\n };\n \n struct ecore_port;\n@@ -136,9 +136,9 @@ struct ecore_hwfn;\n  *\n  * @return enum _ecore_status_t\n  */\n-enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn,\n+enum _ecore_status_t ecore_spq_post(struct ecore_hwfn\t   *p_hwfn,\n \t\t\t\t    struct ecore_spq_entry *p_ent,\n-\t\t\t\t    u8 *fw_return_code);\n+\t\t\t\t    u8                     *fw_return_code);\n \n /**\n  * @brief ecore_spq_allocate - Alloocates & initializes the SPQ and EQ.\n@@ -147,7 +147,7 @@ enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn,\n  *\n  * @return enum _ecore_status_t\n  */\n-enum _ecore_status_t ecore_spq_alloc(struct ecore_hwfn *p_hwfn);\n+enum _ecore_status_t ecore_spq_alloc(struct ecore_hwfn\t*p_hwfn);\n \n /**\n  * @brief ecore_spq_setup - Reset the SPQ to its start state.\n@@ -184,8 +184,8 @@ ecore_spq_get_entry(struct ecore_hwfn *p_hwfn, struct ecore_spq_entry **pp_ent);\n  * @param p_hwfn\n  * @param p_ent\n  */\n-void ecore_spq_return_entry(struct ecore_hwfn *p_hwfn,\n-\t\t\t    struct ecore_spq_entry *p_ent);\n+void ecore_spq_return_entry(struct ecore_hwfn\t\t*p_hwfn,\n+\t\t\t    struct ecore_spq_entry      *p_ent);\n /**\n  * @brief ecore_eq_allocate - Allocates & initializes an EQ struct\n  *\n@@ -228,8 +228,8 @@ void ecore_eq_prod_update(struct ecore_hwfn *p_hwfn, u16 prod);\n  *\n  * @return enum _ecore_status_t\n  */\n-enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t void *cookie);\n+enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn\t*p_hwfn,\n+\t\t\t\t\t void\t\t\t*cookie);\n \n /**\n  * @brief ecore_spq_completion - Completes a single event\n@@ -240,10 +240,10 @@ enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn,\n  *\n  * @return enum _ecore_status_t\n  */\n-enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t  __le16 echo,\n-\t\t\t\t\t  u8 fw_return_code,\n-\t\t\t\t\t  union event_ring_data *p_data);\n+enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn\t*p_hwfn,\n+\t\t\t\t\t  __le16\t\techo,\n+\t\t\t\t\t  u8                    fw_return_code,\n+\t\t\t\t\t  union event_ring_data\t*p_data);\n \n /**\n  * @brief ecore_spq_get_cid - Given p_hwfn, return cid for the hwfn's SPQ\n@@ -262,7 +262,7 @@ u32 ecore_spq_get_cid(struct ecore_hwfn *p_hwfn);\n  *\n  * @return struct ecore_eq* - a newly allocated structure; NULL upon error.\n  */\n-struct ecore_consq *ecore_consq_alloc(struct ecore_hwfn *p_hwfn);\n+struct ecore_consq *ecore_consq_alloc(struct ecore_hwfn\t*p_hwfn);\n \n /**\n  * @brief ecore_consq_setup - Reset the ConsQ to its start\ndiff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c\nindex 1b3119d..d8d1aac 100644\n--- a/drivers/net/qede/base/ecore_sriov.c\n+++ b/drivers/net/qede/base/ecore_sriov.c\n@@ -393,16 +393,16 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn,\n \t\tint *pos = &p_hwfn->p_dev->sriov_info.pos;\n \n \t\t*pos = OSAL_PCI_FIND_EXT_CAPABILITY(p_hwfn->p_dev,\n-\t\t\t\t\t\t    PCI_EXT_CAP_ID_SRIOV);\n+\t\t\t\t\t   PCI_EXT_CAP_ID_SRIOV);\n \t\tif (!*pos) {\n \t\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV,\n \t\t\t\t   \"No PCIe IOV support\\n\");\n-\t\t\treturn ECORE_SUCCESS;\n-\t\t}\n+\t\treturn ECORE_SUCCESS;\n+\t}\n \n-\t\trc = ecore_iov_pci_cfg_info(p_dev);\n-\t\tif (rc)\n-\t\t\treturn rc;\n+\trc = ecore_iov_pci_cfg_info(p_dev);\n+\tif (rc)\n+\t\treturn rc;\n \t} else if (!p_hwfn->p_dev->sriov_info.pos) {\n \t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV, \"No PCIe IOV support\\n\");\n \t\treturn ECORE_SUCCESS;\n@@ -413,7 +413,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn,\n \t * after the first engine's VFs.\n \t */\n \tp_hwfn->hw_info.first_vf_in_pf = p_hwfn->p_dev->sriov_info.offset +\n-\t    p_hwfn->abs_pf_id - 16;\n+\t\t\t\t\t    p_hwfn->abs_pf_id - 16;\n \tif (ECORE_PATH_ID(p_hwfn))\n \t\tp_hwfn->hw_info.first_vf_in_pf -= MAX_NUM_VFS_BB;\n \n@@ -448,12 +448,12 @@ void ecore_iov_set_vf_to_disable(struct ecore_hwfn *p_hwfn,\n {\n \tstruct ecore_vf_info *vf;\n \n-\tvf = ecore_iov_get_vf_info(p_hwfn, rel_vf_id, false);\n-\tif (!vf)\n+\t\tvf = ecore_iov_get_vf_info(p_hwfn, rel_vf_id, false);\n+\t\tif (!vf)\n \t\treturn;\n \n-\tvf->to_disable = to_disable;\n-}\n+\t\tvf->to_disable = to_disable;\n+\t}\n \n void ecore_iov_set_vfs_to_disable(struct ecore_hwfn *p_hwfn, u8 to_disable)\n {\n@@ -504,7 +504,7 @@ static OSAL_INLINE void ecore_iov_vf_semi_clear_err(struct ecore_hwfn *p_hwfn,\n \tecore_wr(p_hwfn, p_ptt, PSEM_REG_VF_ERROR, 1);\n }\n \n-static void ecore_iov_vf_pglue_clear_err(struct ecore_hwfn *p_hwfn,\n+static void ecore_iov_vf_pglue_clear_err(struct ecore_hwfn      *p_hwfn,\n \t\t\t\t\t struct ecore_ptt *p_ptt, u8 abs_vfid)\n {\n \tecore_wr(p_hwfn, p_ptt,\n@@ -754,7 +754,7 @@ enum _ecore_status_t ecore_iov_init_hw_for_vf(struct ecore_hwfn *p_hwfn,\n {\n \tenum _ecore_status_t rc = ECORE_SUCCESS;\n \tstruct ecore_vf_info *vf = OSAL_NULL;\n-\tu8 num_of_vf_available_chains = 0;\n+\tu8 num_of_vf_available_chains  = 0;\n \tu32 cids;\n \tu8 i;\n \n@@ -896,9 +896,9 @@ static void ecore_iov_lock_vf_pf_channel(struct ecore_hwfn *p_hwfn,\n \t/* vf->op_current = tlv; @@@TBD MichalK */\n \n \t/* log the lock */\n-\tDP_VERBOSE(p_hwfn,\n-\t\t   ECORE_MSG_IOV,\n-\t\t   \"VF[%d]: vf pf channel locked by     %s\\n\",\n+\t\tDP_VERBOSE(p_hwfn,\n+\t\t\t   ECORE_MSG_IOV,\n+\t\t\t   \"VF[%d]: vf pf channel locked by %s\\n\",\n \t\t   vf->abs_vf_id, ecore_channel_tlvs_string[tlv]);\n }\n \n@@ -921,9 +921,9 @@ static void ecore_iov_unlock_vf_pf_channel(struct ecore_hwfn *p_hwfn,\n \t/* mutex_unlock(&vf->op_mutex); @@@TBD MichalK add the lock */\n \n \t/* log the unlock */\n-\tDP_VERBOSE(p_hwfn,\n-\t\t   ECORE_MSG_IOV,\n-\t\t   \"VF[%d]: vf pf channel unlocked by %s\\n\",\n+\t\tDP_VERBOSE(p_hwfn,\n+\t\t\t   ECORE_MSG_IOV,\n+\t\t\t   \"VF[%d]: vf pf channel unlocked by %s\\n\",\n \t\t   vf->abs_vf_id, ecore_channel_tlvs_string[expected_tlv]);\n \n \t/* record the locking op */\n@@ -1131,9 +1131,9 @@ static void ecore_iov_vf_cleanup(struct ecore_hwfn *p_hwfn,\n \tOSAL_IOV_VF_CLEANUP(p_hwfn, p_vf->relative_vf_id);\n }\n \n-static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t     struct ecore_ptt *p_ptt,\n-\t\t\t\t     struct ecore_vf_info *vf)\n+static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn       *p_hwfn,\n+\t\t\t\t     struct ecore_ptt\t     *p_ptt,\n+\t\t\t\t     struct ecore_vf_info    *vf)\n {\n \tstruct ecore_iov_vf_mbx *mbx = &vf->vf_mbx;\n \tstruct vfpf_acquire_tlv *req = &mbx->req_virt->acquire;\n@@ -1148,7 +1148,7 @@ static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn,\n \t    req->vfdev_info.fw_minor != FW_MINOR_VERSION ||\n \t    req->vfdev_info.fw_revision != FW_REVISION_VERSION ||\n \t    req->vfdev_info.fw_engineering != FW_ENGINEERING_VERSION) {\n-\t\tDP_INFO(p_hwfn,\n+\t\t\tDP_INFO(p_hwfn,\n \t\t\t\"VF[%d] is running an incompatible driver [VF needs\"\n \t\t\t\" FW %02x:%02x:%02x:%02x but Hypervisor is\"\n \t\t\t\" using %02x:%02x:%02x:%02x]\\n\",\n@@ -1323,25 +1323,25 @@ ecore_iov_reconfigure_unicast_vlan(struct ecore_hwfn *p_hwfn,\n \t/* Reconfigure vlans */\n \tfor (i = 0; i < ECORE_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {\n \t\tif (p_vf->shadow_config.vlans[i].used) {\n-\t\t\tfilter.type = ECORE_FILTER_VLAN;\n-\t\t\tfilter.vlan = p_vf->shadow_config.vlans[i].vid;\n-\t\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV,\n+\t\tfilter.type = ECORE_FILTER_VLAN;\n+\t\tfilter.vlan = p_vf->shadow_config.vlans[i].vid;\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV,\n \t\t\t\t   \"Reconfig VLAN [0x%04x] for VF [%04x]\\n\",\n-\t\t\t\t   filter.vlan, p_vf->relative_vf_id);\n-\t\t\trc = ecore_sp_eth_filter_ucast(p_hwfn,\n-\t\t\t\t\t\t       p_vf->opaque_fid,\n-\t\t\t\t\t\t       &filter,\n-\t\t\t\t\t\t       ECORE_SPQ_MODE_CB,\n+\t\t\t   filter.vlan, p_vf->relative_vf_id);\n+\t\trc = ecore_sp_eth_filter_ucast(p_hwfn,\n+\t\t\t\t\t       p_vf->opaque_fid,\n+\t\t\t\t\t       &filter,\n+\t\t\t\t\t       ECORE_SPQ_MODE_CB,\n \t\t\t\t\t\t       OSAL_NULL);\n-\t\t\tif (rc) {\n-\t\t\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t\t\t  \"Failed to configure VLAN [%04x]\"\n-\t\t\t\t\t  \" to VF [%04x]\\n\",\n-\t\t\t\t\t  filter.vlan, p_vf->relative_vf_id);\n-\t\t\t\tbreak;\n-\t\t\t}\n+\t\tif (rc) {\n+\t\t\tDP_NOTICE(p_hwfn, true,\n+\t\t\t\t  \"Failed to configure VLAN [%04x]\"\n+\t\t\t\t  \" to VF [%04x]\\n\",\n+\t\t\t\t  filter.vlan, p_vf->relative_vf_id);\n+\t\t\tbreak;\n \t\t}\n \t}\n+\t}\n \n \treturn rc;\n }\n@@ -1646,14 +1646,14 @@ static void ecore_iov_vf_mbx_start_txq(struct ecore_hwfn *p_hwfn,\n \tpq_params.eth.vf_id = vf->relative_vf_id;\n \n \trc = ecore_sp_eth_txq_start_ramrod(p_hwfn,\n-\t\t\t\t\t   vf->opaque_fid,\n-\t\t\t\t\t   vf->vf_queues[req->tx_qid].fw_tx_qid,\n-\t\t\t\t\t   vf->vf_queues[req->tx_qid].fw_cid,\n-\t\t\t\t\t   vf->vport_id,\n-\t\t\t\t\t   vf->abs_vf_id + 0x10,\n-\t\t\t\t\t   req->hw_sb,\n-\t\t\t\t\t   req->sb_index,\n-\t\t\t\t\t   req->pbl_addr,\n+\t\tvf->opaque_fid,\n+\t\tvf->vf_queues[req->tx_qid].fw_tx_qid,\n+\t\tvf->vf_queues[req->tx_qid].fw_cid,\n+\t\tvf->vport_id,\n+\t\tvf->abs_vf_id + 0x10,\n+\t\treq->hw_sb,\n+\t\treq->sb_index,\n+\t\treq->pbl_addr,\n \t\t\t\t\t   req->pbl_size, &pq_params);\n \n \tif (rc)\n@@ -1852,12 +1852,12 @@ ecore_iov_vp_update_act_param(struct ecore_hwfn *p_hwfn,\n \tp_act_tlv = (struct vfpf_vport_update_activate_tlv *)\n \t    ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);\n \tif (p_act_tlv) {\n-\t\tp_data->update_vport_active_rx_flg = p_act_tlv->update_rx;\n-\t\tp_data->vport_active_rx_flg = p_act_tlv->active_rx;\n-\t\tp_data->update_vport_active_tx_flg = p_act_tlv->update_tx;\n-\t\tp_data->vport_active_tx_flg = p_act_tlv->active_tx;\n-\t\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACTIVATE;\n-\t}\n+\tp_data->update_vport_active_rx_flg = p_act_tlv->update_rx;\n+\tp_data->vport_active_rx_flg = p_act_tlv->active_rx;\n+\tp_data->update_vport_active_tx_flg = p_act_tlv->update_tx;\n+\tp_data->vport_active_tx_flg = p_act_tlv->active_tx;\n+\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACTIVATE;\n+}\n }\n \n static void\n@@ -1905,10 +1905,10 @@ ecore_iov_vp_update_tx_switch(struct ecore_hwfn *p_hwfn,\n #endif\n \n \tif (p_tx_switch_tlv) {\n-\t\tp_data->update_tx_switching_flg = 1;\n-\t\tp_data->tx_switching_flg = p_tx_switch_tlv->tx_switching;\n-\t\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_TX_SWITCH;\n-\t}\n+\tp_data->update_tx_switching_flg = 1;\n+\tp_data->tx_switching_flg = p_tx_switch_tlv->tx_switching;\n+\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_TX_SWITCH;\n+}\n }\n \n static void\n@@ -1924,12 +1924,12 @@ ecore_iov_vp_update_mcast_bin_param(struct ecore_hwfn *p_hwfn,\n \t    ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);\n \n \tif (p_mcast_tlv) {\n-\t\tp_data->update_approx_mcast_flg = 1;\n-\t\tOSAL_MEMCPY(p_data->bins, p_mcast_tlv->bins,\n-\t\t\t    sizeof(unsigned long) *\n-\t\t\t    ETH_MULTICAST_MAC_BINS_IN_REGS);\n-\t\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_MCAST;\n-\t}\n+\tp_data->update_approx_mcast_flg = 1;\n+\tOSAL_MEMCPY(p_data->bins, p_mcast_tlv->bins,\n+\t\t    sizeof(unsigned long) *\n+\t\t    ETH_MULTICAST_MAC_BINS_IN_REGS);\n+\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_MCAST;\n+}\n }\n \n static void\n@@ -1952,8 +1952,8 @@ ecore_iov_vp_update_accept_flag(struct ecore_hwfn *p_hwfn,\n \t\t    p_accept_tlv->update_tx_mode;\n \t\tp_data->accept_flags.tx_accept_filter =\n \t\t    p_accept_tlv->tx_accept_filter;\n-\t\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_PARAM;\n-\t}\n+\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_PARAM;\n+}\n }\n \n static void\n@@ -1969,11 +1969,11 @@ ecore_iov_vp_update_accept_any_vlan(struct ecore_hwfn *p_hwfn,\n \t    ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);\n \n \tif (p_accept_any_vlan) {\n-\t\tp_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan;\n-\t\tp_data->update_accept_any_vlan_flg =\n-\t\t    p_accept_any_vlan->update_accept_any_vlan_flg;\n-\t\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN;\n-\t}\n+\tp_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan;\n+\tp_data->update_accept_any_vlan_flg =\n+\t\t\tp_accept_any_vlan->update_accept_any_vlan_flg;\n+\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN;\n+}\n }\n \n static void\n@@ -1991,48 +1991,48 @@ ecore_iov_vp_update_rss_param(struct ecore_hwfn *p_hwfn,\n \tp_rss_tlv = (struct vfpf_vport_update_rss_tlv *)\n \t    ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);\n \tif (p_rss_tlv) {\n-\t\tOSAL_MEMSET(p_rss, 0, sizeof(struct ecore_rss_params));\n-\n-\t\tp_rss->update_rss_config =\n-\t\t    !!(p_rss_tlv->update_rss_flags &\n-\t\t\tVFPF_UPDATE_RSS_CONFIG_FLAG);\n-\t\tp_rss->update_rss_capabilities =\n-\t\t    !!(p_rss_tlv->update_rss_flags &\n-\t\t\tVFPF_UPDATE_RSS_CAPS_FLAG);\n-\t\tp_rss->update_rss_ind_table =\n-\t\t    !!(p_rss_tlv->update_rss_flags &\n-\t\t\tVFPF_UPDATE_RSS_IND_TABLE_FLAG);\n-\t\tp_rss->update_rss_key =\n+\tOSAL_MEMSET(p_rss, 0, sizeof(struct ecore_rss_params));\n+\n+\tp_rss->update_rss_config =\n+\t    !!(p_rss_tlv->update_rss_flags &\n+\t\tVFPF_UPDATE_RSS_CONFIG_FLAG);\n+\tp_rss->update_rss_capabilities =\n+\t    !!(p_rss_tlv->update_rss_flags &\n+\t\tVFPF_UPDATE_RSS_CAPS_FLAG);\n+\tp_rss->update_rss_ind_table =\n+\t    !!(p_rss_tlv->update_rss_flags &\n+\t\tVFPF_UPDATE_RSS_IND_TABLE_FLAG);\n+\tp_rss->update_rss_key =\n \t\t    !!(p_rss_tlv->update_rss_flags & VFPF_UPDATE_RSS_KEY_FLAG);\n \n-\t\tp_rss->rss_enable = p_rss_tlv->rss_enable;\n-\t\tp_rss->rss_eng_id = vf->relative_vf_id + 1;\n-\t\tp_rss->rss_caps = p_rss_tlv->rss_caps;\n-\t\tp_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log;\n-\t\tOSAL_MEMCPY(p_rss->rss_ind_table, p_rss_tlv->rss_ind_table,\n-\t\t\t    sizeof(p_rss->rss_ind_table));\n-\t\tOSAL_MEMCPY(p_rss->rss_key, p_rss_tlv->rss_key,\n-\t\t\t    sizeof(p_rss->rss_key));\n+\tp_rss->rss_enable = p_rss_tlv->rss_enable;\n+\tp_rss->rss_eng_id = vf->relative_vf_id + 1;\n+\tp_rss->rss_caps = p_rss_tlv->rss_caps;\n+\tp_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log;\n+\tOSAL_MEMCPY(p_rss->rss_ind_table, p_rss_tlv->rss_ind_table,\n+\t\t    sizeof(p_rss->rss_ind_table));\n+\tOSAL_MEMCPY(p_rss->rss_key, p_rss_tlv->rss_key,\n+\t\t    sizeof(p_rss->rss_key));\n \n \t\ttable_size = OSAL_MIN_T(u16,\n \t\t\t\t\tOSAL_ARRAY_SIZE(p_rss->rss_ind_table),\n-\t\t\t\t\t(1 << p_rss_tlv->rss_table_size_log));\n+\t\t\t\t(1 << p_rss_tlv->rss_table_size_log));\n \n-\t\tmax_q_idx = OSAL_ARRAY_SIZE(vf->vf_queues);\n+\tmax_q_idx = OSAL_ARRAY_SIZE(vf->vf_queues);\n \n-\t\tfor (i = 0; i < table_size; i++) {\n-\t\t\tq_idx = p_rss->rss_ind_table[i];\n+\tfor (i = 0; i < table_size; i++) {\n+\t\tq_idx = p_rss->rss_ind_table[i];\n \t\t\tif (q_idx >= max_q_idx) {\n-\t\t\t\tDP_NOTICE(p_hwfn, true,\n+\t\t\tDP_NOTICE(p_hwfn, true,\n \t\t\t\t\t  \"rss_ind_table[%d] = %d, rxq is out of range\\n\",\n-\t\t\t\t\t  i, q_idx);\n+\t\t\t\t  i, q_idx);\n \t\t\t\t/* TBD: fail the request mark VF as malicious */\n \t\t\t\tp_rss->rss_ind_table[i] =\n \t\t\t\t    vf->vf_queues[0].fw_rx_qid;\n \t\t\t} else if (!vf->vf_queues[q_idx].rxq_active) {\n-\t\t\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t\t\t  \"rss_ind_table[%d] = %d, rxq is not active\\n\",\n-\t\t\t\t\t  i, q_idx);\n+\t\t\tDP_NOTICE(p_hwfn, true,\n+\t\t\t\t  \"rss_ind_table[%d] = %d, rxq is not active\\n\",\n+\t\t\t\t  i, q_idx);\n \t\t\t\t/* TBD: fail the request mark VF as malicious */\n \t\t\t\tp_rss->rss_ind_table[i] =\n \t\t\t\t    vf->vf_queues[0].fw_rx_qid;\n@@ -2040,10 +2040,10 @@ ecore_iov_vp_update_rss_param(struct ecore_hwfn *p_hwfn,\n \t\t\t\tp_rss->rss_ind_table[i] =\n \t\t\t\t    vf->vf_queues[q_idx].fw_rx_qid;\n \t\t\t}\n-\t\t}\n+\t}\n \n-\t\tp_data->rss_params = p_rss;\n-\t\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_RSS;\n+\tp_data->rss_params = p_rss;\n+\t*tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_RSS;\n \t} else {\n \t\tp_data->rss_params = OSAL_NULL;\n \t}\n@@ -2172,8 +2172,8 @@ out:\n \n static enum _ecore_status_t\n ecore_iov_vf_update_unicast_shadow(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t   struct ecore_vf_info *p_vf,\n-\t\t\t\t   struct ecore_filter_ucast *p_params)\n+\t\t\t\tstruct ecore_vf_info *p_vf,\n+\t\t\t\tstruct ecore_filter_ucast *p_params)\n {\n \tint i;\n \n@@ -2212,11 +2212,11 @@ ecore_iov_vf_update_unicast_shadow(struct ecore_hwfn *p_hwfn,\n \t    p_params->opcode == ECORE_FILTER_REPLACE) {\n \t\tfor (i = 0; i < ECORE_ETH_VF_NUM_VLAN_FILTERS + 1; i++)\n \t\t\tif (!p_vf->shadow_config.vlans[i].used) {\n-\t\t\t\tp_vf->shadow_config.vlans[i].used = true;\n+\t\t\tp_vf->shadow_config.vlans[i].used = true;\n \t\t\t\tp_vf->shadow_config.vlans[i].vid =\n \t\t\t\t    p_params->vlan;\n-\t\t\t\tbreak;\n-\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n \t\tif (i == ECORE_ETH_VF_NUM_VLAN_FILTERS + 1) {\n \t\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV,\n \t\t\t\t   \"VF [%d] - Tries to configure more than %d vlan filters\\n\",\n@@ -2737,11 +2737,11 @@ void ecore_iov_process_mbx_req(struct ecore_hwfn *p_hwfn,\n \n \t/* check if tlv type is known */\n \tif (ecore_iov_tlv_supported(mbx->first_tlv.tl.type)) {\n-\t\t/* Lock the per vf op mutex and note the locker's identity.\n-\t\t * The unlock will take place in mbx response.\n-\t\t */\n-\t\tecore_iov_lock_vf_pf_channel(p_hwfn,\n-\t\t\t\t\t     p_vf, mbx->first_tlv.tl.type);\n+\t/* Lock the per vf op mutex and note the locker's identity.\n+\t * The unlock will take place in mbx response.\n+\t */\n+\tecore_iov_lock_vf_pf_channel(p_hwfn,\n+\t\t\t\t     p_vf, mbx->first_tlv.tl.type);\n \n \t\t/* switch on the opcode */\n \t\tswitch (mbx->first_tlv.tl.type) {\ndiff --git a/drivers/net/qede/base/ecore_sriov.h b/drivers/net/qede/base/ecore_sriov.h\nindex 3471e5c..7eca169 100644\n--- a/drivers/net/qede/base/ecore_sriov.h\n+++ b/drivers/net/qede/base/ecore_sriov.h\n@@ -57,13 +57,13 @@ struct ecore_vf_iov {\n  * a message\n  */\n struct ecore_iov_vf_mbx {\n-\tunion vfpf_tlvs *req_virt;\n-\tdma_addr_t req_phys;\n-\tunion pfvf_tlvs *reply_virt;\n-\tdma_addr_t reply_phys;\n+\tunion vfpf_tlvs\t\t*req_virt;\n+\tdma_addr_t\t\treq_phys;\n+\tunion pfvf_tlvs\t\t*reply_virt;\n+\tdma_addr_t\t\treply_phys;\n \n \t/* Address in VF where a pending message is located */\n-\tdma_addr_t pending_req;\n+\tdma_addr_t\t\tpending_req;\n \n \tu8 *offset;\n \n@@ -72,12 +72,12 @@ struct ecore_iov_vf_mbx {\n #endif\n \n \t/* VF GPA address */\n-\tu32 vf_addr_lo;\n-\tu32 vf_addr_hi;\n+\tu32\t\t\tvf_addr_lo;\n+\tu32\t\t\tvf_addr_hi;\n \n-\tstruct vfpf_first_tlv first_tlv;\t/* saved VF request header */\n+\tstruct vfpf_first_tlv\tfirst_tlv;\t/* saved VF request header */\n \n-\tu8 flags;\n+\tu8\t\t\tflags;\n #define VF_MSG_INPROCESS\t0x1\t/* failsafe - the FW should prevent\n \t\t\t\t\t * more then one pending msg\n \t\t\t\t\t */\n@@ -101,11 +101,11 @@ enum int_mod {\n };\n \n enum vf_state {\n-\tVF_FREE = 0,\t\t/* VF ready to be acquired holds no resc */\n-\tVF_ACQUIRED = 1,\t/* VF, acquired, but not initalized */\n-\tVF_ENABLED = 2,\t\t/* VF, Enabled */\n-\tVF_RESET = 3,\t\t/* VF, FLR'd, pending cleanup */\n-\tVF_STOPPED = 4\t\t/* VF, Stopped */\n+\tVF_FREE\t\t= 0,\t/* VF ready to be acquired holds no resc */\n+\tVF_ACQUIRED\t= 1,\t/* VF, acquired, but not initalized */\n+\tVF_ENABLED\t= 2,\t/* VF, Enabled */\n+\tVF_RESET\t= 3,\t/* VF, FLR'd, pending cleanup */\n+\tVF_STOPPED      = 4     /* VF, Stopped */\n };\n \n struct ecore_vf_vlan_shadow {\n@@ -124,34 +124,34 @@ struct ecore_vf_shadow_config {\n struct ecore_vf_info {\n \tstruct ecore_iov_vf_mbx vf_mbx;\n \tenum vf_state state;\n-\tu8 to_disable;\n+\tu8\t\t\tto_disable;\n \n-\tstruct ecore_bulletin bulletin;\n-\tdma_addr_t vf_bulletin;\n+\tstruct ecore_bulletin\tbulletin;\n+\tdma_addr_t\t\tvf_bulletin;\n \n-\tu32 concrete_fid;\n-\tu16 opaque_fid;\n-\tu16 mtu;\n+\tu32\t\t\tconcrete_fid;\n+\tu16\t\t\topaque_fid;\n+\tu16\t\t\tmtu;\n \n-\tu8 vport_id;\n-\tu8 relative_vf_id;\n-\tu8 abs_vf_id;\n+\tu8\t\t\tvport_id;\n+\tu8\t\t\trelative_vf_id;\n+\tu8\t\t\tabs_vf_id;\n #define ECORE_VF_ABS_ID(p_hwfn, p_vf)\t(ECORE_PATH_ID(p_hwfn) ? \\\n \t\t\t\t\t (p_vf)->abs_vf_id + MAX_NUM_VFS_BB : \\\n \t\t\t\t\t (p_vf)->abs_vf_id)\n \n-\tu8 vport_instance;\t/* Number of active vports */\n-\tu8 num_rxqs;\n-\tu8 num_txqs;\n+\tu8\t\t\tvport_instance; /* Number of active vports */\n+\tu8\t\t\tnum_rxqs;\n+\tu8\t\t\tnum_txqs;\n \n-\tu8 num_sbs;\n+\tu8\t\t\tnum_sbs;\n \n-\tu8 num_mac_filters;\n-\tu8 num_vlan_filters;\n+\tu8\t\t\tnum_mac_filters;\n+\tu8\t\t\tnum_vlan_filters;\n \tu8 num_mc_filters;\n \n-\tstruct ecore_vf_q_info vf_queues[ECORE_MAX_VF_CHAINS_PER_PF];\n-\tu16 igu_sbs[ECORE_MAX_VF_CHAINS_PER_PF];\n+\tstruct ecore_vf_q_info\tvf_queues[ECORE_MAX_VF_CHAINS_PER_PF];\n+\tu16\t\t\tigu_sbs[ECORE_MAX_VF_CHAINS_PER_PF];\n \n \t/* TODO - Only windows is using it - should be removed */\n \tu8 was_malicious;\n@@ -159,7 +159,7 @@ struct ecore_vf_info {\n \tvoid *ctx;\n \tstruct ecore_public_vf_info p_vf_info;\n \tbool spoof_chk;\t\t/* Current configured on HW */\n-\tbool req_spoofchk_val;\t/* Requested value */\n+\tbool req_spoofchk_val;  /* Requested value */\n \n \t/* Stores the configuration requested by VF */\n \tstruct ecore_vf_shadow_config shadow_config;\n@@ -176,21 +176,21 @@ struct ecore_vf_info {\n  * capability enabled.\n  */\n struct ecore_pf_iov {\n-\tstruct ecore_vf_info vfs_array[MAX_NUM_VFS];\n-\tu64 pending_events[ECORE_VF_ARRAY_LENGTH];\n-\tu64 pending_flr[ECORE_VF_ARRAY_LENGTH];\n-\tu16 base_vport_id;\n+\tstruct ecore_vf_info\tvfs_array[MAX_NUM_VFS];\n+\tu64\t\t\tpending_events[ECORE_VF_ARRAY_LENGTH];\n+\tu64\t\t\tpending_flr[ECORE_VF_ARRAY_LENGTH];\n+\tu16\t\t\tbase_vport_id;\n \n \t/* Allocate message address continuosuly and split to each VF */\n-\tvoid *mbx_msg_virt_addr;\n-\tdma_addr_t mbx_msg_phys_addr;\n-\tu32 mbx_msg_size;\n-\tvoid *mbx_reply_virt_addr;\n-\tdma_addr_t mbx_reply_phys_addr;\n-\tu32 mbx_reply_size;\n-\tvoid *p_bulletins;\n-\tdma_addr_t bulletins_phys;\n-\tu32 bulletins_size;\n+\tvoid\t\t\t*mbx_msg_virt_addr;\n+\tdma_addr_t\t\tmbx_msg_phys_addr;\n+\tu32\t\t\tmbx_msg_size;\n+\tvoid\t\t\t*mbx_reply_virt_addr;\n+\tdma_addr_t\t\tmbx_reply_phys_addr;\n+\tu32\t\t\tmbx_reply_size;\n+\tvoid\t\t\t*p_bulletins;\n+\tdma_addr_t\t\tbulletins_phys;\n+\tu32\t\t\tbulletins_size;\n };\n \n #ifdef CONFIG_ECORE_SRIOV\n@@ -217,7 +217,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn,\n  *\n  * @return pointer to the newly placed tlv\n  */\n-void *ecore_add_tlv(struct ecore_hwfn *p_hwfn,\n+void *ecore_add_tlv(struct ecore_hwfn\t*p_hwfn,\n \t\t    u8 **offset, u16 type, u16 length);\n \n /**\n@@ -260,9 +260,9 @@ void ecore_iov_free(struct ecore_hwfn *p_hwfn);\n  * @param echo\n  * @param data\n  */\n-enum _ecore_status_t ecore_sriov_eqe_event(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t   u8 opcode,\n-\t\t\t\t\t   __le16 echo,\n+enum _ecore_status_t ecore_sriov_eqe_event(struct ecore_hwfn\t *p_hwfn,\n+\t\t\t\t\t   u8\t\t\t opcode,\n+\t\t\t\t\t   __le16\t\t echo,\n \t\t\t\t\t   union event_ring_data *data);\n \n /**\ndiff --git a/drivers/net/qede/base/ecore_status.h b/drivers/net/qede/base/ecore_status.h\nindex 98d40bb..6277bc8 100644\n--- a/drivers/net/qede/base/ecore_status.h\n+++ b/drivers/net/qede/base/ecore_status.h\n@@ -10,18 +10,18 @@\n #define __ECORE_STATUS_H__\n \n enum _ecore_status_t {\n-\tECORE_UNKNOWN_ERROR = -12,\n-\tECORE_NORESOURCES = -11,\n-\tECORE_NODEV = -10,\n+\tECORE_UNKNOWN_ERROR  = -12,\n+\tECORE_NORESOURCES\t = -11,\n+\tECORE_NODEV   = -10,\n \tECORE_ABORTED = -9,\n-\tECORE_AGAIN = -8,\n+\tECORE_AGAIN   = -8,\n \tECORE_NOTIMPL = -7,\n-\tECORE_EXISTS = -6,\n-\tECORE_IO = -5,\n+\tECORE_EXISTS  = -6,\n+\tECORE_IO      = -5,\n \tECORE_TIMEOUT = -4,\n-\tECORE_INVAL = -3,\n-\tECORE_BUSY = -2,\n-\tECORE_NOMEM = -1,\n+\tECORE_INVAL   = -3,\n+\tECORE_BUSY    = -2,\n+\tECORE_NOMEM   = -1,\n \tECORE_SUCCESS = 0,\n \t/* PENDING is not an error and should be positive */\n \tECORE_PENDING = 1,\ndiff --git a/drivers/net/qede/base/ecore_vf.c b/drivers/net/qede/base/ecore_vf.c\nindex d32fb35..a03a2ce 100644\n--- a/drivers/net/qede/base/ecore_vf.c\n+++ b/drivers/net/qede/base/ecore_vf.c\n@@ -264,7 +264,7 @@ static enum _ecore_status_t ecore_vf_pf_acquire(struct ecore_hwfn *p_hwfn)\n \tp_hwfn->p_dev->chip_num = pfdev_info->chip_num & 0xffff;\n \n \treturn 0;\n-}\n+\t}\n \n enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev)\n {\n@@ -280,7 +280,7 @@ enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev)\n \t\t       \"regview should be initialized before\"\n \t\t\t\" ecore_vf_hw_prepare is called\\n\");\n \t\treturn ECORE_INVAL;\n-\t}\n+}\n \n \t/* Set the doorbell bar. Assumption: regview is set */\n \tp_hwfn->doorbells = (u8 OSAL_IOMEM *)p_hwfn->regview +\n@@ -310,7 +310,7 @@ enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev)\n \t\t\t\t\t\t\t\tvfpf_tlvs));\n \tif (!p_sriov->vf2pf_request) {\n \t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t  \"Failed to allocate `vf2pf_request' DMA memory\\n\");\n+\t\t\t \"Failed to allocate `vf2pf_request' DMA memory\\n\");\n \t\tgoto free_p_sriov;\n \t}\n \n@@ -388,7 +388,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t   dma_addr_t bd_chain_phys_addr,\n \t\t\t\t\t   dma_addr_t cqe_pbl_addr,\n \t\t\t\t\t   u16 cqe_pbl_size,\n-\t\t\t\t\t   void OSAL_IOMEM * *pp_prod)\n+\t\t\t\t\t   void OSAL_IOMEM **pp_prod)\n {\n \tstruct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;\n \tstruct vfpf_start_rxq_tlv *req;\n@@ -421,7 +421,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,\n \t\thw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid];\n \n \t\t*pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +\n-\t\t    MSTORM_QZONE_START(p_hwfn->p_dev) +\n+\t\t\t   MSTORM_QZONE_START(p_hwfn->p_dev) +\n \t\t    (hw_qid) * MSTORM_QZONE_SIZE +\n \t\t    OFFSETOF(struct mstorm_eth_queue_zone, rx_producers);\n \n@@ -481,7 +481,7 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t   u8 sb_index,\n \t\t\t\t\t   dma_addr_t pbl_addr,\n \t\t\t\t\t   u16 pbl_size,\n-\t\t\t\t\t   void OSAL_IOMEM * *pp_doorbell)\n+\t\t\t\t\t   void OSAL_IOMEM **pp_doorbell)\n {\n \tstruct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;\n \tstruct vfpf_start_txq_tlv *req;\n@@ -519,8 +519,8 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,\n \t\tu8 cid = p_iov->acquire_resp.resc.cid[tx_queue_id];\n \n \t\t*pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +\n-\t\t    DB_ADDR_VF(cid, DQ_DEMS_LEGACY);\n-\t}\n+\t\t\t\tDB_ADDR_VF(cid, DQ_DEMS_LEGACY);\n+\t\t}\n \n \treturn rc;\n }\n@@ -1117,7 +1117,7 @@ enum _ecore_status_t ecore_vf_pf_int_cleanup(struct ecore_hwfn *p_hwfn)\n \n \trc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));\n \tif (rc)\n-\t\treturn rc;\n+\treturn rc;\n \n \tif (resp->hdr.status != PFVF_STATUS_SUCCESS)\n \t\treturn ECORE_INVAL;\ndiff --git a/drivers/net/qede/base/ecore_vf.h b/drivers/net/qede/base/ecore_vf.h\nindex 334b588..7600710 100644\n--- a/drivers/net/qede/base/ecore_vf.h\n+++ b/drivers/net/qede/base/ecore_vf.h\n@@ -18,7 +18,7 @@\n /**\n  *\n  * @brief hw preparation for VF\n- *\tsends ACQUIRE message\n+ * sends ACQUIRE message\n  *\n  * @param p_dev\n  *\n@@ -63,7 +63,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t   dma_addr_t bd_chain_phys_addr,\n \t\t\t\t\t   dma_addr_t cqe_pbl_addr,\n \t\t\t\t\t   u16 cqe_pbl_size,\n-\t\t\t\t\t   void OSAL_IOMEM * *pp_prod);\n+\t\t\t\t\t   void OSAL_IOMEM **pp_prod);\n \n /**\n  *\n@@ -76,7 +76,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,\n  * @param sb_index\t\t- index within the status block\n  * @param bd_chain_phys_addr\t- physical address of tx chain\n  * @param pp_doorbell\t\t- pointer to address to which to\n- *\t\twrite the doorbell too..\n+ *\t\t\t\twrite the doorbell too..\n  *\n  * @return enum _ecore_status_t\n  */\n@@ -86,7 +86,7 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t   u8 sb_index,\n \t\t\t\t\t   dma_addr_t pbl_addr,\n \t\t\t\t\t   u16 pbl_size,\n-\t\t\t\t\t   void OSAL_IOMEM * *pp_doorbell);\n+\t\t\t\t\t   void OSAL_IOMEM **pp_doorbell);\n \n /**\n  *\n@@ -98,7 +98,7 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,\n  *\n  * @return enum _ecore_status_t\n  */\n-enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn,\n+enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn\t*p_hwfn,\n \t\t\t\t\t  u16 rx_qid, bool cqe_completion);\n \n /**\n@@ -110,8 +110,8 @@ enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn,\n  *\n  * @return enum _ecore_status_t\n  */\n-enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t  u16 tx_qid);\n+enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn\t*p_hwfn,\n+\t\t\t\t\t  u16\t\t\ttx_qid);\n \n /**\n  * @brief VF - update the RX queue by sending a message to the\n@@ -127,10 +127,10 @@ enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn,\n  * @return enum _ecore_status_t\n  */\n enum _ecore_status_t ecore_vf_pf_rxqs_update(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t     u16 rx_queue_id,\n-\t\t\t\t\t     u8 num_rxqs,\n-\t\t\t\t\t     u8 comp_cqe_flg,\n-\t\t\t\t\t     u8 comp_event_flg);\n+\t\t\tu16\t\t\trx_queue_id,\n+\t\t\tu8\t\t\tnum_rxqs,\n+\t\t\tu8\t\t\tcomp_cqe_flg,\n+\t\t\tu8\t\t\tcomp_event_flg);\n \n /**\n  *\n@@ -191,12 +191,12 @@ u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id);\n  * @return enum _ecore_status\n  */\n enum _ecore_status_t ecore_vf_pf_vport_start(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t     u8 vport_id,\n-\t\t\t\t\t     u16 mtu,\n-\t\t\t\t\t     u8 inner_vlan_removal,\n-\t\t\t\t\t     enum ecore_tpa_mode tpa_mode,\n-\t\t\t\t\t     u8 max_buffers_per_cqe,\n-\t\t\t\t\t     u8 only_untagged);\n+\t\t\tu8 vport_id,\n+\t\t\tu16 mtu,\n+\t\t\tu8 inner_vlan_removal,\n+\t\t\tenum ecore_tpa_mode tpa_mode,\n+\t\t\tu8 max_buffers_per_cqe,\n+\t\t\tu8 only_untagged);\n \n /**\n  * @brief ecore_vf_pf_vport_stop - stop the VF's vport\ndiff --git a/drivers/net/qede/base/ecore_vf_api.h b/drivers/net/qede/base/ecore_vf_api.h\nindex f28b686..a2b4ba5 100644\n--- a/drivers/net/qede/base/ecore_vf_api.h\n+++ b/drivers/net/qede/base/ecore_vf_api.h\n@@ -79,7 +79,7 @@ void ecore_vf_get_num_vlan_filters(struct ecore_hwfn *p_hwfn,\n /**\n  * @brief Get number of MAC filters allocated for VF by ecore\n  *\n- *  @param p_hwfn\n+ * @param p_hwfn\n  *  @param num_mac - allocated MAC filters\n  */\n void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn,\n@@ -101,7 +101,7 @@ bool ecore_vf_check_mac(struct ecore_hwfn *p_hwfn, u8 *mac);\n  * @param hwfn\n  * @param dst_mac\n  * @param p_is_forced - out param which indicate in case mac\n- *\t        exist if it forced or not.\n+ *\t\t\texist if it forced or not.\n  *\n  * @return bool       - return true if mac exist and false if\n  *                      not.\ndiff --git a/drivers/net/qede/base/ecore_vfpf_if.h b/drivers/net/qede/base/ecore_vfpf_if.h\nindex 2fa4d15..e98a2a7 100644\n--- a/drivers/net/qede/base/ecore_vfpf_if.h\n+++ b/drivers/net/qede/base/ecore_vfpf_if.h\n@@ -21,18 +21,18 @@\n  *\n  **/\n struct vf_pf_resc_request {\n-\tu8 num_rxqs;\n-\tu8 num_txqs;\n-\tu8 num_sbs;\n-\tu8 num_mac_filters;\n-\tu8 num_vlan_filters;\n-\tu8 num_mc_filters;\t/* No limit  so superfluous */\n+\tu8  num_rxqs;\n+\tu8  num_txqs;\n+\tu8  num_sbs;\n+\tu8  num_mac_filters;\n+\tu8  num_vlan_filters;\n+\tu8  num_mc_filters; /* No limit  so superfluous */\n \tu16 padding;\n };\n \n struct hw_sb_info {\n-\tu16 hw_sb_id;\t\t/* aka absolute igu id, used to ack the sb */\n-\tu8 sb_qid;\t\t/* used to update DHC for sb */\n+\tu16 hw_sb_id;    /* aka absolute igu id, used to ack the sb */\n+\tu8 sb_qid;      /* used to update DHC for sb */\n \tu8 padding[5];\n };\n \n@@ -114,8 +114,8 @@ struct vfpf_acquire_tlv {\n \t\tu8 fw_revision;\n \t\tu8 fw_engineering;\n \t\tu32 driver_version;\n-\t\tu16 opaque_fid;\t/* ME register value */\n-\t\tu8 os_type;\t/* VFPF_ACQUIRE_OS_* value */\n+\t\tu16 opaque_fid; /* ME register value */\n+\t\tu8 os_type; /* VFPF_ACQUIRE_OS_* value */\n \t\tu8 padding[5];\n \t} vfdev_info;\n \n@@ -128,17 +128,17 @@ struct vfpf_acquire_tlv {\n \n /* receive side scaling tlv */\n struct vfpf_vport_update_rss_tlv {\n-\tstruct channel_tlv tl;\n+\tstruct channel_tlv\ttl;\n \n \tu8 update_rss_flags;\n-#define VFPF_UPDATE_RSS_CONFIG_FLAG\t  (1 << 0)\n-#define VFPF_UPDATE_RSS_CAPS_FLAG\t  (1 << 1)\n-#define VFPF_UPDATE_RSS_IND_TABLE_FLAG\t  (1 << 2)\n-#define VFPF_UPDATE_RSS_KEY_FLAG\t  (1 << 3)\n+\t#define VFPF_UPDATE_RSS_CONFIG_FLAG\t  (1 << 0)\n+\t#define VFPF_UPDATE_RSS_CAPS_FLAG\t  (1 << 1)\n+\t#define VFPF_UPDATE_RSS_IND_TABLE_FLAG\t  (1 << 2)\n+\t#define VFPF_UPDATE_RSS_KEY_FLAG\t  (1 << 3)\n \n \tu8 rss_enable;\n \tu8 rss_caps;\n-\tu8 rss_table_size_log;\t/* The table size is 2 ^ rss_table_size_log */\n+\tu8 rss_table_size_log; /* The table size is 2 ^ rss_table_size_log */\n \tu16 rss_ind_table[T_ETH_INDIRECTION_TABLE_SIZE];\n \tu32 rss_key[T_ETH_RSS_KEY_SIZE];\n };\n@@ -172,7 +172,7 @@ struct pfvf_acquire_resp_tlv {\n #define PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED\t(1 << 0)\n \n \t\tu16 db_size;\n-\t\tu8 indices_per_sb;\n+\t\tu8  indices_per_sb;\n \t\tu8 os_type;\n \n \t\t/* Thesee should match the PF's ecore_dev values */\n@@ -192,19 +192,19 @@ struct pfvf_acquire_resp_tlv {\n \t\t * this struct with suggested amount of resources for next\n \t\t * acquire request\n \t\t */\n-#define PFVF_MAX_QUEUES_PER_VF         16\n-#define PFVF_MAX_SBS_PER_VF            16\n+\t\t#define PFVF_MAX_QUEUES_PER_VF         16\n+\t\t#define PFVF_MAX_SBS_PER_VF            16\n \t\tstruct hw_sb_info hw_sbs[PFVF_MAX_SBS_PER_VF];\n-\t\tu8 hw_qid[PFVF_MAX_QUEUES_PER_VF];\n-\t\tu8 cid[PFVF_MAX_QUEUES_PER_VF];\n-\n-\t\tu8 num_rxqs;\n-\t\tu8 num_txqs;\n-\t\tu8 num_sbs;\n-\t\tu8 num_mac_filters;\n-\t\tu8 num_vlan_filters;\n-\t\tu8 num_mc_filters;\n-\t\tu8 padding[2];\n+\t\tu8      hw_qid[PFVF_MAX_QUEUES_PER_VF];\n+\t\tu8      cid[PFVF_MAX_QUEUES_PER_VF];\n+\n+\t\tu8      num_rxqs;\n+\t\tu8      num_txqs;\n+\t\tu8      num_sbs;\n+\t\tu8      num_mac_filters;\n+\t\tu8      num_vlan_filters;\n+\t\tu8      num_mc_filters;\n+\t\tu8      padding[2];\n \t} resc;\n \n \tu32 bulletin_size;\n@@ -225,141 +225,141 @@ struct vfpf_init_tlv {\n \n /* Setup Queue */\n struct vfpf_start_rxq_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n \t/* physical addresses */\n \taligned_u64 rxq_addr;\n \taligned_u64 deprecated_sge_addr;\n \taligned_u64 cqe_pbl_addr;\n \n-\tu16 cqe_pbl_size;\n-\tu16 hw_sb;\n-\tu16 rx_qid;\n-\tu16 hc_rate;\t\t/* desired interrupts per sec. */\n+\tu16\t\t\tcqe_pbl_size;\n+\tu16\t\t\thw_sb;\n+\tu16\t\t\trx_qid;\n+\tu16\t\t\thc_rate; /* desired interrupts per sec. */\n \n-\tu16 bd_max_bytes;\n-\tu16 stat_id;\n-\tu8 sb_index;\n-\tu8 padding[3];\n+\tu16\t\t\tbd_max_bytes;\n+\tu16\t\t\tstat_id;\n+\tu8\t\t\tsb_index;\n+\tu8\t\t\tpadding[3];\n \n };\n \n struct vfpf_start_txq_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n \t/* physical addresses */\n \taligned_u64 pbl_addr;\n-\tu16 pbl_size;\n-\tu16 stat_id;\n-\tu16 tx_qid;\n-\tu16 hw_sb;\n-\n-\tu32 flags;\t\t/* VFPF_QUEUE_FLG_X flags */\n-\tu16 hc_rate;\t\t/* desired interrupts per sec. */\n-\tu8 sb_index;\n-\tu8 padding[3];\n+\tu16\t\t\tpbl_size;\n+\tu16\t\t\tstat_id;\n+\tu16\t\t\ttx_qid;\n+\tu16\t\t\thw_sb;\n+\n+\tu32\t\t\tflags; /* VFPF_QUEUE_FLG_X flags */\n+\tu16\t\t\thc_rate; /* desired interrupts per sec. */\n+\tu8\t\t\tsb_index;\n+\tu8\t\t\tpadding[3];\n };\n \n /* Stop RX Queue */\n struct vfpf_stop_rxqs_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n-\tu16 rx_qid;\n-\tu8 num_rxqs;\n-\tu8 cqe_completion;\n-\tu8 padding[4];\n+\tu16\t\t\trx_qid;\n+\tu8\t\t\tnum_rxqs;\n+\tu8\t\t\tcqe_completion;\n+\tu8\t\t\tpadding[4];\n };\n \n /* Stop TX Queues */\n struct vfpf_stop_txqs_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n-\tu16 tx_qid;\n-\tu8 num_txqs;\n-\tu8 padding[5];\n+\tu16\t\t\ttx_qid;\n+\tu8\t\t\tnum_txqs;\n+\tu8\t\t\tpadding[5];\n };\n \n struct vfpf_update_rxq_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n \taligned_u64 deprecated_sge_addr[PFVF_MAX_QUEUES_PER_VF];\n \n-\tu16 rx_qid;\n-\tu8 num_rxqs;\n-\tu8 flags;\n-#define VFPF_RXQ_UPD_INIT_SGE_DEPRECATE_FLAG\t(1 << 0)\n-#define VFPF_RXQ_UPD_COMPLETE_CQE_FLAG\t\t(1 << 1)\n-#define VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG\t(1 << 2)\n+\tu16\t\t\trx_qid;\n+\tu8\t\t\tnum_rxqs;\n+\tu8\t\t\tflags;\n+\t#define VFPF_RXQ_UPD_INIT_SGE_DEPRECATE_FLAG\t(1 << 0)\n+\t#define VFPF_RXQ_UPD_COMPLETE_CQE_FLAG\t\t(1 << 1)\n+\t#define VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG\t(1 << 2)\n \n-\tu8 padding[4];\n+\tu8\t\t\tpadding[4];\n };\n \n /* Set Queue Filters */\n struct vfpf_q_mac_vlan_filter {\n \tu32 flags;\n-#define VFPF_Q_FILTER_DEST_MAC_VALID    0x01\n-#define VFPF_Q_FILTER_VLAN_TAG_VALID    0x02\n-#define VFPF_Q_FILTER_SET_MAC\t0x100\t/* set/clear */\n+\t#define VFPF_Q_FILTER_DEST_MAC_VALID    0x01\n+\t#define VFPF_Q_FILTER_VLAN_TAG_VALID    0x02\n+\t#define VFPF_Q_FILTER_SET_MAC\t\t0x100   /* set/clear */\n \n-\tu8 mac[ETH_ALEN];\n+\tu8  mac[ETH_ALEN];\n \tu16 vlan_tag;\n \n-\tu8 padding[4];\n+\tu8\tpadding[4];\n };\n \n /* Start a vport */\n struct vfpf_vport_start_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n \taligned_u64 sb_addr[PFVF_MAX_SBS_PER_VF];\n \n-\tu32 tpa_mode;\n-\tu16 dep1;\n-\tu16 mtu;\n+\tu32\t\t\ttpa_mode;\n+\tu16\t\t\tdep1;\n+\tu16\t\t\tmtu;\n \n-\tu8 vport_id;\n-\tu8 inner_vlan_removal;\n+\tu8\t\t\tvport_id;\n+\tu8\t\t\tinner_vlan_removal;\n \n-\tu8 only_untagged;\n-\tu8 max_buffers_per_cqe;\n+\tu8\t\t\tonly_untagged;\n+\tu8\t\t\tmax_buffers_per_cqe;\n \n-\tu8 padding[4];\n+\tu8\t\t\tpadding[4];\n };\n \n /* Extended tlvs - need to add rss, mcast, accept mode tlvs */\n struct vfpf_vport_update_activate_tlv {\n-\tstruct channel_tlv tl;\n-\tu8 update_rx;\n-\tu8 update_tx;\n-\tu8 active_rx;\n-\tu8 active_tx;\n+\tstruct channel_tlv\ttl;\n+\tu8\t\t\tupdate_rx;\n+\tu8\t\t\tupdate_tx;\n+\tu8\t\t\tactive_rx;\n+\tu8\t\t\tactive_tx;\n };\n \n struct vfpf_vport_update_tx_switch_tlv {\n-\tstruct channel_tlv tl;\n-\tu8 tx_switching;\n-\tu8 padding[3];\n+\tstruct channel_tlv\ttl;\n+\tu8\t\t\ttx_switching;\n+\tu8\t\t\tpadding[3];\n };\n \n struct vfpf_vport_update_vlan_strip_tlv {\n-\tstruct channel_tlv tl;\n-\tu8 remove_vlan;\n-\tu8 padding[3];\n+\tstruct channel_tlv\ttl;\n+\tu8\t\t\tremove_vlan;\n+\tu8\t\t\tpadding[3];\n };\n \n struct vfpf_vport_update_mcast_bin_tlv {\n-\tstruct channel_tlv tl;\n-\tu8 padding[4];\n+\tstruct channel_tlv\ttl;\n+\tu8\t\t\tpadding[4];\n \n \taligned_u64 bins[8];\n };\n \n struct vfpf_vport_update_accept_param_tlv {\n \tstruct channel_tlv tl;\n-\tu8 update_rx_mode;\n-\tu8 update_tx_mode;\n-\tu8 rx_accept_filter;\n-\tu8 tx_accept_filter;\n+\tu8\tupdate_rx_mode;\n+\tu8\tupdate_tx_mode;\n+\tu8\trx_accept_filter;\n+\tu8\ttx_accept_filter;\n };\n \n struct vfpf_vport_update_accept_any_vlan_tlv {\n@@ -371,29 +371,29 @@ struct vfpf_vport_update_accept_any_vlan_tlv {\n };\n \n struct vfpf_vport_update_sge_tpa_tlv {\n-\tstruct channel_tlv tl;\n+\tstruct channel_tlv\ttl;\n \n-\tu16 sge_tpa_flags;\n-#define VFPF_TPA_IPV4_EN_FLAG\t     (1 << 0)\n-#define VFPF_TPA_IPV6_EN_FLAG        (1 << 1)\n-#define VFPF_TPA_PKT_SPLIT_FLAG      (1 << 2)\n-#define VFPF_TPA_HDR_DATA_SPLIT_FLAG (1 << 3)\n-#define VFPF_TPA_GRO_CONSIST_FLAG    (1 << 4)\n+\tu16\t\t\tsge_tpa_flags;\n+\t#define VFPF_TPA_IPV4_EN_FLAG\t     (1 << 0)\n+\t#define VFPF_TPA_IPV6_EN_FLAG        (1 << 1)\n+\t#define VFPF_TPA_PKT_SPLIT_FLAG      (1 << 2)\n+\t#define VFPF_TPA_HDR_DATA_SPLIT_FLAG (1 << 3)\n+\t#define VFPF_TPA_GRO_CONSIST_FLAG    (1 << 4)\n \n-\tu8 update_sge_tpa_flags;\n-#define VFPF_UPDATE_SGE_DEPRECATED_FLAG\t   (1 << 0)\n-#define VFPF_UPDATE_TPA_EN_FLAG    (1 << 1)\n-#define VFPF_UPDATE_TPA_PARAM_FLAG (1 << 2)\n+\tu8\t\t\tupdate_sge_tpa_flags;\n+\t#define VFPF_UPDATE_SGE_DEPRECATED_FLAG\t   (1 << 0)\n+\t#define VFPF_UPDATE_TPA_EN_FLAG    (1 << 1)\n+\t#define VFPF_UPDATE_TPA_PARAM_FLAG (1 << 2)\n \n-\tu8 max_buffers_per_cqe;\n+\tu8\t\t\tmax_buffers_per_cqe;\n \n-\tu16 deprecated_sge_buff_size;\n-\tu16 tpa_max_size;\n-\tu16 tpa_min_size_to_start;\n-\tu16 tpa_min_size_to_cont;\n+\tu16\t\t\tdeprecated_sge_buff_size;\n+\tu16\t\t\ttpa_max_size;\n+\tu16\t\t\ttpa_min_size_to_start;\n+\tu16\t\t\ttpa_min_size_to_cont;\n \n-\tu8 tpa_max_aggs_num;\n-\tu8 padding[7];\n+\tu8\t\t\ttpa_max_aggs_num;\n+\tu8\t\t\tpadding[7];\n \n };\n \n@@ -405,15 +405,15 @@ struct vfpf_vport_update_tlv {\n };\n \n struct vfpf_ucast_filter_tlv {\n-\tstruct vfpf_first_tlv first_tlv;\n+\tstruct vfpf_first_tlv\tfirst_tlv;\n \n-\tu8 opcode;\n-\tu8 type;\n+\tu8\t\t\topcode;\n+\tu8\t\t\ttype;\n \n-\tu8 mac[ETH_ALEN];\n+\tu8\t\t\tmac[ETH_ALEN];\n \n-\tu16 vlan;\n-\tu16 padding[3];\n+\tu16\t\t\tvlan;\n+\tu16\t\t\tpadding[3];\n };\n \n struct tlv_buffer_size {\n@@ -421,26 +421,26 @@ struct tlv_buffer_size {\n };\n \n union vfpf_tlvs {\n-\tstruct vfpf_first_tlv first_tlv;\n-\tstruct vfpf_acquire_tlv acquire;\n+\tstruct vfpf_first_tlv\t\t\tfirst_tlv;\n+\tstruct vfpf_acquire_tlv\t\t\tacquire;\n \tstruct vfpf_init_tlv init;\n-\tstruct vfpf_start_rxq_tlv start_rxq;\n-\tstruct vfpf_start_txq_tlv start_txq;\n-\tstruct vfpf_stop_rxqs_tlv stop_rxqs;\n-\tstruct vfpf_stop_txqs_tlv stop_txqs;\n-\tstruct vfpf_update_rxq_tlv update_rxq;\n-\tstruct vfpf_vport_start_tlv start_vport;\n-\tstruct vfpf_vport_update_tlv vport_update;\n-\tstruct vfpf_ucast_filter_tlv ucast_filter;\n+\tstruct vfpf_start_rxq_tlv\t\tstart_rxq;\n+\tstruct vfpf_start_txq_tlv\t\tstart_txq;\n+\tstruct vfpf_stop_rxqs_tlv\t\tstop_rxqs;\n+\tstruct vfpf_stop_txqs_tlv\t\tstop_txqs;\n+\tstruct vfpf_update_rxq_tlv\t\tupdate_rxq;\n+\tstruct vfpf_vport_start_tlv\t\tstart_vport;\n+\tstruct vfpf_vport_update_tlv\t\tvport_update;\n+\tstruct vfpf_ucast_filter_tlv\t\tucast_filter;\n \tstruct channel_list_end_tlv list_end;\n-\tstruct tlv_buffer_size tlv_buf_size;\n+\tstruct tlv_buffer_size\t\t\ttlv_buf_size;\n };\n \n union pfvf_tlvs {\n-\tstruct pfvf_def_resp_tlv default_resp;\n-\tstruct pfvf_acquire_resp_tlv acquire_resp;\n+\tstruct pfvf_def_resp_tlv\t\tdefault_resp;\n+\tstruct pfvf_acquire_resp_tlv\t\tacquire_resp;\n \tstruct channel_list_end_tlv list_end;\n-\tstruct tlv_buffer_size tlv_buf_size;\n+\tstruct tlv_buffer_size\t\t\ttlv_buf_size;\n };\n \n /* This is a structure which is allocated in the VF, which the PF may update\n@@ -533,7 +533,7 @@ struct ecore_bulletin {\n enum {\n /*!!!!! Make sure to update STRINGS structure accordingly !!!!!*/\n \n-\tCHANNEL_TLV_NONE,\t/* ends tlv sequence */\n+\tCHANNEL_TLV_NONE, /* ends tlv sequence */\n \tCHANNEL_TLV_ACQUIRE,\n \tCHANNEL_TLV_VPORT_START,\n \tCHANNEL_TLV_VPORT_UPDATE,\ndiff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h\nindex 046bbb2..71ef615 100644\n--- a/drivers/net/qede/base/eth_common.h\n+++ b/drivers/net/qede/base/eth_common.h\n@@ -12,43 +12,43 @@\n /* ETH FW CONSTANTS */\n /********************/\n #define ETH_CACHE_LINE_SIZE                 64\n-#define ETH_RX_CQE_GAP\t\t\t\t\t\t32\n-#define ETH_MAX_RAMROD_PER_CON\t\t\t\t8\n-#define ETH_TX_BD_PAGE_SIZE_BYTES\t\t\t4096\n-#define ETH_RX_BD_PAGE_SIZE_BYTES\t\t\t4096\n-#define ETH_RX_CQE_PAGE_SIZE_BYTES\t\t\t4096\n-#define ETH_RX_NUM_NEXT_PAGE_BDS\t\t\t2\n-\n-#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT\t\t\t\t1\n-#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET\t\t\t18\n-#define ETH_TX_MAX_LSO_HDR_NBD\t\t\t\t\t\t4\n-#define ETH_TX_MIN_BDS_PER_LSO_PKT\t\t\t\t\t3\n-#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT\t3\n-#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT\t\t2\n-#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE\t\t2\n+#define ETH_RX_CQE_GAP                      32\n+#define ETH_MAX_RAMROD_PER_CON              8\n+#define ETH_TX_BD_PAGE_SIZE_BYTES           4096\n+#define ETH_RX_BD_PAGE_SIZE_BYTES           4096\n+#define ETH_RX_CQE_PAGE_SIZE_BYTES          4096\n+#define ETH_RX_NUM_NEXT_PAGE_BDS            2\n+\n+#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT              1\n+#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET           18\n+#define ETH_TX_MAX_LSO_HDR_NBD                      4\n+#define ETH_TX_MIN_BDS_PER_LSO_PKT                  3\n+#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT   3\n+#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT        2\n+#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE      2\n #define ETH_TX_MAX_NON_LSO_PKT_LEN                  (9700 - (4 + 12 + 8))\n #define ETH_TX_MAX_LSO_HDR_BYTES                    510\n #define ETH_TX_LSO_WINDOW_BDS_NUM                   18\n #define ETH_TX_LSO_WINDOW_MIN_LEN                   9700\n #define ETH_TX_MAX_LSO_PAYLOAD_LEN                  0xFFFF\n \n-#define ETH_NUM_STATISTIC_COUNTERS\t\t\tMAX_NUM_VPORTS\n+#define ETH_NUM_STATISTIC_COUNTERS                  MAX_NUM_VPORTS\n \n #define ETH_RX_MAX_BUFF_PER_PKT             5\n \n /* num of MAC/VLAN filters */\n-#define ETH_NUM_MAC_FILTERS\t\t\t\t\t512\n-#define ETH_NUM_VLAN_FILTERS\t\t\t\t512\n+#define ETH_NUM_MAC_FILTERS                 512\n+#define ETH_NUM_VLAN_FILTERS                512\n \n /* approx. multicast constants */\n-#define ETH_MULTICAST_BIN_FROM_MAC_SEED\t    0\n-#define ETH_MULTICAST_MAC_BINS\t\t\t\t256\n-#define ETH_MULTICAST_MAC_BINS_IN_REGS\t\t(ETH_MULTICAST_MAC_BINS / 32)\n+#define ETH_MULTICAST_BIN_FROM_MAC_SEED     0\n+#define ETH_MULTICAST_MAC_BINS              256\n+#define ETH_MULTICAST_MAC_BINS_IN_REGS      (ETH_MULTICAST_MAC_BINS / 32)\n \n /*  ethernet vport update constants */\n-#define ETH_FILTER_RULES_COUNT\t\t\t\t10\n-#define ETH_RSS_IND_TABLE_ENTRIES_NUM\t\t128\n-#define ETH_RSS_KEY_SIZE_REGS\t\t\t    10\n+#define ETH_FILTER_RULES_COUNT              10\n+#define ETH_RSS_IND_TABLE_ENTRIES_NUM       128\n+#define ETH_RSS_KEY_SIZE_REGS               10\n #define ETH_RSS_ENGINE_NUM_K2               207\n #define ETH_RSS_ENGINE_NUM_BB               127\n \n@@ -115,14 +115,14 @@ struct eth_tx_data_1st_bd {\n \t__le16 vlan /* VLAN to insert to packet (if needed). */;\n \t\t/* Number of BDs in packet. Should be at least 2 in non-LSO\n \t\t* packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet.\n-\t\t*/\n+ */\n \tu8 nbds;\n \tstruct eth_tx_1st_bd_flags bd_flags;\n \t__le16 bitfields;\n #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK  0x1\n #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0\n-#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK          0x1\n-#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT         1\n+#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK  0x1\n+#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1\n #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK        0x3FFF\n #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT       2\n };\ndiff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h\nindex 7192265..6f4b4f8 100644\n--- a/drivers/net/qede/base/mcp_public.h\n+++ b/drivers/net/qede/base/mcp_public.h\n@@ -26,7 +26,7 @@\n #define MCP_GLOB_PORT_MAX\t4\t/* Global */\n #define MCP_GLOB_FUNC_MAX\t16\t/* Global */\n \n-typedef u32 offsize_t;\t\t/* In DWORDS !!! */\n+typedef u32 offsize_t;      /* In DWORDS !!! */\n /* Offset from the beginning of the MCP scratchpad */\n #define OFFSIZE_OFFSET_SHIFT\t0\n #define OFFSIZE_OFFSET_MASK\t0x0000ffff\n@@ -35,18 +35,18 @@ typedef u32 offsize_t;\t\t/* In DWORDS !!! */\n #define OFFSIZE_SIZE_MASK\t0xffff0000\n \n /* SECTION_OFFSET is calculating the offset in bytes out of offsize */\n-#define SECTION_OFFSET(_offsize) \\\n-((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))\n+#define SECTION_OFFSET(_offsize)\t\\\n+\t((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))\n \n /* SECTION_SIZE is calculating the size in bytes out of offsize */\n-#define SECTION_SIZE(_offsize) \\\n-(((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)\n+#define SECTION_SIZE(_offsize)\t\t\\\n+\t(((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)\n \n-#define SECTION_ADDR(_offsize, idx) \\\n+#define SECTION_ADDR(_offsize, idx)\t\\\n (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))\n \n #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \\\n-(_pub_base + offsetof(struct mcp_public_data, sections[_section]))\n+\t(_pub_base + offsetof(struct mcp_public_data, sections[_section]))\n \n /* PHY configuration */\n struct pmm_phy_cfg {\n@@ -54,13 +54,13 @@ struct pmm_phy_cfg {\n #define PMM_SPEED_AUTONEG   0\n #define PMM_SPEED_SMARTLINQ  0x8\n \n-\tu32 pause;\t\t/* bitmask */\n+\tu32 pause;      /* bitmask */\n #define PMM_PAUSE_NONE\t\t0x0\n #define PMM_PAUSE_AUTONEG\t0x1\n #define PMM_PAUSE_RX\t\t0x2\n #define PMM_PAUSE_TX\t\t0x4\n \n-\tu32 adv_speed;\t\t/* Default should be the speed_cap_mask */\n+\tu32 adv_speed;      /* Default should be the speed_cap_mask */\n \tu32 loopback_mode;\n #define PMM_LOOPBACK_NONE\t\t0\n #define PMM_LOOPBACK_INT_PHY\t\t1\n@@ -76,7 +76,7 @@ struct pmm_phy_cfg {\n };\n \n struct port_mf_cfg {\n-\tu32 dynamic_cfg;\t/* device control channel */\n+\tu32 dynamic_cfg;    /* device control channel */\n #define PORT_MF_CFG_OV_TAG_MASK              0x0000ffff\n #define PORT_MF_CFG_OV_TAG_SHIFT             0\n #define PORT_MF_CFG_OV_TAG_DEFAULT         PORT_MF_CFG_OV_TAG_MASK\n@@ -88,51 +88,51 @@ struct port_mf_cfg {\n  * MUST be synced with struct pmm_stats_map\n  */\n struct pmm_stats {\n-\tu64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter */\n-\tu64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter */\n-\tu64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter */\n-\tu64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter */\n-\tu64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter */\n+\tu64 r64;        /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/\n+\tu64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/\n+\tu64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/\n+\tu64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/\n+\tu64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/\n \tu64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */\n \tu64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged  */\n-\tu64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter */\n-\tu64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter */\n-\tu64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter */\n+\tu64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/\n+\tu64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/\n+\tu64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/\n \tu64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame ctr */\n-\tu64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter */\n-\tu64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter */\n-\tu64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter */\n-\tu64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter */\n-\tu64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter */\n-\tu64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */\n-\tu64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter */\n-\tu64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */\n-\tu64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */\n-\tu64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */\n-\tu64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */\n+\tu64 rfcs;       /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/\n+\tu64 rxcf;       /* 0x10 (Offset 0x60 ) RX control frame counter*/\n+\tu64 rxpf;       /* 0x11 (Offset 0x68 ) RX pause frame counter*/\n+\tu64 rxpp;       /* 0x12 (Offset 0x70 ) RX PFC frame counter*/\n+\tu64 raln;       /* 0x16 (Offset 0x78 ) RX alignment error counter*/\n+\tu64 rfcr;       /* 0x19 (Offset 0x80 ) RX false carrier counter */\n+\tu64 rovr;       /* 0x1A (Offset 0x88 ) RX oversized frame counter*/\n+\tu64 rjbr;       /* 0x1B (Offset 0x90 ) RX jabber frame counter */\n+\tu64 rund;       /* 0x34 (Offset 0x98 ) RX undersized frame counter */\n+\tu64 rfrg;       /* 0x35 (Offset 0xa0 ) RX fragment counter */\n+\tu64 t64;        /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */\n \tu64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */\n-\tu64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter */\n-\tu64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter */\n-\tu64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter */\n+\tu64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/\n+\tu64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/\n+\tu64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/\n \tu64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */\n \tu64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */\n \tu64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */\n \tu64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */\n \tu64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame ctr */\n-\tu64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */\n-\tu64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */\n+\tu64 txpf;       /* 0x50 (Offset 0xf8 ) TX pause frame counter */\n+\tu64 txpp;       /* 0x51 (Offset 0x100) TX PFC frame counter */\n \tu64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC */\n \tu64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */\n-\tu64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */\n-\tu64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */\n-\tu64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */\n-\tu64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */\n+\tu64 rbyte;      /* 0x3d (Offset 0x118) RX byte counter */\n+\tu64 rxuca;      /* 0x0c (Offset 0x120) RX UC frame counter */\n+\tu64 rxmca;      /* 0x0d (Offset 0x128) RX MC frame counter */\n+\tu64 rxbca;      /* 0x0e (Offset 0x130) RX BC frame counter */\n \tu64 rxpok; /* 0x22 (Offset 0x138) RX good frame */\n-\tu64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */\n-\tu64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */\n-\tu64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */\n-\tu64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */\n-\tu64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */\n+\tu64 tbyte;      /* 0x6f (Offset 0x140) TX byte counter */\n+\tu64 txuca;      /* 0x4d (Offset 0x148) TX UC frame counter */\n+\tu64 txmca;      /* 0x4e (Offset 0x150) TX MC frame counter */\n+\tu64 txbca;      /* 0x4f (Offset 0x158) TX BC frame counter */\n+\tu64 txcf;       /* 0x54 (Offset 0x160) TX control frame counter */\n };\n \n struct brb_stats {\n@@ -151,18 +151,18 @@ struct port_stats {\n  *      | ports            |         |         |        |          |\n  *======+==================+=========+=========+========+======================\n  * BB   | 1x100G           | This is special mode, where there are 2 HW func\n- * BB   | 2x10/20Gbps      | 0,1     | NA      |  No    | 1        | 1\n- * BB   | 2x40 Gbps        | 0,1     | NA      |  Yes   | 1        | 1\n- * BB   | 2x50Gbps         | 0,1     | NA      |  No    | 1        | 1\n+ * BB | 2x10/20Gbps| 0,1     | NA      |  No    | 1        | 1\n+ * BB | 2x40 Gbps  | 0,1     | NA      |  Yes   | 1        | 1\n+ * BB | 2x50Gbps   | 0,1     | NA      |  No    | 1        | 1\n  * BB   | 4x10Gbps         | 0,2     | 1,3     |  No    | 1/2      | 1,2\n  * BB   | 4x10Gbps         | 0,1     | 2,3     |  No    | 1/2      | 1,2\n  * BB   | 4x10Gbps         | 0,3     | 1,2     |  No    | 1/2      | 1,2\n- * BB   | 4x10Gbps         | 0,1,2,3 | NA      |  No    | 1        | 1\n- * AH   | 2x10/20Gbps      | 0,1     | NA      |  NA    | 1        | NA\n- * AH   | 4x10Gbps         | 0,1     | 2,3     |  NA    | 2        | NA\n- * AH   | 4x10Gbps         | 0,2     | 1,3     |  NA    | 2        | NA\n- * AH   | 4x10Gbps         | 0,3     | 1,2     |  NA    | 2        | NA\n- * AH   | 4x10Gbps         | 0,1,2,3 | NA      |  NA    | 1        | NA\n+ * BB | 4x10Gbps   | 0,1,2,3 | NA      |  No    | 1        | 1\n+ * AH | 2x10/20Gbps| 0,1     | NA      |  NA    | 1        | NA\n+ * AH | 4x10Gbps   | 0,1     | 2,3     |  NA    | 2        | NA\n+ * AH | 4x10Gbps   | 0,2     | 1,3     |  NA    | 2        | NA\n+ * AH | 4x10Gbps   | 0,3     | 1,2     |  NA    | 2        | NA\n+ * AH | 4x10Gbps   | 0,1,2,3 | NA      |  NA    | 1        | NA\n  *======+==================+=========+=========+========+=======================\n  */\n \n@@ -216,13 +216,13 @@ struct lldp_config_params_s {\n \tu32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];\n \t/* Holds local Port ID TLV header, subtype and 9B of payload.\n \t * If firtst byte is 0, then we will use default port ID\n-\t */\n+\t*/\n \tu32 local_port_id[LLDP_PORT_ID_STAT_LEN];\n };\n \n struct lldp_status_params_s {\n \tu32 prefix_seq_num;\n-\tu32 status;\t\t/* TBD */\n+\tu32 status; /* TBD */\n \t/* Holds remote Chassis ID TLV header, subtype and 9B of payload.\n \t */\n \tu32 local_port_id[LLDP_PORT_ID_STAT_LEN];\n@@ -245,11 +245,11 @@ struct dcbx_ets_feature {\n #define DCBX_ETS_CBS_SHIFT                      3\n #define DCBX_ETS_MAX_TCS_MASK                   0x000000f0\n #define DCBX_ETS_MAX_TCS_SHIFT                  4\n-\tu32 pri_tc_tbl[1];\n+\tu32  pri_tc_tbl[1];\n #define DCBX_CEE_STRICT_PRIORITY\t\t0xf\n #define DCBX_CEE_STRICT_PRIORITY_TC\t\t0x7\n-\tu32 tc_bw_tbl[2];\n-\tu32 tc_tsa_tbl[2];\n+\tu32  tc_bw_tbl[2];\n+\tu32  tc_tsa_tbl[2];\n #define DCBX_ETS_TSA_STRICT\t\t\t0\n #define DCBX_ETS_TSA_CBS\t\t\t1\n #define DCBX_ETS_TSA_ETS\t\t\t2\n@@ -287,12 +287,12 @@ struct dcbx_app_priority_feature {\n \t/* Not in use\n \t * #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00\n \t * #define DCBX_APP_DEFAULT_PRI_SHIFT      8\n-\t */\n+\t*/\n #define DCBX_APP_MAX_TCS_MASK           0x0000f000\n #define DCBX_APP_MAX_TCS_SHIFT          12\n #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000\n #define DCBX_APP_NUM_ENTRIES_SHIFT      16\n-\tstruct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];\n+\tstruct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];\n };\n \n /* FW structure in BE */\n@@ -350,7 +350,7 @@ struct dcbx_mib {\n \t * #define DCBX_CONFIG_VERSION_DISABLED        0\n \t * #define DCBX_CONFIG_VERSION_IEEE            1\n \t * #define DCBX_CONFIG_VERSION_CEE             2\n-\t */\n+\t*/\n \tstruct dcbx_features features;\n \tu32 suffix_seq_num;\n };\n@@ -367,9 +367,9 @@ struct lldp_system_tlvs_buffer_s {\n /*                                    */\n /**************************************/\n struct public_global {\n-\tu32 max_path; /* 32bit is wasty, but this will be used often */\n+\tu32 max_path;       /* 32bit is wasty, but this will be used often */\n \tu32 max_ports; /* (Global) 32bit is wasty, this will be used often */\n-#define MODE_1P\t1 /* TBD - NEED TO THINK OF A BETTER NAME */\n+#define MODE_1P\t1\t\t/* TBD - NEED TO THINK OF A BETTER NAME */\n #define MODE_2P\t2\n #define MODE_3P\t3\n #define MODE_4P\t4\n@@ -406,7 +406,7 @@ struct public_global {\n struct fw_flr_mb {\n \tu32 aggint;\n \tu32 opgen_addr;\n-\tu32 accum_ack;\t\t/* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */\n+\tu32 accum_ack;      /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */\n #define ACCUM_ACK_PF_BASE\t0\n #define ACCUM_ACK_PF_SHIFT\t0\n \n@@ -424,10 +424,10 @@ struct public_path {\n \t * mcp_vf_disabled is set by the MCP to indicate the driver about VFs\n \t * which were disabled/flred\n \t */\n-\tu32 mcp_vf_disabled[VF_MAX_STATIC / 32];\t/* 0x003c */\n+\tu32 mcp_vf_disabled[VF_MAX_STATIC / 32];    /* 0x003c */\n \n \tu32 process_kill;\n-\t/* Reset on mcp reset, and incremented for eveny process kill event. */\n+/* Reset on mcp reset, and incremented for eveny process kill event. */\n #define PROCESS_KILL_COUNTER_MASK\t\t0x0000ffff\n #define PROCESS_KILL_COUNTER_SHIFT\t\t0\n #define PROCESS_KILL_GLOB_AEU_BIT_MASK\t\t0xffff0000\n@@ -464,7 +464,7 @@ struct dci_fc_npiv_tbl {\n  ****************************************************************************/\n \n struct public_port {\n-\tu32 validity_map;\t/* 0x0 (4*2 = 0x8) */\n+\tu32 validity_map;   /* 0x0 (4*2 = 0x8) */\n \n \t/* validity bits */\n #define MCP_VALIDITY_PCI_CFG                    0x00100000\n@@ -485,7 +485,7 @@ struct public_port {\n #define MCP_VALIDITY_ACTIVE_MFW_NONE            0x000001c0\n \n \tu32 link_status;\n-#define LINK_STATUS_LINK_UP\t\t\t0x00000001\n+#define LINK_STATUS_LINK_UP\t\t\t\t\t0x00000001\n #define LINK_STATUS_SPEED_AND_DUPLEX_MASK\t\t\t0x0000001e\n #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD\t\t(1 << 1)\n #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD\t\t(2 << 1)\n@@ -501,7 +501,7 @@ struct public_port {\n #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE\t\t\t0x00000040\n #define LINK_STATUS_PARALLEL_DETECTION_USED\t\t\t0x00000080\n \n-#define LINK_STATUS_PFC_ENABLED\t\t\t\t0x00000100\n+#define LINK_STATUS_PFC_ENABLED\t\t\t\t\t0x00000100\n #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE\t0x00000200\n #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE\t0x00000400\n #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE\t\t0x00000800\n@@ -537,15 +537,15 @@ struct public_port {\n \tstruct port_stats stats;\n \n \tu32 media_type;\n-#define\tMEDIA_UNSPECIFIED\t\t0x0\n+#define\tMEDIA_UNSPECIFIED\t0x0\n #define\tMEDIA_SFPP_10G_FIBER\t0x1\n #define\tMEDIA_XFP_FIBER\t\t\t0x2\n-#define\tMEDIA_DA_TWINAX\t\t\t0x3\n-#define\tMEDIA_BASE_T\t\t\t0x4\n+#define\tMEDIA_DA_TWINAX\t\t0x3\n+#define\tMEDIA_BASE_T\t\t0x4\n #define MEDIA_SFP_1G_FIBER\t\t0x5\n-#define MEDIA_MODULE_FIBER\t\t0x6\n-#define\tMEDIA_KR\t\t\t\t0xf0\n-#define\tMEDIA_NOT_PRESENT\t\t0xff\n+#define MEDIA_MODULE_FIBER\t0x6\n+#define\tMEDIA_KR\t\t0xf0\n+#define\tMEDIA_NOT_PRESENT\t0xff\n \n \tu32 lfa_status;\n #define LFA_LINK_FLAP_REASON_OFFSET\t\t0\n@@ -574,7 +574,7 @@ struct public_port {\n \tstruct dcbx_mib remote_dcbx_mib;\n \tstruct dcbx_mib operational_dcbx_mib;\n \n-\t/* FC_NPIV table offset & size in NVRAM value of 0 means not present */\n+/* FC_NPIV table offset & size in NVRAM value of 0 means not present */\n \tu32 fc_npiv_nvram_tbl_addr;\n \tu32 fc_npiv_nvram_tbl_size;\n \tu32 transceiver_data;\n@@ -641,7 +641,7 @@ struct public_func {\n \n \t/* MTU size per funciton is needed for the OV feature */\n \tu32 mtu_size;\n-\t/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */\n+/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */\n \t/* For PCP values 0-3 use the map lower */\n \t/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,\n \t * 0x0000FF00 - PCP 2, 0x000000FF PCP 3\n@@ -650,7 +650,7 @@ struct public_func {\n \t/* For PCP values 4-7 use the map upper */\n \t/* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,\n \t * 0x0000FF00 - PCP 6, 0x000000FF PCP 7\n-\t */\n+\t*/\n \tu32 c2s_pcp_map_upper;\n \n \t/* For PCP default value get the MSB byte of the map default */\n@@ -683,7 +683,7 @@ struct public_func {\n \tu32 status;\n #define FUNC_STATUS_VLINK_DOWN\t\t\t0x00000001\n \n-\tu32 mac_upper;\t\t/* MAC */\n+\tu32 mac_upper;      /* MAC */\n #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff\n #define FUNC_MF_CFG_UPPERMAC_SHIFT              0\n #define FUNC_MF_CFG_UPPERMAC_DEFAULT            FUNC_MF_CFG_UPPERMAC_MASK\n@@ -692,14 +692,14 @@ struct public_func {\n \n \tu32 dpdk_rsvd2[4];\n \n-\tu32 ovlan_stag;\t\t/* tags */\n+\tu32 ovlan_stag;     /* tags */\n #define FUNC_MF_CFG_OV_STAG_MASK              0x0000ffff\n #define FUNC_MF_CFG_OV_STAG_SHIFT             0\n #define FUNC_MF_CFG_OV_STAG_DEFAULT           FUNC_MF_CFG_OV_STAG_MASK\n \n-\tu32 pf_allocation;\t/* vf per pf */\n+\tu32 pf_allocation; /* vf per pf */\n \n-\tu32 preserve_data;\t/* Will be used bt CCM */\n+\tu32 preserve_data; /* Will be used bt CCM */\n \n \tu32 driver_last_activity_ts;\n \n@@ -707,7 +707,7 @@ struct public_func {\n \t * drv_ack_vf_disabled is set by the PF driver to ack handled disabled\n \t * VFs\n \t */\n-\tu32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];\t/* 0x0044 */\n+\tu32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];    /* 0x0044 */\n \n \tu32 drv_id;\n #define DRV_ID_PDA_COMP_VER_MASK\t0x0000ffff\n@@ -747,7 +747,7 @@ struct public_func {\n  */\n \n struct mcp_mac {\n-\tu32 mac_upper;\t\t/* Upper 16 bits are always zeroes */\n+\tu32 mac_upper;      /* Upper 16 bits are always zeroes */\n \tu32 mac_lower;\n };\n \n@@ -784,12 +784,12 @@ struct ocbb_data_stc {\n };\n \n union drv_union_data {\n-\tu32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];\t/* LOAD_REQ */\n-\tstruct mcp_mac wol_mac;\t/* UNLOAD_DONE */\n+\tu32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];    /* LOAD_REQ */\n+\tstruct mcp_mac wol_mac; /* UNLOAD_DONE */\n \n \tstruct pmm_phy_cfg drv_phy_cfg;\n \n-\tstruct mcp_val64 val64;\t/* For PHY / AVS commands */\n+\tstruct mcp_val64 val64; /* For PHY / AVS commands */\n \n \tu8 raw_data[MCP_DRV_NVM_BUF_LEN];\n \n@@ -822,7 +822,7 @@ struct public_drv_mb {\n \t/* Vitaly: LLDP commands */\n #define DRV_MSG_CODE_SET_LLDP                   0x24000000\n #define DRV_MSG_CODE_SET_DCBX                   0x25000000\n-\t/* OneView feature driver HSI */\n+\t/* OneView feature driver HSI*/\n #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG\t\t0x26000000\n #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM\t\t0x27000000\n #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS\t0x28000000\n@@ -893,7 +893,7 @@ struct public_drv_mb {\n #define DRV_MB_PARAM_INIT_PHY_FORCE\t\t0x00000001\n #define DRV_MB_PARAM_INIT_PHY_DONT_CARE\t\t0x00000002\n \n-\t/* LLDP / DCBX params */\n+\t/* LLDP / DCBX params*/\n #define DRV_MB_PARAM_LLDP_SEND_MASK\t\t0x00000001\n #define DRV_MB_PARAM_LLDP_SEND_SHIFT\t\t0\n #define DRV_MB_PARAM_LLDP_AGENT_MASK\t\t0x00000006\n@@ -925,7 +925,7 @@ struct public_drv_mb {\n #define DRV_MB_PARAM_PHYMOD_LANE_MASK\t\t0x000000FF\n #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT\t\t8\n #define DRV_MB_PARAM_PHYMOD_SIZE_MASK\t\t0x000FFF00\n-\t/* configure vf MSIX params */\n+\t/* configure vf MSIX params*/\n #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT\t0\n #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK\t0x000000FF\n #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT\t8\n@@ -943,16 +943,16 @@ struct public_drv_mb {\n #define DRV_MB_PARAM_OV_CURR_CFG_DCI\t\t6\n #define DRV_MB_PARAM_OV_CURR_CFG_HII\t\t7\n \n-#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT\t\t\t0\n+#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT\t\t\t\t0\n #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK\t\t\t0x000000FF\n-#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE\t\t\t(1 << 0)\n+#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE\t\t\t\t(1 << 0)\n #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND\t\t\t(1 << 2)\n #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT\t\t(1 << 4)\n #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED\t\t\t(1 << 5)\n #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF\t\t\t(1 << 6)\n #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED\t\t\t\t0\n \n-#define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT\t\t0\n+#define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT\t\t\t\t0\n #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK\t\t0x000000FF\n \n #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT\t\t0\n@@ -1063,7 +1063,7 @@ struct public_drv_mb {\n #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK           0x00160000\n #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR        0x00170000\n #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT\t\t0x00020000\n-#define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE\t\t0x000f0000\n+#define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE\t0x000f0000\n #define FW_MSG_CODE_GPIO_OK           0x00160000\n #define FW_MSG_CODE_GPIO_DIRECTION_ERR        0x00170000\n #define FW_MSG_CODE_GPIO_CTRL_ERR\t\t0x00020000\n@@ -1152,7 +1152,7 @@ enum MFW_DRV_MSG_TYPE {\n ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;)\n \n struct public_mfw_mb {\n-\tu32 sup_msgs;\t\t/* Assigend with MFW_DRV_MSG_MAX */\n+\tu32 sup_msgs;       /* Assigend with MFW_DRV_MSG_MAX */\n \tu32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];\n \tu32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];\n };\n@@ -1163,8 +1163,8 @@ struct public_mfw_mb {\n /*                                    */\n /**************************************/\n enum public_sections {\n-\tPUBLIC_DRV_MB,\t\t/* Points to the first drv_mb of path0 */\n-\tPUBLIC_MFW_MB,\t\t/* Points to the first mfw_mb of path0 */\n+\tPUBLIC_DRV_MB,      /* Points to the first drv_mb of path0 */\n+\tPUBLIC_MFW_MB,      /* Points to the first mfw_mb of path0 */\n \tPUBLIC_GLOBAL,\n \tPUBLIC_PATH,\n \tPUBLIC_PORT,\n@@ -1202,4 +1202,4 @@ struct mcp_public_data {\n #define MAX_I2C_TRANSACTION_SIZE\t16\n #define MAX_I2C_TRANSCEIVER_PAGE_SIZE\t256\n \n-#endif /* MCP_PUBLIC_H */\n+#endif\t\t\t\t/* MCP_PUBLIC_H */\ndiff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h\nindex 7f1a60d..8d99880 100644\n--- a/drivers/net/qede/base/nvm_cfg.h\n+++ b/drivers/net/qede/base/nvm_cfg.h\n@@ -22,8 +22,8 @@\n \n struct nvm_cfg_mac_address {\n \tu32 mac_addr_hi;\n-#define NVM_CFG_MAC_ADDRESS_HI_MASK                             0x0000FFFF\n-#define NVM_CFG_MAC_ADDRESS_HI_OFFSET                           0\n+\t\t#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF\n+\t\t#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0\n \tu32 mac_addr_lo;\n };\n \n@@ -31,107 +31,107 @@ struct nvm_cfg_mac_address {\n  * nvm_cfg1 structs\n  ******************************************/\n struct nvm_cfg1_glob {\n-\tu32 generic_cont0;\t/* 0x0 */\n-#define NVM_CFG1_GLOB_BOARD_SWAP_MASK                           0x0000000F\n-#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET                         0\n-#define NVM_CFG1_GLOB_BOARD_SWAP_NONE                           0x0\n-#define NVM_CFG1_GLOB_BOARD_SWAP_PATH                           0x1\n-#define NVM_CFG1_GLOB_BOARD_SWAP_PORT                           0x2\n-#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH                           0x3\n-#define NVM_CFG1_GLOB_MF_MODE_MASK                              0x00000FF0\n-#define NVM_CFG1_GLOB_MF_MODE_OFFSET                            4\n-#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED                        0x0\n-#define NVM_CFG1_GLOB_MF_MODE_DEFAULT                           0x1\n-#define NVM_CFG1_GLOB_MF_MODE_SPIO4                             0x2\n-#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0                           0x3\n-#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5                           0x4\n-#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0                           0x5\n-#define NVM_CFG1_GLOB_MF_MODE_BD                                0x6\n-#define NVM_CFG1_GLOB_MF_MODE_UFP                               0x7\n-#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK              0x00001000\n-#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET            12\n-#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED          0x0\n-#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED           0x1\n-#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK                       0x001FE000\n-#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET                     13\n-#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK                      0x1FE00000\n-#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET                    21\n-#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK                         0x20000000\n-#define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET                       29\n-#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED                     0x0\n-#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED                      0x1\n-#define NVM_CFG1_GLOB_ENABLE_ATC_MASK                           0x40000000\n-#define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET                         30\n-#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED                       0x0\n-#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED                        0x1\n-#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK                       0x80000000\n-#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET                     31\n-#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED                   0x0\n-#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED                    0x1\n-\tu32 engineering_change[3];\t/* 0x4 */\n-\tu32 manufacturing_id;\t/* 0x10 */\n-\tu32 serial_number[4];\t/* 0x14 */\n-\tu32 pcie_cfg;\t\t/* 0x24 */\n-#define NVM_CFG1_GLOB_PCI_GEN_MASK                              0x00000003\n-#define NVM_CFG1_GLOB_PCI_GEN_OFFSET                            0\n-#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1                          0x0\n-#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2                          0x1\n-#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3                          0x2\n-#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK                   0x00000004\n-#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET                 2\n-#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED               0x0\n-#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED                0x1\n-#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK                         0x00000018\n-#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET                       3\n-#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED               0x0\n-#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED                  0x2\n+\tu32 generic_cont0; /* 0x0 */\n+\t\t#define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F\n+\t\t#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0\n+\t\t#define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1\n+\t\t#define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2\n+\t\t#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_BD 0x6\n+\t\t#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7\n+\t\t#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000\n+\t\t#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12\n+\t\t#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1\n+\t\t#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000\n+\t\t#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13\n+\t\t#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000\n+\t\t#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21\n+\t\t#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000\n+\t\t#define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29\n+\t\t#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1\n+\t\t#define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000\n+\t\t#define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30\n+\t\t#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1\n+\t\t#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000\n+\t\t#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31\n+\t\t#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1\n+\tu32 engineering_change[3]; /* 0x4 */\n+\tu32 manufacturing_id; /* 0x10 */\n+\tu32 serial_number[4]; /* 0x14 */\n+\tu32 pcie_cfg; /* 0x24 */\n+\t\t#define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003\n+\t\t#define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0\n+\t\t#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1\n+\t\t#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2\n+\t\t#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004\n+\t\t#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2\n+\t\t#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1\n+\t\t#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018\n+\t\t#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3\n+\t\t#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2\n #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK     0x00000020\n-#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET   5\n-#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK                 0x000003C0\n-#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET               6\n-#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK                     0x00001C00\n-#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET                   10\n-#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW                       0x0\n-#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB                      0x1\n-#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB                    0x2\n-#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB                    0x3\n-#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK                     0x001FE000\n-#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET                   13\n-#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK                     0x1FE00000\n-#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET                   21\n-#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK                      0x60000000\n-#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET                    29\n+\t\t#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5\n+\t\t#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0\n+\t\t#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6\n+\t\t#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00\n+\t\t#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10\n+\t\t#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0\n+\t\t#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1\n+\t\t#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2\n+\t\t#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3\n+\t\t#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000\n+\t\t#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13\n+\t\t#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000\n+\t\t#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21\n+\t\t#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000\n+\t\t#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29\n \t/* Set the duration, in seconds, fan failure signal should be\n \t * sampled\n \t */\n #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK        0x80000000\n-#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET      31\n-\tu32 mgmt_traffic;\t/* 0x28 */\n-#define NVM_CFG1_GLOB_RESERVED60_MASK                           0x00000001\n-#define NVM_CFG1_GLOB_RESERVED60_OFFSET                         0\n-#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK                     0x000001FE\n-#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET                   1\n-#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK                     0x0001FE00\n-#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET                   9\n-#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK                        0x01FE0000\n-#define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET                      17\n-#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK                        0x06000000\n-#define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET                      25\n-#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED                    0x0\n-#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII                        0x1\n-#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII                       0x2\n-#define NVM_CFG1_GLOB_AUX_MODE_MASK                             0x78000000\n-#define NVM_CFG1_GLOB_AUX_MODE_OFFSET                           27\n-#define NVM_CFG1_GLOB_AUX_MODE_DEFAULT                          0x0\n-#define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY                       0x1\n+\t\t#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31\n+\tu32 mgmt_traffic; /* 0x28 */\n+\t\t#define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001\n+\t\t#define NVM_CFG1_GLOB_RESERVED60_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE\n+\t\t#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1\n+\t\t#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00\n+\t\t#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9\n+\t\t#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000\n+\t\t#define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17\n+\t\t#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000\n+\t\t#define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25\n+\t\t#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1\n+\t\t#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2\n+\t\t#define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000\n+\t\t#define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27\n+\t\t#define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0\n+\t\t#define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1\n \t/*  Indicates whether external thermal sonsor is available */\n-#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK              0x80000000\n-#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET            31\n-#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED          0x0\n-#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED           0x1\n-\tu32 core_cfg;\t\t/* 0x2C */\n-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK                    0x000000FF\n-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET                  0\n+\t\t#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000\n+\t\t#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31\n+\t\t#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1\n+\tu32 core_cfg; /* 0x2C */\n+\t\t#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0\n #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G                0x0\n #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G                0x1\n #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G               0x2\n@@ -153,753 +153,753 @@ struct nvm_cfg1_glob {\n #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET                    10\n #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK                     0x03FC0000\n #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET                   18\n-#define NVM_CFG1_GLOB_AVS_MODE_MASK                             0x1C000000\n-#define NVM_CFG1_GLOB_AVS_MODE_OFFSET                           26\n-#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP                       0x0\n-#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG                    0x1\n-#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP                    0x2\n-#define NVM_CFG1_GLOB_AVS_MODE_DISABLED                         0x3\n-#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK                 0x60000000\n-#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET               29\n-#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED             0x0\n-#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED              0x1\n-\tu32 e_lane_cfg1;\t/* 0x30 */\n-#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F\n-#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0\n-#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0\n-#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4\n-#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00\n-#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8\n-#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000\n-#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12\n-#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000\n-#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16\n-#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000\n-#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20\n-#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000\n-#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24\n-#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000\n-#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28\n-\tu32 e_lane_cfg2;\t/* 0x34 */\n-#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001\n-#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0\n-#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002\n-#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1\n-#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004\n-#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2\n-#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008\n-#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3\n-#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010\n-#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4\n-#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020\n-#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5\n-#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040\n-#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6\n-#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080\n-#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7\n-#define NVM_CFG1_GLOB_SMBUS_MODE_MASK                           0x00000F00\n-#define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET                         8\n-#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED                       0x0\n-#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ                         0x1\n-#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ                         0x2\n-#define NVM_CFG1_GLOB_NCSI_MASK                                 0x0000F000\n-#define NVM_CFG1_GLOB_NCSI_OFFSET                               12\n-#define NVM_CFG1_GLOB_NCSI_DISABLED                             0x0\n-#define NVM_CFG1_GLOB_NCSI_ENABLED                              0x1\n+\t\t#define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000\n+\t\t#define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26\n+\t\t#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0\n+\t\t#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1\n+\t\t#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2\n+\t\t#define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3\n+\t\t#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000\n+\t\t#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29\n+\t\t#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1\n+\tu32 e_lane_cfg1; /* 0x30 */\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28\n+\tu32 e_lane_cfg2; /* 0x34 */\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7\n+\t\t#define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00\n+\t\t#define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1\n+\t\t#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2\n+\t\t#define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000\n+\t\t#define NVM_CFG1_GLOB_NCSI_OFFSET 12\n+\t\t#define NVM_CFG1_GLOB_NCSI_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_NCSI_ENABLED 0x1\n \t/*  Maximum advertised pcie link width */\n-#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK                       0x000F0000\n-#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET                     16\n+\t\t#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000\n+\t\t#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16\n #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_16_LANES                   0x0\n-#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE                     0x1\n-#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES                    0x2\n-#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES                    0x3\n-#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES                    0x4\n+\t\t#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1\n+\t\t#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2\n+\t\t#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3\n+\t\t#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4\n \t/*  ASPM L1 mode */\n-#define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK                         0x00300000\n-#define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET                       20\n-#define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED                       0x0\n-#define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY          0x1\n-#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK                  0x01C00000\n-#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET                22\n-#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED              0x0\n-#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C           0x1\n-#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY              0x2\n-#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS         0x3\n+\t\t#define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000\n+\t\t#define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20\n+\t\t#define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0\n+\t\t#define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1\n+\t\t#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000\n+\t\t#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22\n+\t\t#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1\n+\t\t#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2\n+\t\t#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3\n #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK          0x06000000\n-#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET        25\n-#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE       0x0\n-#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL      0x1\n-#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL      0x2\n-#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH          0x3\n+\t\t#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25\n+\t\t#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0\n+\t\t#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1\n+\t\t#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2\n+\t\t#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3\n \t/*  Set the PLDM sensor modes */\n-#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK                     0x38000000\n-#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET                   27\n-#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL                 0x0\n-#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL                 0x1\n-#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH                     0x2\n-\tu32 f_lane_cfg1;\t/* 0x38 */\n-#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F\n-#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0\n-#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0\n-#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4\n-#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00\n-#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8\n-#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000\n-#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12\n-#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000\n-#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16\n-#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000\n-#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20\n-#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000\n-#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24\n-#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000\n-#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28\n-\tu32 f_lane_cfg2;\t/* 0x3C */\n-#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001\n-#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0\n-#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002\n-#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1\n-#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004\n-#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2\n-#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008\n-#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3\n-#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010\n-#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4\n-#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020\n-#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5\n-#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040\n-#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6\n-#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080\n-#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7\n+\t\t#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000\n+\t\t#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27\n+\t\t#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0\n+\t\t#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1\n+\t\t#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2\n+\tu32 f_lane_cfg1; /* 0x38 */\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28\n+\tu32 f_lane_cfg2; /* 0x3C */\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001\n+\t\t#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002\n+\t\t#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004\n+\t\t#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008\n+\t\t#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010\n+\t\t#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020\n+\t\t#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040\n+\t\t#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080\n+\t\t#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7\n \t/*  Control the period between two successive checks */\n #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK    0x0000FF00\n-#define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET  8\n+\t\t#define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8\n \t/*  Set shutdown temperature */\n #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK       0x00FF0000\n-#define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET     16\n+\t\t#define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16\n \t/*  Set max. count for over operational temperature */\n-#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK             0xFF000000\n-#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET           24\n+\t\t#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24\n \tu32 eagle_preemphasis;\t/* 0x40 */\n-#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0\n-#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8\n-#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16\n-#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24\n+\t\t#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24\n \tu32 eagle_driver_current;\t/* 0x44 */\n-#define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0\n-#define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8\n-#define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16\n-#define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24\n+\t\t#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24\n \tu32 falcon_preemphasis;\t/* 0x48 */\n-#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0\n-#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8\n-#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16\n-#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24\n+\t\t#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24\n \tu32 falcon_driver_current;\t/* 0x4C */\n-#define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0\n-#define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8\n-#define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16\n-#define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24\n-\tu32 pci_id;\t\t/* 0x50 */\n-#define NVM_CFG1_GLOB_VENDOR_ID_MASK                            0x0000FFFF\n-#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET                          0\n+\t\t#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24\n+\tu32 pci_id; /* 0x50 */\n+\t\t#define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0\n \t/*  Set caution temperature */\n #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK        0x00FF0000\n-#define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET      16\n+\t\t#define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16\n \t/*  Set external thermal sensor I2C address */\n #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK      0xFF000000\n-#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET    24\n-\tu32 pci_subsys_id;\t/* 0x54 */\n-#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK                  0x0000FFFF\n-#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET                0\n-#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK                  0xFFFF0000\n-#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET                16\n-\tu32 bar;\t\t/* 0x58 */\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK                   0x0000000F\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET                 0\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED               0x0\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K                     0x1\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K                     0x2\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K                     0x3\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K                    0x4\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K                    0x5\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K                    0x6\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K                   0x7\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K                   0x8\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K                   0x9\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M                     0xA\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M                     0xB\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M                     0xC\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M                     0xD\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M                    0xE\n-#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M                    0xF\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK                     0x000000F0\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET                   4\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED                 0x0\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K                       0x1\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K                       0x2\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K                      0x3\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K                      0x4\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K                      0x5\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K                     0x6\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K                     0x7\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K                     0x8\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M                       0x9\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M                       0xA\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M                       0xB\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M                       0xC\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M                      0xD\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M                      0xE\n-#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M                      0xF\n-#define NVM_CFG1_GLOB_BAR2_SIZE_MASK                            0x00000F00\n-#define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET                          8\n-#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED                        0x0\n-#define NVM_CFG1_GLOB_BAR2_SIZE_64K                             0x1\n-#define NVM_CFG1_GLOB_BAR2_SIZE_128K                            0x2\n-#define NVM_CFG1_GLOB_BAR2_SIZE_256K                            0x3\n-#define NVM_CFG1_GLOB_BAR2_SIZE_512K                            0x4\n-#define NVM_CFG1_GLOB_BAR2_SIZE_1M                              0x5\n-#define NVM_CFG1_GLOB_BAR2_SIZE_2M                              0x6\n-#define NVM_CFG1_GLOB_BAR2_SIZE_4M                              0x7\n-#define NVM_CFG1_GLOB_BAR2_SIZE_8M                              0x8\n-#define NVM_CFG1_GLOB_BAR2_SIZE_16M                             0x9\n-#define NVM_CFG1_GLOB_BAR2_SIZE_32M                             0xA\n-#define NVM_CFG1_GLOB_BAR2_SIZE_64M                             0xB\n-#define NVM_CFG1_GLOB_BAR2_SIZE_128M                            0xC\n-#define NVM_CFG1_GLOB_BAR2_SIZE_256M                            0xD\n-#define NVM_CFG1_GLOB_BAR2_SIZE_512M                            0xE\n-#define NVM_CFG1_GLOB_BAR2_SIZE_1G                              0xF\n+\t\t#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24\n+\tu32 pci_subsys_id; /* 0x54 */\n+\t\t#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000\n+\t\t#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16\n+\tu32 bar; /* 0x58 */\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE\n+\t\t#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE\n+\t\t#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE\n+\t\t#define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF\n \t/* Set the duration, in seconds, fan failure signal should be\n \t * sampled\n \t */\n-#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK                 0x0000F000\n-#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET               12\n+\t\t#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000\n+\t\t#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12\n \tu32 eagle_txfir_main;\t/* 0x5C */\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24\n \tu32 eagle_txfir_post;\t/* 0x60 */\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24\n \tu32 falcon_txfir_main;\t/* 0x64 */\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24\n \tu32 falcon_txfir_post;\t/* 0x68 */\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF\n-#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00\n-#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000\n-#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000\n-#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24\n-\tu32 manufacture_ver;\t/* 0x6C */\n-#define NVM_CFG1_GLOB_MANUF0_VER_MASK                           0x0000003F\n-#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET                         0\n-#define NVM_CFG1_GLOB_MANUF1_VER_MASK                           0x00000FC0\n-#define NVM_CFG1_GLOB_MANUF1_VER_OFFSET                         6\n-#define NVM_CFG1_GLOB_MANUF2_VER_MASK                           0x0003F000\n-#define NVM_CFG1_GLOB_MANUF2_VER_OFFSET                         12\n-#define NVM_CFG1_GLOB_MANUF3_VER_MASK                           0x00FC0000\n-#define NVM_CFG1_GLOB_MANUF3_VER_OFFSET                         18\n-#define NVM_CFG1_GLOB_MANUF4_VER_MASK                           0x3F000000\n-#define NVM_CFG1_GLOB_MANUF4_VER_OFFSET                         24\n-\tu32 manufacture_time;\t/* 0x70 */\n-#define NVM_CFG1_GLOB_MANUF0_TIME_MASK                          0x0000003F\n-#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET                        0\n-#define NVM_CFG1_GLOB_MANUF1_TIME_MASK                          0x00000FC0\n-#define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET                        6\n-#define NVM_CFG1_GLOB_MANUF2_TIME_MASK                          0x0003F000\n-#define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET                        12\n-\tu32 led_global_settings;\t/* 0x74 */\n-#define NVM_CFG1_GLOB_LED_SWAP_0_MASK                           0x0000000F\n-#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET                         0\n-#define NVM_CFG1_GLOB_LED_SWAP_1_MASK                           0x000000F0\n-#define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET                         4\n-#define NVM_CFG1_GLOB_LED_SWAP_2_MASK                           0x00000F00\n-#define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET                         8\n-#define NVM_CFG1_GLOB_LED_SWAP_3_MASK                           0x0000F000\n-#define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET                         12\n-\tu32 generic_cont1;\t/* 0x78 */\n-#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK                         0x000003FF\n-#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET                       0\n-\tu32 mbi_version;\t/* 0x7C */\n-#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                        0x000000FF\n-#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET                      0\n-#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                        0x0000FF00\n-#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET                      8\n-#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                        0x00FF0000\n-#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET                      16\n-\tu32 mbi_date;\t\t/* 0x80 */\n-\tu32 misc_sig;\t\t/* 0x84 */\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24\n+\tu32 manufacture_ver; /* 0x6C */\n+\t\t#define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F\n+\t\t#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0\n+\t\t#define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6\n+\t\t#define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000\n+\t\t#define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12\n+\t\t#define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000\n+\t\t#define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18\n+\t\t#define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000\n+\t\t#define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24\n+\tu32 manufacture_time; /* 0x70 */\n+\t\t#define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F\n+\t\t#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0\n+\t\t#define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6\n+\t\t#define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000\n+\t\t#define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12\n+\tu32 led_global_settings; /* 0x74 */\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000\n+\t\t#define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12\n+\tu32 generic_cont1; /* 0x78 */\n+\t\t#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF\n+\t\t#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0\n+\tu32 mbi_version; /* 0x7C */\n+\t\t#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16\n+\tu32 mbi_date; /* 0x80 */\n+\tu32 misc_sig; /* 0x84 */\n \t/*  Define the GPIO mapping to switch i2c mux */\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK                   0x000000FF\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET                 0\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK                   0x0000FF00\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET                 8\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA                      0x0\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0                   0x1\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1                   0x2\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2                   0x3\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3                   0x4\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4                   0x5\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5                   0x6\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6                   0x7\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7                   0x8\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8                   0x9\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9                   0xA\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10                  0xB\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11                  0xC\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12                  0xD\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13                  0xE\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14                  0xF\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15                  0x10\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16                  0x11\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17                  0x12\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18                  0x13\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19                  0x14\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20                  0x15\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21                  0x16\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22                  0x17\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23                  0x18\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24                  0x19\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25                  0x1A\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26                  0x1B\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27                  0x1C\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28                  0x1D\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29                  0x1E\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30                  0x1F\n-#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31                  0x20\n-\tu32 device_capabilities;\t/* 0x88 */\n-#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET              0x1\n-\tu32 power_dissipated;\t/* 0x8C */\n-#define NVM_CFG1_GLOB_POWER_DIS_D0_MASK                         0x000000FF\n-#define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET                       0\n-#define NVM_CFG1_GLOB_POWER_DIS_D1_MASK                         0x0000FF00\n-#define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET                       8\n-#define NVM_CFG1_GLOB_POWER_DIS_D2_MASK                         0x00FF0000\n-#define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET                       16\n-#define NVM_CFG1_GLOB_POWER_DIS_D3_MASK                         0xFF000000\n-#define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET                       24\n-\tu32 power_consumed;\t/* 0x90 */\n-#define NVM_CFG1_GLOB_POWER_CONS_D0_MASK                        0x000000FF\n-#define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET                      0\n-#define NVM_CFG1_GLOB_POWER_CONS_D1_MASK                        0x0000FF00\n-#define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET                      8\n-#define NVM_CFG1_GLOB_POWER_CONS_D2_MASK                        0x00FF0000\n-#define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET                      16\n-#define NVM_CFG1_GLOB_POWER_CONS_D3_MASK                        0xFF000000\n-#define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET                      24\n-\tu32 efi_version;\t/* 0x94 */\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F\n+\t\t#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20\n+\tu32 device_capabilities; /* 0x88 */\n+\t\t#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1\n+\tu32 power_dissipated; /* 0x8C */\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24\n+\tu32 power_consumed; /* 0x90 */\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000\n+\t\t#define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24\n+\tu32 efi_version; /* 0x94 */\n \tu32 reserved[42];\t/* 0x98 */\n };\n \n struct nvm_cfg1_path {\n-\tu32 reserved[30];\t/* 0x0 */\n+\tu32 reserved[30]; /* 0x0 */\n };\n \n struct nvm_cfg1_port {\n-\tu32 reserved__m_relocated_to_option_123;\t/* 0x0 */\n-\tu32 reserved__m_relocated_to_option_124;\t/* 0x4 */\n-\tu32 generic_cont0;\t/* 0x8 */\n-#define NVM_CFG1_PORT_LED_MODE_MASK                             0x000000FF\n-#define NVM_CFG1_PORT_LED_MODE_OFFSET                           0\n-#define NVM_CFG1_PORT_LED_MODE_MAC1                             0x0\n-#define NVM_CFG1_PORT_LED_MODE_PHY1                             0x1\n-#define NVM_CFG1_PORT_LED_MODE_PHY2                             0x2\n-#define NVM_CFG1_PORT_LED_MODE_PHY3                             0x3\n-#define NVM_CFG1_PORT_LED_MODE_MAC2                             0x4\n-#define NVM_CFG1_PORT_LED_MODE_PHY4                             0x5\n-#define NVM_CFG1_PORT_LED_MODE_PHY5                             0x6\n-#define NVM_CFG1_PORT_LED_MODE_PHY6                             0x7\n-#define NVM_CFG1_PORT_LED_MODE_MAC3                             0x8\n-#define NVM_CFG1_PORT_LED_MODE_PHY7                             0x9\n-#define NVM_CFG1_PORT_LED_MODE_PHY8                             0xA\n-#define NVM_CFG1_PORT_LED_MODE_PHY9                             0xB\n-#define NVM_CFG1_PORT_LED_MODE_MAC4                             0xC\n-#define NVM_CFG1_PORT_LED_MODE_PHY10                            0xD\n-#define NVM_CFG1_PORT_LED_MODE_PHY11                            0xE\n-#define NVM_CFG1_PORT_LED_MODE_PHY12                            0xF\n-#define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000\n-#define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16\n-#define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0\n-#define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1\n-#define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2\n-#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3\n-#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000\n-#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET          20\n-#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1\n-\tu32 pcie_cfg;\t\t/* 0xC */\n-#define NVM_CFG1_PORT_RESERVED15_MASK                           0x00000007\n-#define NVM_CFG1_PORT_RESERVED15_OFFSET                         0\n-\tu32 features;\t\t/* 0x10 */\n-#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK           0x00000001\n-#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET         0\n-#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED       0x0\n-#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED        0x1\n-#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK                     0x00000002\n-#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET                   1\n-#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED                 0x0\n-#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED                  0x1\n-\tu32 speed_cap_mask;\t/* 0x14 */\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10\n-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20\n+\tu32 reserved__m_relocated_to_option_123; /* 0x0 */\n+\tu32 reserved__m_relocated_to_option_124; /* 0x4 */\n+\tu32 generic_cont0; /* 0x8 */\n+\t\t#define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF\n+\t\t#define NVM_CFG1_PORT_LED_MODE_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_LED_MODE_MAC1 0x0\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY1 0x1\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY2 0x2\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY3 0x3\n+\t\t#define NVM_CFG1_PORT_LED_MODE_MAC2 0x4\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY4 0x5\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY5 0x6\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY6 0x7\n+\t\t#define NVM_CFG1_PORT_LED_MODE_MAC3 0x8\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY7 0x9\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY8 0xA\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY9 0xB\n+\t\t#define NVM_CFG1_PORT_LED_MODE_MAC4 0xC\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY10 0xD\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY11 0xE\n+\t\t#define NVM_CFG1_PORT_LED_MODE_PHY12 0xF\n+\t\t#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000\n+\t\t#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16\n+\t\t#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0\n+\t\t#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1\n+\t\t#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2\n+\t\t#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3\n+\t\t#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000\n+\t\t#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20\n+\t\t#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1\n+\tu32 pcie_cfg; /* 0xC */\n+\t\t#define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007\n+\t\t#define NVM_CFG1_PORT_RESERVED15_OFFSET 0\n+\tu32 features; /* 0x10 */\n+\t\t#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001\n+\t\t#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0\n+\t\t#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1\n+\t\t#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002\n+\t\t#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1\n+\t\t#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0\n+\t\t#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1\n+\tu32 speed_cap_mask; /* 0x14 */\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10\n+\t\t#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20\n #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G            0x40\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK            0xFFFF0000\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET          16\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G              0x1\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G             0x2\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G             0x8\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G             0x10\n-#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G             0x20\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10\n+\t\t#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20\n #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G            0x40\n-\tu32 link_settings;\t/* 0x18 */\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6\n+\tu32 link_settings; /* 0x18 */\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6\n #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G                       0x7\n-#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ                  0x8\n-#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070\n-#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4\n-#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1\n-#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2\n-#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK                       0x00000780\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET                     7\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG                    0x0\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G                         0x1\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G                        0x2\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G                        0x4\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G                        0x5\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G                        0x6\n+\t\t#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8\n+\t\t#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070\n+\t\t#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4\n+\t\t#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1\n+\t\t#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2\n+\t\t#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6\n #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G                       0x7\n-#define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ                  0x8\n-#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK                     0x00003800\n-#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET                   11\n-#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG                  0x1\n-#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX                       0x2\n-#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX                       0x4\n+\t\t#define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8\n+\t\t#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800\n+\t\t#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11\n+\t\t#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1\n+\t\t#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2\n+\t\t#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4\n #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK      0x00004000\n-#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET    14\n+\t\t#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14\n #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED  0x0\n #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED   0x1\n-#define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK                       0x00018000\n-#define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET                     15\n-#define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM                 0x0\n-#define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM                        0x1\n-#define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK                       0x000E0000\n-#define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET                     17\n+\t\t#define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000\n+\t\t#define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15\n+\t\t#define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0\n+\t\t#define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1\n+\t\t#define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000\n+\t\t#define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17\n #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_NONE             0x0\n #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_FIRECODE         0x1\n #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_RS               0x2\n-\tu32 phy_cfg;\t\t/* 0x1C */\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK                  0x0000FFFF\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET                0\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG                 0x1\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER             0x2\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER                 0x4\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN       0x8\n-#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN        0x10\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK                 0x00FF0000\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET               16\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS               0x0\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR                   0x2\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2                  0x3\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4                  0x4\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI                  0x8\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI                  0x9\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X                0xB\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII                0xC\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI                0x11\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI                0x12\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI                 0x21\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI                 0x22\n-#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI               0x31\n-#define NVM_CFG1_PORT_AN_MODE_MASK                              0xFF000000\n-#define NVM_CFG1_PORT_AN_MODE_OFFSET                            24\n-#define NVM_CFG1_PORT_AN_MODE_NONE                              0x0\n-#define NVM_CFG1_PORT_AN_MODE_CL73                              0x1\n-#define NVM_CFG1_PORT_AN_MODE_CL37                              0x2\n-#define NVM_CFG1_PORT_AN_MODE_CL73_BAM                          0x3\n+\tu32 phy_cfg; /* 0x1C */\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8\n+\t\t#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22\n+\t\t#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31\n+\t\t#define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000\n+\t\t#define NVM_CFG1_PORT_AN_MODE_OFFSET 24\n+\t\t#define NVM_CFG1_PORT_AN_MODE_NONE 0x0\n+\t\t#define NVM_CFG1_PORT_AN_MODE_CL73 0x1\n+\t\t#define NVM_CFG1_PORT_AN_MODE_CL37 0x2\n+\t\t#define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3\n #define NVM_CFG1_PORT_AN_MODE_CL37_BAM                          0x4\n #define NVM_CFG1_PORT_AN_MODE_HPAM                              0x5\n #define NVM_CFG1_PORT_AN_MODE_SGMII                             0x6\n-\tu32 mgmt_traffic;\t/* 0x20 */\n-#define NVM_CFG1_PORT_RESERVED61_MASK                           0x0000000F\n-#define NVM_CFG1_PORT_RESERVED61_OFFSET                         0\n-\tu32 ext_phy;\t\t/* 0x24 */\n-#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK                    0x000000FF\n-#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET                  0\n-#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE                    0x0\n-#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844                0x1\n-#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK                 0x0000FF00\n-#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET               8\n-\tu32 mba_cfg1;\t\t/* 0x28 */\n-#define NVM_CFG1_PORT_PREBOOT_OPROM_MASK                        0x00000001\n-#define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET                      0\n-#define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED                    0x0\n-#define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED                     0x1\n-#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK            0x00000006\n-#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET          1\n-#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK                       0x00000078\n-#define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET                     3\n-#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK                    0x00000080\n-#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET                  7\n-#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S                  0x0\n-#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B                  0x1\n-#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK                0x00000100\n-#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET              8\n-#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED            0x0\n-#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED             0x1\n-#define NVM_CFG1_PORT_RESERVED5_MASK                            0x0001FE00\n-#define NVM_CFG1_PORT_RESERVED5_OFFSET                          9\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK                   0x001E0000\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET                 17\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG                0x0\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G                     0x1\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G                    0x2\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G                    0x4\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G                    0x5\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G                    0x6\n+\tu32 mgmt_traffic; /* 0x20 */\n+\t\t#define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F\n+\t\t#define NVM_CFG1_PORT_RESERVED61_OFFSET 0\n+\tu32 ext_phy; /* 0x24 */\n+\t\t#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF\n+\t\t#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0\n+\t\t#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1\n+\t\t#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8\n+\tu32 mba_cfg1; /* 0x28 */\n+\t\t#define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001\n+\t\t#define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0\n+\t\t#define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1\n+\t\t#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006\n+\t\t#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1\n+\t\t#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078\n+\t\t#define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3\n+\t\t#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080\n+\t\t#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7\n+\t\t#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0\n+\t\t#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1\n+\t\t#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100\n+\t\t#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8\n+\t\t#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0\n+\t\t#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1\n+\t\t#define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00\n+\t\t#define NVM_CFG1_PORT_RESERVED5_OFFSET 9\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6\n #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G                   0x7\n-#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ              0x8\n+\t\t#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8\n #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK     0x00E00000\n-#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET   21\n-\tu32 mba_cfg2;\t\t/* 0x2C */\n-#define NVM_CFG1_PORT_RESERVED65_MASK                           0x0000FFFF\n-#define NVM_CFG1_PORT_RESERVED65_OFFSET                         0\n-#define NVM_CFG1_PORT_RESERVED66_MASK                           0x00010000\n-#define NVM_CFG1_PORT_RESERVED66_OFFSET                         16\n-\tu32 vf_cfg;\t\t/* 0x30 */\n-#define NVM_CFG1_PORT_RESERVED8_MASK                            0x0000FFFF\n-#define NVM_CFG1_PORT_RESERVED8_OFFSET                          0\n-#define NVM_CFG1_PORT_RESERVED6_MASK                            0x000F0000\n-#define NVM_CFG1_PORT_RESERVED6_OFFSET                          16\n-\tstruct nvm_cfg_mac_address lldp_mac_address;\t/* 0x34 */\n-\tu32 led_port_settings;\t/* 0x3C */\n-#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK                   0x000000FF\n-#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET                 0\n-#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK                   0x0000FF00\n-#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET                 8\n-#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK                   0x00FF0000\n-#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET                 16\n-#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G                      0x1\n-#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G                     0x2\n-#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G                     0x8\n-#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G                     0x10\n-#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G                     0x20\n+\t\t#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21\n+\tu32 mba_cfg2; /* 0x2C */\n+\t\t#define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_PORT_RESERVED65_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000\n+\t\t#define NVM_CFG1_PORT_RESERVED66_OFFSET 16\n+\tu32 vf_cfg; /* 0x30 */\n+\t\t#define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_PORT_RESERVED8_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000\n+\t\t#define NVM_CFG1_PORT_RESERVED6_OFFSET 16\n+\tstruct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */\n+\tu32 led_port_settings; /* 0x3C */\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10\n+\t\t#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20\n #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G                    0x40\n-\tu32 transceiver_00;\t/* 0x40 */\n+\tu32 transceiver_00; /* 0x40 */\n \t/*  Define for mapping of transceiver signal module absent */\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK                     0x000000FF\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET                   0\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA                       0x0\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0                    0x1\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1                    0x2\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2                    0x3\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3                    0x4\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4                    0x5\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5                    0x6\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6                    0x7\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7                    0x8\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8                    0x9\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9                    0xA\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10                   0xB\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11                   0xC\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12                   0xD\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13                   0xE\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14                   0xF\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15                   0x10\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16                   0x11\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17                   0x12\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18                   0x13\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19                   0x14\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20                   0x15\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21                   0x16\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22                   0x17\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23                   0x18\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24                   0x19\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25                   0x1A\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26                   0x1B\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27                   0x1C\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28                   0x1D\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29                   0x1E\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30                   0x1F\n-#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31                   0x20\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F\n+\t\t#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20\n \t/*  Define the GPIO mux settings  to switch i2c mux to this port */\n-#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK                  0x00000F00\n-#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET                8\n-#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK                  0x0000F000\n-#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET                12\n-\tu32 device_ids;\t\t/* 0x44 */\n-#define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK                       0x000000FF\n-#define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET                     0\n-#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK                  0xFF000000\n-#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET                24\n-\tu32 board_cfg;\t\t/* 0x48 */\n-\t/* This field defines the board technology\n+\t\t#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00\n+\t\t#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8\n+\t\t#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000\n+\t\t#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12\n+\tu32 device_ids; /* 0x44 */\n+\t\t#define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF\n+\t\t#define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000\n+\t\t#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24\n+\tu32 board_cfg; /* 0x48 */\n+\t/*  This field defines the board technology\n \t * (backpane,transceiver,external PHY)\n \t */\n-#define NVM_CFG1_PORT_PORT_TYPE_MASK                            0x000000FF\n-#define NVM_CFG1_PORT_PORT_TYPE_OFFSET                          0\n-#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED                       0x0\n-#define NVM_CFG1_PORT_PORT_TYPE_MODULE                          0x1\n-#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE                       0x2\n-#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY                         0x3\n-#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE                    0x4\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3\n+\t\t#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4\n \t/*  This field defines the GPIO mapped to tx_disable signal in SFP */\n-#define NVM_CFG1_PORT_TX_DISABLE_MASK                           0x0000FF00\n-#define NVM_CFG1_PORT_TX_DISABLE_OFFSET                         8\n-#define NVM_CFG1_PORT_TX_DISABLE_NA                             0x0\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO0                          0x1\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO1                          0x2\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO2                          0x3\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO3                          0x4\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO4                          0x5\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO5                          0x6\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO6                          0x7\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO7                          0x8\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO8                          0x9\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO9                          0xA\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO10                         0xB\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO11                         0xC\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO12                         0xD\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO13                         0xE\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO14                         0xF\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO15                         0x10\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO16                         0x11\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO17                         0x12\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO18                         0x13\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO19                         0x14\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO20                         0x15\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO21                         0x16\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO22                         0x17\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO23                         0x18\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO24                         0x19\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO25                         0x1A\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO26                         0x1B\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO27                         0x1C\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO28                         0x1D\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO29                         0x1E\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO30                         0x1F\n-#define NVM_CFG1_PORT_TX_DISABLE_GPIO31                         0x20\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_NA 0x0\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F\n+\t\t#define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20\n \tu32 reserved[131];\t/* 0x4C */\n };\n \n struct nvm_cfg1_func {\n-\tstruct nvm_cfg_mac_address mac_address;\t/* 0x0 */\n-\tu32 rsrv1;\t\t/* 0x8 */\n-#define NVM_CFG1_FUNC_RESERVED1_MASK                            0x0000FFFF\n-#define NVM_CFG1_FUNC_RESERVED1_OFFSET                          0\n-#define NVM_CFG1_FUNC_RESERVED2_MASK                            0xFFFF0000\n-#define NVM_CFG1_FUNC_RESERVED2_OFFSET                          16\n-\tu32 rsrv2;\t\t/* 0xC */\n-#define NVM_CFG1_FUNC_RESERVED3_MASK                            0x0000FFFF\n-#define NVM_CFG1_FUNC_RESERVED3_OFFSET                          0\n-#define NVM_CFG1_FUNC_RESERVED4_MASK                            0xFFFF0000\n-#define NVM_CFG1_FUNC_RESERVED4_OFFSET                          16\n-\tu32 device_id;\t\t/* 0x10 */\n-#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK                  0x0000FFFF\n-#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET                0\n-#define NVM_CFG1_FUNC_RESERVED77_MASK                           0xFFFF0000\n-#define NVM_CFG1_FUNC_RESERVED77_OFFSET                         16\n-\tu32 cmn_cfg;\t\t/* 0x14 */\n-#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK                0x00000007\n-#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET              0\n-#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE                 0x0\n-#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE                0x7\n-#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK                     0x0007FFF8\n-#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET                   3\n-#define NVM_CFG1_FUNC_PERSONALITY_MASK                          0x00780000\n-#define NVM_CFG1_FUNC_PERSONALITY_OFFSET                        19\n-#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET                      0x0\n-#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK                     0x7F800000\n-#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET                   23\n-#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK                   0x80000000\n-#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET                 31\n-#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED               0x0\n-#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED                0x1\n-\tu32 pci_cfg;\t\t/* 0x18 */\n-#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK                 0x0000007F\n-#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET               0\n+\tstruct nvm_cfg_mac_address mac_address; /* 0x0 */\n+\tu32 rsrv1; /* 0x8 */\n+\t\t#define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_FUNC_RESERVED1_OFFSET 0\n+\t\t#define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000\n+\t\t#define NVM_CFG1_FUNC_RESERVED2_OFFSET 16\n+\tu32 rsrv2; /* 0xC */\n+\t\t#define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_FUNC_RESERVED3_OFFSET 0\n+\t\t#define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000\n+\t\t#define NVM_CFG1_FUNC_RESERVED4_OFFSET 16\n+\tu32 device_id; /* 0x10 */\n+\t\t#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0\n+\t\t#define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000\n+\t\t#define NVM_CFG1_FUNC_RESERVED77_OFFSET 16\n+\tu32 cmn_cfg; /* 0x14 */\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7\n+\t\t#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8\n+\t\t#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3\n+\t\t#define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000\n+\t\t#define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19\n+\t\t#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0\n+\t\t#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000\n+\t\t#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23\n+\t\t#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000\n+\t\t#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31\n+\t\t#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0\n+\t\t#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1\n+\tu32 pci_cfg; /* 0x18 */\n+\t\t#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F\n+\t\t#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0\n #define NVM_CFG1_FUNC_RESERVESD12_MASK                          0x00003F80\n #define NVM_CFG1_FUNC_RESERVESD12_OFFSET                        7\n-#define NVM_CFG1_FUNC_BAR1_SIZE_MASK                            0x0003C000\n-#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET                          14\n-#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED                        0x0\n-#define NVM_CFG1_FUNC_BAR1_SIZE_64K                             0x1\n-#define NVM_CFG1_FUNC_BAR1_SIZE_128K                            0x2\n-#define NVM_CFG1_FUNC_BAR1_SIZE_256K                            0x3\n-#define NVM_CFG1_FUNC_BAR1_SIZE_512K                            0x4\n-#define NVM_CFG1_FUNC_BAR1_SIZE_1M                              0x5\n-#define NVM_CFG1_FUNC_BAR1_SIZE_2M                              0x6\n-#define NVM_CFG1_FUNC_BAR1_SIZE_4M                              0x7\n-#define NVM_CFG1_FUNC_BAR1_SIZE_8M                              0x8\n-#define NVM_CFG1_FUNC_BAR1_SIZE_16M                             0x9\n-#define NVM_CFG1_FUNC_BAR1_SIZE_32M                             0xA\n-#define NVM_CFG1_FUNC_BAR1_SIZE_64M                             0xB\n-#define NVM_CFG1_FUNC_BAR1_SIZE_128M                            0xC\n-#define NVM_CFG1_FUNC_BAR1_SIZE_256M                            0xD\n-#define NVM_CFG1_FUNC_BAR1_SIZE_512M                            0xE\n-#define NVM_CFG1_FUNC_BAR1_SIZE_1G                              0xF\n-#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK                        0x03FC0000\n-#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET                      18\n-\tu32 preboot_generic_cfg;\t/* 0x2C */\n-#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK                   0x0000FFFF\n-#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET                 0\n-#define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK                         0x00010000\n-#define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET                       16\n-\tu32 reserved[8];\t/* 0x30 */\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE\n+\t\t#define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF\n+\t\t#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000\n+\t\t#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18\n+\tu32 preboot_generic_cfg; /* 0x2C */\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000\n+\t\t#define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16\n+\tu32 reserved[8]; /* 0x30 */\n };\n \n struct nvm_cfg1 {\n-\tstruct nvm_cfg1_glob glob;\t/* 0x0 */\n-\tstruct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];\t/* 0x140 */\n-\tstruct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];\t/* 0x230 */\n-\tstruct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];\t/* 0xB90 */\n+\tstruct nvm_cfg1_glob glob; /* 0x0 */\n+\tstruct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */\n+\tstruct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */\n+\tstruct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */\n };\n \n /******************************************\n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "02/32"
    ]
}