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GET /api/patches/1468/?format=api
https://patches.dpdk.org/api/patches/1468/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416792142-23132-3-git-send-email-chaozhu@linux.vnet.ibm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416792142-23132-3-git-send-email-chaozhu@linux.vnet.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416792142-23132-3-git-send-email-chaozhu@linux.vnet.ibm.com", "date": "2014-11-24T01:22:10", "name": "[dpdk-dev,v3,02/14] Add atomic operations for IBM Power architecture", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0af8f4ac458bb7fffe1103eeaf4f1012148940c6", "submitter": { "id": 114, "url": "https://patches.dpdk.org/api/people/114/?format=api", "name": "Chao Zhu", "email": "chaozhu@linux.vnet.ibm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416792142-23132-3-git-send-email-chaozhu@linux.vnet.ibm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1468/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1468/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0C31A7FF6;\n\tSun, 23 Nov 2014 14:11:43 +0100 (CET)", "from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140])\n\tby dpdk.org (Postfix) with ESMTP id 0C2AB7FC5\n\tfor <dev@dpdk.org>; Sun, 23 Nov 2014 14:11:31 +0100 (CET)", "from /spool/local\n\tby e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <dev@dpdk.org> from <chaozhu@linux.vnet.ibm.com>;\n\tSun, 23 Nov 2014 23:22:13 +1000", "from d23dlp01.au.ibm.com (202.81.31.203)\n\tby e23smtp07.au.ibm.com (202.81.31.204) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tSun, 23 Nov 2014 23:22:10 +1000", "from d23relay10.au.ibm.com (d23relay10.au.ibm.com [9.190.26.77])\n\tby d23dlp01.au.ibm.com (Postfix) with ESMTP id A0FE32CE8050\n\tfor <dev@dpdk.org>; Mon, 24 Nov 2014 00:22:10 +1100 (EST)", "from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97])\n\tby d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tsANDM1d221233752 for <dev@dpdk.org>; Mon, 24 Nov 2014 00:22:10 +1100", "from d23av03.au.ibm.com (localhost [127.0.0.1])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tsANDLbkZ017326 for <dev@dpdk.org>; Mon, 24 Nov 2014 00:21:37 +1100", "from os_controller.crl.ibm.com ([9.186.57.97])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tsANDLYfr017172 for <dev@dpdk.org>; Mon, 24 Nov 2014 00:21:36 +1100" ], "From": "Chao Zhu <chaozhu@linux.vnet.ibm.com>", "To": "dev@dpdk.org", "Date": "Sun, 23 Nov 2014 20:22:10 -0500", "Message-Id": "<1416792142-23132-3-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1416792142-23132-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "References": "<1416792142-23132-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "14112313-0025-0000-0000-0000008F8AAB", "Subject": "[dpdk-dev] [PATCH v3 02/14] Add atomic operations for IBM Power\n\tarchitecture", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds architecture specific atomic operation file for IBM\nPower architecture CPU.\n\nSigned-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>\n---\n .../common/include/arch/ppc_64/rte_atomic.h | 415 ++++++++++++++++++++\n 1 files changed, 415 insertions(+), 0 deletions(-)\n create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h\nnew file mode 100644\nindex 0000000..9c69935\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h\n@@ -0,0 +1,415 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+/*\n+ * Inspired from FreeBSD src/sys/powerpc/include/atomic.h\n+ * Copyright (c) 2008 Marcel Moolenaar\n+ * Copyright (c) 2001 Benno Rice\n+ * Copyright (c) 2001 David E. O'Brien\n+ * Copyright (c) 1998 Doug Rabson\n+ * All rights reserved.\n+ */\n+\n+#ifndef _RTE_ATOMIC_PPC_64_H_\n+#define _RTE_ATOMIC_PPC_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ */\n+#define\trte_mb() asm volatile(\"sync\" : : : \"memory\")\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ */\n+#define\trte_wmb() asm volatile(\"sync\" : : : \"memory\")\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ */\n+#define\trte_rmb() asm volatile(\"sync\" : : : \"memory\")\n+\n+/*------------------------- 16 bit atomic operations -------------------------*/\n+/* To be compatible with Power7, use GCC built-in functions for 16 bit operations */\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+static inline int\n+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n+{\n+\treturn __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE) ? 1 : 0;\n+}\n+\n+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n+{\n+\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void\n+rte_atomic16_inc(rte_atomic16_t *v)\n+{\n+\t__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline void\n+rte_atomic16_dec(rte_atomic16_t *v)\n+{\n+\t__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+/*------------------------- 32 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n+{\n+\tunsigned int ret = 0;\n+\n+\tasm volatile(\n+\t\t\t\"\\tlwsync\\n\"\n+\t\t\t\"1:\\tlwarx %[ret], 0, %[dst]\\n\"\n+\t\t\t\"cmplw %[exp], %[ret]\\n\"\n+\t\t\t\"bne 2f\\n\"\n+\t\t\t\"stwcx. %[src], 0, %[dst]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"li %[ret], 1\\n\"\n+\t\t\t\"b 3f\\n\"\n+\t\t\t\"2:\\n\"\n+\t\t\t\"stwcx. %[ret], 0, %[dst]\\n\" \n+\t\t\t\"li %[ret], 0\\n\"\n+\t\t\t\"3:\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret), \"=m\" (*dst)\n+\t\t\t: [dst] \"r\" (dst), [exp] \"r\" (exp), [src] \"r\" (src), \"m\" (*dst)\n+\t\t\t: \"cc\", \"memory\");\n+\n+\treturn ret;\n+}\n+\n+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n+{\n+\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void\n+rte_atomic32_inc(rte_atomic32_t *v)\n+{\n+\tint t;\n+\n+\tasm volatile(\n+\t\t\t\"1: lwarx %[t],0,%[cnt]\\n\"\n+\t\t\t\"addic %[t],%[t],1\\n\"\n+\t\t\t\"stwcx. %[t],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t: [t] \"=&r\" (t), \"=m\" (v->cnt)\n+\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+}\n+\n+static inline void\n+rte_atomic32_dec(rte_atomic32_t *v)\n+{\n+\tint t;\n+\n+\tasm volatile(\n+\t\t\t\"1: lwarx %[t],0,%[cnt]\\n\"\n+\t\t\t\"addic %[t],%[t],-1\\n\"\n+\t\t\t\"stwcx. %[t],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t: [t] \"=&r\" (t), \"=m\" (v->cnt)\n+\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+}\n+\n+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n+{\n+\tint ret;\n+\n+\tasm volatile(\n+\t\t\t\"\\n\\tlwsync\\n\"\n+\t\t\t\"1: lwarx %[ret],0,%[cnt]\\n\"\n+\t\t\t\"addic\t%[ret],%[ret],1\\n\"\n+\t\t\t\"stwcx. %[ret],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret)\n+\t\t\t: [cnt] \"r\" (&v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+\n+\treturn (ret == 0);\n+}\n+\n+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n+{\n+\tint ret;\n+\n+\tasm volatile(\n+\t\t\t\"\\n\\tlwsync\\n\"\n+\t\t\t\"1: lwarx %[ret],0,%[cnt]\\n\"\n+\t\t\t\"addic %[ret],%[ret],-1\\n\"\n+\t\t\t\"stwcx. %[ret],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret)\n+\t\t\t: [cnt] \"r\" (&v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+\n+\treturn (ret == 0);\n+}\n+/*------------------------- 64 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n+{\n+\tunsigned int ret = 0;\n+\n+\tasm volatile (\n+\t\t\t\"\\tlwsync\\n\"\n+\t\t\t\"1: ldarx %[ret], 0, %[dst]\\n\"\n+\t\t\t\"cmpld %[exp], %[ret]\\n\"\n+\t\t\t\"bne 2f\\n\"\n+\t\t\t\"stdcx. %[src], 0, %[dst]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"li %[ret], 1\\n\"\n+\t\t\t\"b 3f\\n\"\n+\t\t\t\"2:\\n\"\n+\t\t\t\"stdcx. %[ret], 0, %[dst]\\n\"\n+\t\t\t\"li %[ret], 0\\n\"\n+\t\t\t\"3:\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret), \"=m\" (*dst)\n+\t\t\t: [dst] \"r\" (dst), [exp] \"r\" (exp), [src] \"r\" (src), \"m\" (*dst)\n+\t\t\t: \"cc\", \"memory\");\n+\treturn ret;\n+}\n+\n+static inline void\n+rte_atomic64_init(rte_atomic64_t *v)\n+{\n+\tv->cnt = 0;\n+}\n+\n+static inline int64_t\n+rte_atomic64_read(rte_atomic64_t *v)\n+{\n+\tlong ret;\n+\n+\tasm volatile(\"ld%U1%X1 %[ret],%[cnt]\" : [ret] \"=r\"(ret) : [cnt] \"m\"(v->cnt));\n+\n+\treturn ret;\n+}\n+\n+static inline void\n+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n+{\n+\tasm volatile(\"std%U0%X0 %[new_value],%[cnt]\" : [cnt] \"=m\"(v->cnt) : [new_value] \"r\"(new_value));\n+}\n+\n+static inline void\n+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n+{\n+\tlong t;\n+\n+\tasm volatile(\n+\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n+\t\t\t\"add %[t],%[inc],%[t]\\n\"\n+\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t: [t] \"=&r\" (t), \"=m\" (v->cnt)\n+\t\t\t: [cnt] \"r\" (&v->cnt), [inc] \"r\" (inc), \"m\" (v->cnt)\n+\t\t\t: \"cc\", \"memory\");\n+}\n+\n+static inline void\n+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n+{\n+\tlong t;\n+\n+\tasm volatile(\n+\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n+\t\t\t\"subf %[t],%[dec],%[t]\\n\"\n+\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t: [t] \"=&r\" (t), \"+m\" (v->cnt)\n+\t\t\t: [cnt] \"r\" (&v->cnt), [dec] \"r\" (dec), \"m\" (v->cnt)\n+\t\t\t: \"cc\", \"memory\");\n+}\n+\n+static inline void\n+rte_atomic64_inc(rte_atomic64_t *v)\n+{\n+\tlong t;\n+\n+\tasm volatile(\n+\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n+\t\t\t\"addic %[t],%[t],1\\n\"\n+\t\t\t\"stdcx. %[t],0,%[cnt] \\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t: [t] \"=&r\" (t), \"+m\" (v->cnt)\n+\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+}\n+\n+static inline void\n+rte_atomic64_dec(rte_atomic64_t *v)\n+{\n+\tlong t;\n+\n+\tasm volatile(\n+\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n+\t\t\t\"addic %[t],%[t],-1\\n\"\n+\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t: [t] \"=&r\" (t), \"+m\" (v->cnt)\n+\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+}\n+\n+static inline int64_t\n+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n+{\n+\tlong ret;\n+\n+\tasm volatile(\n+\t\t\t\"\\n\\tlwsync\\n\"\n+\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n+\t\t\t\"add %[ret],%[inc],%[ret]\\n\"\n+\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret)\n+\t\t\t: [inc] \"r\" (inc), [cnt] \"r\" (&v->cnt)\n+\t\t\t: \"cc\", \"memory\");\n+\n+\treturn ret;\n+}\n+\n+static inline int64_t\n+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n+{\n+\tlong ret;\n+\n+\tasm volatile(\n+\t\t\t\"\\n\\tlwsync\\n\"\n+\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n+\t\t\t\"subf %[ret],%[dec],%[ret]\\n\"\n+\t\t\t\"stdcx. %[ret],0,%[cnt] \\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret)\n+\t\t\t: [dec] \"r\" (dec), [cnt] \"r\" (&v->cnt)\n+\t\t\t: \"cc\", \"memory\");\n+\n+\treturn ret;\n+}\n+\n+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n+{\n+\tlong ret;\n+\n+\tasm volatile(\n+\t\t\t\"\\n\\tlwsync\\n\"\n+\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n+\t\t\t\"addic %[ret],%[ret],1\\n\"\n+\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret)\n+\t\t\t: [cnt] \"r\" (&v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+\n+\treturn (ret==0);\n+}\n+\n+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n+{\n+\tlong ret;\n+\n+\tasm volatile(\n+\t\t\t\"\\n\\tlwsync\\n\"\n+\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n+\t\t\t\"addic %[ret],%[ret],-1\\n\"\n+\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n+\t\t\t\"bne- 1b\\n\"\n+\t\t\t\"isync\\n\"\n+\t\t\t: [ret] \"=&r\" (ret)\n+\t\t\t: [cnt] \"r\" (&v->cnt)\n+\t\t\t: \"cc\", \"xer\", \"memory\");\n+\n+\treturn (ret==0);\n+}\n+\n+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n+}\n+\n+/**\n+ * Atomically set a 64-bit counter to 0.\n+ *\n+ * @param v\n+ * A pointer to the atomic counter.\n+ */\n+static inline void rte_atomic64_clear(rte_atomic64_t *v)\n+{\n+\tv->cnt = 0;\n+}\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_PPC_64_H_ */\n+\n", "prefixes": [ "dpdk-dev", "v3", "02/14" ] }{ "id": 1468, "url": "