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{
    "id": 1435,
    "url": "https://patches.dpdk.org/api/patches/1435/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416587583-2021-4-git-send-email-ssujith@cisco.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1416587583-2021-4-git-send-email-ssujith@cisco.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1416587583-2021-4-git-send-email-ssujith@cisco.com",
    "date": "2014-11-21T16:33:00",
    "name": "[dpdk-dev,v2,3/6] VNIC common code partially shared with ENIC kernel mode driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e9efad41648f23e45a06ad3082664e8f72c4b94a",
    "submitter": {
        "id": 110,
        "url": "https://patches.dpdk.org/api/people/110/?format=api",
        "name": "Sujith Sankar",
        "email": "ssujith@cisco.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416587583-2021-4-git-send-email-ssujith@cisco.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/1435/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/1435/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n\td=cisco.com; i=@cisco.com; l=156355; q=dns/txt;\n\ts=iport; t=1416553472; x=1417763072;\n\th=from:to:cc:subject:date:message-id:in-reply-to: references;\n\tbh=5m2L0erf++sUKVvvOZ8bzzeji5MnKHHm/jzZ2SrgIMI=;\n\tb=ayeuzSsWPcE3BQic51GtPwgH2xiT6/YXPmSLnQlwQKiz6E/tOJNRKH9W\n\tBQEIox808RGIPlfH/fekDKtqc1QhkX+Kspv8dZnnJo7uC/FkRwOZZqYkd\n\tFVls8W1mY2zxWL4OH1+LFdGOZ6PoZrV5kHKplBmPDvhNibqXApeoeb33o k=;",
        "X-IronPort-AV": "E=Sophos;i=\"5.07,429,1413244800\"; d=\"scan'208\";a=\"47683296\"",
        "From": "Sujith Sankar <ssujith@cisco.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 21 Nov 2014 22:03:00 +0530",
        "Message-Id": "<1416587583-2021-4-git-send-email-ssujith@cisco.com>",
        "X-Mailer": "git-send-email 1.9.1",
        "In-Reply-To": "<1416587583-2021-1-git-send-email-ssujith@cisco.com>",
        "References": "<1416587583-2021-1-git-send-email-ssujith@cisco.com>",
        "X-Authenticated-User": "ssujith@cisco.com",
        "Subject": "[dpdk-dev] [PATCH v2 3/6] VNIC common code partially shared with\n\tENIC kernel mode driver",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Signed-off-by: Sujith Sankar <ssujith@cisco.com>\n---\n lib/librte_pmd_enic/vnic/cq_desc.h       |  126 ++++\n lib/librte_pmd_enic/vnic/cq_enet_desc.h  |  261 ++++++++\n lib/librte_pmd_enic/vnic/rq_enet_desc.h  |   76 +++\n lib/librte_pmd_enic/vnic/vnic_cq.c       |  117 ++++\n lib/librte_pmd_enic/vnic/vnic_cq.h       |  152 +++++\n lib/librte_pmd_enic/vnic/vnic_dev.c      | 1081 ++++++++++++++++++++++++++++++\n lib/librte_pmd_enic/vnic/vnic_dev.h      |  202 ++++++\n lib/librte_pmd_enic/vnic/vnic_devcmd.h   |  774 +++++++++++++++++++++\n lib/librte_pmd_enic/vnic/vnic_enet.h     |   78 +++\n lib/librte_pmd_enic/vnic/vnic_intr.c     |   83 +++\n lib/librte_pmd_enic/vnic/vnic_intr.h     |  126 ++++\n lib/librte_pmd_enic/vnic/vnic_nic.h      |   88 +++\n lib/librte_pmd_enic/vnic/vnic_resource.h |   97 +++\n lib/librte_pmd_enic/vnic/vnic_rq.c       |  246 +++++++\n lib/librte_pmd_enic/vnic/vnic_rq.h       |  282 ++++++++\n lib/librte_pmd_enic/vnic/vnic_rss.c      |   85 +++\n lib/librte_pmd_enic/vnic/vnic_rss.h      |   61 ++\n lib/librte_pmd_enic/vnic/vnic_stats.h    |   86 +++\n lib/librte_pmd_enic/vnic/vnic_wq.c       |  245 +++++++\n lib/librte_pmd_enic/vnic/vnic_wq.h       |  283 ++++++++\n lib/librte_pmd_enic/vnic/wq_enet_desc.h  |  114 ++++\n 21 files changed, 4663 insertions(+)\n create mode 100644 lib/librte_pmd_enic/vnic/cq_desc.h\n create mode 100644 lib/librte_pmd_enic/vnic/cq_enet_desc.h\n create mode 100644 lib/librte_pmd_enic/vnic/rq_enet_desc.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_cq.c\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_cq.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_dev.c\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_dev.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_devcmd.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_enet.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_intr.c\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_intr.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_nic.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_resource.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_rq.c\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_rq.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_rss.c\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_rss.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_stats.h\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_wq.c\n create mode 100644 lib/librte_pmd_enic/vnic/vnic_wq.h\n create mode 100644 lib/librte_pmd_enic/vnic/wq_enet_desc.h",
    "diff": "diff --git a/lib/librte_pmd_enic/vnic/cq_desc.h b/lib/librte_pmd_enic/vnic/cq_desc.h\nnew file mode 100644\nindex 0000000..7dfb2b6\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/cq_desc.h\n@@ -0,0 +1,126 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: cq_desc.h 129574 2013-04-26 22:11:14Z rfaucett $\"\n+\n+#ifndef _CQ_DESC_H_\n+#define _CQ_DESC_H_\n+\n+/*\n+ * Completion queue descriptor types\n+ */\n+enum cq_desc_types {\n+\tCQ_DESC_TYPE_WQ_ENET = 0,\n+\tCQ_DESC_TYPE_DESC_COPY = 1,\n+\tCQ_DESC_TYPE_WQ_EXCH = 2,\n+\tCQ_DESC_TYPE_RQ_ENET = 3,\n+\tCQ_DESC_TYPE_RQ_FCP = 4,\n+\tCQ_DESC_TYPE_IOMMU_MISS = 5,\n+\tCQ_DESC_TYPE_SGL = 6,\n+\tCQ_DESC_TYPE_CLASSIFIER = 7,\n+\tCQ_DESC_TYPE_TEST = 127,\n+};\n+\n+/* Completion queue descriptor: 16B\n+ *\n+ * All completion queues have this basic layout.  The\n+ * type_specfic area is unique for each completion\n+ * queue type.\n+ */\n+struct cq_desc {\n+\t__le16 completed_index;\n+\t__le16 q_number;\n+\tu8 type_specfic[11];\n+\tu8 type_color;\n+};\n+\n+#define CQ_DESC_TYPE_BITS        4\n+#define CQ_DESC_TYPE_MASK        ((1 << CQ_DESC_TYPE_BITS) - 1)\n+#define CQ_DESC_COLOR_MASK       1\n+#define CQ_DESC_COLOR_SHIFT      7\n+#define CQ_DESC_Q_NUM_BITS       10\n+#define CQ_DESC_Q_NUM_MASK       ((1 << CQ_DESC_Q_NUM_BITS) - 1)\n+#define CQ_DESC_COMP_NDX_BITS    12\n+#define CQ_DESC_COMP_NDX_MASK    ((1 << CQ_DESC_COMP_NDX_BITS) - 1)\n+\n+static inline void cq_color_enc(struct cq_desc *desc, const u8 color)\n+{\n+\tif (color)\n+\t\tdesc->type_color |=  (1 << CQ_DESC_COLOR_SHIFT);\n+\telse\n+\t\tdesc->type_color &= ~(1 << CQ_DESC_COLOR_SHIFT);\n+}\n+\n+static inline void cq_desc_enc(struct cq_desc *desc,\n+\tconst u8 type, const u8 color, const u16 q_number,\n+\tconst u16 completed_index)\n+{\n+\tdesc->type_color = (type & CQ_DESC_TYPE_MASK) |\n+\t\t((color & CQ_DESC_COLOR_MASK) << CQ_DESC_COLOR_SHIFT);\n+\tdesc->q_number = cpu_to_le16(q_number & CQ_DESC_Q_NUM_MASK);\n+\tdesc->completed_index = cpu_to_le16(completed_index &\n+\t\tCQ_DESC_COMP_NDX_MASK);\n+}\n+\n+static inline void cq_desc_dec(const struct cq_desc *desc_arg,\n+\tu8 *type, u8 *color, u16 *q_number, u16 *completed_index)\n+{\n+\tconst struct cq_desc *desc = desc_arg;\n+\tconst u8 type_color = desc->type_color;\n+\n+\t*color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;\n+\n+\t/*\n+\t * Make sure color bit is read from desc *before* other fields\n+\t * are read from desc.  Hardware guarantees color bit is last\n+\t * bit (byte) written.  Adding the rmb() prevents the compiler\n+\t * and/or CPU from reordering the reads which would potentially\n+\t * result in reading stale values.\n+\t */\n+\n+\trmb();\n+\n+\t*type = type_color & CQ_DESC_TYPE_MASK;\n+\t*q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK;\n+\t*completed_index = le16_to_cpu(desc->completed_index) &\n+\t\tCQ_DESC_COMP_NDX_MASK;\n+}\n+\n+static inline void cq_color_dec(const struct cq_desc *desc_arg, u8 *color)\n+{\n+\tvolatile const struct cq_desc *desc = desc_arg;\n+\n+\t*color = (desc->type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;\n+}\n+\n+#endif /* _CQ_DESC_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/cq_enet_desc.h b/lib/librte_pmd_enic/vnic/cq_enet_desc.h\nnew file mode 100644\nindex 0000000..271ce3e\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/cq_enet_desc.h\n@@ -0,0 +1,261 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: cq_enet_desc.h 160468 2014-02-18 09:50:15Z gvaradar $\"\n+\n+#ifndef _CQ_ENET_DESC_H_\n+#define _CQ_ENET_DESC_H_\n+\n+#include \"cq_desc.h\"\n+\n+/* Ethernet completion queue descriptor: 16B */\n+struct cq_enet_wq_desc {\n+\t__le16 completed_index;\n+\t__le16 q_number;\n+\tu8 reserved[11];\n+\tu8 type_color;\n+};\n+\n+static inline void cq_enet_wq_desc_enc(struct cq_enet_wq_desc *desc,\n+\tu8 type, u8 color, u16 q_number, u16 completed_index)\n+{\n+\tcq_desc_enc((struct cq_desc *)desc, type,\n+\t\tcolor, q_number, completed_index);\n+}\n+\n+static inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,\n+\tu8 *type, u8 *color, u16 *q_number, u16 *completed_index)\n+{\n+\tcq_desc_dec((struct cq_desc *)desc, type,\n+\t\tcolor, q_number, completed_index);\n+}\n+\n+/* Completion queue descriptor: Ethernet receive queue, 16B */\n+struct cq_enet_rq_desc {\n+\t__le16 completed_index_flags;\n+\t__le16 q_number_rss_type_flags;\n+\t__le32 rss_hash;\n+\t__le16 bytes_written_flags;\n+\t__le16 vlan;\n+\t__le16 checksum_fcoe;\n+\tu8 flags;\n+\tu8 type_color;\n+};\n+\n+#define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT          (0x1 << 12)\n+#define CQ_ENET_RQ_DESC_FLAGS_FCOE                  (0x1 << 13)\n+#define CQ_ENET_RQ_DESC_FLAGS_EOP                   (0x1 << 14)\n+#define CQ_ENET_RQ_DESC_FLAGS_SOP                   (0x1 << 15)\n+\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_BITS               4\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_NONE               0\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4               1\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4           2\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6               3\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6           4\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX            5\n+#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX        6\n+\n+#define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC         (0x1 << 14)\n+\n+#define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS          14\n+#define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED             (0x1 << 14)\n+#define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED         (0x1 << 15)\n+\n+#define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS          12\n+#define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK           (0x1 << 12)\n+#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS     3\n+#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT    13\n+\n+#define CQ_ENET_RQ_DESC_FCOE_SOF_BITS               8\n+#define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_FCOE_EOF_BITS               8\n+#define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT              8\n+\n+#define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK       (0x1 << 0)\n+#define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK              (0x1 << 0)\n+#define CQ_ENET_RQ_DESC_FLAGS_UDP                   (0x1 << 1)\n+#define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR              (0x1 << 1)\n+#define CQ_ENET_RQ_DESC_FLAGS_TCP                   (0x1 << 2)\n+#define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK          (0x1 << 3)\n+#define CQ_ENET_RQ_DESC_FLAGS_IPV6                  (0x1 << 4)\n+#define CQ_ENET_RQ_DESC_FLAGS_IPV4                  (0x1 << 5)\n+#define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT         (0x1 << 6)\n+#define CQ_ENET_RQ_DESC_FLAGS_FCS_OK                (0x1 << 7)\n+\n+static inline void cq_enet_rq_desc_enc(struct cq_enet_rq_desc *desc,\n+\tu8 type, u8 color, u16 q_number, u16 completed_index,\n+\tu8 ingress_port, u8 fcoe, u8 eop, u8 sop, u8 rss_type, u8 csum_not_calc,\n+\tu32 rss_hash, u16 bytes_written, u8 packet_error, u8 vlan_stripped,\n+\tu16 vlan, u16 checksum, u8 fcoe_sof, u8 fcoe_fc_crc_ok,\n+\tu8 fcoe_enc_error, u8 fcoe_eof, u8 tcp_udp_csum_ok, u8 udp, u8 tcp,\n+\tu8 ipv4_csum_ok, u8 ipv6, u8 ipv4, u8 ipv4_fragment, u8 fcs_ok)\n+{\n+\tcq_desc_enc((struct cq_desc *)desc, type,\n+\t\tcolor, q_number, completed_index);\n+\n+\tdesc->completed_index_flags |= cpu_to_le16(\n+\t\t(ingress_port ? CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT : 0) |\n+\t\t(fcoe ? CQ_ENET_RQ_DESC_FLAGS_FCOE : 0) |\n+\t\t(eop ? CQ_ENET_RQ_DESC_FLAGS_EOP : 0) |\n+\t\t(sop ? CQ_ENET_RQ_DESC_FLAGS_SOP : 0));\n+\n+\tdesc->q_number_rss_type_flags |= cpu_to_le16(\n+\t\t((rss_type & CQ_ENET_RQ_DESC_RSS_TYPE_MASK) <<\n+\t\tCQ_DESC_Q_NUM_BITS) |\n+\t\t(csum_not_calc ? CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC : 0));\n+\n+\tdesc->rss_hash = cpu_to_le32(rss_hash);\n+\n+\tdesc->bytes_written_flags = cpu_to_le16(\n+\t\t(bytes_written & CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK) |\n+\t\t(packet_error ? CQ_ENET_RQ_DESC_FLAGS_TRUNCATED : 0) |\n+\t\t(vlan_stripped ? CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED : 0));\n+\n+\tdesc->vlan = cpu_to_le16(vlan);\n+\n+\tif (fcoe) {\n+\t\tdesc->checksum_fcoe = cpu_to_le16(\n+\t\t\t(fcoe_sof & CQ_ENET_RQ_DESC_FCOE_SOF_MASK) |\n+\t\t\t((fcoe_eof & CQ_ENET_RQ_DESC_FCOE_EOF_MASK) <<\n+\t\t\t\tCQ_ENET_RQ_DESC_FCOE_EOF_SHIFT));\n+\t} else {\n+\t\tdesc->checksum_fcoe = cpu_to_le16(checksum);\n+\t}\n+\n+\tdesc->flags =\n+\t\t(tcp_udp_csum_ok ? CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK : 0) |\n+\t\t(udp ? CQ_ENET_RQ_DESC_FLAGS_UDP : 0) |\n+\t\t(tcp ? CQ_ENET_RQ_DESC_FLAGS_TCP : 0) |\n+\t\t(ipv4_csum_ok ? CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK : 0) |\n+\t\t(ipv6 ? CQ_ENET_RQ_DESC_FLAGS_IPV6 : 0) |\n+\t\t(ipv4 ? CQ_ENET_RQ_DESC_FLAGS_IPV4 : 0) |\n+\t\t(ipv4_fragment ? CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT : 0) |\n+\t\t(fcs_ok ? CQ_ENET_RQ_DESC_FLAGS_FCS_OK : 0) |\n+\t\t(fcoe_fc_crc_ok ? CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK : 0) |\n+\t\t(fcoe_enc_error ? CQ_ENET_RQ_DESC_FCOE_ENC_ERROR : 0);\n+}\n+\n+static inline void cq_enet_rq_desc_dec(struct cq_enet_rq_desc *desc,\n+\tu8 *type, u8 *color, u16 *q_number, u16 *completed_index,\n+\tu8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type,\n+\tu8 *csum_not_calc, u32 *rss_hash, u16 *bytes_written, u8 *packet_error,\n+\tu8 *vlan_stripped, u16 *vlan_tci, u16 *checksum, u8 *fcoe_sof,\n+\tu8 *fcoe_fc_crc_ok, u8 *fcoe_enc_error, u8 *fcoe_eof,\n+\tu8 *tcp_udp_csum_ok, u8 *udp, u8 *tcp, u8 *ipv4_csum_ok,\n+\tu8 *ipv6, u8 *ipv4, u8 *ipv4_fragment, u8 *fcs_ok)\n+{\n+\tu16 completed_index_flags;\n+\tu16 q_number_rss_type_flags;\n+\tu16 bytes_written_flags;\n+\n+\tcq_desc_dec((struct cq_desc *)desc, type,\n+\t\tcolor, q_number, completed_index);\n+\n+\tcompleted_index_flags = le16_to_cpu(desc->completed_index_flags);\n+\tq_number_rss_type_flags =\n+\t\tle16_to_cpu(desc->q_number_rss_type_flags);\n+\tbytes_written_flags = le16_to_cpu(desc->bytes_written_flags);\n+\n+\t*ingress_port = (completed_index_flags &\n+\t\tCQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT) ? 1 : 0;\n+\t*fcoe = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_FCOE) ?\n+\t\t1 : 0;\n+\t*eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ?\n+\t\t1 : 0;\n+\t*sop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_SOP) ?\n+\t\t1 : 0;\n+\n+\t*rss_type = (u8)((q_number_rss_type_flags >> CQ_DESC_Q_NUM_BITS) &\n+\t\tCQ_ENET_RQ_DESC_RSS_TYPE_MASK);\n+\t*csum_not_calc = (q_number_rss_type_flags &\n+\t\tCQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ? 1 : 0;\n+\n+\t*rss_hash = le32_to_cpu(desc->rss_hash);\n+\n+\t*bytes_written = bytes_written_flags &\n+\t\tCQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;\n+\t*packet_error = (bytes_written_flags &\n+\t\tCQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ? 1 : 0;\n+\t*vlan_stripped = (bytes_written_flags &\n+\t\tCQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) ? 1 : 0;\n+\n+\t/*\n+\t * Tag Control Information(16) = user_priority(3) + cfi(1) + vlan(12)\n+\t */\n+\t*vlan_tci = le16_to_cpu(desc->vlan);\n+\n+\tif (*fcoe) {\n+\t\t*fcoe_sof = (u8)(le16_to_cpu(desc->checksum_fcoe) &\n+\t\t\tCQ_ENET_RQ_DESC_FCOE_SOF_MASK);\n+\t\t*fcoe_fc_crc_ok = (desc->flags &\n+\t\t\tCQ_ENET_RQ_DESC_FCOE_FC_CRC_OK) ? 1 : 0;\n+\t\t*fcoe_enc_error = (desc->flags &\n+\t\t\tCQ_ENET_RQ_DESC_FCOE_ENC_ERROR) ? 1 : 0;\n+\t\t*fcoe_eof = (u8)((le16_to_cpu(desc->checksum_fcoe) >>\n+\t\t\tCQ_ENET_RQ_DESC_FCOE_EOF_SHIFT) &\n+\t\t\tCQ_ENET_RQ_DESC_FCOE_EOF_MASK);\n+\t\t*checksum = 0;\n+\t} else {\n+\t\t*fcoe_sof = 0;\n+\t\t*fcoe_fc_crc_ok = 0;\n+\t\t*fcoe_enc_error = 0;\n+\t\t*fcoe_eof = 0;\n+\t\t*checksum = le16_to_cpu(desc->checksum_fcoe);\n+\t}\n+\n+\t*tcp_udp_csum_ok =\n+\t\t(desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ? 1 : 0;\n+\t*udp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_UDP) ? 1 : 0;\n+\t*tcp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP) ? 1 : 0;\n+\t*ipv4_csum_ok =\n+\t\t(desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ? 1 : 0;\n+\t*ipv6 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV6) ? 1 : 0;\n+\t*ipv4 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4) ? 1 : 0;\n+\t*ipv4_fragment =\n+\t\t(desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT) ? 1 : 0;\n+\t*fcs_ok = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_FCS_OK) ? 1 : 0;\n+}\n+\n+#endif /* _CQ_ENET_DESC_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/rq_enet_desc.h b/lib/librte_pmd_enic/vnic/rq_enet_desc.h\nnew file mode 100644\nindex 0000000..41a8cc4\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/rq_enet_desc.h\n@@ -0,0 +1,76 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: rq_enet_desc.h 59839 2010-09-27 20:36:31Z roprabhu $\"\n+\n+#ifndef _RQ_ENET_DESC_H_\n+#define _RQ_ENET_DESC_H_\n+\n+/* Ethernet receive queue descriptor: 16B */\n+struct rq_enet_desc {\n+\t__le64 address;\n+\t__le16 length_type;\n+\tu8 reserved[6];\n+};\n+\n+enum rq_enet_type_types {\n+\tRQ_ENET_TYPE_ONLY_SOP = 0,\n+\tRQ_ENET_TYPE_NOT_SOP = 1,\n+\tRQ_ENET_TYPE_RESV2 = 2,\n+\tRQ_ENET_TYPE_RESV3 = 3,\n+};\n+\n+#define RQ_ENET_ADDR_BITS\t\t64\n+#define RQ_ENET_LEN_BITS\t\t14\n+#define RQ_ENET_LEN_MASK\t\t((1 << RQ_ENET_LEN_BITS) - 1)\n+#define RQ_ENET_TYPE_BITS\t\t2\n+#define RQ_ENET_TYPE_MASK\t\t((1 << RQ_ENET_TYPE_BITS) - 1)\n+\n+static inline void rq_enet_desc_enc(struct rq_enet_desc *desc,\n+\tu64 address, u8 type, u16 length)\n+{\n+\tdesc->address = cpu_to_le64(address);\n+\tdesc->length_type = cpu_to_le16((length & RQ_ENET_LEN_MASK) |\n+\t\t((type & RQ_ENET_TYPE_MASK) << RQ_ENET_LEN_BITS));\n+}\n+\n+static inline void rq_enet_desc_dec(struct rq_enet_desc *desc,\n+\tu64 *address, u8 *type, u16 *length)\n+{\n+\t*address = le64_to_cpu(desc->address);\n+\t*length = le16_to_cpu(desc->length_type) & RQ_ENET_LEN_MASK;\n+\t*type = (u8)((le16_to_cpu(desc->length_type) >> RQ_ENET_LEN_BITS) &\n+\t\tRQ_ENET_TYPE_MASK);\n+}\n+\n+#endif /* _RQ_ENET_DESC_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_cq.c b/lib/librte_pmd_enic/vnic/vnic_cq.c\nnew file mode 100644\nindex 0000000..b1a1085\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_cq.c\n@@ -0,0 +1,117 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_cq.c 171146 2014-05-02 07:08:20Z ssujith $\"\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_cq.h\"\n+\n+int vnic_cq_mem_size(struct vnic_cq *cq, unsigned int desc_count,\n+\tunsigned int desc_size)\n+{\n+\tint mem_size;\n+\n+\tmem_size = vnic_dev_desc_ring_size(&cq->ring, desc_count, desc_size);\n+\n+\treturn mem_size;\n+}\n+\n+void vnic_cq_free(struct vnic_cq *cq)\n+{\n+\tvnic_dev_free_desc_ring(cq->vdev, &cq->ring);\n+\n+\tcq->ctrl = NULL;\n+}\n+\n+int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,\n+\tunsigned int socket_id,  \n+\tunsigned int desc_count, unsigned int desc_size)\n+{\n+\tint err;\n+\tchar res_name[NAME_MAX];\n+        static int instance = 0;\n+\n+\tcq->index = index;\n+\tcq->vdev = vdev;\n+\n+\tcq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_CQ, index);\n+\tif (!cq->ctrl) {\n+\t\tpr_err(\"Failed to hook CQ[%d] resource\\n\", index);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsnprintf(res_name, sizeof(res_name), \"%d-cq-%d\", instance++, index);\n+\terr = vnic_dev_alloc_desc_ring(vdev, &cq->ring, desc_count, desc_size, \n+\t\tsocket_id, res_name);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn 0;\n+}\n+\n+void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,\n+\tunsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,\n+\tunsigned int cq_tail_color, unsigned int interrupt_enable,\n+\tunsigned int cq_entry_enable, unsigned int cq_message_enable,\n+\tunsigned int interrupt_offset, u64 cq_message_addr)\n+{\n+\tu64 paddr;\n+\n+\tpaddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;\n+\twriteq(paddr, &cq->ctrl->ring_base);\n+\tiowrite32(cq->ring.desc_count, &cq->ctrl->ring_size);\n+\tiowrite32(flow_control_enable, &cq->ctrl->flow_control_enable);\n+\tiowrite32(color_enable, &cq->ctrl->color_enable);\n+\tiowrite32(cq_head, &cq->ctrl->cq_head);\n+\tiowrite32(cq_tail, &cq->ctrl->cq_tail);\n+\tiowrite32(cq_tail_color, &cq->ctrl->cq_tail_color);\n+\tiowrite32(interrupt_enable, &cq->ctrl->interrupt_enable);\n+\tiowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable);\n+\tiowrite32(cq_message_enable, &cq->ctrl->cq_message_enable);\n+\tiowrite32(interrupt_offset, &cq->ctrl->interrupt_offset);\n+\twriteq(cq_message_addr, &cq->ctrl->cq_message_addr);\n+\n+\tcq->interrupt_offset = interrupt_offset;\n+}\n+\n+void vnic_cq_clean(struct vnic_cq *cq)\n+{\n+\tcq->to_clean = 0;\n+\tcq->last_color = 0;\n+\n+\tiowrite32(0, &cq->ctrl->cq_head);\n+\tiowrite32(0, &cq->ctrl->cq_tail);\n+\tiowrite32(1, &cq->ctrl->cq_tail_color);\n+\n+\tvnic_dev_clear_desc_ring(&cq->ring);\n+}\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_cq.h b/lib/librte_pmd_enic/vnic/vnic_cq.h\nnew file mode 100644\nindex 0000000..599fb56\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_cq.h\n@@ -0,0 +1,152 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_cq.h 173398 2014-05-19 09:17:02Z gvaradar $\"\n+\n+#ifndef _VNIC_CQ_H_\n+#define _VNIC_CQ_H_\n+\n+#include <rte_mbuf.h>\n+\n+#include \"cq_desc.h\"\n+#include \"vnic_dev.h\"\n+\n+/* Completion queue control */\n+struct vnic_cq_ctrl {\n+\tu64 ring_base;\t\t\t/* 0x00 */\n+\tu32 ring_size;\t\t\t/* 0x08 */\n+\tu32 pad0;\n+\tu32 flow_control_enable;\t/* 0x10 */\n+\tu32 pad1;\n+\tu32 color_enable;\t\t/* 0x18 */\n+\tu32 pad2;\n+\tu32 cq_head;\t\t\t/* 0x20 */\n+\tu32 pad3;\n+\tu32 cq_tail;\t\t\t/* 0x28 */\n+\tu32 pad4;\n+\tu32 cq_tail_color;\t\t/* 0x30 */\n+\tu32 pad5;\n+\tu32 interrupt_enable;\t\t/* 0x38 */\n+\tu32 pad6;\n+\tu32 cq_entry_enable;\t\t/* 0x40 */\n+\tu32 pad7;\n+\tu32 cq_message_enable;\t\t/* 0x48 */\n+\tu32 pad8;\n+\tu32 interrupt_offset;\t\t/* 0x50 */\n+\tu32 pad9;\n+\tu64 cq_message_addr;\t\t/* 0x58 */\n+\tu32 pad10;\n+};\n+\n+#ifdef ENIC_AIC\n+struct vnic_rx_bytes_counter {\n+        unsigned int small_pkt_bytes_cnt;\n+        unsigned int large_pkt_bytes_cnt;\n+};\n+#endif\n+\n+struct vnic_cq {\n+\tunsigned int index;\n+\tstruct vnic_dev *vdev;\n+\tstruct vnic_cq_ctrl __iomem *ctrl;              /* memory-mapped */\n+\tstruct vnic_dev_ring ring;\n+\tunsigned int to_clean;\n+\tunsigned int last_color;\n+\tunsigned int interrupt_offset;\n+#ifdef ENIC_AIC\n+\tstruct vnic_rx_bytes_counter pkt_size_counter;\n+\tunsigned int cur_rx_coal_timeval;\n+\tunsigned int tobe_rx_coal_timeval;\n+\tktime_t prev_ts;\n+#endif\n+};\n+\n+static inline unsigned int vnic_cq_service(struct vnic_cq *cq,\n+\tunsigned int work_to_do,\n+\tint (*q_service)(struct vnic_dev *vdev, struct cq_desc *cq_desc,\n+\tu8 type, u16 q_number, u16 completed_index, void *opaque),\n+\tvoid *opaque)\n+{\n+        struct cq_desc *cq_desc;\n+        unsigned int work_done = 0;\n+        u16 q_number, completed_index;\n+        u8 type, color;\n+        struct rte_mbuf **rx_pkts = opaque;\n+        unsigned int ret;\n+        unsigned int split_hdr_size = vnic_get_hdr_split_size(cq->vdev);\n+\n+        cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +\n+                cq->ring.desc_size * cq->to_clean);\n+        cq_desc_dec(cq_desc, &type, &color,\n+                &q_number, &completed_index);\n+\n+        while (color != cq->last_color) {\n+            if(opaque)\n+                opaque = (void *)&(rx_pkts[work_done]);\n+\n+            ret = (*q_service)(cq->vdev, cq_desc, type,\n+                        q_number, completed_index, opaque);\n+            cq->to_clean++;\n+            if (cq->to_clean == cq->ring.desc_count) {\n+                cq->to_clean = 0;\n+                cq->last_color = cq->last_color ? 0 : 1;\n+            }\n+\n+            cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +\n+                    cq->ring.desc_size * cq->to_clean);\n+            cq_desc_dec(cq_desc, &type, &color,\n+                    &q_number, &completed_index);\n+\n+            if(ret)\n+            work_done++;\n+            if (work_done >= work_to_do)\n+                break;\n+        }\n+\n+        return work_done;\n+}\n+\n+void vnic_cq_free(struct vnic_cq *cq);\n+int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,\n+        unsigned int socket_id,\n+\tunsigned int desc_count, unsigned int desc_size);\n+void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,\n+\tunsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,\n+\tunsigned int cq_tail_color, unsigned int interrupt_enable,\n+\tunsigned int cq_entry_enable, unsigned int message_enable,\n+\tunsigned int interrupt_offset, u64 message_addr);\n+void vnic_cq_clean(struct vnic_cq *cq);\n+int vnic_cq_mem_size(struct vnic_cq *cq, unsigned int desc_count,\n+\tunsigned int desc_size);\n+\n+#endif /* _VNIC_CQ_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_dev.c b/lib/librte_pmd_enic/vnic/vnic_dev.c\nnew file mode 100644\nindex 0000000..ec3a958\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_dev.c\n@@ -0,0 +1,1081 @@\n+/*\n+ * Copyright 2008-2014 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id$\"\n+\n+#include <rte_memzone.h>\n+#include <rte_memcpy.h>\n+#include <rte_string_fns.h>\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_resource.h\"\n+#include \"vnic_devcmd.h\"\n+#include \"vnic_stats.h\"\n+\n+\n+enum vnic_proxy_type {\n+\tPROXY_NONE,\n+\tPROXY_BY_BDF,\n+\tPROXY_BY_INDEX,\n+};\n+\n+struct vnic_res {\n+\tvoid __iomem *vaddr;\n+\tdma_addr_t bus_addr;\n+\tunsigned int count;\n+};\n+\n+struct vnic_intr_coal_timer_info {\n+\tu32 mul;\n+\tu32 div;\n+\tu32 max_usec;\n+};\n+\n+struct vnic_dev {\n+\tvoid *priv;\n+\tstruct rte_pci_device *pdev;\n+\tstruct vnic_res res[RES_TYPE_MAX];\n+\tenum vnic_dev_intr_mode intr_mode;\n+\tstruct vnic_devcmd __iomem *devcmd;\n+\tstruct vnic_devcmd_notify *notify;\n+\tstruct vnic_devcmd_notify notify_copy;\n+\tdma_addr_t notify_pa;\n+\tu32 notify_sz;\n+\tdma_addr_t linkstatus_pa;\n+\tstruct vnic_stats *stats;\n+\tdma_addr_t stats_pa;\n+\tstruct vnic_devcmd_fw_info *fw_info;\n+\tdma_addr_t fw_info_pa;\n+\tenum vnic_proxy_type proxy;\n+\tu32 proxy_index;\n+\tu64 args[VNIC_DEVCMD_NARGS];\n+\tu16 split_hdr_size;\n+\tint in_reset;\n+\tstruct vnic_intr_coal_timer_info intr_coal_timer_info;\n+#ifdef RTE_EAL_VFIO\n+\tvoid *(*buf_map)(void *priv, void *addr, size_t size);\n+#endif\n+\tvoid *(*alloc_consistent)(void *priv, size_t size,\n+\t\tdma_addr_t *dma_handle, u8 *name);\n+\tvoid (*free_consistent)(struct rte_pci_device *hwdev,\n+\t\tsize_t size, void *vaddr,\n+\t\tdma_addr_t dma_handle);\n+};\n+\n+#define VNIC_MAX_RES_HDR_SIZE \\\n+\t(sizeof(struct vnic_resource_header) + \\\n+\tsizeof(struct vnic_resource) * RES_TYPE_MAX)\n+#define VNIC_RES_STRIDE\t128\n+\n+void *vnic_dev_priv(struct vnic_dev *vdev)\n+{\n+\treturn vdev->priv;\n+}\n+\n+void vnic_register_cbacks(struct vnic_dev *vdev,\n+#ifdef RTE_EAL_VFIO\n+\tvoid *(*buf_map)(void *priv, void *addr, size_t size),\n+#endif\n+\tvoid *(*alloc_consistent)(void *priv, size_t size,\n+\t    dma_addr_t *dma_handle, u8 *name),\n+\tvoid (*free_consistent)(struct rte_pci_device *hwdev,\n+\t    size_t size, void *vaddr,\n+\t    dma_addr_t dma_handle))\n+{\n+#ifdef RTE_EAL_VFIO\n+\tvdev->buf_map = buf_map;\n+#endif\n+\tvdev->alloc_consistent = alloc_consistent;\n+\tvdev->free_consistent = free_consistent;\n+}\n+\n+static int vnic_dev_discover_res(struct vnic_dev *vdev,\n+\tstruct vnic_dev_bar *bar, unsigned int num_bars)\n+{\n+\tstruct vnic_resource_header __iomem *rh;\n+\tstruct mgmt_barmap_hdr __iomem *mrh;\n+\tstruct vnic_resource __iomem *r;\n+\tu8 type;\n+\n+\tif (num_bars == 0)\n+\t\treturn -EINVAL;\n+\n+\tif (bar->len < VNIC_MAX_RES_HDR_SIZE) {\n+\t\tpr_err(\"vNIC BAR0 res hdr length error\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trh  = bar->vaddr;\n+\tmrh = bar->vaddr;\n+\tif (!rh) {\n+\t\tpr_err(\"vNIC BAR0 res hdr not mem-mapped\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Check for mgmt vnic in addition to normal vnic */\n+\tif ((ioread32(&rh->magic) != VNIC_RES_MAGIC) ||\n+\t\t(ioread32(&rh->version) != VNIC_RES_VERSION)) {\n+\t\tif ((ioread32(&mrh->magic) != MGMTVNIC_MAGIC) ||\n+\t\t\t(ioread32(&mrh->version) != MGMTVNIC_VERSION)) {\n+\t\t\tpr_err(\"vNIC BAR0 res magic/version error \" \\\n+\t\t\t\t\"exp (%lx/%lx) or (%lx/%lx), curr (%x/%x)\\n\",\n+\t\t\t\tVNIC_RES_MAGIC, VNIC_RES_VERSION,\n+\t\t\t\tMGMTVNIC_MAGIC, MGMTVNIC_VERSION,\n+\t\t\t\tioread32(&rh->magic), ioread32(&rh->version));\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (ioread32(&mrh->magic) == MGMTVNIC_MAGIC)\n+\t\tr = (struct vnic_resource __iomem *)(mrh + 1);\n+\telse\n+\t\tr = (struct vnic_resource __iomem *)(rh + 1);\n+\n+\n+\twhile ((type = ioread8(&r->type)) != RES_TYPE_EOL) {\n+\t\tu8 bar_num = ioread8(&r->bar);\n+\t\tu32 bar_offset = ioread32(&r->bar_offset);\n+\t\tu32 count = ioread32(&r->count);\n+\t\tu32 len;\n+\n+\t\tr++;\n+\n+\t\tif (bar_num >= num_bars)\n+\t\t\tcontinue;\n+\n+\t\tif (!bar[bar_num].len || !bar[bar_num].vaddr)\n+\t\t\tcontinue;\n+\n+\t\tswitch (type) {\n+\t\tcase RES_TYPE_WQ:\n+\t\tcase RES_TYPE_RQ:\n+\t\tcase RES_TYPE_CQ:\n+\t\tcase RES_TYPE_INTR_CTRL:\n+\t\t\t/* each count is stride bytes long */\n+\t\t\tlen = count * VNIC_RES_STRIDE;\n+\t\t\tif (len + bar_offset > bar[bar_num].len) {\n+\t\t\t\tpr_err(\"vNIC BAR0 resource %d \" \\\n+\t\t\t\t\t\"out-of-bounds, offset 0x%x + \" \\\n+\t\t\t\t\t\"size 0x%x > bar len 0x%lx\\n\",\n+\t\t\t\t\ttype, bar_offset,\n+\t\t\t\t\tlen,\n+\t\t\t\t\tbar[bar_num].len);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RES_TYPE_INTR_PBA_LEGACY:\n+\t\tcase RES_TYPE_DEVCMD:\n+\t\t\tlen = count;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tvdev->res[type].count = count;\n+\t\tvdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr +\n+\t\t    bar_offset;\n+\t\tvdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+unsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,\n+\tenum vnic_res_type type)\n+{\n+\treturn vdev->res[type].count;\n+}\n+\n+void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,\n+\tunsigned int index)\n+{\n+\tif (!vdev->res[type].vaddr)\n+\t\treturn NULL;\n+\n+\tswitch (type) {\n+\tcase RES_TYPE_WQ:\n+\tcase RES_TYPE_RQ:\n+\tcase RES_TYPE_CQ:\n+\tcase RES_TYPE_INTR_CTRL:\n+\t\treturn (char __iomem *)vdev->res[type].vaddr +\n+\t\t\tindex * VNIC_RES_STRIDE;\n+\tdefault:\n+\t\treturn (char __iomem *)vdev->res[type].vaddr;\n+\t}\n+}\n+\n+unsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,\n+\tunsigned int desc_count, unsigned int desc_size)\n+{\n+\t/* The base address of the desc rings must be 512 byte aligned.\n+\t * Descriptor count is aligned to groups of 32 descriptors.  A\n+\t * count of 0 means the maximum 4096 descriptors.  Descriptor\n+\t * size is aligned to 16 bytes.\n+\t */\n+\n+\tunsigned int count_align = 32;\n+\tunsigned int desc_align = 16;\n+\n+\tring->base_align = 512;\n+\n+\tif (desc_count == 0)\n+\t\tdesc_count = 4096;\n+\n+\tring->desc_count = ALIGN(desc_count, count_align);\n+\n+\tring->desc_size = ALIGN(desc_size, desc_align);\n+\n+\tring->size = ring->desc_count * ring->desc_size;\n+\tring->size_unaligned = ring->size + ring->base_align;\n+\n+\treturn ring->size_unaligned;\n+}\n+\n+void vnic_set_hdr_split_size(struct vnic_dev *vdev, u16 size)\n+{\n+\tvdev->split_hdr_size = size;\n+}\n+\n+u16 vnic_get_hdr_split_size(struct vnic_dev *vdev)\n+{\n+\treturn vdev->split_hdr_size;\n+}\n+\n+void vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)\n+{\n+\tmemset(ring->descs, 0, ring->size);\n+}\n+\n+int vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,\n+\tunsigned int desc_count, unsigned int desc_size, unsigned int socket_id,\n+\tchar *z_name)\n+{\n+\tconst struct rte_memzone *rz;\n+\n+\tvnic_dev_desc_ring_size(ring, desc_count, desc_size);\n+\n+\trz = rte_memzone_reserve_aligned(z_name,\n+\t\tring->size_unaligned, socket_id,\n+\t\t0, ENIC_ALIGN);\n+\tif (!rz) {\n+\t\tpr_err(\"Failed to allocate ring (size=%d), aborting\\n\",\n+\t\t\t(int)ring->size);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+#ifdef RTE_EAL_VFIO\n+\tring->descs_unaligned = vdev->buf_map(vdev->priv, rz->addr,\n+\t\t(size_t)(rz->len));\n+#else\n+\tring->descs_unaligned = rz->addr;\n+#endif\n+\tif (!ring->descs_unaligned) {\n+\t\tpr_err(\"Failed to map allocated ring (size=%d), aborting\\n\",\n+\t\t\t(int)ring->size);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+#ifdef RTE_EAL_VFIO\n+\tring->base_addr_unaligned = (dma_addr_t)ring->descs_unaligned;\n+#else\n+\tring->base_addr_unaligned = (dma_addr_t)rz->phys_addr;\n+#endif\n+\n+\tring->base_addr = ALIGN(ring->base_addr_unaligned,\n+\t\tring->base_align);\n+\tring->descs = (u8 *)ring->descs_unaligned +\n+\t    (ring->base_addr - ring->base_addr_unaligned);\n+\n+\tvnic_dev_clear_desc_ring(ring);\n+\n+\tring->desc_avail = ring->desc_count - 1;\n+\n+\treturn 0;\n+}\n+\n+void vnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)\n+{\n+\tif (ring->descs)\n+\t\tring->descs = NULL;\n+}\n+\n+static int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n+\tint wait)\n+{\n+\tstruct vnic_devcmd __iomem *devcmd = vdev->devcmd;\n+\tunsigned int i;\n+\tint delay;\n+\tu32 status;\n+\tint err;\n+\n+\tstatus = ioread32(&devcmd->status);\n+\tif (status == 0xFFFFFFFF) {\n+\t\t/* PCI-e target device is gone */\n+\t\treturn -ENODEV;\n+\t}\n+\tif (status & STAT_BUSY) {\n+\n+\t\tpr_err(\"Busy devcmd %d\\n\",  _CMD_N(cmd));\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tif (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {\n+\t\tfor (i = 0; i < VNIC_DEVCMD_NARGS; i++)\n+\t\t\twriteq(vdev->args[i], &devcmd->args[i]);\n+\t\twmb(); /* complete all writes initiated till now */\n+\t}\n+\n+\tiowrite32(cmd, &devcmd->cmd);\n+\n+\tif ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))\n+\t\treturn 0;\n+\n+\tfor (delay = 0; delay < wait; delay++) {\n+\n+\t\tudelay(100);\n+\n+\t\tstatus = ioread32(&devcmd->status);\n+\t\tif (status == 0xFFFFFFFF) {\n+\t\t\t/* PCI-e target device is gone */\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\n+\t\tif (!(status & STAT_BUSY)) {\n+\t\t\tif (status & STAT_ERROR) {\n+\t\t\t\terr = -(int)readq(&devcmd->args[0]);\n+\t\t\t\tif (cmd != CMD_CAPABILITY)\n+\t\t\t\t\tpr_err(\"Devcmd %d failed \" \\\n+\t\t\t\t\t\t\"with error code %d\\n\",\n+\t\t\t\t\t\t_CMD_N(cmd), err);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\n+\t\t\tif (_CMD_DIR(cmd) & _CMD_DIR_READ) {\n+\t\t\t\trmb();/* finish all reads initiated till now */\n+\t\t\t\tfor (i = 0; i < VNIC_DEVCMD_NARGS; i++)\n+\t\t\t\t\tvdev->args[i] = readq(&devcmd->args[i]);\n+\t\t\t}\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\tpr_err(\"Timedout devcmd %d\\n\", _CMD_N(cmd));\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int vnic_dev_cmd_proxy(struct vnic_dev *vdev,\n+\tenum vnic_devcmd_cmd proxy_cmd, enum vnic_devcmd_cmd cmd,\n+\tu64 *a0, u64 *a1, int wait)\n+{\n+\tu32 status;\n+\tint err;\n+\n+\tmemset(vdev->args, 0, sizeof(vdev->args));\n+\n+\tvdev->args[0] = vdev->proxy_index;\n+\tvdev->args[1] = cmd;\n+\tvdev->args[2] = *a0;\n+\tvdev->args[3] = *a1;\n+\n+\terr = _vnic_dev_cmd(vdev, proxy_cmd, wait);\n+\tif (err)\n+\t\treturn err;\n+\n+\tstatus = (u32)vdev->args[0];\n+\tif (status & STAT_ERROR) {\n+\t\terr = (int)vdev->args[1];\n+\t\tif (err != ERR_ECMDUNKNOWN ||\n+\t\t    cmd != CMD_CAPABILITY)\n+\t\t\tpr_err(\"Error %d proxy devcmd %d\\n\", err, _CMD_N(cmd));\n+\t\treturn err;\n+\t}\n+\n+\t*a0 = vdev->args[1];\n+\t*a1 = vdev->args[2];\n+\n+\treturn 0;\n+}\n+\n+static int vnic_dev_cmd_no_proxy(struct vnic_dev *vdev,\n+\tenum vnic_devcmd_cmd cmd, u64 *a0, u64 *a1, int wait)\n+{\n+\tint err;\n+\n+\tvdev->args[0] = *a0;\n+\tvdev->args[1] = *a1;\n+\n+\terr = _vnic_dev_cmd(vdev, cmd, wait);\n+\n+\t*a0 = vdev->args[0];\n+\t*a1 = vdev->args[1];\n+\n+\treturn err;\n+}\n+\n+void vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index)\n+{\n+\tvdev->proxy = PROXY_BY_INDEX;\n+\tvdev->proxy_index = index;\n+}\n+\n+void vnic_dev_cmd_proxy_by_bdf_start(struct vnic_dev *vdev, u16 bdf)\n+{\n+\tvdev->proxy = PROXY_BY_BDF;\n+\tvdev->proxy_index = bdf;\n+}\n+\n+void vnic_dev_cmd_proxy_end(struct vnic_dev *vdev)\n+{\n+\tvdev->proxy = PROXY_NONE;\n+\tvdev->proxy_index = 0;\n+}\n+\n+int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n+\tu64 *a0, u64 *a1, int wait)\n+{\n+\tmemset(vdev->args, 0, sizeof(vdev->args));\n+\n+\tswitch (vdev->proxy) {\n+\tcase PROXY_BY_INDEX:\n+\t\treturn vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX, cmd,\n+\t\t\t\ta0, a1, wait);\n+\tcase PROXY_BY_BDF:\n+\t\treturn vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF, cmd,\n+\t\t\t\ta0, a1, wait);\n+\tcase PROXY_NONE:\n+\tdefault:\n+\t\treturn vnic_dev_cmd_no_proxy(vdev, cmd, a0, a1, wait);\n+\t}\n+}\n+\n+static int vnic_dev_capable(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd)\n+{\n+\tu64 a0 = (u32)cmd, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\n+\terr = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);\n+\n+\treturn !(err || a0);\n+}\n+\n+int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,\n+\tvoid *value)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tint err;\n+\n+\ta0 = offset;\n+\ta1 = size;\n+\n+\terr = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);\n+\n+\tswitch (size) {\n+\tcase 1:\n+\t\t*(u8 *)value = (u8)a0;\n+\t\tbreak;\n+\tcase 2:\n+\t\t*(u16 *)value = (u16)a0;\n+\t\tbreak;\n+\tcase 4:\n+\t\t*(u32 *)value = (u32)a0;\n+\t\tbreak;\n+\tcase 8:\n+\t\t*(u64 *)value = a0;\n+\t\tbreak;\n+\tdefault:\n+\t\tBUG();\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+int vnic_dev_stats_clear(struct vnic_dev *vdev)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_STATS_CLEAR, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tstatic instance;\n+\tchar name[NAME_MAX];\n+\n+\tif (!vdev->stats) {\n+\t\tsnprintf(name, sizeof(name), \"vnic_stats-%d\", instance++);\n+\t\tvdev->stats = vdev->alloc_consistent(vdev->priv,\n+\t\t\tsizeof(struct vnic_stats), &vdev->stats_pa, name);\n+\t\tif (!vdev->stats)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\t*stats = vdev->stats;\n+\ta0 = vdev->stats_pa;\n+\ta1 = sizeof(struct vnic_stats);\n+\n+\treturn vnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_close(struct vnic_dev *vdev)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);\n+}\n+\n+/** Deprecated.  @see vnic_dev_enable_wait */\n+int vnic_dev_enable(struct vnic_dev *vdev)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_enable_wait(struct vnic_dev *vdev)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\n+\tif (vnic_dev_capable(vdev, CMD_ENABLE_WAIT))\n+\t\treturn vnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);\n+\telse\n+\t\treturn vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_disable(struct vnic_dev *vdev)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_open(struct vnic_dev *vdev, int arg)\n+{\n+\tu64 a0 = (u32)arg, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_open_done(struct vnic_dev *vdev, int *done)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\n+\t*done = 0;\n+\n+\terr = vnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);\n+\tif (err)\n+\t\treturn err;\n+\n+\t*done = (a0 == 0);\n+\n+\treturn 0;\n+}\n+\n+int vnic_dev_soft_reset(struct vnic_dev *vdev, int arg)\n+{\n+\tu64 a0 = (u32)arg, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_SOFT_RESET, &a0, &a1, wait);\n+}\n+\n+int vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\n+\t*done = 0;\n+\n+\terr = vnic_dev_cmd(vdev, CMD_SOFT_RESET_STATUS, &a0, &a1, wait);\n+\tif (err)\n+\t\treturn err;\n+\n+\t*done = (a0 == 0);\n+\n+\treturn 0;\n+}\n+\n+int vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tint err, i;\n+\n+\tfor (i = 0; i < ETH_ALEN; i++)\n+\t\tmac_addr[i] = 0;\n+\n+\terr = vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);\n+\tif (err)\n+\t\treturn err;\n+\n+\tfor (i = 0; i < ETH_ALEN; i++)\n+\t\tmac_addr[i] = ((u8 *)&a0)[i];\n+\n+\treturn 0;\n+}\n+\n+int vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,\n+\tint broadcast, int promisc, int allmulti)\n+{\n+\tu64 a0, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\n+\ta0 = (directed ? CMD_PFILTER_DIRECTED : 0) |\n+\t     (multicast ? CMD_PFILTER_MULTICAST : 0) |\n+\t     (broadcast ? CMD_PFILTER_BROADCAST : 0) |\n+\t     (promisc ? CMD_PFILTER_PROMISCUOUS : 0) |\n+\t     (allmulti ? CMD_PFILTER_ALL_MULTICAST : 0);\n+\n+\terr = vnic_dev_cmd(vdev, CMD_PACKET_FILTER, &a0, &a1, wait);\n+\tif (err)\n+\t\tpr_err(\"Can't set packet filter\\n\");\n+\n+\treturn err;\n+}\n+\n+int vnic_dev_add_addr(struct vnic_dev *vdev, u8 *addr)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\tint i;\n+\n+\tfor (i = 0; i < ETH_ALEN; i++)\n+\t\t((u8 *)&a0)[i] = addr[i];\n+\n+\terr = vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);\n+\tif (err)\n+\t\tpr_err(\"Can't add addr [%02x:%02x:%02x:%02x:%02x:%02x], %d\\n\",\n+\t\t\taddr[0], addr[1], addr[2], addr[3], addr[4], addr[5],\n+\t\t\terr);\n+\n+\treturn err;\n+}\n+\n+int vnic_dev_del_addr(struct vnic_dev *vdev, u8 *addr)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\tint i;\n+\n+\tfor (i = 0; i < ETH_ALEN; i++)\n+\t\t((u8 *)&a0)[i] = addr[i];\n+\n+\terr = vnic_dev_cmd(vdev, CMD_ADDR_DEL, &a0, &a1, wait);\n+\tif (err)\n+\t\tpr_err(\"Can't del addr [%02x:%02x:%02x:%02x:%02x:%02x], %d\\n\",\n+\t\t\taddr[0], addr[1], addr[2], addr[3], addr[4], addr[5],\n+\t\t\terr);\n+\n+\treturn err;\n+}\n+\n+int vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,\n+\tu8 ig_vlan_rewrite_mode)\n+{\n+\tu64 a0 = ig_vlan_rewrite_mode, a1 = 0;\n+\tint wait = 1000;\n+\n+\tif (vnic_dev_capable(vdev, CMD_IG_VLAN_REWRITE_MODE))\n+\t\treturn vnic_dev_cmd(vdev, CMD_IG_VLAN_REWRITE_MODE,\n+\t\t\t\t&a0, &a1, wait);\n+\telse\n+\t\treturn 0;\n+}\n+\n+int vnic_dev_raise_intr(struct vnic_dev *vdev, u16 intr)\n+{\n+\tu64 a0 = intr, a1 = 0;\n+\tint wait = 1000;\n+\tint err;\n+\n+\terr = vnic_dev_cmd(vdev, CMD_IAR, &a0, &a1, wait);\n+\tif (err)\n+\t\tpr_err(\"Failed to raise INTR[%d], err %d\\n\", intr, err);\n+\n+\treturn err;\n+}\n+\n+void vnic_dev_set_reset_flag(struct vnic_dev *vdev, int state)\n+{\n+\tvdev->in_reset = state;\n+}\n+\n+static inline int vnic_dev_in_reset(struct vnic_dev *vdev)\n+{\n+\treturn vdev->in_reset;\n+}\n+\n+int vnic_dev_notify_setcmd(struct vnic_dev *vdev,\n+\tvoid *notify_addr, dma_addr_t notify_pa, u16 intr)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tint r;\n+\n+\tmemset(notify_addr, 0, sizeof(struct vnic_devcmd_notify));\n+\tif (!vnic_dev_in_reset(vdev)) {\n+\t\tvdev->notify = notify_addr;\n+\t\tvdev->notify_pa = notify_pa;\n+\t}\n+\n+\ta0 = (u64)notify_pa;\n+\ta1 = ((u64)intr << 32) & 0x0000ffff00000000ULL;\n+\ta1 += sizeof(struct vnic_devcmd_notify);\n+\n+\tr = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);\n+\tif (!vnic_dev_in_reset(vdev))\n+\t\tvdev->notify_sz = (r == 0) ? (u32)a1 : 0;\n+\n+\treturn r;\n+}\n+\n+int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)\n+{\n+\tvoid *notify_addr;\n+\tdma_addr_t notify_pa;\n+\tchar name[NAME_MAX];\n+\tstatic int instance;\n+\n+\tif (vdev->notify || vdev->notify_pa) {\n+\t\tpr_warn(\"notify block %p still allocated.\\n\" \\\n+\t\t\t\"Ignore if restarting port\\n\", vdev->notify);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!vnic_dev_in_reset(vdev)) {\n+\t\tsnprintf(name, sizeof(name), \"vnic_notify-%d\", instance++);\n+\t\tnotify_addr = vdev->alloc_consistent(vdev->priv,\n+\t\t\tsizeof(struct vnic_devcmd_notify),\n+\t\t\t&notify_pa, name);\n+\t\tif (!notify_addr)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn vnic_dev_notify_setcmd(vdev, notify_addr, notify_pa, intr);\n+}\n+\n+int vnic_dev_notify_unsetcmd(struct vnic_dev *vdev)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tint err;\n+\n+\ta0 = 0;  /* paddr = 0 to unset notify buffer */\n+\ta1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */\n+\ta1 += sizeof(struct vnic_devcmd_notify);\n+\n+\terr = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);\n+\tif (!vnic_dev_in_reset(vdev)) {\n+\t\tvdev->notify = NULL;\n+\t\tvdev->notify_pa = 0;\n+\t\tvdev->notify_sz = 0;\n+\t}\n+\n+\treturn err;\n+}\n+\n+int vnic_dev_notify_unset(struct vnic_dev *vdev)\n+{\n+\tif (vdev->notify && !vnic_dev_in_reset(vdev)) {\n+\t\tvdev->free_consistent(vdev->pdev,\n+\t\t\tsizeof(struct vnic_devcmd_notify),\n+\t\t\tvdev->notify,\n+\t\t\tvdev->notify_pa);\n+\t}\n+\n+\treturn vnic_dev_notify_unsetcmd(vdev);\n+}\n+\n+static int vnic_dev_notify_ready(struct vnic_dev *vdev)\n+{\n+\tu32 *words;\n+\tunsigned int nwords = vdev->notify_sz / 4;\n+\tunsigned int i;\n+\tu32 csum;\n+\n+\tif (!vdev->notify || !vdev->notify_sz)\n+\t\treturn 0;\n+\n+\tdo {\n+\t\tcsum = 0;\n+\t\trte_memcpy(&vdev->notify_copy, vdev->notify, vdev->notify_sz);\n+\t\twords = (u32 *)&vdev->notify_copy;\n+\t\tfor (i = 1; i < nwords; i++)\n+\t\t\tcsum += words[i];\n+\t} while (csum != words[0]);\n+\n+\treturn 1;\n+}\n+\n+int vnic_dev_init(struct vnic_dev *vdev, int arg)\n+{\n+\tu64 a0 = (u32)arg, a1 = 0;\n+\tint wait = 1000;\n+\tint r = 0;\n+\n+\tif (vnic_dev_capable(vdev, CMD_INIT))\n+\t\tr = vnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);\n+\telse {\n+\t\tvnic_dev_cmd(vdev, CMD_INIT_v1, &a0, &a1, wait);\n+\t\tif (a0 & CMD_INITF_DEFAULT_MAC) {\n+\t\t\t/* Emulate these for old CMD_INIT_v1 which\n+\t\t\t * didn't pass a0 so no CMD_INITF_*.\n+\t\t\t */\n+\t\t\tvnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);\n+\t\t\tvnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);\n+\t\t}\n+\t}\n+\treturn r;\n+}\n+\n+int vnic_dev_deinit(struct vnic_dev *vdev)\n+{\n+\tu64 a0 = 0, a1 = 0;\n+\tint wait = 1000;\n+\n+\treturn vnic_dev_cmd(vdev, CMD_DEINIT, &a0, &a1, wait);\n+}\n+\n+void vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev)\n+{\n+\t/* Default: hardware intr coal timer is in units of 1.5 usecs */\n+\tvdev->intr_coal_timer_info.mul = 2;\n+\tvdev->intr_coal_timer_info.div = 3;\n+\tvdev->intr_coal_timer_info.max_usec =\n+\t\tvnic_dev_intr_coal_timer_hw_to_usec(vdev, 0xffff);\n+}\n+\n+int vnic_dev_link_status(struct vnic_dev *vdev)\n+{\n+\tif (!vnic_dev_notify_ready(vdev))\n+\t\treturn 0;\n+\n+\treturn vdev->notify_copy.link_state;\n+}\n+\n+u32 vnic_dev_port_speed(struct vnic_dev *vdev)\n+{\n+\tif (!vnic_dev_notify_ready(vdev))\n+\t\treturn 0;\n+\n+\treturn vdev->notify_copy.port_speed;\n+}\n+\n+void vnic_dev_set_intr_mode(struct vnic_dev *vdev,\n+\tenum vnic_dev_intr_mode intr_mode)\n+{\n+\tvdev->intr_mode = intr_mode;\n+}\n+\n+enum vnic_dev_intr_mode vnic_dev_get_intr_mode(\n+\tstruct vnic_dev *vdev)\n+{\n+\treturn vdev->intr_mode;\n+}\n+\n+u32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec)\n+{\n+\treturn (usec * vdev->intr_coal_timer_info.mul) /\n+\t\tvdev->intr_coal_timer_info.div;\n+}\n+\n+u32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles)\n+{\n+\treturn (hw_cycles * vdev->intr_coal_timer_info.div) /\n+\t\tvdev->intr_coal_timer_info.mul;\n+}\n+\n+u32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev)\n+{\n+\treturn vdev->intr_coal_timer_info.max_usec;\n+}\n+\n+void vnic_dev_unregister(struct vnic_dev *vdev)\n+{\n+\tif (vdev) {\n+\t\tif (vdev->notify)\n+\t\t\tvdev->free_consistent(vdev->pdev,\n+\t\t\t\tsizeof(struct vnic_devcmd_notify),\n+\t\t\t\tvdev->notify,\n+\t\t\t\tvdev->notify_pa);\n+\t\tif (vdev->stats)\n+\t\t\tvdev->free_consistent(vdev->pdev,\n+\t\t\t\tsizeof(struct vnic_stats),\n+\t\t\t\tvdev->stats, vdev->stats_pa);\n+\t\tif (vdev->fw_info)\n+\t\t\tvdev->free_consistent(vdev->pdev,\n+\t\t\t\tsizeof(struct vnic_devcmd_fw_info),\n+\t\t\t\tvdev->fw_info, vdev->fw_info_pa);\n+\t\tkfree(vdev);\n+\t}\n+}\n+\n+struct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,\n+\tvoid *priv, struct rte_pci_device *pdev, struct vnic_dev_bar *bar,\n+\tunsigned int num_bars)\n+{\n+\tif (!vdev) {\n+\t\tvdev = kzalloc(sizeof(struct vnic_dev), GFP_ATOMIC);\n+\t\tif (!vdev)\n+\t\t\treturn NULL;\n+\t}\n+\n+\tvdev->priv = priv;\n+\tvdev->pdev = pdev;\n+\n+\tif (vnic_dev_discover_res(vdev, bar, num_bars))\n+\t\tgoto err_out;\n+\n+\tvdev->devcmd = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD, 0);\n+\tif (!vdev->devcmd)\n+\t\tgoto err_out;\n+\n+\treturn vdev;\n+\n+err_out:\n+\tvnic_dev_unregister(vdev);\n+\treturn NULL;\n+}\n+\n+struct rte_pci_device *vnic_dev_get_pdev(struct vnic_dev *vdev)\n+{\n+\treturn vdev->pdev;\n+}\n+\n+static int vnic_dev_cmd_status(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n+\tint *status)\n+{\n+\tu64 a0 = cmd, a1 = 0;\n+\tint wait = 1000;\n+\tint ret;\n+\n+\tret = vnic_dev_cmd(vdev, CMD_STATUS, &a0, &a1, wait);\n+\tif (!ret)\n+\t\t*status = (int)a0;\n+\n+\treturn ret;\n+}\n+\n+int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tint i;\n+\n+\tfor (i = 0; i < ETH_ALEN; i++)\n+\t\t((u8 *)&a0)[i] = mac_addr[i];\n+\n+\treturn vnic_dev_cmd(vdev, CMD_SET_MAC_ADDR, &a0, &a1, wait);\n+}\n+\n+/*\n+ *  vnic_dev_classifier: Add/Delete classifier entries\n+ *  @vdev: vdev of the device\n+ *  @cmd: CLSF_ADD for Add filter\n+ *        CLSF_DEL for Delete filter\n+ *  @entry: In case of ADD filter, the caller passes the RQ number in this\n+ *          variable.\n+ *          This function stores the filter_id returned by the\n+ *          firmware in the same variable before return;\n+ *\n+ *          In case of DEL filter, the caller passes the RQ number. Return\n+ *          value is irrelevant.\n+ * @data: filter data\n+ */\n+int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,\n+\tstruct filter *data)\n+{\n+\tu64 a0, a1;\n+\tint wait = 1000;\n+\tdma_addr_t tlv_pa;\n+\tint ret = -EINVAL;\n+\tstruct filter_tlv *tlv, *tlv_va;\n+\tstruct filter_action *action;\n+\tu64 tlv_size;\n+\tstatic unsigned int unique_id;\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\n+\tif (cmd == CLSF_ADD) {\n+\t\ttlv_size = sizeof(struct filter) +\n+\t\t    sizeof(struct filter_action) +\n+\t\t    2*sizeof(struct filter_tlv);\n+\t\tsnprintf(z_name, sizeof(z_name), \"vnic_clsf_%d\", unique_id++);\n+\t\ttlv_va = vdev->alloc_consistent(vdev->priv,\n+\t\t\ttlv_size, &tlv_pa, z_name);\n+\t\tif (!tlv_va)\n+\t\t\treturn -ENOMEM;\n+\t\ttlv = tlv_va;\n+\t\ta0 = tlv_pa;\n+\t\ta1 = tlv_size;\n+\t\tmemset(tlv, 0, tlv_size);\n+\t\ttlv->type = CLSF_TLV_FILTER;\n+\t\ttlv->length = sizeof(struct filter);\n+\t\t*(struct filter *)&tlv->val = *data;\n+\n+\t\ttlv = (struct filter_tlv *)((char *)tlv +\n+\t\t\t\t\t sizeof(struct filter_tlv) +\n+\t\t\t\t\t sizeof(struct filter));\n+\n+\t\ttlv->type = CLSF_TLV_ACTION;\n+\t\ttlv->length = sizeof(struct filter_action);\n+\t\taction = (struct filter_action *)&tlv->val;\n+\t\taction->type = FILTER_ACTION_RQ_STEERING;\n+\t\taction->u.rq_idx = *entry;\n+\n+\t\tret = vnic_dev_cmd(vdev, CMD_ADD_FILTER, &a0, &a1, wait);\n+\t\t*entry = (u16)a0;\n+\t\tvdev->free_consistent(vdev->pdev, tlv_size, tlv_va, tlv_pa);\n+\t} else if (cmd == CLSF_DEL) {\n+\t\ta0 = *entry;\n+\t\tret = vnic_dev_cmd(vdev, CMD_DEL_FILTER, &a0, &a1, wait);\n+\t}\n+\n+\treturn ret;\n+}\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_dev.h b/lib/librte_pmd_enic/vnic/vnic_dev.h\nnew file mode 100644\nindex 0000000..407b902\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_dev.h\n@@ -0,0 +1,202 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_dev.h 196958 2014-11-04 18:23:37Z xuywang $\"\n+\n+#ifndef _VNIC_DEV_H_\n+#define _VNIC_DEV_H_\n+\n+#include \"enic_compat.h\"\n+#include \"rte_pci.h\"\n+#include \"vnic_resource.h\"\n+#include \"vnic_devcmd.h\"\n+\n+#ifndef VNIC_PADDR_TARGET\n+#define VNIC_PADDR_TARGET\t0x0000000000000000ULL\n+#endif\n+\n+#ifndef readq\n+static inline u64 readq(void __iomem *reg)\n+{\n+\treturn ((u64)readl(reg + 0x4UL) << 32) |\n+\t\t(u64)readl(reg);\n+}\n+\n+static inline void writeq(u64 val, void __iomem *reg)\n+{\n+\twritel(val & 0xffffffff, reg);\n+\twritel(val >> 32, reg + 0x4UL);\n+}\n+#endif\n+\n+#undef pr_fmt\n+#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n+\n+enum vnic_dev_intr_mode {\n+\tVNIC_DEV_INTR_MODE_UNKNOWN,\n+\tVNIC_DEV_INTR_MODE_INTX,\n+\tVNIC_DEV_INTR_MODE_MSI,\n+\tVNIC_DEV_INTR_MODE_MSIX,\n+};\n+\n+struct vnic_dev_bar {\n+\tvoid __iomem *vaddr;\n+\tdma_addr_t bus_addr;\n+\tunsigned long len;\n+};\n+\n+struct vnic_dev_ring {\n+\tvoid *descs;\n+\tsize_t size;\n+\tdma_addr_t base_addr;\n+\tsize_t base_align;\n+\tvoid *descs_unaligned;\n+\tsize_t size_unaligned;\n+\tdma_addr_t base_addr_unaligned;\n+\tunsigned int desc_size;\n+\tunsigned int desc_count;\n+\tunsigned int desc_avail;\n+};\n+\n+struct vnic_dev_iomap_info {\n+\tdma_addr_t bus_addr;\n+\tunsigned long len;\n+\tvoid __iomem *vaddr;\n+};\n+\n+struct vnic_dev;\n+struct vnic_stats;\n+\n+void *vnic_dev_priv(struct vnic_dev *vdev);\n+unsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,\n+\tenum vnic_res_type type);\n+void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,\n+\tunsigned int index);\n+dma_addr_t vnic_dev_get_res_bus_addr(struct vnic_dev *vdev,\n+\tenum vnic_res_type type, unsigned int index);\n+uint8_t vnic_dev_get_res_bar(struct vnic_dev *vdev,\n+\tenum vnic_res_type type);\n+uint32_t vnic_dev_get_res_offset(struct vnic_dev *vdev,\n+\tenum vnic_res_type type, unsigned int index);\n+unsigned long vnic_dev_get_res_type_len(struct vnic_dev *vdev,\n+\t\t\t\t\tenum vnic_res_type type);\n+unsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,\n+\tunsigned int desc_count, unsigned int desc_size);\n+void vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring);\n+int vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,\n+\tunsigned int desc_count, unsigned int desc_size, unsigned int socket_id, \n+        char *z_name);\n+void vnic_dev_free_desc_ring(struct vnic_dev *vdev,\n+\tstruct vnic_dev_ring *ring);\n+int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n+\tu64 *a0, u64 *a1, int wait);\n+int vnic_dev_cmd_args(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n+                               u64 *args, int nargs, int wait);\n+void vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index);\n+void vnic_dev_cmd_proxy_by_bdf_start(struct vnic_dev *vdev, u16 bdf);\n+void vnic_dev_cmd_proxy_end(struct vnic_dev *vdev);\n+int vnic_dev_fw_info(struct vnic_dev *vdev,\n+\tstruct vnic_devcmd_fw_info **fw_info);\n+int vnic_dev_asic_info(struct vnic_dev *vdev, u16 *asic_type, u16 *asic_rev);\n+int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,\n+\tvoid *value);\n+int vnic_dev_stats_clear(struct vnic_dev *vdev);\n+int vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats);\n+int vnic_dev_hang_notify(struct vnic_dev *vdev);\n+int vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,\n+\tint broadcast, int promisc, int allmulti);\n+int vnic_dev_packet_filter_all(struct vnic_dev *vdev, int directed,\n+\tint multicast, int broadcast, int promisc, int allmulti);\n+int vnic_dev_add_addr(struct vnic_dev *vdev, u8 *addr);\n+int vnic_dev_del_addr(struct vnic_dev *vdev, u8 *addr);\n+int vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr);\n+int vnic_dev_raise_intr(struct vnic_dev *vdev, u16 intr);\n+int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr);\n+int vnic_dev_notify_unset(struct vnic_dev *vdev);\n+int vnic_dev_notify_setcmd(struct vnic_dev *vdev,\n+\tvoid *notify_addr, dma_addr_t notify_pa, u16 intr);\n+int vnic_dev_notify_unsetcmd(struct vnic_dev *vdev);\n+int vnic_dev_link_status(struct vnic_dev *vdev);\n+u32 vnic_dev_port_speed(struct vnic_dev *vdev);\n+u32 vnic_dev_msg_lvl(struct vnic_dev *vdev);\n+u32 vnic_dev_mtu(struct vnic_dev *vdev);\n+u32 vnic_dev_link_down_cnt(struct vnic_dev *vdev);\n+u32 vnic_dev_notify_status(struct vnic_dev *vdev);\n+u32 vnic_dev_uif(struct vnic_dev *vdev);\n+int vnic_dev_close(struct vnic_dev *vdev);\n+int vnic_dev_enable(struct vnic_dev *vdev);\n+int vnic_dev_enable_wait(struct vnic_dev *vdev);\n+int vnic_dev_disable(struct vnic_dev *vdev);\n+int vnic_dev_open(struct vnic_dev *vdev, int arg);\n+int vnic_dev_open_done(struct vnic_dev *vdev, int *done);\n+int vnic_dev_init(struct vnic_dev *vdev, int arg);\n+int vnic_dev_init_done(struct vnic_dev *vdev, int *done, int *err);\n+int vnic_dev_init_prov(struct vnic_dev *vdev, u8 *buf, u32 len);\n+int vnic_dev_deinit(struct vnic_dev *vdev);\n+void vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev);\n+int vnic_dev_intr_coal_timer_info(struct vnic_dev *vdev);\n+int vnic_dev_soft_reset(struct vnic_dev *vdev, int arg);\n+int vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done);\n+int vnic_dev_hang_reset(struct vnic_dev *vdev, int arg);\n+int vnic_dev_hang_reset_done(struct vnic_dev *vdev, int *done);\n+void vnic_dev_set_intr_mode(struct vnic_dev *vdev,\n+\tenum vnic_dev_intr_mode intr_mode);\n+enum vnic_dev_intr_mode vnic_dev_get_intr_mode(struct vnic_dev *vdev);\n+u32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec);\n+u32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles);\n+u32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev);\n+void vnic_dev_unregister(struct vnic_dev *vdev);\n+int vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,\n+\tu8 ig_vlan_rewrite_mode);\n+struct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,\n+\tvoid *priv, struct rte_pci_device *pdev, struct vnic_dev_bar *bar,\n+\tunsigned int num_bars);\n+struct rte_pci_device *vnic_dev_get_pdev(struct vnic_dev *vdev);\n+int vnic_dev_cmd_init(struct vnic_dev *vdev, int fallback);\n+int vnic_dev_get_size(void);\n+int vnic_dev_int13(struct vnic_dev *vdev, u64 arg, u32 op);\n+int vnic_dev_perbi(struct vnic_dev *vdev, u64 arg, u32 op);\n+u32 vnic_dev_perbi_rebuild_cnt(struct vnic_dev *vdev);\n+int vnic_dev_init_prov2(struct vnic_dev *vdev, u8 *buf, u32 len);\n+int vnic_dev_enable2(struct vnic_dev *vdev, int active);\n+int vnic_dev_enable2_done(struct vnic_dev *vdev, int *status);\n+int vnic_dev_deinit_done(struct vnic_dev *vdev, int *status);\n+int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr);\n+int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry, struct filter *data);\n+#ifdef ENIC_VXLAN\n+int vnic_dev_overlay_offload_enable_disable(struct vnic_dev *vdev,\n+\tu8 overlay, u8 config);\n+int vnic_dev_overlay_offload_cfg(struct vnic_dev *vdev, u8 overlay,\n+\tu16 vxlan_udp_port_number);\n+#endif\n+#endif /* _VNIC_DEV_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_devcmd.h b/lib/librte_pmd_enic/vnic/vnic_devcmd.h\nnew file mode 100644\nindex 0000000..d5e3361\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_devcmd.h\n@@ -0,0 +1,774 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_devcmd.h 173135 2014-05-16 03:14:07Z sanpilla $\"\n+\n+#ifndef _VNIC_DEVCMD_H_\n+#define _VNIC_DEVCMD_H_\n+\n+#define _CMD_NBITS      14\n+#define _CMD_VTYPEBITS\t10\n+#define _CMD_FLAGSBITS  6\n+#define _CMD_DIRBITS\t2\n+\n+#define _CMD_NMASK      ((1 << _CMD_NBITS)-1)\n+#define _CMD_VTYPEMASK  ((1 << _CMD_VTYPEBITS)-1)\n+#define _CMD_FLAGSMASK  ((1 << _CMD_FLAGSBITS)-1)\n+#define _CMD_DIRMASK    ((1 << _CMD_DIRBITS)-1)\n+\n+#define _CMD_NSHIFT     0\n+#define _CMD_VTYPESHIFT (_CMD_NSHIFT+_CMD_NBITS)\n+#define _CMD_FLAGSSHIFT (_CMD_VTYPESHIFT+_CMD_VTYPEBITS)\n+#define _CMD_DIRSHIFT   (_CMD_FLAGSSHIFT+_CMD_FLAGSBITS)\n+\n+/*\n+ * Direction bits (from host perspective).\n+ */\n+#define _CMD_DIR_NONE   0U\n+#define _CMD_DIR_WRITE  1U\n+#define _CMD_DIR_READ   2U\n+#define _CMD_DIR_RW     (_CMD_DIR_WRITE | _CMD_DIR_READ)\n+\n+/*\n+ * Flag bits.\n+ */\n+#define _CMD_FLAGS_NONE 0U\n+#define _CMD_FLAGS_NOWAIT 1U\n+\n+/*\n+ * vNIC type bits.\n+ */\n+#define _CMD_VTYPE_NONE  0U\n+#define _CMD_VTYPE_ENET  1U\n+#define _CMD_VTYPE_FC    2U\n+#define _CMD_VTYPE_SCSI  4U\n+#define _CMD_VTYPE_ALL   (_CMD_VTYPE_ENET | _CMD_VTYPE_FC | _CMD_VTYPE_SCSI)\n+\n+/*\n+ * Used to create cmds..\n+ */\n+#define _CMDCF(dir, flags, vtype, nr)  \\\n+\t(((dir)   << _CMD_DIRSHIFT) | \\\n+\t((flags) << _CMD_FLAGSSHIFT) | \\\n+\t((vtype) << _CMD_VTYPESHIFT) | \\\n+\t((nr)    << _CMD_NSHIFT))\n+#define _CMDC(dir, vtype, nr)    _CMDCF(dir, 0, vtype, nr)\n+#define _CMDCNW(dir, vtype, nr)  _CMDCF(dir, _CMD_FLAGS_NOWAIT, vtype, nr)\n+\n+/*\n+ * Used to decode cmds..\n+ */\n+#define _CMD_DIR(cmd)            (((cmd) >> _CMD_DIRSHIFT) & _CMD_DIRMASK)\n+#define _CMD_FLAGS(cmd)          (((cmd) >> _CMD_FLAGSSHIFT) & _CMD_FLAGSMASK)\n+#define _CMD_VTYPE(cmd)          (((cmd) >> _CMD_VTYPESHIFT) & _CMD_VTYPEMASK)\n+#define _CMD_N(cmd)              (((cmd) >> _CMD_NSHIFT) & _CMD_NMASK)\n+\n+enum vnic_devcmd_cmd {\n+\tCMD_NONE                = _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_NONE, 0),\n+\n+\t/*\n+\t * mcpu fw info in mem:\n+\t * in:\n+\t *   (u64)a0=paddr to struct vnic_devcmd_fw_info\n+\t * action:\n+\t *   Fills in struct vnic_devcmd_fw_info (128 bytes)\n+\t * note:\n+\t *   An old definition of CMD_MCPU_FW_INFO\n+\t */\n+\tCMD_MCPU_FW_INFO_OLD    = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 1),\n+\n+\t/*\n+\t * mcpu fw info in mem:\n+\t * in:\n+\t *   (u64)a0=paddr to struct vnic_devcmd_fw_info\n+\t *   (u16)a1=size of the structure\n+\t * out:\n+\t *\t (u16)a1=0                          for in:a1 = 0,\n+\t *\t         data size actually written for other values.\n+\t * action:\n+\t *   Fills in first 128 bytes of vnic_devcmd_fw_info for in:a1 = 0,\n+\t *            first in:a1 bytes               for 0 < in:a1 <= 132,\n+\t *            132 bytes                       for other values of in:a1.\n+\t * note:\n+\t *   CMD_MCPU_FW_INFO and CMD_MCPU_FW_INFO_OLD have the same enum 1\n+\t *   for source compatibility.\n+\t */\n+\tCMD_MCPU_FW_INFO        = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 1),\n+\n+\t/* dev-specific block member:\n+\t *    in: (u16)a0=offset,(u8)a1=size\n+\t *    out: a0=value */\n+\tCMD_DEV_SPEC            = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 2),\n+\n+\t/* stats clear */\n+\tCMD_STATS_CLEAR         = _CMDCNW(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 3),\n+\n+\t/* stats dump in mem: (u64)a0=paddr to stats area,\n+\t *                    (u16)a1=sizeof stats area */\n+\tCMD_STATS_DUMP          = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 4),\n+\n+\t/* set Rx packet filter: (u32)a0=filters (see CMD_PFILTER_*) */\n+\tCMD_PACKET_FILTER\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 7),\n+\n+\t/* set Rx packet filter for all: (u32)a0=filters (see CMD_PFILTER_*) */\n+\tCMD_PACKET_FILTER_ALL   = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 7),\n+\n+\t/* hang detection notification */\n+\tCMD_HANG_NOTIFY         = _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 8),\n+\n+\t/* MAC address in (u48)a0 */\n+\tCMD_GET_MAC_ADDR\t= _CMDC(_CMD_DIR_READ,\n+\t\t\t\t\t_CMD_VTYPE_ENET | _CMD_VTYPE_FC, 9),\n+\n+\t/* add addr from (u48)a0 */\n+\tCMD_ADDR_ADD            = _CMDCNW(_CMD_DIR_WRITE,\n+\t\t\t\t\t_CMD_VTYPE_ENET | _CMD_VTYPE_FC, 12),\n+\n+\t/* del addr from (u48)a0 */\n+\tCMD_ADDR_DEL            = _CMDCNW(_CMD_DIR_WRITE,\n+\t\t\t\t\t_CMD_VTYPE_ENET | _CMD_VTYPE_FC, 13),\n+\n+\t/* add VLAN id in (u16)a0 */\n+\tCMD_VLAN_ADD            = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 14),\n+\n+\t/* del VLAN id in (u16)a0 */\n+\tCMD_VLAN_DEL            = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 15),\n+\n+\t/* nic_cfg in (u32)a0 */\n+\tCMD_NIC_CFG             = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 16),\n+\n+\t/* union vnic_rss_key in mem: (u64)a0=paddr, (u16)a1=len */\n+\tCMD_RSS_KEY             = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 17),\n+\n+\t/* union vnic_rss_cpu in mem: (u64)a0=paddr, (u16)a1=len */\n+\tCMD_RSS_CPU             = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 18),\n+\n+\t/* initiate softreset */\n+\tCMD_SOFT_RESET          = _CMDCNW(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 19),\n+\n+\t/* softreset status:\n+\t *    out: a0=0 reset complete, a0=1 reset in progress */\n+\tCMD_SOFT_RESET_STATUS   = _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 20),\n+\n+\t/* set struct vnic_devcmd_notify buffer in mem:\n+\t * in:\n+\t *   (u64)a0=paddr to notify (set paddr=0 to unset)\n+\t *   (u32)a1 & 0x00000000ffffffff=sizeof(struct vnic_devcmd_notify)\n+\t *   (u16)a1 & 0x0000ffff00000000=intr num (-1 for no intr)\n+\t * out:\n+\t *   (u32)a1 = effective size\n+\t */\n+\tCMD_NOTIFY              = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 21),\n+\n+\t/* UNDI API: (u64)a0=paddr to s_PXENV_UNDI_ struct,\n+\t *           (u8)a1=PXENV_UNDI_xxx */\n+\tCMD_UNDI                = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 22),\n+\n+\t/* initiate open sequence (u32)a0=flags (see CMD_OPENF_*) */\n+\tCMD_OPEN\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 23),\n+\n+\t/* open status:\n+\t *    out: a0=0 open complete, a0=1 open in progress */\n+\tCMD_OPEN_STATUS\t\t= _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 24),\n+\n+\t/* close vnic */\n+\tCMD_CLOSE\t\t= _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 25),\n+\n+\t/* initialize virtual link: (u32)a0=flags (see CMD_INITF_*) */\n+/***** Replaced by CMD_INIT *****/\n+\tCMD_INIT_v1\t\t= _CMDCNW(_CMD_DIR_READ, _CMD_VTYPE_ALL, 26),\n+\n+\t/* variant of CMD_INIT, with provisioning info\n+\t *     (u64)a0=paddr of vnic_devcmd_provinfo\n+\t *     (u32)a1=sizeof provision info */\n+\tCMD_INIT_PROV_INFO\t= _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 27),\n+\n+\t/* enable virtual link */\n+\tCMD_ENABLE\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 28),\n+\n+\t/* enable virtual link, waiting variant. */\n+\tCMD_ENABLE_WAIT\t\t= _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 28),\n+\n+\t/* disable virtual link */\n+\tCMD_DISABLE\t\t= _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 29),\n+\n+\t/* stats dump sum of all vnic stats on same uplink in mem:\n+\t *     (u64)a0=paddr\n+\t *     (u16)a1=sizeof stats area */\n+\tCMD_STATS_DUMP_ALL\t= _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 30),\n+\n+\t/* init status:\n+\t *    out: a0=0 init complete, a0=1 init in progress\n+\t *         if a0=0, a1=errno */\n+\tCMD_INIT_STATUS\t\t= _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 31),\n+\n+\t/* INT13 API: (u64)a0=paddr to vnic_int13_params struct\n+\t *            (u32)a1=INT13_CMD_xxx */\n+\tCMD_INT13               = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_FC, 32),\n+\n+\t/* logical uplink enable/disable: (u64)a0: 0/1=disable/enable */\n+\tCMD_LOGICAL_UPLINK      = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 33),\n+\n+\t/* undo initialize of virtual link */\n+\tCMD_DEINIT\t\t= _CMDCNW(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 34),\n+\n+\t/* initialize virtual link: (u32)a0=flags (see CMD_INITF_*) */\n+\tCMD_INIT\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 35),\n+\n+\t/* check fw capability of a cmd:\n+\t * in:  (u32)a0=cmd\n+\t * out: (u32)a0=errno, 0:valid cmd, a1=supported VNIC_STF_* bits */\n+\tCMD_CAPABILITY\t\t= _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 36),\n+\n+\t/* persistent binding info\n+\t * in:  (u64)a0=paddr of arg\n+\t *      (u32)a1=CMD_PERBI_XXX */\n+\tCMD_PERBI\t\t= _CMDC(_CMD_DIR_RW, _CMD_VTYPE_FC, 37),\n+\n+\t/* Interrupt Assert Register functionality\n+\t * in: (u16)a0=interrupt number to assert\n+\t */\n+\tCMD_IAR\t\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 38),\n+\n+\t/* initiate hangreset, like softreset after hang detected */\n+\tCMD_HANG_RESET\t\t= _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 39),\n+\n+\t/* hangreset status:\n+\t *    out: a0=0 reset complete, a0=1 reset in progress */\n+\tCMD_HANG_RESET_STATUS   = _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 40),\n+\n+\t/*\n+\t * Set hw ingress packet vlan rewrite mode:\n+\t * in:  (u32)a0=new vlan rewrite mode\n+\t * out: (u32)a0=old vlan rewrite mode */\n+\tCMD_IG_VLAN_REWRITE_MODE = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ENET, 41),\n+\n+\t/*\n+\t * in:  (u16)a0=bdf of target vnic\n+\t *      (u32)a1=cmd to proxy\n+\t *      a2-a15=args to cmd in a1\n+\t * out: (u32)a0=status of proxied cmd\n+\t *      a1-a15=out args of proxied cmd */\n+\tCMD_PROXY_BY_BDF =\t_CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 42),\n+\n+\t/*\n+\t * As for BY_BDF except a0 is index of hvnlink subordinate vnic\n+\t * or SR-IOV virtual vnic\n+\t */\n+\tCMD_PROXY_BY_INDEX =    _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 43),\n+\n+\t/*\n+\t * For HPP toggle:\n+\t * adapter-info-get\n+\t * in:  (u64)a0=phsical address of buffer passed in from caller.\n+\t *      (u16)a1=size of buffer specified in a0.\n+\t * out: (u64)a0=phsical address of buffer passed in from caller.\n+\t *      (u16)a1=actual bytes from VIF-CONFIG-INFO TLV, or\n+\t *              0 if no VIF-CONFIG-INFO TLV was ever received. */\n+\tCMD_CONFIG_INFO_GET = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 44),\n+\n+\t/*\n+\t * INT13 API: (u64)a0=paddr to vnic_int13_params struct\n+\t *            (u32)a1=INT13_CMD_xxx\n+\t */\n+\tCMD_INT13_ALL = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 45),\n+\n+\t/*\n+\t * Set default vlan:\n+\t * in: (u16)a0=new default vlan\n+\t *     (u16)a1=zero for overriding vlan with param a0,\n+\t *\t\t       non-zero for resetting vlan to the default\n+\t * out: (u16)a0=old default vlan\n+\t */\n+\tCMD_SET_DEFAULT_VLAN = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 46),\n+\n+\t/* init_prov_info2:\n+\t * Variant of CMD_INIT_PROV_INFO, where it will not try to enable\n+\t * the vnic until CMD_ENABLE2 is issued.\n+\t *     (u64)a0=paddr of vnic_devcmd_provinfo\n+\t *     (u32)a1=sizeof provision info */\n+\tCMD_INIT_PROV_INFO2  = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 47),\n+\n+\t/* enable2:\n+\t *      (u32)a0=0                  ==> standby\n+\t *             =CMD_ENABLE2_ACTIVE ==> active\n+\t */\n+\tCMD_ENABLE2 = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 48),\n+\n+\t/*\n+\t * cmd_status:\n+\t *     Returns the status of the specified command\n+\t * Input:\n+\t *     a0 = command for which status is being queried.\n+\t *          Possible values are:\n+\t *              CMD_SOFT_RESET\n+\t *              CMD_HANG_RESET\n+\t *              CMD_OPEN\n+\t *              CMD_INIT\n+\t *              CMD_INIT_PROV_INFO\n+\t *              CMD_DEINIT\n+\t *              CMD_INIT_PROV_INFO2\n+\t *              CMD_ENABLE2\n+\t * Output:\n+\t *     if status == STAT_ERROR\n+\t *        a0 = ERR_ENOTSUPPORTED - status for command in a0 is\n+\t *                                 not supported\n+\t *     if status == STAT_NONE\n+\t *        a0 = status of the devcmd specified in a0 as follows.\n+\t *             ERR_SUCCESS   - command in a0 completed successfully\n+\t *             ERR_EINPROGRESS - command in a0 is still in progress\n+\t */\n+\tCMD_STATUS = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 49),\n+\n+\t/*\n+\t * Returns interrupt coalescing timer conversion factors.\n+\t * After calling this devcmd, ENIC driver can convert\n+\t * interrupt coalescing timer in usec into CPU cycles as follows:\n+\t *\n+\t *   intr_timer_cycles = intr_timer_usec * multiplier / divisor\n+\t *\n+\t * Interrupt coalescing timer in usecs can be be converted/obtained\n+\t * from CPU cycles as follows:\n+\t *\n+\t *   intr_timer_usec = intr_timer_cycles * divisor / multiplier\n+\t *\n+\t * in: none\n+\t * out: (u32)a0 = multiplier\n+\t *      (u32)a1 = divisor\n+\t *      (u32)a2 = maximum timer value in usec\n+\t */\n+\tCMD_INTR_COAL_CONVERT = _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 50),\n+\n+\t/*\n+\t * ISCSI DUMP API:\n+\t * in: (u64)a0=paddr of the param or param itself\n+\t *     (u32)a1=ISCSI_CMD_xxx\n+\t */\n+\tCMD_ISCSI_DUMP_REQ = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 51),\n+\n+\t/*\n+\t * ISCSI DUMP STATUS API:\n+\t * in: (u32)a0=cmd tag\n+\t * in: (u32)a1=ISCSI_CMD_xxx\n+\t * out: (u32)a0=cmd status\n+\t */\n+\tCMD_ISCSI_DUMP_STATUS = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 52),\n+\n+\t/*\n+\t * Subvnic migration from MQ <--> VF.\n+\t * Enable the LIF migration from MQ to VF and vice versa. MQ and VF\n+\t * indexes are statically bound at the time of initialization.\n+\t * Based on the\n+\t * direction of migration, the resources of either MQ or the VF shall\n+\t * be attached to the LIF.\n+\t * in:        (u32)a0=Direction of Migration\n+\t *\t\t\t\t\t0=> Migrate to VF\n+\t *\t\t\t\t\t1=> Migrate to MQ\n+\t *            (u32)a1=VF index (MQ index)\n+\t */\n+\tCMD_MIGRATE_SUBVNIC = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 53),\n+\n+\n+\t/*\n+\t * Register / Deregister the notification block for MQ subvnics\n+\t * in:\n+\t *   (u64)a0=paddr to notify (set paddr=0 to unset)\n+\t *   (u32)a1 & 0x00000000ffffffff=sizeof(struct vnic_devcmd_notify)\n+\t *   (u16)a1 & 0x0000ffff00000000=intr num (-1 for no intr)\n+\t * out:\n+\t *   (u32)a1 = effective size\n+\t */\n+\tCMD_SUBVNIC_NOTIFY = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 54),\n+\n+\t/*\n+\t * Set the predefined mac address as default\n+\t * in:\n+\t *   (u48)a0=mac addr\n+\t */\n+\tCMD_SET_MAC_ADDR = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 55),\n+\n+\t/* Update the provisioning info of the given VIF\n+\t *     (u64)a0=paddr of vnic_devcmd_provinfo\n+\t *     (u32)a1=sizeof provision info */\n+\tCMD_PROV_INFO_UPDATE = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 56),\n+\n+\t/*\n+\t * Initialization for the devcmd2 interface.\n+\t * in: (u64) a0=host result buffer physical address\n+\t * in: (u16) a1=number of entries in result buffer\n+\t */\n+\tCMD_INITIALIZE_DEVCMD2 = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 57),\n+\n+\t/*\n+\t * Add a filter.\n+\t * in: (u64) a0= filter address\n+\t *     (u32) a1= size of filter\n+\t * out: (u32) a0=filter identifier\n+\t */\n+\tCMD_ADD_FILTER = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ENET, 58),\n+\n+\t/*\n+\t * Delete a filter.\n+\t * in: (u32) a0=filter identifier\n+\t */\n+\tCMD_DEL_FILTER = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 59),\n+\n+\t/*\n+\t * Enable a Queue Pair in User space NIC\n+\t * in: (u32) a0=Queue Pair number\n+\t *     (u32) a1= command\n+\t */\n+\tCMD_QP_ENABLE = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 60),\n+\n+\t/*\n+\t * Disable a Queue Pair in User space NIC\n+\t * in: (u32) a0=Queue Pair number\n+\t *     (u32) a1= command\n+\t */\n+\tCMD_QP_DISABLE = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 61),\n+\n+\t/*\n+\t * Stats dump Queue Pair in User space NIC\n+\t * in: (u32) a0=Queue Pair number\n+\t *     (u64) a1=host buffer addr for status dump\n+\t *     (u32) a2=length of the buffer\n+\t */\n+\tCMD_QP_STATS_DUMP = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 62),\n+\n+\t/*\n+\t * Clear stats for Queue Pair in User space NIC\n+\t * in: (u32) a0=Queue Pair number\n+\t */\n+\tCMD_QP_STATS_CLEAR = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 63),\n+\n+\t/*\n+\t * Enable/Disable overlay offloads on the given vnic\n+\t * in: (u8) a0 = OVERLAY_FEATURE_NVGRE : NVGRE\n+\t *          a0 = OVERLAY_FEATURE_VXLAN : VxLAN\n+\t * in: (u8) a1 = OVERLAY_OFFLOAD_ENABLE : Enable\n+\t *          a1 = OVERLAY_OFFLOAD_DISABLE : Disable\n+\t */\n+\tCMD_OVERLAY_OFFLOAD_ENABLE_DISABLE =\n+\t\t_CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 72),\n+\n+\t/*\n+\t * Configuration of overlay offloads feature on a given vNIC\n+\t * in: (u8) a0 = DEVCMD_OVERLAY_NVGRE : NVGRE\n+\t *          a0 = DEVCMD_OVERLAY_VXLAN : VxLAN\n+\t * in: (u8) a1 = VXLAN_PORT_UPDATE : VxLAN\n+\t * in: (u16) a2 = unsigned short int port information\n+\t */\n+\tCMD_OVERLAY_OFFLOAD_CFG = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 73),\n+};\n+\n+/* CMD_ENABLE2 flags */\n+#define CMD_ENABLE2_STANDBY 0x0\n+#define CMD_ENABLE2_ACTIVE  0x1\n+\n+/* flags for CMD_OPEN */\n+#define CMD_OPENF_OPROM\t\t0x1\t/* open coming from option rom */\n+\n+/* flags for CMD_INIT */\n+#define CMD_INITF_DEFAULT_MAC\t0x1\t/* init with default mac addr */\n+\n+/* flags for CMD_PACKET_FILTER */\n+#define CMD_PFILTER_DIRECTED\t\t0x01\n+#define CMD_PFILTER_MULTICAST\t\t0x02\n+#define CMD_PFILTER_BROADCAST\t\t0x04\n+#define CMD_PFILTER_PROMISCUOUS\t\t0x08\n+#define CMD_PFILTER_ALL_MULTICAST\t0x10\n+\n+/* Commands for CMD_QP_ENABLE/CM_QP_DISABLE */\n+#define CMD_QP_RQWQ                     0x0\n+\n+/* rewrite modes for CMD_IG_VLAN_REWRITE_MODE */\n+#define IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK              0\n+#define IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN         1\n+#define IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN  2\n+#define IG_VLAN_REWRITE_MODE_PASS_THRU                  3\n+\n+enum vnic_devcmd_status {\n+\tSTAT_NONE = 0,\n+\tSTAT_BUSY = 1 << 0,\t/* cmd in progress */\n+\tSTAT_ERROR = 1 << 1,\t/* last cmd caused error (code in a0) */\n+};\n+\n+enum vnic_devcmd_error {\n+\tERR_SUCCESS = 0,\n+\tERR_EINVAL = 1,\n+\tERR_EFAULT = 2,\n+\tERR_EPERM = 3,\n+\tERR_EBUSY = 4,\n+\tERR_ECMDUNKNOWN = 5,\n+\tERR_EBADSTATE = 6,\n+\tERR_ENOMEM = 7,\n+\tERR_ETIMEDOUT = 8,\n+\tERR_ELINKDOWN = 9,\n+\tERR_EMAXRES = 10,\n+\tERR_ENOTSUPPORTED = 11,\n+\tERR_EINPROGRESS = 12,\n+\tERR_MAX\n+};\n+\n+/*\n+ * note: hw_version and asic_rev refer to the same thing,\n+ *       but have different formats. hw_version is\n+ *       a 32-byte string (e.g. \"A2\") and asic_rev is\n+ *       a 16-bit integer (e.g. 0xA2).\n+ */\n+struct vnic_devcmd_fw_info {\n+\tchar fw_version[32];\n+\tchar fw_build[32];\n+\tchar hw_version[32];\n+\tchar hw_serial_number[32];\n+\tu16 asic_type;\n+\tu16 asic_rev;\n+};\n+\n+enum fwinfo_asic_type {\n+\tFWINFO_ASIC_TYPE_UNKNOWN,\n+\tFWINFO_ASIC_TYPE_PALO,\n+\tFWINFO_ASIC_TYPE_SERENO,\n+};\n+\n+\n+struct vnic_devcmd_notify {\n+\tu32 csum;\t\t/* checksum over following words */\n+\n+\tu32 link_state;\t\t/* link up == 1 */\n+\tu32 port_speed;\t\t/* effective port speed (rate limit) */\n+\tu32 mtu;\t\t/* MTU */\n+\tu32 msglvl;\t\t/* requested driver msg lvl */\n+\tu32 uif;\t\t/* uplink interface */\n+\tu32 status;\t\t/* status bits (see VNIC_STF_*) */\n+\tu32 error;\t\t/* error code (see ERR_*) for first ERR */\n+\tu32 link_down_cnt;\t/* running count of link down transitions */\n+\tu32 perbi_rebuild_cnt;\t/* running count of perbi rebuilds */\n+};\n+#define VNIC_STF_FATAL_ERR\t0x0001\t/* fatal fw error */\n+#define VNIC_STF_STD_PAUSE\t0x0002\t/* standard link-level pause on */\n+#define VNIC_STF_PFC_PAUSE\t0x0004\t/* priority flow control pause on */\n+/* all supported status flags */\n+#define VNIC_STF_ALL\t\t(VNIC_STF_FATAL_ERR |\\\n+\t\t\t\t VNIC_STF_STD_PAUSE |\\\n+\t\t\t\t VNIC_STF_PFC_PAUSE |\\\n+\t\t\t\t 0)\n+\n+struct vnic_devcmd_provinfo {\n+\tu8 oui[3];\n+\tu8 type;\n+\tu8 data[0];\n+};\n+\n+/*\n+ * These are used in flags field of different filters to denote\n+ * valid fields used.\n+ */\n+#define FILTER_FIELD_VALID(fld) (1 << (fld - 1))\n+\n+#define FILTER_FIELDS_USNIC (FILTER_FIELD_VALID(1) | \\\n+\t\t\t     FILTER_FIELD_VALID(2) | \\\n+\t\t\t     FILTER_FIELD_VALID(3) | \\\n+\t\t\t     FILTER_FIELD_VALID(4))\n+\n+#define FILTER_FIELDS_IPV4_5TUPLE (FILTER_FIELD_VALID(1) | \\\n+\t\t\t\t   FILTER_FIELD_VALID(2) | \\\n+\t\t\t\t   FILTER_FIELD_VALID(3) | \\\n+\t\t\t\t   FILTER_FIELD_VALID(4) | \\\n+\t\t\t\t   FILTER_FIELD_VALID(5))\n+\n+#define FILTER_FIELDS_MAC_VLAN (FILTER_FIELD_VALID(1) | \\\n+\t\t\t\tFILTER_FIELD_VALID(2))\n+\n+#define FILTER_FIELD_USNIC_VLAN    FILTER_FIELD_VALID(1)\n+#define FILTER_FIELD_USNIC_ETHTYPE FILTER_FIELD_VALID(2)\n+#define FILTER_FIELD_USNIC_PROTO   FILTER_FIELD_VALID(3)\n+#define FILTER_FIELD_USNIC_ID      FILTER_FIELD_VALID(4)\n+\n+struct filter_usnic_id {\n+\tu32 flags;\n+\tu16 vlan;\n+\tu16 ethtype;\n+\tu8 proto_version;\n+\tu32 usnic_id;\n+} __attribute__((packed));\n+\n+#define FILTER_FIELD_5TUP_PROTO  FILTER_FIELD_VALID(1)\n+#define FILTER_FIELD_5TUP_SRC_AD FILTER_FIELD_VALID(2)\n+#define FILTER_FIELD_5TUP_DST_AD FILTER_FIELD_VALID(3)\n+#define FILTER_FIELD_5TUP_SRC_PT FILTER_FIELD_VALID(4)\n+#define FILTER_FIELD_5TUP_DST_PT FILTER_FIELD_VALID(5)\n+\n+/* Enums for the protocol field. */\n+enum protocol_e {\n+\tPROTO_UDP = 0,\n+\tPROTO_TCP = 1,\n+};\n+\n+struct filter_ipv4_5tuple {\n+\tu32 flags;\n+\tu32 protocol;\n+\tu32 src_addr;\n+\tu32 dst_addr;\n+\tu16 src_port;\n+\tu16 dst_port;\n+} __attribute__((packed));\n+\n+#define FILTER_FIELD_VMQ_VLAN   FILTER_FIELD_VALID(1)\n+#define FILTER_FIELD_VMQ_MAC    FILTER_FIELD_VALID(2)\n+\n+struct filter_mac_vlan {\n+\tu32 flags;\n+\tu16 vlan;\n+\tu8 mac_addr[6];\n+} __attribute__((packed));\n+\n+/* Specifies the filter_action type. */\n+enum {\n+\tFILTER_ACTION_RQ_STEERING = 0,\n+\tFILTER_ACTION_MAX\n+};\n+\n+struct filter_action {\n+\tu32 type;\n+\tunion {\n+\t\tu32 rq_idx;\n+\t} u;\n+} __attribute__((packed));\n+\n+/* Specifies the filter type. */\n+enum filter_type {\n+\tFILTER_USNIC_ID = 0,\n+\tFILTER_IPV4_5TUPLE = 1,\n+\tFILTER_MAC_VLAN = 2,\n+\tFILTER_MAX\n+};\n+\n+struct filter {\n+\tu32 type;\n+\tunion {\n+\t\tstruct filter_usnic_id usnic;\n+\t\tstruct filter_ipv4_5tuple ipv4;\n+\t\tstruct filter_mac_vlan mac_vlan;\n+\t} u;\n+} __attribute__((packed));\n+\n+enum {\n+\tCLSF_TLV_FILTER = 0,\n+\tCLSF_TLV_ACTION = 1,\n+};\n+\n+#define FILTER_MAX_BUF_SIZE 100  /* Maximum size of buffer to CMD_ADD_FILTER */\n+\n+struct filter_tlv {\n+\tu_int32_t type;\n+\tu_int32_t length;\n+\tu_int32_t val[0];\n+};\n+\n+enum {\n+\tCLSF_ADD = 0,\n+\tCLSF_DEL = 1,\n+};\t\n+\n+/*\n+ * Writing cmd register causes STAT_BUSY to get set in status register.\n+ * When cmd completes, STAT_BUSY will be cleared.\n+ *\n+ * If cmd completed successfully STAT_ERROR will be clear\n+ * and args registers contain cmd-specific results.\n+ *\n+ * If cmd error, STAT_ERROR will be set and args[0] contains error code.\n+ *\n+ * status register is read-only.  While STAT_BUSY is set,\n+ * all other register contents are read-only.\n+ */\n+\n+/* Make sizeof(vnic_devcmd) a power-of-2 for I/O BAR. */\n+#define VNIC_DEVCMD_NARGS 15\n+struct vnic_devcmd {\n+\tu32 status;\t\t\t/* RO */\n+\tu32 cmd;\t\t\t/* RW */\n+\tu64 args[VNIC_DEVCMD_NARGS];\t/* RW cmd args (little-endian) */\n+};\n+\n+/*\n+ * Version 2 of the interface.\n+ *\n+ * Some things are carried over, notably the vnic_devcmd_cmd enum.\n+ */\n+\n+/*\n+ * Flags for vnic_devcmd2.flags\n+ */\n+\n+#define DEVCMD2_FNORESULT       0x1     /* Don't copy result to host */\n+\n+#define VNIC_DEVCMD2_NARGS      VNIC_DEVCMD_NARGS\n+struct vnic_devcmd2 {\n+\tu16 pad;\n+\tu16 flags;\n+\tu32 cmd;                /* same command #defines as original */\n+\tu64 args[VNIC_DEVCMD2_NARGS];\n+};\n+\n+#define VNIC_DEVCMD2_NRESULTS   VNIC_DEVCMD_NARGS\n+struct devcmd2_result {\n+\tu64 results[VNIC_DEVCMD2_NRESULTS];\n+\tu32 pad;\n+\tu16 completed_index;    /* into copy WQ */\n+\tu8  error;              /* same error codes as original */\n+\tu8  color;              /* 0 or 1 as with completion queues */\n+};\n+\n+#define DEVCMD2_RING_SIZE   32\n+#define DEVCMD2_DESC_SIZE   128\n+\n+#define DEVCMD2_RESULTS_SIZE_MAX   ((1 << 16) - 1)\n+\n+// Overlay related definitions\n+\n+/*\n+ * This enum lists the flag associated with each of the overlay features\n+ */\n+typedef enum {\n+\tOVERLAY_FEATURE_NVGRE = 1,\n+\tOVERLAY_FEATURE_VXLAN,\n+\tOVERLAY_FEATURE_MAX,\n+} overlay_feature_t;\n+\n+#define OVERLAY_OFFLOAD_ENABLE 0\n+#define OVERLAY_OFFLOAD_DISABLE 1\n+\n+#define OVERLAY_CFG_VXLAN_PORT_UPDATE 0\n+#endif /* _VNIC_DEVCMD_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_enet.h b/lib/librte_pmd_enic/vnic/vnic_enet.h\nnew file mode 100644\nindex 0000000..58ecdc9\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_enet.h\n@@ -0,0 +1,78 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_enet.h 175806 2014-06-04 19:31:17Z rfaucett $\"\n+\n+#ifndef _VNIC_ENIC_H_\n+#define _VNIC_ENIC_H_\n+\n+/* Device-specific region: enet configuration */\n+struct vnic_enet_config {\n+\tu32 flags;\n+\tu32 wq_desc_count;\n+\tu32 rq_desc_count;\n+\tu16 mtu;\n+\tu16 intr_timer_deprecated;\n+\tu8 intr_timer_type;\n+\tu8 intr_mode;\n+\tchar devname[16];\n+\tu32 intr_timer_usec;\n+\tu16 loop_tag;\n+\tu16 vf_rq_count;\n+\tu16 num_arfs;\n+\tu64 mem_paddr;\n+};\n+\n+#define VENETF_TSO\t\t0x1\t/* TSO enabled */\n+#define VENETF_LRO\t\t0x2\t/* LRO enabled */\n+#define VENETF_RXCSUM\t\t0x4\t/* RX csum enabled */\n+#define VENETF_TXCSUM\t\t0x8\t/* TX csum enabled */\n+#define VENETF_RSS\t\t0x10\t/* RSS enabled */\n+#define VENETF_RSSHASH_IPV4\t0x20\t/* Hash on IPv4 fields */\n+#define VENETF_RSSHASH_TCPIPV4\t0x40\t/* Hash on TCP + IPv4 fields */\n+#define VENETF_RSSHASH_IPV6\t0x80\t/* Hash on IPv6 fields */\n+#define VENETF_RSSHASH_TCPIPV6\t0x100\t/* Hash on TCP + IPv6 fields */\n+#define VENETF_RSSHASH_IPV6_EX\t0x200\t/* Hash on IPv6 extended fields */\n+#define VENETF_RSSHASH_TCPIPV6_EX 0x400\t/* Hash on TCP + IPv6 ext. fields */\n+#define VENETF_LOOP\t\t0x800\t/* Loopback enabled */\n+#define VENETF_VMQ\t\t0x4000  /* using VMQ flag for VMware NETQ */\n+#define VENETF_VXLAN    0x10000 /* VxLAN offload */\n+#define VENETF_NVGRE    0x20000 /* NVGRE offload */\n+#define VENET_INTR_TYPE_MIN\t0\t/* Timer specs min interrupt spacing */\n+#define VENET_INTR_TYPE_IDLE\t1\t/* Timer specs idle time before irq */\n+\n+#define VENET_INTR_MODE_ANY\t0\t/* Try MSI-X, then MSI, then INTx */\n+#define VENET_INTR_MODE_MSI\t1\t/* Try MSI then INTx */\n+#define VENET_INTR_MODE_INTX\t2\t/* Try INTx only */\n+\n+#endif /* _VNIC_ENIC_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_intr.c b/lib/librte_pmd_enic/vnic/vnic_intr.c\nnew file mode 100644\nindex 0000000..f834163\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_intr.c\n@@ -0,0 +1,83 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_intr.c 171146 2014-05-02 07:08:20Z ssujith $\"\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_intr.h\"\n+\n+void vnic_intr_free(struct vnic_intr *intr)\n+{\n+\tintr->ctrl = NULL;\n+}\n+\n+int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,\n+\tunsigned int index)\n+{\n+\tintr->index = index;\n+\tintr->vdev = vdev;\n+\n+\tintr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index);\n+\tif (!intr->ctrl) {\n+\t\tpr_err(\"Failed to hook INTR[%d].ctrl resource\\n\", index);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer,\n+\tunsigned int coalescing_type, unsigned int mask_on_assertion)\n+{\n+\tvnic_intr_coalescing_timer_set(intr, coalescing_timer);\n+\tiowrite32(coalescing_type, &intr->ctrl->coalescing_type);\n+\tiowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion);\n+\tiowrite32(0, &intr->ctrl->int_credits);\n+}\n+\n+void vnic_intr_coalescing_timer_set(struct vnic_intr *intr,\n+\tu32 coalescing_timer)\n+{\n+\tiowrite32(vnic_dev_intr_coal_timer_usec_to_hw(intr->vdev,\n+\t\tcoalescing_timer), &intr->ctrl->coalescing_timer);\n+}\n+\n+void vnic_intr_clean(struct vnic_intr *intr)\n+{\n+\tiowrite32(0, &intr->ctrl->int_credits);\n+}\n+\n+void vnic_intr_raise(struct vnic_intr *intr)\n+{\n+\tvnic_dev_raise_intr(intr->vdev, (u16)intr->index);\n+}\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_intr.h b/lib/librte_pmd_enic/vnic/vnic_intr.h\nnew file mode 100644\nindex 0000000..ad9eb63\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_intr.h\n@@ -0,0 +1,126 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_intr.h 171146 2014-05-02 07:08:20Z ssujith $\"\n+\n+#ifndef _VNIC_INTR_H_\n+#define _VNIC_INTR_H_\n+\n+\n+#include \"vnic_dev.h\"\n+\n+#define VNIC_INTR_TIMER_TYPE_ABS\t0\n+#define VNIC_INTR_TIMER_TYPE_QUIET\t1\n+\n+/* Interrupt control */\n+struct vnic_intr_ctrl {\n+\tu32 coalescing_timer;\t\t/* 0x00 */\n+\tu32 pad0;\n+\tu32 coalescing_value;\t\t/* 0x08 */\n+\tu32 pad1;\n+\tu32 coalescing_type;\t\t/* 0x10 */\n+\tu32 pad2;\n+\tu32 mask_on_assertion;\t\t/* 0x18 */\n+\tu32 pad3;\n+\tu32 mask;\t\t\t/* 0x20 */\n+\tu32 pad4;\n+\tu32 int_credits;\t\t/* 0x28 */\n+\tu32 pad5;\n+\tu32 int_credit_return;\t\t/* 0x30 */\n+\tu32 pad6;\n+};\n+\n+struct vnic_intr {\n+\tunsigned int index;\n+\tstruct vnic_dev *vdev;\n+\tstruct vnic_intr_ctrl __iomem *ctrl;\t\t/* memory-mapped */\n+};\n+\n+static inline void vnic_intr_unmask(struct vnic_intr *intr)\n+{\n+\tiowrite32(0, &intr->ctrl->mask);\n+}\n+\n+static inline void vnic_intr_mask(struct vnic_intr *intr)\n+{\n+\tiowrite32(1, &intr->ctrl->mask);\n+}\n+\n+static inline int vnic_intr_masked(struct vnic_intr *intr)\n+{\n+\treturn ioread32(&intr->ctrl->mask);\n+}\n+\n+static inline void vnic_intr_return_credits(struct vnic_intr *intr,\n+\tunsigned int credits, int unmask, int reset_timer)\n+{\n+#define VNIC_INTR_UNMASK_SHIFT\t\t16\n+#define VNIC_INTR_RESET_TIMER_SHIFT\t17\n+\n+\tu32 int_credit_return = (credits & 0xffff) |\n+\t\t(unmask ? (1 << VNIC_INTR_UNMASK_SHIFT) : 0) |\n+\t\t(reset_timer ? (1 << VNIC_INTR_RESET_TIMER_SHIFT) : 0);\n+\n+\tiowrite32(int_credit_return, &intr->ctrl->int_credit_return);\n+}\n+\n+static inline unsigned int vnic_intr_credits(struct vnic_intr *intr)\n+{\n+\treturn ioread32(&intr->ctrl->int_credits);\n+}\n+\n+static inline void vnic_intr_return_all_credits(struct vnic_intr *intr)\n+{\n+\tunsigned int credits = vnic_intr_credits(intr);\n+\tint unmask = 1;\n+\tint reset_timer = 1;\n+\n+\tvnic_intr_return_credits(intr, credits, unmask, reset_timer);\n+}\n+\n+static inline u32 vnic_intr_legacy_pba(u32 __iomem *legacy_pba)\n+{\n+\t/* read PBA without clearing */\n+\treturn ioread32(legacy_pba);\n+}\n+\n+void vnic_intr_free(struct vnic_intr *intr);\n+int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,\n+\tunsigned int index);\n+void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer,\n+\tunsigned int coalescing_type, unsigned int mask_on_assertion);\n+void vnic_intr_coalescing_timer_set(struct vnic_intr *intr,\n+\tu32 coalescing_timer);\n+void vnic_intr_clean(struct vnic_intr *intr);\n+\n+#endif /* _VNIC_INTR_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_nic.h b/lib/librte_pmd_enic/vnic/vnic_nic.h\nnew file mode 100644\nindex 0000000..e268549\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_nic.h\n@@ -0,0 +1,88 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_nic.h 59839 2010-09-27 20:36:31Z roprabhu $\"\n+\n+#ifndef _VNIC_NIC_H_\n+#define _VNIC_NIC_H_\n+\n+#define NIC_CFG_RSS_DEFAULT_CPU_MASK_FIELD\t0xffUL\n+#define NIC_CFG_RSS_DEFAULT_CPU_SHIFT\t\t0\n+#define NIC_CFG_RSS_HASH_TYPE\t\t\t(0xffUL << 8)\n+#define NIC_CFG_RSS_HASH_TYPE_MASK_FIELD\t0xffUL\n+#define NIC_CFG_RSS_HASH_TYPE_SHIFT\t\t8\n+#define NIC_CFG_RSS_HASH_BITS\t\t\t(7UL << 16)\n+#define NIC_CFG_RSS_HASH_BITS_MASK_FIELD\t7UL\n+#define NIC_CFG_RSS_HASH_BITS_SHIFT\t\t16\n+#define NIC_CFG_RSS_BASE_CPU\t\t\t(7UL << 19)\n+#define NIC_CFG_RSS_BASE_CPU_MASK_FIELD\t\t7UL\n+#define NIC_CFG_RSS_BASE_CPU_SHIFT\t\t19\n+#define NIC_CFG_RSS_ENABLE\t\t\t(1UL << 22)\n+#define NIC_CFG_RSS_ENABLE_MASK_FIELD\t\t1UL\n+#define NIC_CFG_RSS_ENABLE_SHIFT\t\t22\n+#define NIC_CFG_TSO_IPID_SPLIT_EN\t\t(1UL << 23)\n+#define NIC_CFG_TSO_IPID_SPLIT_EN_MASK_FIELD\t1UL\n+#define NIC_CFG_TSO_IPID_SPLIT_EN_SHIFT\t\t23\n+#define NIC_CFG_IG_VLAN_STRIP_EN\t\t(1UL << 24)\n+#define NIC_CFG_IG_VLAN_STRIP_EN_MASK_FIELD\t1UL\n+#define NIC_CFG_IG_VLAN_STRIP_EN_SHIFT\t\t24\n+\n+#define NIC_CFG_RSS_HASH_TYPE_IPV4\t\t(1 << 1)\n+#define NIC_CFG_RSS_HASH_TYPE_TCP_IPV4\t\t(1 << 2)\n+#define NIC_CFG_RSS_HASH_TYPE_IPV6\t\t(1 << 3)\n+#define NIC_CFG_RSS_HASH_TYPE_TCP_IPV6\t\t(1 << 4)\n+#define NIC_CFG_RSS_HASH_TYPE_IPV6_EX\t\t(1 << 5)\n+#define NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX\t(1 << 6)\n+\n+static inline void vnic_set_nic_cfg(u32 *nic_cfg,\n+\tu8 rss_default_cpu, u8 rss_hash_type,\n+\tu8 rss_hash_bits, u8 rss_base_cpu,\n+\tu8 rss_enable, u8 tso_ipid_split_en,\n+\tu8 ig_vlan_strip_en)\n+{\n+\t*nic_cfg = (rss_default_cpu & NIC_CFG_RSS_DEFAULT_CPU_MASK_FIELD) |\n+\t\t((rss_hash_type & NIC_CFG_RSS_HASH_TYPE_MASK_FIELD)\n+\t\t\t<< NIC_CFG_RSS_HASH_TYPE_SHIFT) |\n+\t\t((rss_hash_bits & NIC_CFG_RSS_HASH_BITS_MASK_FIELD)\n+\t\t\t<< NIC_CFG_RSS_HASH_BITS_SHIFT) |\n+\t\t((rss_base_cpu & NIC_CFG_RSS_BASE_CPU_MASK_FIELD)\n+\t\t\t<< NIC_CFG_RSS_BASE_CPU_SHIFT) |\n+\t\t((rss_enable & NIC_CFG_RSS_ENABLE_MASK_FIELD)\n+\t\t\t<< NIC_CFG_RSS_ENABLE_SHIFT) |\n+\t\t((tso_ipid_split_en & NIC_CFG_TSO_IPID_SPLIT_EN_MASK_FIELD)\n+\t\t\t<< NIC_CFG_TSO_IPID_SPLIT_EN_SHIFT) |\n+\t\t((ig_vlan_strip_en & NIC_CFG_IG_VLAN_STRIP_EN_MASK_FIELD)\n+\t\t\t<< NIC_CFG_IG_VLAN_STRIP_EN_SHIFT);\n+}\n+\n+#endif /* _VNIC_NIC_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_resource.h b/lib/librte_pmd_enic/vnic/vnic_resource.h\nnew file mode 100644\nindex 0000000..9330eca\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_resource.h\n@@ -0,0 +1,97 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_resource.h 196958 2014-11-04 18:23:37Z xuywang $\"\n+\n+#ifndef _VNIC_RESOURCE_H_\n+#define _VNIC_RESOURCE_H_\n+\n+#define VNIC_RES_MAGIC\t\t0x766E6963L\t/* 'vnic' */\n+#define VNIC_RES_VERSION\t0x00000000L\n+#define MGMTVNIC_MAGIC\t\t0x544d474dL\t/* 'MGMT' */\n+#define MGMTVNIC_VERSION\t0x00000000L\n+\n+/* The MAC address assigned to the CFG vNIC is fixed. */\n+#define MGMTVNIC_MAC\t\t{ 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d }\n+\n+/* vNIC resource types */\n+enum vnic_res_type {\n+\tRES_TYPE_EOL,\t\t\t/* End-of-list */\n+\tRES_TYPE_WQ,\t\t\t/* Work queues */\n+\tRES_TYPE_RQ,\t\t\t/* Receive queues */\n+\tRES_TYPE_CQ,\t\t\t/* Completion queues */\n+\tRES_TYPE_MEM,\t\t\t/* Window to dev memory */\n+\tRES_TYPE_NIC_CFG,\t\t/* Enet NIC config registers */\n+\tRES_TYPE_RSS_KEY,\t\t/* Enet RSS secret key */\n+\tRES_TYPE_RSS_CPU,\t\t/* Enet RSS indirection table */\n+\tRES_TYPE_TX_STATS,\t\t/* Netblock Tx statistic regs */\n+\tRES_TYPE_RX_STATS,\t\t/* Netblock Rx statistic regs */\n+\tRES_TYPE_INTR_CTRL,\t\t/* Interrupt ctrl table */\n+\tRES_TYPE_INTR_TABLE,\t\t/* MSI/MSI-X Interrupt table */\n+\tRES_TYPE_INTR_PBA,\t\t/* MSI/MSI-X PBA table */\n+\tRES_TYPE_INTR_PBA_LEGACY,\t/* Legacy intr status */\n+\tRES_TYPE_DEBUG,\t\t\t/* Debug-only info */\n+\tRES_TYPE_DEV,\t\t\t/* Device-specific region */\n+\tRES_TYPE_DEVCMD,\t\t/* Device command region */\n+\tRES_TYPE_PASS_THRU_PAGE,\t/* Pass-thru page */\n+\tRES_TYPE_SUBVNIC,               /* subvnic resource type */\n+\tRES_TYPE_MQ_WQ,                 /* MQ Work queues */\n+\tRES_TYPE_MQ_RQ,                 /* MQ Receive queues */\n+\tRES_TYPE_MQ_CQ,                 /* MQ Completion queues */\n+\tRES_TYPE_DEPRECATED1,           /* Old version of devcmd 2 */\n+\tRES_TYPE_DEVCMD2,               /* Device control region */\n+\tRES_TYPE_MAX,\t\t\t/* Count of resource types */\n+};\n+\n+struct vnic_resource_header {\n+\tu32 magic;\n+\tu32 version;\n+};\n+\n+struct mgmt_barmap_hdr {\n+\tu32 magic;\t\t\t/* magic number */\n+\tu32 version;\t\t\t/* header format version */\n+\tu16 lif;\t\t\t/* loopback lif for mgmt frames */\n+\tu16 pci_slot;\t\t\t/* installed pci slot */\n+\tchar serial[16];\t\t/* card serial number */\n+};\n+\n+struct vnic_resource {\n+\tu8 type;\n+\tu8 bar;\n+\tu8 pad[2];\n+\tu32 bar_offset;\n+\tu32 count;\n+};\n+\n+#endif /* _VNIC_RESOURCE_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_rq.c b/lib/librte_pmd_enic/vnic/vnic_rq.c\nnew file mode 100644\nindex 0000000..a06969a\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_rq.c\n@@ -0,0 +1,246 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_rq.c 171146 2014-05-02 07:08:20Z ssujith $\"\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_rq.h\"\n+\n+static int vnic_rq_alloc_bufs(struct vnic_rq *rq)\n+{\n+\tstruct vnic_rq_buf *buf;\n+\tunsigned int i, j, count = rq->ring.desc_count;\n+\tunsigned int blks = VNIC_RQ_BUF_BLKS_NEEDED(count);\n+\n+\tfor (i = 0; i < blks; i++) {\n+\t\trq->bufs[i] = kzalloc(VNIC_RQ_BUF_BLK_SZ(count), GFP_ATOMIC);\n+\t\tif (!rq->bufs[i])\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tfor (i = 0; i < blks; i++) {\n+\t\tbuf = rq->bufs[i];\n+\t\tfor (j = 0; j < VNIC_RQ_BUF_BLK_ENTRIES(count); j++) {\n+\t\t\tbuf->index = i * VNIC_RQ_BUF_BLK_ENTRIES(count) + j;\n+\t\t\tbuf->desc = (u8 *)rq->ring.descs +\n+\t\t\t\trq->ring.desc_size * buf->index;\n+\t\t\tif (buf->index + 1 == count) {\n+\t\t\t\tbuf->next = rq->bufs[0];\n+\t\t\t\tbreak;\n+\t\t\t} else if (j + 1 == VNIC_RQ_BUF_BLK_ENTRIES(count)) {\n+\t\t\t\tbuf->next = rq->bufs[i + 1];\n+\t\t\t} else {\n+\t\t\t\tbuf->next = buf + 1;\n+\t\t\t\tbuf++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\trq->to_use = rq->to_clean = rq->bufs[0];\n+\n+\treturn 0;\n+}\n+\n+int vnic_rq_mem_size(struct vnic_rq *rq, unsigned int desc_count,\n+\tunsigned int desc_size)\n+{\n+\tint mem_size = 0;\n+\n+\tmem_size += vnic_dev_desc_ring_size(&rq->ring, desc_count, desc_size);\n+\n+\tmem_size += VNIC_RQ_BUF_BLKS_NEEDED(rq->ring.desc_count) *\n+\t\tVNIC_RQ_BUF_BLK_SZ(rq->ring.desc_count);\n+\n+\treturn mem_size;\n+}\n+\n+void vnic_rq_free(struct vnic_rq *rq)\n+{\n+\tstruct vnic_dev *vdev;\n+\tunsigned int i;\n+\n+\tvdev = rq->vdev;\n+\n+\tvnic_dev_free_desc_ring(vdev, &rq->ring);\n+\n+\tfor (i = 0; i < VNIC_RQ_BUF_BLKS_MAX; i++) {\n+\t\tif (rq->bufs[i]) {\n+\t\t\tkfree(rq->bufs[i]);\n+\t\t\trq->bufs[i] = NULL;\n+\t\t}\n+\t}\n+\n+\trq->ctrl = NULL;\n+}\n+\n+int vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,\n+\tunsigned int desc_count, unsigned int desc_size)\n+{\n+\tint err;\n+\tchar res_name[NAME_MAX];\n+        static int instance = 0;\n+\n+\trq->index = index;\n+\trq->vdev = vdev;\n+\n+\trq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_RQ, index);\n+\tif (!rq->ctrl) {\n+\t\tpr_err(\"Failed to hook RQ[%d] resource\\n\", index);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tvnic_rq_disable(rq);\n+\n+\tsnprintf(res_name, sizeof(res_name), \"%d-rq-%d\", instance++, index);\n+\terr = vnic_dev_alloc_desc_ring(vdev, &rq->ring, desc_count, desc_size,\n+          rq->socket_id, res_name);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = vnic_rq_alloc_bufs(rq);\n+\tif (err) {\n+\t\tvnic_rq_free(rq);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void vnic_rq_init_start(struct vnic_rq *rq, unsigned int cq_index,\n+\tunsigned int fetch_index, unsigned int posted_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset)\n+{\n+\tu64 paddr;\n+\tunsigned int count = rq->ring.desc_count;\n+\n+\tpaddr = (u64)rq->ring.base_addr | VNIC_PADDR_TARGET;\n+\twriteq(paddr, &rq->ctrl->ring_base);\n+\tiowrite32(count, &rq->ctrl->ring_size);\n+\tiowrite32(cq_index, &rq->ctrl->cq_index);\n+\tiowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable);\n+\tiowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset);\n+\tiowrite32(0, &rq->ctrl->dropped_packet_count);\n+\tiowrite32(0, &rq->ctrl->error_status);\n+\tiowrite32(fetch_index, &rq->ctrl->fetch_index);\n+\tiowrite32(posted_index, &rq->ctrl->posted_index);\n+\n+\trq->to_use = rq->to_clean =\n+\t\t&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]\n+\t\t\t[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];\n+}\n+\n+void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset)\n+{\n+\tu32 fetch_index = 0;\n+\t/* Use current fetch_index as the ring starting point */\n+\tfetch_index = ioread32(&rq->ctrl->fetch_index);\n+\n+\tif (fetch_index == 0xFFFFFFFF) { /* check for hardware gone  */\n+\t\t/* Hardware surprise removal: reset fetch_index */\n+\t\tfetch_index = 0;\n+\t}\n+\n+\tvnic_rq_init_start(rq, cq_index,\n+\t\tfetch_index, fetch_index,\n+\t\terror_interrupt_enable,\n+\t\terror_interrupt_offset);\n+}\n+\n+void vnic_rq_error_out(struct vnic_rq *rq, unsigned int error)\n+{\n+\tiowrite32(error, &rq->ctrl->error_status);\n+}\n+\n+unsigned int vnic_rq_error_status(struct vnic_rq *rq)\n+{\n+\treturn ioread32(&rq->ctrl->error_status);\n+}\n+\n+void vnic_rq_enable(struct vnic_rq *rq)\n+{\n+\tiowrite32(1, &rq->ctrl->enable);\n+}\n+\n+int vnic_rq_disable(struct vnic_rq *rq)\n+{\n+\tunsigned int wait;\n+\n+\tiowrite32(0, &rq->ctrl->enable);\n+\n+\t/* Wait for HW to ACK disable request */\n+\tfor (wait = 0; wait < 1000; wait++) {\n+\t\tif (!(ioread32(&rq->ctrl->running)))\n+\t\t\treturn 0;\n+\t\tudelay(10);\n+\t}\n+\n+\tpr_err(\"Failed to disable RQ[%d]\\n\", rq->index);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+void vnic_rq_clean(struct vnic_rq *rq,\n+\tvoid (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf))\n+{\n+\tstruct vnic_rq_buf *buf;\n+\tu32 fetch_index;\n+\tunsigned int count = rq->ring.desc_count;\n+\n+\tbuf = rq->to_clean;\n+\n+\twhile (vnic_rq_desc_used(rq) > 0) {\n+\n+\t\t(*buf_clean)(rq, buf);\n+\n+\t\tbuf = rq->to_clean = buf->next;\n+\t\trq->ring.desc_avail++;\n+\t}\n+\n+\t/* Use current fetch_index as the ring starting point */\n+\tfetch_index = ioread32(&rq->ctrl->fetch_index);\n+\n+\tif (fetch_index == 0xFFFFFFFF) { /* check for hardware gone  */\n+\t\t/* Hardware surprise removal: reset fetch_index */\n+\t\tfetch_index = 0;\n+\t}\n+\trq->to_use = rq->to_clean =\n+\t\t&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]\n+\t\t\t[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];\n+\tiowrite32(fetch_index, &rq->ctrl->posted_index);\n+\n+\tvnic_dev_clear_desc_ring(&rq->ring);\n+}\n+\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_rq.h b/lib/librte_pmd_enic/vnic/vnic_rq.h\nnew file mode 100644\nindex 0000000..4800a42\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_rq.h\n@@ -0,0 +1,282 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_rq.h 180262 2014-07-02 07:57:43Z gvaradar $\"\n+\n+#ifndef _VNIC_RQ_H_\n+#define _VNIC_RQ_H_\n+\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_cq.h\"\n+\n+/* Receive queue control */\n+struct vnic_rq_ctrl {\n+\tu64 ring_base;\t\t\t/* 0x00 */\n+\tu32 ring_size;\t\t\t/* 0x08 */\n+\tu32 pad0;\n+\tu32 posted_index;\t\t/* 0x10 */\n+\tu32 pad1;\n+\tu32 cq_index;\t\t\t/* 0x18 */\n+\tu32 pad2;\n+\tu32 enable;\t\t\t/* 0x20 */\n+\tu32 pad3;\n+\tu32 running;\t\t\t/* 0x28 */\n+\tu32 pad4;\n+\tu32 fetch_index;\t\t/* 0x30 */\n+\tu32 pad5;\n+\tu32 error_interrupt_enable;\t/* 0x38 */\n+\tu32 pad6;\n+\tu32 error_interrupt_offset;\t/* 0x40 */\n+\tu32 pad7;\n+\tu32 error_status;\t\t/* 0x48 */\n+\tu32 pad8;\n+\tu32 dropped_packet_count;\t/* 0x50 */\n+\tu32 pad9;\n+\tu32 dropped_packet_count_rc;\t/* 0x58 */\n+\tu32 pad10;\n+};\n+\n+/* Break the vnic_rq_buf allocations into blocks of 32/64 entries */\n+#define VNIC_RQ_BUF_MIN_BLK_ENTRIES 32\n+#define VNIC_RQ_BUF_DFLT_BLK_ENTRIES 64\n+#define VNIC_RQ_BUF_BLK_ENTRIES(entries) \\\n+\t((unsigned int)((entries < VNIC_RQ_BUF_DFLT_BLK_ENTRIES) ? \\\n+\tVNIC_RQ_BUF_MIN_BLK_ENTRIES : VNIC_RQ_BUF_DFLT_BLK_ENTRIES))\n+#define VNIC_RQ_BUF_BLK_SZ(entries) \\\n+\t(VNIC_RQ_BUF_BLK_ENTRIES(entries) * sizeof(struct vnic_rq_buf))\n+#define VNIC_RQ_BUF_BLKS_NEEDED(entries) \\\n+\tDIV_ROUND_UP(entries, VNIC_RQ_BUF_BLK_ENTRIES(entries))\n+#define VNIC_RQ_BUF_BLKS_MAX VNIC_RQ_BUF_BLKS_NEEDED(4096)\n+\n+struct vnic_rq_buf {\n+\tstruct vnic_rq_buf *next;\n+\tdma_addr_t dma_addr;\n+\tvoid *os_buf;\n+\tunsigned int os_buf_index;\n+\tunsigned int len;\n+\tunsigned int index;\n+\tvoid *desc;\n+\tuint64_t wr_id;\n+};\n+\n+struct vnic_rq {\n+\tunsigned int index;\n+\tstruct vnic_dev *vdev;\n+\tstruct vnic_rq_ctrl __iomem *ctrl;              /* memory-mapped */\n+\tstruct vnic_dev_ring ring;\n+\tstruct vnic_rq_buf *bufs[VNIC_RQ_BUF_BLKS_MAX];\n+\tstruct vnic_rq_buf *to_use;\n+\tstruct vnic_rq_buf *to_clean;\n+\tvoid *os_buf_head;\n+\tunsigned int pkts_outstanding;\n+\n+\tunsigned int socket_id;\n+        struct rte_mempool *mp;\n+};\n+\n+static inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq)\n+{\n+\t/* how many does SW own? */\n+\treturn rq->ring.desc_avail;\n+}\n+\n+static inline unsigned int vnic_rq_desc_used(struct vnic_rq *rq)\n+{\n+\t/* how many does HW own? */\n+\treturn rq->ring.desc_count - rq->ring.desc_avail - 1;\n+}\n+\n+static inline void *vnic_rq_next_desc(struct vnic_rq *rq)\n+{\n+\treturn rq->to_use->desc;\n+}\n+\n+static inline unsigned int vnic_rq_next_index(struct vnic_rq *rq)\n+{\n+\treturn rq->to_use->index;\n+}\n+\n+static inline void vnic_rq_post(struct vnic_rq *rq,\n+\tvoid *os_buf, unsigned int os_buf_index,\n+\tdma_addr_t dma_addr, unsigned int len,\n+\tuint64_t wrid)\n+{\n+\tstruct vnic_rq_buf *buf = rq->to_use;\n+\n+\tbuf->os_buf = os_buf;\n+\tbuf->os_buf_index = os_buf_index;\n+\tbuf->dma_addr = dma_addr;\n+\tbuf->len = len;\n+\tbuf->wr_id = wrid;\n+\n+\tbuf = buf->next;\n+\trq->to_use = buf;\n+\trq->ring.desc_avail--;\n+\n+\t/* Move the posted_index every nth descriptor\n+\t */\n+\n+#ifndef VNIC_RQ_RETURN_RATE\n+#define VNIC_RQ_RETURN_RATE\t\t0xf\t/* keep 2^n - 1 */\n+#endif\n+\n+\tif ((buf->index & VNIC_RQ_RETURN_RATE) == 0) {\n+\t\t/* Adding write memory barrier prevents compiler and/or CPU\n+\t\t * reordering, thus avoiding descriptor posting before\n+\t\t * descriptor is initialized. Otherwise, hardware can read\n+\t\t * stale descriptor fields.\n+\t\t */\n+\t\twmb();\n+\t\tiowrite32(buf->index, &rq->ctrl->posted_index);\n+\t}\n+}\n+\n+static inline void vnic_rq_post_commit(struct vnic_rq *rq,\n+\tvoid *os_buf, unsigned int os_buf_index,\n+\tdma_addr_t dma_addr, unsigned int len)\n+{\n+\tstruct vnic_rq_buf *buf = rq->to_use;\n+\n+\tbuf->os_buf = os_buf;\n+\tbuf->os_buf_index = os_buf_index;\n+\tbuf->dma_addr = dma_addr;\n+\tbuf->len = len;\n+\n+\tbuf = buf->next;\n+\trq->to_use = buf;\n+\trq->ring.desc_avail--;\n+\n+\t/* Move the posted_index every descriptor\n+\t */\n+\n+\t/* Adding write memory barrier prevents compiler and/or CPU\n+\t * reordering, thus avoiding descriptor posting before\n+\t * descriptor is initialized. Otherwise, hardware can read\n+\t * stale descriptor fields.\n+\t */\n+\twmb();\n+\tiowrite32(buf->index, &rq->ctrl->posted_index);\n+}\n+\n+static inline void vnic_rq_return_descs(struct vnic_rq *rq, unsigned int count)\n+{\n+\trq->ring.desc_avail += count;\n+}\n+\n+enum desc_return_options {\n+\tVNIC_RQ_RETURN_DESC,\n+\tVNIC_RQ_DEFER_RETURN_DESC,\n+};\n+\n+static inline int vnic_rq_service(struct vnic_rq *rq,\n+\tstruct cq_desc *cq_desc, u16 completed_index,\n+\tint desc_return, int (*buf_service)(struct vnic_rq *rq,\n+\tstruct cq_desc *cq_desc, struct vnic_rq_buf *buf,\n+\tint skipped, void *opaque), void *opaque)\n+{\n+\tstruct vnic_rq_buf *buf;\n+\tint skipped;\n+        int eop = 0;\n+\n+\tbuf = rq->to_clean;\n+\twhile (1) {\n+\n+\t\tskipped = (buf->index != completed_index);\n+\n+\t\tif((*buf_service)(rq, cq_desc, buf, skipped, opaque))\n+                    eop++;\n+\n+\t\tif (desc_return == VNIC_RQ_RETURN_DESC)\n+\t\t\trq->ring.desc_avail++;\n+\n+\t\trq->to_clean = buf->next;\n+\n+\t\tif (!skipped)\n+\t\t\tbreak;\n+\n+\t\tbuf = rq->to_clean;\n+\t}\n+        return eop;\n+}\n+\n+static inline int vnic_rq_fill(struct vnic_rq *rq,\n+\tint (*buf_fill)(struct vnic_rq *rq))\n+{\n+\tint err;\n+\n+\twhile (vnic_rq_desc_avail(rq) > 0) {\n+\n+\t\terr = (*buf_fill)(rq);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int vnic_rq_fill_count(struct vnic_rq *rq,\n+\tint (*buf_fill)(struct vnic_rq *rq), unsigned int count)\n+{\n+\tint err;\n+\n+\twhile ((vnic_rq_desc_avail(rq) > 0) && (count--)) {\n+\n+\t\terr = (*buf_fill)(rq);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void vnic_rq_free(struct vnic_rq *rq);\n+int vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,\n+\tunsigned int desc_count, unsigned int desc_size);\n+void vnic_rq_init_start(struct vnic_rq *rq, unsigned int cq_index,\n+\tunsigned int fetch_index, unsigned int posted_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset);\n+void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset);\n+void vnic_rq_error_out(struct vnic_rq *rq, unsigned int error);\n+unsigned int vnic_rq_error_status(struct vnic_rq *rq);\n+void vnic_rq_enable(struct vnic_rq *rq);\n+int vnic_rq_disable(struct vnic_rq *rq);\n+void vnic_rq_clean(struct vnic_rq *rq,\n+\tvoid (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf));\n+int vnic_rq_mem_size(struct vnic_rq *rq, unsigned int desc_count,\n+\tunsigned int desc_size);\n+\n+#endif /* _VNIC_RQ_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_rss.c b/lib/librte_pmd_enic/vnic/vnic_rss.c\nnew file mode 100644\nindex 0000000..6bf7009\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_rss.c\n@@ -0,0 +1,85 @@\n+/*\n+ * Copyright 2008 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id$\"\n+\n+#include \"enic_compat.h\"\n+#include \"vnic_rss.h\"\n+\n+void vnic_set_rss_key(union vnic_rss_key *rss_key, u8 *key)\n+{\n+\tu32 i;\n+\tu32 *p;\n+\tu16 *q;\n+\n+\tfor (i = 0; i < 4; ++i) {\n+\t\tp = (u32 *)(key + (10 * i));\n+\t\tiowrite32(*p++, &rss_key->key[i].b[0]);\n+\t\tiowrite32(*p++, &rss_key->key[i].b[4]);\n+\t\tq = (u16 *)p;\n+\t\tiowrite32(*q, &rss_key->key[i].b[8]);\n+\t}\n+}\n+\n+void vnic_set_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu)\n+{\n+\tu32 i;\n+\tu32 *p = (u32 *)cpu;\n+\n+\tfor (i = 0; i < 32; ++i)\n+\t\tiowrite32(*p++, &rss_cpu->cpu[i].b[0]);\n+}\n+\n+void vnic_get_rss_key(union vnic_rss_key *rss_key, u8 *key)\n+{\n+\tu32 i;\n+\tu32 *p;\n+\tu16 *q;\n+\n+\tfor (i = 0; i < 4; ++i) {\n+\t\tp = (u32 *)(key + (10 * i));\n+\t\t*p++ = ioread32(&rss_key->key[i].b[0]);\n+\t\t*p++ = ioread32(&rss_key->key[i].b[4]);\n+\t\tq = (u16 *)p;\n+\t\t*q = (u16)ioread32(&rss_key->key[i].b[8]);\n+\t}\n+}\n+\n+void vnic_get_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu)\n+{\n+\tu32 i;\n+\tu32 *p = (u32 *)cpu;\n+\n+\tfor (i = 0; i < 32; ++i)\n+\t\t*p++ = ioread32(&rss_cpu->cpu[i].b[0]);\n+}\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_rss.h b/lib/librte_pmd_enic/vnic/vnic_rss.h\nnew file mode 100644\nindex 0000000..39e57bb\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_rss.h\n@@ -0,0 +1,61 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ident \"$Id: vnic_rss.h 64224 2010-11-09 19:43:13Z vkolluri $\"\n+\n+#ifndef _VNIC_RSS_H_\n+#define _VNIC_RSS_H_\n+\n+/* RSS key array */\n+union vnic_rss_key {\n+\tstruct {\n+\t\tu8 b[10];\n+\t\tu8 b_pad[6];\n+\t} key[4];\n+\tu64 raw[8];\n+};\n+\n+/* RSS cpu array */\n+union vnic_rss_cpu {\n+\tstruct {\n+\t\tu8 b[4] ;\n+\t\tu8 b_pad[4];\n+\t} cpu[32];\n+\tu64 raw[32];\n+};\n+\n+void vnic_set_rss_key(union vnic_rss_key *rss_key, u8 *key);\n+void vnic_set_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu);\n+void vnic_get_rss_key(union vnic_rss_key *rss_key, u8 *key);\n+void vnic_get_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu);\n+\n+#endif /* _VNIC_RSS_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_stats.h b/lib/librte_pmd_enic/vnic/vnic_stats.h\nnew file mode 100644\nindex 0000000..fea1856\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_stats.h\n@@ -0,0 +1,86 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_stats.h 84040 2011-08-09 23:38:43Z dwang2 $\"\n+\n+#ifndef _VNIC_STATS_H_\n+#define _VNIC_STATS_H_\n+\n+/* Tx statistics */\n+struct vnic_tx_stats {\n+\tu64 tx_frames_ok;\n+\tu64 tx_unicast_frames_ok;\n+\tu64 tx_multicast_frames_ok;\n+\tu64 tx_broadcast_frames_ok;\n+\tu64 tx_bytes_ok;\n+\tu64 tx_unicast_bytes_ok;\n+\tu64 tx_multicast_bytes_ok;\n+\tu64 tx_broadcast_bytes_ok;\n+\tu64 tx_drops;\n+\tu64 tx_errors;\n+\tu64 tx_tso;\n+\tu64 rsvd[16];\n+};\n+\n+/* Rx statistics */\n+struct vnic_rx_stats {\n+\tu64 rx_frames_ok;\n+\tu64 rx_frames_total;\n+\tu64 rx_unicast_frames_ok;\n+\tu64 rx_multicast_frames_ok;\n+\tu64 rx_broadcast_frames_ok;\n+\tu64 rx_bytes_ok;\n+\tu64 rx_unicast_bytes_ok;\n+\tu64 rx_multicast_bytes_ok;\n+\tu64 rx_broadcast_bytes_ok;\n+\tu64 rx_drop;\n+\tu64 rx_no_bufs;\n+\tu64 rx_errors;\n+\tu64 rx_rss;\n+\tu64 rx_crc_errors;\n+\tu64 rx_frames_64;\n+\tu64 rx_frames_127;\n+\tu64 rx_frames_255;\n+\tu64 rx_frames_511;\n+\tu64 rx_frames_1023;\n+\tu64 rx_frames_1518;\n+\tu64 rx_frames_to_max;\n+\tu64 rsvd[16];\n+};\n+\n+struct vnic_stats {\n+\tstruct vnic_tx_stats tx;\n+\tstruct vnic_rx_stats rx;\n+};\n+\n+#endif /* _VNIC_STATS_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_wq.c b/lib/librte_pmd_enic/vnic/vnic_wq.c\nnew file mode 100644\nindex 0000000..7bdfcf6\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_wq.c\n@@ -0,0 +1,245 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_wq.c 183023 2014-07-22 23:47:25Z xuywang $\"\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_wq.h\"\n+\n+static inline\n+int vnic_wq_get_ctrl(struct vnic_dev *vdev, struct vnic_wq *wq,\n+\t\t\t\tunsigned int index, enum vnic_res_type res_type)\n+{\n+\twq->ctrl = vnic_dev_get_res(vdev, res_type, index);\n+\tif (!wq->ctrl)\n+\t\treturn -EINVAL;\n+\treturn 0;\n+}\n+\n+static inline\n+int vnic_wq_alloc_ring(struct vnic_dev *vdev, struct vnic_wq *wq,\n+\t\t\t\tunsigned int desc_count, unsigned int desc_size)\n+{\n+        char res_name[NAME_MAX];\n+        static int instance = 0;\n+\n+\tsnprintf(res_name, sizeof(res_name), \"%d-wq-%d\", instance++, wq->index);\n+\treturn vnic_dev_alloc_desc_ring(vdev, &wq->ring, desc_count, desc_size,\n+                wq->socket_id, res_name);\n+}\n+\n+static int vnic_wq_alloc_bufs(struct vnic_wq *wq)\n+{\n+\tstruct vnic_wq_buf *buf;\n+\tunsigned int i, j, count = wq->ring.desc_count;\n+\tunsigned int blks = VNIC_WQ_BUF_BLKS_NEEDED(count);\n+\n+\tfor (i = 0; i < blks; i++) {\n+\t\twq->bufs[i] = kzalloc(VNIC_WQ_BUF_BLK_SZ(count), GFP_ATOMIC);\n+\t\tif (!wq->bufs[i])\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tfor (i = 0; i < blks; i++) {\n+\t\tbuf = wq->bufs[i];\n+\t\tfor (j = 0; j < VNIC_WQ_BUF_BLK_ENTRIES(count); j++) {\n+\t\t\tbuf->index = i * VNIC_WQ_BUF_BLK_ENTRIES(count) + j;\n+\t\t\tbuf->desc = (u8 *)wq->ring.descs +\n+\t\t\t\twq->ring.desc_size * buf->index;\n+\t\t\tif (buf->index + 1 == count) {\n+\t\t\t\tbuf->next = wq->bufs[0];\n+\t\t\t\tbreak;\n+\t\t\t} else if (j + 1 == VNIC_WQ_BUF_BLK_ENTRIES(count)) {\n+\t\t\t\tbuf->next = wq->bufs[i + 1];\n+\t\t\t} else {\n+\t\t\t\tbuf->next = buf + 1;\n+\t\t\t\tbuf++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\twq->to_use = wq->to_clean = wq->bufs[0];\n+\n+\treturn 0;\n+}\n+\n+void vnic_wq_free(struct vnic_wq *wq)\n+{\n+\tstruct vnic_dev *vdev;\n+\tunsigned int i;\n+\n+\tvdev = wq->vdev;\n+\n+\tvnic_dev_free_desc_ring(vdev, &wq->ring);\n+\n+\tfor (i = 0; i < VNIC_WQ_BUF_BLKS_MAX; i++) {\n+\t\tif (wq->bufs[i]) {\n+\t\t\tkfree(wq->bufs[i]);\n+\t\t\twq->bufs[i] = NULL;\n+\t\t}\n+\t}\n+\n+\twq->ctrl = NULL;\n+}\n+\n+int vnic_wq_mem_size(struct vnic_wq *wq, unsigned int desc_count,\n+\tunsigned int desc_size)\n+{\n+\tint mem_size = 0;\n+\n+\tmem_size += vnic_dev_desc_ring_size(&wq->ring, desc_count, desc_size);\n+\n+\tmem_size += VNIC_WQ_BUF_BLKS_NEEDED(wq->ring.desc_count) *\n+\t\tVNIC_WQ_BUF_BLK_SZ(wq->ring.desc_count);\n+\n+\treturn mem_size;\n+}\n+\n+\n+int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,\n+\tunsigned int desc_count, unsigned int desc_size)\n+{\n+\tint err;\n+\n+\twq->index = index;\n+\twq->vdev = vdev;\n+\n+\terr = vnic_wq_get_ctrl(vdev, wq, index, RES_TYPE_WQ);\n+\tif (err) {\n+\t\tpr_err(\"Failed to hook WQ[%d] resource, err %d\\n\", index, err);\n+\t\treturn err;\n+\t}\n+\n+\tvnic_wq_disable(wq);\n+\n+\terr = vnic_wq_alloc_ring(vdev, wq, desc_count, desc_size);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = vnic_wq_alloc_bufs(wq);\n+\tif (err) {\n+\t\tvnic_wq_free(wq);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,\n+\tunsigned int fetch_index, unsigned int posted_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset)\n+{\n+\tu64 paddr;\n+\tunsigned int count = wq->ring.desc_count;\n+\n+\tpaddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET;\n+\twriteq(paddr, &wq->ctrl->ring_base);\n+\tiowrite32(count, &wq->ctrl->ring_size);\n+\tiowrite32(fetch_index, &wq->ctrl->fetch_index);\n+\tiowrite32(posted_index, &wq->ctrl->posted_index);\n+\tiowrite32(cq_index, &wq->ctrl->cq_index);\n+\tiowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable);\n+\tiowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset);\n+\tiowrite32(0, &wq->ctrl->error_status);\n+\n+\twq->to_use = wq->to_clean =\n+\t\t&wq->bufs[fetch_index / VNIC_WQ_BUF_BLK_ENTRIES(count)]\n+\t\t\t[fetch_index % VNIC_WQ_BUF_BLK_ENTRIES(count)];\n+}\n+\n+void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset)\n+{\n+\tvnic_wq_init_start(wq, cq_index, 0, 0,\n+\t\terror_interrupt_enable,\n+\t\terror_interrupt_offset);\n+}\n+\n+void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error)\n+{\n+\tiowrite32(error, &wq->ctrl->error_status);\n+}\n+\n+unsigned int vnic_wq_error_status(struct vnic_wq *wq)\n+{\n+\treturn ioread32(&wq->ctrl->error_status);\n+}\n+\n+void vnic_wq_enable(struct vnic_wq *wq)\n+{\n+\tiowrite32(1, &wq->ctrl->enable);\n+}\n+\n+int vnic_wq_disable(struct vnic_wq *wq)\n+{\n+\tunsigned int wait;\n+\n+\tiowrite32(0, &wq->ctrl->enable);\n+\n+\t/* Wait for HW to ACK disable request */\n+\tfor (wait = 0; wait < 1000; wait++) {\n+\t\tif (!(ioread32(&wq->ctrl->running)))\n+\t\t\treturn 0;\n+\t\tudelay(10);\n+\t}\n+\n+\tpr_err(\"Failed to disable WQ[%d]\\n\", wq->index);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+void vnic_wq_clean(struct vnic_wq *wq,\n+\tvoid (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf))\n+{\n+\tstruct vnic_wq_buf *buf;\n+\n+\tbuf = wq->to_clean;\n+\n+\twhile (vnic_wq_desc_used(wq) > 0) {\n+\n+\t\t(*buf_clean)(wq, buf);\n+\n+\t\tbuf = wq->to_clean = buf->next;\n+\t\twq->ring.desc_avail++;\n+\t}\n+\n+\twq->to_use = wq->to_clean = wq->bufs[0];\n+\n+\tiowrite32(0, &wq->ctrl->fetch_index);\n+\tiowrite32(0, &wq->ctrl->posted_index);\n+\tiowrite32(0, &wq->ctrl->error_status);\n+\n+\tvnic_dev_clear_desc_ring(&wq->ring);\n+}\ndiff --git a/lib/librte_pmd_enic/vnic/vnic_wq.h b/lib/librte_pmd_enic/vnic/vnic_wq.h\nnew file mode 100644\nindex 0000000..bb52cda\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/vnic_wq.h\n@@ -0,0 +1,283 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: vnic_wq.h 183023 2014-07-22 23:47:25Z xuywang $\"\n+\n+#ifndef _VNIC_WQ_H_\n+#define _VNIC_WQ_H_\n+\n+\n+#include \"vnic_dev.h\"\n+#include \"vnic_cq.h\"\n+\n+/* Work queue control */\n+struct vnic_wq_ctrl {\n+\tu64 ring_base;\t\t\t/* 0x00 */\n+\tu32 ring_size;\t\t\t/* 0x08 */\n+\tu32 pad0;\n+\tu32 posted_index;\t\t/* 0x10 */\n+\tu32 pad1;\n+\tu32 cq_index;\t\t\t/* 0x18 */\n+\tu32 pad2;\n+\tu32 enable;\t\t\t/* 0x20 */\n+\tu32 pad3;\n+\tu32 running;\t\t\t/* 0x28 */\n+\tu32 pad4;\n+\tu32 fetch_index;\t\t/* 0x30 */\n+\tu32 pad5;\n+\tu32 dca_value;\t\t\t/* 0x38 */\n+\tu32 pad6;\n+\tu32 error_interrupt_enable;\t/* 0x40 */\n+\tu32 pad7;\n+\tu32 error_interrupt_offset;\t/* 0x48 */\n+\tu32 pad8;\n+\tu32 error_status;\t\t/* 0x50 */\n+\tu32 pad9;\n+};\n+\n+struct vnic_wq_buf {\n+\tstruct vnic_wq_buf *next;\n+\tdma_addr_t dma_addr;\n+\tvoid *os_buf;\n+\tunsigned int len;\n+\tunsigned int index;\n+\tint sop;\n+\tvoid *desc;\n+\tuint64_t wr_id; /* Cookie */\n+\tuint8_t cq_entry; /* Gets completion event from hw */\n+\tuint8_t desc_skip_cnt; /* Num descs to occupy */\n+\tuint8_t compressed_send; /* Both hdr and payload in one desc */\n+};\n+\n+/* Break the vnic_wq_buf allocations into blocks of 32/64 entries */\n+#define VNIC_WQ_BUF_MIN_BLK_ENTRIES 32\n+#define VNIC_WQ_BUF_DFLT_BLK_ENTRIES 64\n+#define VNIC_WQ_BUF_BLK_ENTRIES(entries) \\\n+\t((unsigned int)((entries < VNIC_WQ_BUF_DFLT_BLK_ENTRIES) ? \\\n+\tVNIC_WQ_BUF_MIN_BLK_ENTRIES : VNIC_WQ_BUF_DFLT_BLK_ENTRIES))\n+#define VNIC_WQ_BUF_BLK_SZ(entries) \\\n+\t(VNIC_WQ_BUF_BLK_ENTRIES(entries) * sizeof(struct vnic_wq_buf))\n+#define VNIC_WQ_BUF_BLKS_NEEDED(entries) \\\n+\tDIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES(entries))\n+#define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)\n+\n+struct vnic_wq {\n+\tunsigned int index;\n+\tstruct vnic_dev *vdev;\n+\tstruct vnic_wq_ctrl __iomem *ctrl;              /* memory-mapped */\n+\tstruct vnic_dev_ring ring;\n+\tstruct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];\n+\tstruct vnic_wq_buf *to_use;\n+\tstruct vnic_wq_buf *to_clean;\n+\tunsigned int pkts_outstanding;\n+        unsigned int socket_id;\n+};\n+\n+static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)\n+{\n+\t/* how many does SW own? */\n+\treturn wq->ring.desc_avail;\n+}\n+\n+static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)\n+{\n+\t/* how many does HW own? */\n+\treturn wq->ring.desc_count - wq->ring.desc_avail - 1;\n+}\n+\n+static inline void *vnic_wq_next_desc(struct vnic_wq *wq)\n+{\n+\treturn wq->to_use->desc;\n+}\n+\n+#define PI_LOG2_CACHE_LINE_SIZE        5\n+#define PI_INDEX_BITS            12\n+#define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)\n+#define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)\n+#define PI_PREFETCH_LEN_OFF 16\n+#define PI_PREFETCH_ADDR_BITS 43\n+#define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)\n+#define PI_PREFETCH_ADDR_OFF 21\n+\n+/** How many cache lines are touched by buffer (addr, len). */\n+static inline unsigned int num_cache_lines_touched(dma_addr_t addr,\n+\t\t\t\t\t\t\tunsigned int len)\n+{\n+\tconst unsigned long mask = PI_PREFETCH_LEN_MASK;\n+\tconst unsigned long laddr = (unsigned long)addr;\n+\tunsigned long lines, equiv_len;\n+\t/* A. If addr is aligned, our solution is just to round up len to the\n+\tnext boundary.\n+\n+\te.g. addr = 0, len = 48\n+\t+--------------------+\n+\t|XXXXXXXXXXXXXXXXXXXX|    32-byte cacheline a\n+\t+--------------------+\n+\t|XXXXXXXXXX          |    cacheline b\n+\t+--------------------+\n+\n+\tB. If addr is not aligned, however, we may use an extra\n+\tcacheline.  e.g. addr = 12, len = 22\n+\n+\t+--------------------+\n+\t|       XXXXXXXXXXXXX|\n+\t+--------------------+\n+\t|XX                  |\n+\t+--------------------+\n+\n+\tOur solution is to make the problem equivalent to case A\n+\tabove by adding the empty space in the first cacheline to the length:\n+\tunsigned long len;\n+\n+\t+--------------------+\n+\t|eeeeeeeXXXXXXXXXXXXX|    \"e\" is empty space, which we add to len\n+\t+--------------------+\n+\t|XX                  |\n+\t+--------------------+\n+\n+\t*/\n+\tequiv_len = len + (laddr & mask);\n+\n+\t/* Now we can just round up this len to the next 32-byte boundary. */\n+\tlines = (equiv_len + mask) & (~mask);\n+\n+\t/* Scale bytes -> cachelines. */\n+\treturn lines >> PI_LOG2_CACHE_LINE_SIZE;\n+}\n+\n+static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,\n+\t\t\t\t\t\tunsigned int index)\n+{\n+\tunsigned int num_cache_lines = num_cache_lines_touched(addr, len);\n+\t/* Wish we could avoid a branch here.  We could have separate\n+\t * vnic_wq_post() and vinc_wq_post_inline(), the latter\n+\t * only supporting < 1k (2^5 * 2^5) sends, I suppose.  This would\n+\t * eliminate the if (eop) branch as well.\n+\t */\n+\tif (num_cache_lines > PI_PREFETCH_LEN_MASK)\n+\t\tnum_cache_lines = 0;\n+\treturn (index & PI_INDEX_MASK) |\n+\t((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |\n+\t\t(((addr >> PI_LOG2_CACHE_LINE_SIZE) &\n+\tPI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);\n+}\n+\n+static inline void vnic_wq_post(struct vnic_wq *wq,\n+\tvoid *os_buf, dma_addr_t dma_addr,\n+\tunsigned int len, int sop, int eop,\n+\tuint8_t desc_skip_cnt, uint8_t cq_entry,\n+\tuint8_t compressed_send, uint64_t wrid)\n+{\n+\tstruct vnic_wq_buf *buf = wq->to_use;\n+\n+\tbuf->sop = sop;\n+\tbuf->cq_entry = cq_entry;\n+\tbuf->compressed_send = compressed_send;\n+\tbuf->desc_skip_cnt = desc_skip_cnt;\n+\tbuf->os_buf = os_buf;\n+\tbuf->dma_addr = dma_addr;\n+\tbuf->len = len;\n+\tbuf->wr_id = wrid;\n+\n+\tbuf = buf->next;\n+\tif (eop) {\n+#ifdef DO_PREFETCH\n+\t\tuint64_t wr = vnic_cached_posted_index(dma_addr, len,\n+\t\t\t\t\t\t\tbuf->index);\n+#endif\n+\t\t/* Adding write memory barrier prevents compiler and/or CPU\n+\t\t * reordering, thus avoiding descriptor posting before\n+\t\t * descriptor is initialized. Otherwise, hardware can read\n+\t\t * stale descriptor fields.\n+\t\t */\n+\t\twmb();\n+#ifdef DO_PREFETCH\n+\t\t/* Intel chipsets seem to limit the rate of PIOs that we can\n+\t\t * push on the bus.  Thus, it is very important to do a single\n+\t\t * 64 bit write here.  With two 32-bit writes, my maximum\n+\t\t * pkt/sec rate was cut almost in half. -AJF\n+\t\t */\n+\t\tiowrite64((uint64_t)wr, &wq->ctrl->posted_index);\n+#else\n+\t\tiowrite32(buf->index, &wq->ctrl->posted_index);\n+#endif\n+\t}\n+\twq->to_use = buf;\n+\n+\twq->ring.desc_avail -= desc_skip_cnt;\n+}\n+\n+static inline void vnic_wq_service(struct vnic_wq *wq,\n+\tstruct cq_desc *cq_desc, u16 completed_index,\n+\tvoid (*buf_service)(struct vnic_wq *wq,\n+\tstruct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),\n+\tvoid *opaque)\n+{\n+\tstruct vnic_wq_buf *buf;\n+\n+\tbuf = wq->to_clean;\n+\twhile (1) {\n+\n+\t\t(*buf_service)(wq, cq_desc, buf, opaque);\n+\n+\t\twq->ring.desc_avail++;\n+\n+\t\twq->to_clean = buf->next;\n+\n+\t\tif (buf->index == completed_index)\n+\t\t\tbreak;\n+\n+\t\tbuf = wq->to_clean;\n+\t}\n+}\n+\n+void vnic_wq_free(struct vnic_wq *wq);\n+int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,\n+\tunsigned int desc_count, unsigned int desc_size);\n+void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,\n+\tunsigned int fetch_index, unsigned int posted_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset);\n+void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,\n+\tunsigned int error_interrupt_enable,\n+\tunsigned int error_interrupt_offset);\n+void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);\n+unsigned int vnic_wq_error_status(struct vnic_wq *wq);\n+void vnic_wq_enable(struct vnic_wq *wq);\n+int vnic_wq_disable(struct vnic_wq *wq);\n+void vnic_wq_clean(struct vnic_wq *wq,\n+\tvoid (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));\n+int vnic_wq_mem_size(struct vnic_wq *wq, unsigned int desc_count,\n+\tunsigned int desc_size);\n+\n+#endif /* _VNIC_WQ_H_ */\ndiff --git a/lib/librte_pmd_enic/vnic/wq_enet_desc.h b/lib/librte_pmd_enic/vnic/wq_enet_desc.h\nnew file mode 100644\nindex 0000000..1d8ceb8\n--- /dev/null\n+++ b/lib/librte_pmd_enic/vnic/wq_enet_desc.h\n@@ -0,0 +1,114 @@\n+/*\n+ * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.\n+ * Copyright 2007 Nuova Systems, Inc.  All rights reserved.\n+ *\n+ * Copyright (c) 2014, Cisco Systems, Inc. \n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ */\n+#ident \"$Id: wq_enet_desc.h 59839 2010-09-27 20:36:31Z roprabhu $\"\n+\n+#ifndef _WQ_ENET_DESC_H_\n+#define _WQ_ENET_DESC_H_\n+\n+/* Ethernet work queue descriptor: 16B */\n+struct wq_enet_desc {\n+\t__le64 address;\n+\t__le16 length;\n+\t__le16 mss_loopback;\n+\t__le16 header_length_flags;\n+\t__le16 vlan_tag;\n+};\n+\n+#define WQ_ENET_ADDR_BITS\t\t64\n+#define WQ_ENET_LEN_BITS\t\t14\n+#define WQ_ENET_LEN_MASK\t\t((1 << WQ_ENET_LEN_BITS) - 1)\n+#define WQ_ENET_MSS_BITS\t\t14\n+#define WQ_ENET_MSS_MASK\t\t((1 << WQ_ENET_MSS_BITS) - 1)\n+#define WQ_ENET_MSS_SHIFT\t\t2\n+#define WQ_ENET_LOOPBACK_SHIFT\t\t1\n+#define WQ_ENET_HDRLEN_BITS\t\t10\n+#define WQ_ENET_HDRLEN_MASK\t\t((1 << WQ_ENET_HDRLEN_BITS) - 1)\n+#define WQ_ENET_FLAGS_OM_BITS\t\t2\n+#define WQ_ENET_FLAGS_OM_MASK\t\t((1 << WQ_ENET_FLAGS_OM_BITS) - 1)\n+#define WQ_ENET_FLAGS_EOP_SHIFT\t\t12\n+#define WQ_ENET_FLAGS_CQ_ENTRY_SHIFT\t13\n+#define WQ_ENET_FLAGS_FCOE_ENCAP_SHIFT\t14\n+#define WQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT\t15\n+\n+#define WQ_ENET_OFFLOAD_MODE_CSUM\t0\n+#define WQ_ENET_OFFLOAD_MODE_RESERVED\t1\n+#define WQ_ENET_OFFLOAD_MODE_CSUM_L4\t2\n+#define WQ_ENET_OFFLOAD_MODE_TSO\t3\n+\n+static inline void wq_enet_desc_enc(struct wq_enet_desc *desc,\n+\tu64 address, u16 length, u16 mss, u16 header_length,\n+\tu8 offload_mode, u8 eop, u8 cq_entry, u8 fcoe_encap,\n+\tu8 vlan_tag_insert, u16 vlan_tag, u8 loopback)\n+{\n+\tdesc->address = cpu_to_le64(address);\n+\tdesc->length = cpu_to_le16(length & WQ_ENET_LEN_MASK);\n+\tdesc->mss_loopback = cpu_to_le16((mss & WQ_ENET_MSS_MASK) <<\n+\t\tWQ_ENET_MSS_SHIFT | (loopback & 1) << WQ_ENET_LOOPBACK_SHIFT);\n+\tdesc->header_length_flags = cpu_to_le16(\n+\t\t(header_length & WQ_ENET_HDRLEN_MASK) |\n+\t\t(offload_mode & WQ_ENET_FLAGS_OM_MASK) << WQ_ENET_HDRLEN_BITS |\n+\t\t(eop & 1) << WQ_ENET_FLAGS_EOP_SHIFT |\n+\t\t(cq_entry & 1) << WQ_ENET_FLAGS_CQ_ENTRY_SHIFT |\n+\t\t(fcoe_encap & 1) << WQ_ENET_FLAGS_FCOE_ENCAP_SHIFT |\n+\t\t(vlan_tag_insert & 1) << WQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT);\n+\tdesc->vlan_tag = cpu_to_le16(vlan_tag);\n+}\n+\n+static inline void wq_enet_desc_dec(struct wq_enet_desc *desc,\n+\tu64 *address, u16 *length, u16 *mss, u16 *header_length,\n+\tu8 *offload_mode, u8 *eop, u8 *cq_entry, u8 *fcoe_encap,\n+\tu8 *vlan_tag_insert, u16 *vlan_tag, u8 *loopback)\n+{\n+\t*address = le64_to_cpu(desc->address);\n+\t*length = le16_to_cpu(desc->length) & WQ_ENET_LEN_MASK;\n+\t*mss = (le16_to_cpu(desc->mss_loopback) >> WQ_ENET_MSS_SHIFT) &\n+\t\tWQ_ENET_MSS_MASK;\n+\t*loopback = (u8)((le16_to_cpu(desc->mss_loopback) >>\n+\t\tWQ_ENET_LOOPBACK_SHIFT) & 1);\n+\t*header_length = le16_to_cpu(desc->header_length_flags) &\n+\t\tWQ_ENET_HDRLEN_MASK;\n+\t*offload_mode = (u8)((le16_to_cpu(desc->header_length_flags) >>\n+\t\tWQ_ENET_HDRLEN_BITS) & WQ_ENET_FLAGS_OM_MASK);\n+\t*eop = (u8)((le16_to_cpu(desc->header_length_flags) >>\n+\t\tWQ_ENET_FLAGS_EOP_SHIFT) & 1);\n+\t*cq_entry = (u8)((le16_to_cpu(desc->header_length_flags) >>\n+\t\tWQ_ENET_FLAGS_CQ_ENTRY_SHIFT) & 1);\n+\t*fcoe_encap = (u8)((le16_to_cpu(desc->header_length_flags) >>\n+\t\tWQ_ENET_FLAGS_FCOE_ENCAP_SHIFT) & 1);\n+\t*vlan_tag_insert = (u8)((le16_to_cpu(desc->header_length_flags) >>\n+\t\tWQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT) & 1);\n+\t*vlan_tag = le16_to_cpu(desc->vlan_tag);\n+}\n+\n+#endif /* _WQ_ENET_DESC_H_ */\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "3/6"
    ]
}