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GET /api/patches/139983/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 139983,
    "url": "https://patches.dpdk.org/api/patches/139983/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-20-venkatkumar.ande@amd.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20240507124305.2318-20-venkatkumar.ande@amd.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20240507124305.2318-20-venkatkumar.ande@amd.com",
    "date": "2024-05-07T12:43:00",
    "name": "[v2,20/25] net/axgbe: replace mii generic macro for c45 with AXGBE",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "b55d3b7804dee1c6a348036652812bf31b8224fc",
    "submitter": {
        "id": 3256,
        "url": "https://patches.dpdk.org/api/people/3256/?format=api",
        "name": "Venkat Kumar Ande",
        "email": "venkatkumar.ande@amd.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-20-venkatkumar.ande@amd.com/mbox/",
    "series": [
        {
            "id": 31890,
            "url": "https://patches.dpdk.org/api/series/31890/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31890",
            "date": "2024-05-07T12:42:41",
            "name": "[v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/31890/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/139983/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/139983/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Venkat Kumar Ande <venkatkumar.ande@amd.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<Selwin.Sebastian@amd.com>, Venkat Kumar Ande <venkatkumar.ande@amd.com>",
        "Subject": "[PATCH v2 20/25] net/axgbe: replace mii generic macro for c45 with\n AXGBE",
        "Date": "Tue, 7 May 2024 18:13:00 +0530",
        "Message-ID": "<20240507124305.2318-20-venkatkumar.ande@amd.com>",
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        "References": "<20240412125013.10498-1-VenkatKumar.Ande@amd.com>\n <20240507124305.2318-1-venkatkumar.ande@amd.com>",
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    },
    "content": "The axgbe driver reuses MII_ADDR_C45 for its own purpose. The values\nderived with it are never passed to phylib or a linux MDIO bus driver.\nIn order that MII_ADDR_C45 can be removed, add an AXGBE specific\n\nSigned-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>\n---\n drivers/net/axgbe/axgbe_common.h | 4 ++--\n drivers/net/axgbe/axgbe_dev.c    | 8 ++++----\n drivers/net/axgbe/axgbe_phy.h    | 2 +-\n 3 files changed, 7 insertions(+), 7 deletions(-)",
    "diff": "diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h\nindex 51532fb34a..1a43192630 100644\n--- a/drivers/net/axgbe/axgbe_common.h\n+++ b/drivers/net/axgbe/axgbe_common.h\n@@ -1732,14 +1732,14 @@ do {\t\t\t\t\t\t\t\t\t\\\n  */\n #define XMDIO_READ(_pdata, _mmd, _reg)\t\t\t\t\t\\\n \t((_pdata)->hw_if.read_mmd_regs((_pdata), 0,\t\t\t\\\n-\t\tMII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))\n+\t\tAXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))\n \n #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask)\t\t\t\\\n \t(XMDIO_READ((_pdata), _mmd, _reg) & _mask)\n \n #define XMDIO_WRITE(_pdata, _mmd, _reg, _val)\t\t\t\t\\\n \t((_pdata)->hw_if.write_mmd_regs((_pdata), 0,\t\t\t\\\n-\t\tMII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))\n+\t\tAXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))\n \n #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val)\t\t\\\n do {\t\t\t\t\t\t\t\t\t\\\ndiff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c\nindex fa7324efa7..ebe64295aa 100644\n--- a/drivers/net/axgbe/axgbe_dev.c\n+++ b/drivers/net/axgbe/axgbe_dev.c\n@@ -207,8 +207,8 @@ static int axgbe_read_mmd_regs_v2(struct axgbe_port *pdata,\n \tunsigned int mmd_address, index, offset;\n \tint mmd_data;\n \n-\tif (mmd_reg & MII_ADDR_C45)\n-\t\tmmd_address = mmd_reg & ~MII_ADDR_C45;\n+\tif (mmd_reg & AXGBE_ADDR_C45)\n+\t\tmmd_address = mmd_reg & ~AXGBE_ADDR_C45;\n \telse\n \t\tmmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);\n \n@@ -241,8 +241,8 @@ static void axgbe_write_mmd_regs_v2(struct axgbe_port *pdata,\n {\n \tunsigned int mmd_address, index, offset;\n \n-\tif (mmd_reg & MII_ADDR_C45)\n-\t\tmmd_address = mmd_reg & ~MII_ADDR_C45;\n+\tif (mmd_reg & AXGBE_ADDR_C45)\n+\t\tmmd_address = mmd_reg & ~AXGBE_ADDR_C45;\n \telse\n \t\tmmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);\n \ndiff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h\nindex 5b844e81cd..eee3afc370 100644\n--- a/drivers/net/axgbe/axgbe_phy.h\n+++ b/drivers/net/axgbe/axgbe_phy.h\n@@ -16,7 +16,7 @@\n /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit\n  * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.\n  */\n-#define MII_ADDR_C45 (1 << 30)\n+#define AXGBE_ADDR_C45  (1 << 30)\n \n /* Basic mode status register. */\n #define BMSR_LSTATUS            0x0004  /* Link status */\n",
    "prefixes": [
        "v2",
        "20/25"
    ]
}