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GET /api/patches/139970/?format=api
{ "id": 139970, "url": "https://patches.dpdk.org/api/patches/139970/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-7-venkatkumar.ande@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240507124305.2318-7-venkatkumar.ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240507124305.2318-7-venkatkumar.ande@amd.com", "date": "2024-05-07T12:42:47", "name": "[v2,07/25] net/axgbe: enable PLL control for fixed PHY modes only", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5cfbaf1d659db75a0b5341ad4737fc95c0bc165f", "submitter": { "id": 3256, "url": "https://patches.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-7-venkatkumar.ande@amd.com/mbox/", "series": [ { "id": 31890, "url": "https://patches.dpdk.org/api/series/31890/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31890", "date": "2024-05-07T12:42:41", "name": "[v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs", "version": 2, "mbox": "https://patches.dpdk.org/series/31890/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139970/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/139970/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 447BD43FC9;\n\tTue, 7 May 2024 14:44:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E74D3433BC;\n\tTue, 7 May 2024 14:43:59 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2089.outbound.protection.outlook.com [40.107.93.89])\n by mails.dpdk.org (Postfix) with ESMTP id 2C220433AF;\n Tue, 7 May 2024 14:43:53 +0200 (CEST)", "from PH7P220CA0037.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:32b::18)\n by IA1PR12MB8080.namprd12.prod.outlook.com (2603:10b6:208:3fd::6)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.42; 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CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(82310400017)(1800799015)(376005)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2024 12:43:50.3248 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 287de0ba-583b-4ad7-211c-08dc6e935881", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00036F43.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8080", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "PLL control setting(RRC) is needed only in fixed PHY configuration to\nfix the peer-peer issues. Without the PLL control setting, the link up\ntakes longer time in a fixed phy configuration.\n\nWithout the fix the user will not get the link come UP.\n\nDriver implements SW RRC for Autoneg On configuration, hence PLL control\nsetting (RRC) is not needed for AN On configuration, and can be skipped.\n\nAlso, PLL re-initialization is not needed for PHY Power Off and RRC\ncommands. Otherwise, they lead to mailbox errors. Added the changes\naccordingly.\n\nFixes: 09b0a36cc7ae (\"net/axgbe: toggle PLL settings during rate change\")\nCc: stable@dpdk.org\n\nSigned-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>\n---\n drivers/net/axgbe/axgbe_phy_impl.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c\nindex f51830f800..9c2ae7bba0 100644\n--- a/drivers/net/axgbe/axgbe_phy_impl.c\n+++ b/drivers/net/axgbe/axgbe_phy_impl.c\n@@ -1228,6 +1228,10 @@ static void axgbe_phy_rx_reset(struct axgbe_port *pdata)\n \n static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)\n {\n+\t/* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */\n+\tif (pdata->phy.autoneg != AUTONEG_DISABLE)\n+\t\treturn;\n+\n \tXMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,\n \t\t\tXGBE_PMA_PLL_CTRL_MASK,\n \t\t\tenable ? XGBE_PMA_PLL_CTRL_SET\n@@ -1272,8 +1276,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,\n \taxgbe_phy_rx_reset(pdata);\n \n reenable_pll:\n-\t /* Re-enable the PLL control */\n-\taxgbe_phy_pll_ctrl(pdata, true);\n+\t/* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */\n+\tif (cmd != AXGBE_MB_CMD_POWER_OFF &&\n+\t cmd != AXGBE_MB_CMD_RRC)\n+\t\taxgbe_phy_pll_ctrl(pdata, true);\n \n \tPMD_DRV_LOG(NOTICE, \"firmware mailbox command did not complete\\n\");\n }\n", "prefixes": [ "v2", "07/25" ] }