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GET /api/patches/139876/?format=api
{ "id": 139876, "url": "https://patches.dpdk.org/api/patches/139876/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240506082721.120666-6-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240506082721.120666-6-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240506082721.120666-6-mattias.ronnblom@ericsson.com", "date": "2024-05-06T08:27:20", "name": "[RFC,v6,5/6] service: keep per-lcore state in lcore variable", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d4de99f4bf320727662afedd8254ade841b97c95", "submitter": { "id": 1077, "url": "https://patches.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240506082721.120666-6-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31884, "url": "https://patches.dpdk.org/api/series/31884/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31884", "date": "2024-05-06T08:27:15", "name": "Lcore variables", "version": 6, "mbox": "https://patches.dpdk.org/series/31884/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139876/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/139876/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 46C7343FC4;\n\tMon, 6 May 2024 10:38:50 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 16B484067A;\n\tMon, 6 May 2024 10:38:32 +0200 (CEST)", "from EUR02-VI1-obe.outbound.protection.outlook.com\n (mail-vi1eur02on2089.outbound.protection.outlook.com [40.107.241.89])\n by mails.dpdk.org (Postfix) with ESMTP id 151A5402E5\n for <dev@dpdk.org>; Mon, 6 May 2024 10:38:26 +0200 (CEST)", "from DUZPR01CA0027.eurprd01.prod.exchangelabs.com\n (2603:10a6:10:46b::14) by AM7PR07MB6994.eurprd07.prod.outlook.com\n (2603:10a6:20b:1b2::15) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.41; Mon, 6 May\n 2024 08:38:24 +0000", "from DU6PEPF00009526.eurprd02.prod.outlook.com\n (2603:10a6:10:46b:cafe::a9) by DUZPR01CA0027.outlook.office365.com\n (2603:10a6:10:46b::14) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.39 via Frontend\n Transport; Mon, 6 May 2024 08:38:24 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n DU6PEPF00009526.mail.protection.outlook.com (10.167.8.7) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7544.18 via Frontend Transport; Mon, 6 May 2024 08:38:24 +0000", "from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.68) with Microsoft SMTP Server\n id 15.2.1544.9; Mon, 6 May 2024 10:38:23 +0200", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>, =?utf-8?q?Mattias_R?=\n\t=?utf-8?q?=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC v6 5/6] service: keep per-lcore state in lcore variable", "Date": "Mon, 6 May 2024 10:27:20 +0200", "Message-ID": "<20240506082721.120666-6-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240506082721.120666-1-mattias.ronnblom@ericsson.com>", "References": "<20240228100928.524277-2-mattias.ronnblom@ericsson.com>\n <20240506082721.120666-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DU6PEPF00009526:EE_|AM7PR07MB6994:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d3b74d05-665a-4884-ff1c-08dc6da7e49c", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400017|376005|36860700004|1800799015;", "X-Microsoft-Antispam-Message-Info": "=?utf-8?q?7PF1m6UroGHN1+tpWRsgz0iWTugBl4i?=\n\t=?utf-8?q?lXhWVc5Mtyu/qhro9PspfI2fcU3CzvGiOcp1HD+vnDdykjqkKwY3ThKRdib2kThvt?=\n\t=?utf-8?q?EwElmpVGZozXRoy/+oRghaerKe1d0KtzgKDBj5lN8u8WD/BegFEhC8KCQ8j8R9v5q?=\n\t=?utf-8?q?Hhaq+1Zs6eWsBrHsoIkeNxtTGHuOae5JyvO7zAmnAyAzDgzHvkT6aJHAw8g0yw173?=\n\t=?utf-8?q?KLv2w12mtlCLGyD4mCoj4q+a87gp7QkNYhlLd/hM3MmWsL1lmWXh8dGswZJqZUGlV?=\n\t=?utf-8?q?nVHD3txqg1hY9DixC3MLuXfew8UTAUr9kOspxXYd9LKEWlnEnnYuKt3ZGjN7UwhiK?=\n\t=?utf-8?q?4H96+jYVG4ZjVIqHnK41m0zn3J3PkwziPdDuPmQJOF6/ODTmDJqec5mRy1BKJPYWY?=\n\t=?utf-8?q?rBRY/1m8U6V7Jj3aithfFcDBrnNAmleOK/JHz4uAjgDgKqa3VTKiSKmUqtOm/i9XI?=\n\t=?utf-8?q?mUPO+10DcuwcTgfbALPfTYloZbt1eZl39Y43of9zZIJMgTjFmTNknJcg4VnsqxINR?=\n\t=?utf-8?q?u1pK2xwIkGsVDYMnyj0AYQznX2QLAVSkAJiYZFN91Kycx3u98sutX5NwMvUfkDhy+?=\n\t=?utf-8?q?LpjcPx5DEPQdGPAEoIDLgw6aEG6C63rNzOpy0nVoUwPTNkGaToYRFieSWa8nkOOm3?=\n\t=?utf-8?q?gRi3+IdU9dvPJel8JijohQ9+3VOhO6YedligXustOO4Ac5+op3/UNjx/O/7/aQWTB?=\n\t=?utf-8?q?Otp8A9/+qQ+9ICglrNlxIsJvXsHyxr/AZEOOcNdUrgoTg7Jhq8EYTae2wR5qbNlws?=\n\t=?utf-8?q?OOdFoh9pVYuUXf3GVU1VjVpG6NE1i7rj7EjXZvw0qH60cv2tuX4QWtA+0SxvFIcbJ?=\n\t=?utf-8?q?SrftUGXZGriMXAm+U8fhg6n65jGNtFHzynZUZ1VcCBux40FrcHaYhVO3U2nYf69an?=\n\t=?utf-8?q?0cQRgqnzgl7//9LUbkwd8fiQefBPJ89ivgxwaUb1SiTnBKs9HeyrxfSTMDD8O+DSd?=\n\t=?utf-8?q?lfLTNsE6kftbutQr7ceFQY1B5c1SSApP95TgD9PRhfPcA93jt1r4pftxiqLyiPFw/?=\n\t=?utf-8?q?g2X1/exi7T0xPSrKuVzaDv6R8p3vcfJkbpl/xvZqbwM9kjWrunhMXFEo9zBeBPerd?=\n\t=?utf-8?q?PzWo9F2J3Eh7IO2bcYoMf90r/oCvZEpMM7XOC3QUiMXDW0gM0PpwNDZ+GbSscxItF?=\n\t=?utf-8?q?6BRhb7yci7iROei4uIJrzQB5PdtEYlOOHSSKTf8L20bzCRjQPmy3Jx0PtBPE0G5P+?=\n\t=?utf-8?q?QM3el6U/w+sbCPdAcYiH16fJZ4z/jjvD/K9gPWBl1Z9pJVClh6DSvoAJeRw2JDdu8?=\n\t=?utf-8?q?fdm4TsgoTCRWRhlasQAm+WYe5h1pLdchnjmCiNnGs6w6E5kH1brH/XAfEL7eKa/tb?=\n\t=?utf-8?q?B74lmT74Ph7J?=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(82310400017)(376005)(36860700004)(1800799015);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 May 2024 08:38:24.0977 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d3b74d05-665a-4884-ff1c-08dc6da7e49c", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DU6PEPF00009526.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM7PR07MB6994", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Replace static array of cache-aligned structs with an lcore variable,\nto slightly benefit code simplicity and performance.\n\nRFC v6:\n * Remove a now-redundant lcore variable value memset().\n\nRFC v5:\n * Fix lcore value pointer bug introduced by RFC v4.\n\nRFC v4:\n * Remove strange-looking lcore value lookup potentially containing\n invalid lcore id. (Morten Brørup)\n * Replace misplaced tab with space. (Morten Brørup)\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n lib/eal/common/rte_service.c | 115 +++++++++++++++++++----------------\n 1 file changed, 63 insertions(+), 52 deletions(-)", "diff": "diff --git a/lib/eal/common/rte_service.c b/lib/eal/common/rte_service.c\nindex 56379930b6..03379f1588 100644\n--- a/lib/eal/common/rte_service.c\n+++ b/lib/eal/common/rte_service.c\n@@ -11,6 +11,7 @@\n \n #include <eal_trace_internal.h>\n #include <rte_lcore.h>\n+#include <rte_lcore_var.h>\n #include <rte_branch_prediction.h>\n #include <rte_common.h>\n #include <rte_cycles.h>\n@@ -75,7 +76,7 @@ struct __rte_cache_aligned core_state {\n \n static uint32_t rte_service_count;\n static struct rte_service_spec_impl *rte_services;\n-static struct core_state *lcore_states;\n+static RTE_LCORE_VAR_HANDLE(struct core_state, lcore_states);\n static uint32_t rte_service_library_initialized;\n \n int32_t\n@@ -101,12 +102,8 @@ rte_service_init(void)\n \t\tgoto fail_mem;\n \t}\n \n-\tlcore_states = rte_calloc(\"rte_service_core_states\", RTE_MAX_LCORE,\n-\t\t\tsizeof(struct core_state), RTE_CACHE_LINE_SIZE);\n-\tif (!lcore_states) {\n-\t\tEAL_LOG(ERR, \"error allocating core states array\");\n-\t\tgoto fail_mem;\n-\t}\n+\tif (lcore_states == NULL)\n+\t\tRTE_LCORE_VAR_ALLOC(lcore_states);\n \n \tint i;\n \tstruct rte_config *cfg = rte_eal_get_configuration();\n@@ -122,7 +119,6 @@ rte_service_init(void)\n \treturn 0;\n fail_mem:\n \trte_free(rte_services);\n-\trte_free(lcore_states);\n \treturn -ENOMEM;\n }\n \n@@ -136,7 +132,6 @@ rte_service_finalize(void)\n \trte_eal_mp_wait_lcore();\n \n \trte_free(rte_services);\n-\trte_free(lcore_states);\n \n \trte_service_library_initialized = 0;\n }\n@@ -286,7 +281,6 @@ rte_service_component_register(const struct rte_service_spec *spec,\n int32_t\n rte_service_component_unregister(uint32_t id)\n {\n-\tuint32_t i;\n \tstruct rte_service_spec_impl *s;\n \tSERVICE_VALID_GET_OR_ERR_RET(id, s, -EINVAL);\n \n@@ -294,9 +288,10 @@ rte_service_component_unregister(uint32_t id)\n \n \ts->internal_flags &= ~(SERVICE_F_REGISTERED);\n \n+\tstruct core_state *cs;\n \t/* clear the run-bit in all cores */\n-\tfor (i = 0; i < RTE_MAX_LCORE; i++)\n-\t\tlcore_states[i].service_mask &= ~(UINT64_C(1) << id);\n+\tRTE_LCORE_VAR_FOREACH_VALUE(cs, lcore_states)\n+\t\tcs->service_mask &= ~(UINT64_C(1) << id);\n \n \tmemset(&rte_services[id], 0, sizeof(struct rte_service_spec_impl));\n \n@@ -454,7 +449,10 @@ rte_service_may_be_active(uint32_t id)\n \t\treturn -EINVAL;\n \n \tfor (i = 0; i < lcore_count; i++) {\n-\t\tif (lcore_states[ids[i]].service_active_on_lcore[id])\n+\t\tstruct core_state *cs =\n+\t\t\tRTE_LCORE_VAR_LCORE_VALUE(ids[i], lcore_states);\n+\n+\t\tif (cs->service_active_on_lcore[id])\n \t\t\treturn 1;\n \t}\n \n@@ -464,7 +462,7 @@ rte_service_may_be_active(uint32_t id)\n int32_t\n rte_service_run_iter_on_app_lcore(uint32_t id, uint32_t serialize_mt_unsafe)\n {\n-\tstruct core_state *cs = &lcore_states[rte_lcore_id()];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_VALUE(lcore_states);\n \tstruct rte_service_spec_impl *s;\n \n \tSERVICE_VALID_GET_OR_ERR_RET(id, s, -EINVAL);\n@@ -486,8 +484,7 @@ service_runner_func(void *arg)\n {\n \tRTE_SET_USED(arg);\n \tuint8_t i;\n-\tconst int lcore = rte_lcore_id();\n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs = RTE_LCORE_VAR_VALUE(lcore_states);\n \n \trte_atomic_store_explicit(&cs->thread_active, 1, rte_memory_order_seq_cst);\n \n@@ -533,13 +530,15 @@ service_runner_func(void *arg)\n int32_t\n rte_service_lcore_may_be_active(uint32_t lcore)\n {\n-\tif (lcore >= RTE_MAX_LCORE || !lcore_states[lcore].is_service_core)\n+\tstruct core_state *cs = RTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n+\n+\tif (lcore >= RTE_MAX_LCORE || !cs->is_service_core)\n \t\treturn -EINVAL;\n \n \t/* Load thread_active using ACQUIRE to avoid instructions dependent on\n \t * the result being re-ordered before this load completes.\n \t */\n-\treturn rte_atomic_load_explicit(&lcore_states[lcore].thread_active,\n+\treturn rte_atomic_load_explicit(&cs->thread_active,\n \t\t\t rte_memory_order_acquire);\n }\n \n@@ -547,9 +546,11 @@ int32_t\n rte_service_lcore_count(void)\n {\n \tint32_t count = 0;\n-\tuint32_t i;\n-\tfor (i = 0; i < RTE_MAX_LCORE; i++)\n-\t\tcount += lcore_states[i].is_service_core;\n+\n+\tstruct core_state *cs;\n+\tRTE_LCORE_VAR_FOREACH_VALUE(cs, lcore_states)\n+\t\tcount += cs->is_service_core;\n+\n \treturn count;\n }\n \n@@ -566,7 +567,8 @@ rte_service_lcore_list(uint32_t array[], uint32_t n)\n \tuint32_t i;\n \tuint32_t idx = 0;\n \tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n-\t\tstruct core_state *cs = &lcore_states[i];\n+\t\tstruct core_state *cs =\n+\t\t\tRTE_LCORE_VAR_LCORE_VALUE(i, lcore_states);\n \t\tif (cs->is_service_core) {\n \t\t\tarray[idx] = i;\n \t\t\tidx++;\n@@ -582,7 +584,7 @@ rte_service_lcore_count_services(uint32_t lcore)\n \tif (lcore >= RTE_MAX_LCORE)\n \t\treturn -EINVAL;\n \n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs = RTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \tif (!cs->is_service_core)\n \t\treturn -ENOTSUP;\n \n@@ -634,30 +636,31 @@ rte_service_start_with_defaults(void)\n static int32_t\n service_update(uint32_t sid, uint32_t lcore, uint32_t *set, uint32_t *enabled)\n {\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n+\n \t/* validate ID, or return error value */\n \tif (!service_valid(sid) || lcore >= RTE_MAX_LCORE ||\n-\t\t\t!lcore_states[lcore].is_service_core)\n+\t\t\t!cs->is_service_core)\n \t\treturn -EINVAL;\n \n \tuint64_t sid_mask = UINT64_C(1) << sid;\n \tif (set) {\n-\t\tuint64_t lcore_mapped = lcore_states[lcore].service_mask &\n-\t\t\tsid_mask;\n+\t\tuint64_t lcore_mapped = cs->service_mask & sid_mask;\n \n \t\tif (*set && !lcore_mapped) {\n-\t\t\tlcore_states[lcore].service_mask |= sid_mask;\n+\t\t\tcs->service_mask |= sid_mask;\n \t\t\trte_atomic_fetch_add_explicit(&rte_services[sid].num_mapped_cores,\n \t\t\t\t1, rte_memory_order_relaxed);\n \t\t}\n \t\tif (!*set && lcore_mapped) {\n-\t\t\tlcore_states[lcore].service_mask &= ~(sid_mask);\n+\t\t\tcs->service_mask &= ~(sid_mask);\n \t\t\trte_atomic_fetch_sub_explicit(&rte_services[sid].num_mapped_cores,\n \t\t\t\t1, rte_memory_order_relaxed);\n \t\t}\n \t}\n \n \tif (enabled)\n-\t\t*enabled = !!(lcore_states[lcore].service_mask & (sid_mask));\n+\t\t*enabled = !!(cs->service_mask & (sid_mask));\n \n \treturn 0;\n }\n@@ -685,13 +688,14 @@ set_lcore_state(uint32_t lcore, int32_t state)\n {\n \t/* mark core state in hugepage backed config */\n \tstruct rte_config *cfg = rte_eal_get_configuration();\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \tcfg->lcore_role[lcore] = state;\n \n \t/* mark state in process local lcore_config */\n \tlcore_config[lcore].core_role = state;\n \n \t/* update per-lcore optimized state tracking */\n-\tlcore_states[lcore].is_service_core = (state == ROLE_SERVICE);\n+\tcs->is_service_core = (state == ROLE_SERVICE);\n \n \trte_eal_trace_service_lcore_state_change(lcore, state);\n }\n@@ -702,14 +706,16 @@ rte_service_lcore_reset_all(void)\n \t/* loop over cores, reset all to mask 0 */\n \tuint32_t i;\n \tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n-\t\tif (lcore_states[i].is_service_core) {\n-\t\t\tlcore_states[i].service_mask = 0;\n+\t\tstruct core_state *cs =\n+\t\t\tRTE_LCORE_VAR_LCORE_VALUE(i, lcore_states);\n+\t\tif (cs->is_service_core) {\n+\t\t\tcs->service_mask = 0;\n \t\t\tset_lcore_state(i, ROLE_RTE);\n \t\t\t/* runstate act as guard variable Use\n \t\t\t * store-release memory order here to synchronize\n \t\t\t * with load-acquire in runstate read functions.\n \t\t\t */\n-\t\t\trte_atomic_store_explicit(&lcore_states[i].runstate,\n+\t\t\trte_atomic_store_explicit(&cs->runstate,\n \t\t\t\tRUNSTATE_STOPPED, rte_memory_order_release);\n \t\t}\n \t}\n@@ -725,17 +731,19 @@ rte_service_lcore_add(uint32_t lcore)\n {\n \tif (lcore >= RTE_MAX_LCORE)\n \t\treturn -EINVAL;\n-\tif (lcore_states[lcore].is_service_core)\n+\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n+\tif (cs->is_service_core)\n \t\treturn -EALREADY;\n \n \tset_lcore_state(lcore, ROLE_SERVICE);\n \n \t/* ensure that after adding a core the mask and state are defaults */\n-\tlcore_states[lcore].service_mask = 0;\n+\tcs->service_mask = 0;\n \t/* Use store-release memory order here to synchronize with\n \t * load-acquire in runstate read functions.\n \t */\n-\trte_atomic_store_explicit(&lcore_states[lcore].runstate, RUNSTATE_STOPPED,\n+\trte_atomic_store_explicit(&cs->runstate, RUNSTATE_STOPPED,\n \t\trte_memory_order_release);\n \n \treturn rte_eal_wait_lcore(lcore);\n@@ -747,7 +755,7 @@ rte_service_lcore_del(uint32_t lcore)\n \tif (lcore >= RTE_MAX_LCORE)\n \t\treturn -EINVAL;\n \n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \tif (!cs->is_service_core)\n \t\treturn -EINVAL;\n \n@@ -771,7 +779,7 @@ rte_service_lcore_start(uint32_t lcore)\n \tif (lcore >= RTE_MAX_LCORE)\n \t\treturn -EINVAL;\n \n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \tif (!cs->is_service_core)\n \t\treturn -EINVAL;\n \n@@ -801,6 +809,8 @@ rte_service_lcore_start(uint32_t lcore)\n int32_t\n rte_service_lcore_stop(uint32_t lcore)\n {\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n+\n \tif (lcore >= RTE_MAX_LCORE)\n \t\treturn -EINVAL;\n \n@@ -808,12 +818,11 @@ rte_service_lcore_stop(uint32_t lcore)\n \t * memory order here to synchronize with store-release\n \t * in runstate update functions.\n \t */\n-\tif (rte_atomic_load_explicit(&lcore_states[lcore].runstate, rte_memory_order_acquire) ==\n+\tif (rte_atomic_load_explicit(&cs->runstate, rte_memory_order_acquire) ==\n \t\t\tRUNSTATE_STOPPED)\n \t\treturn -EALREADY;\n \n \tuint32_t i;\n-\tstruct core_state *cs = &lcore_states[lcore];\n \tuint64_t service_mask = cs->service_mask;\n \n \tfor (i = 0; i < RTE_SERVICE_NUM_MAX; i++) {\n@@ -834,7 +843,7 @@ rte_service_lcore_stop(uint32_t lcore)\n \t/* Use store-release memory order here to synchronize with\n \t * load-acquire in runstate read functions.\n \t */\n-\trte_atomic_store_explicit(&lcore_states[lcore].runstate, RUNSTATE_STOPPED,\n+\trte_atomic_store_explicit(&cs->runstate, RUNSTATE_STOPPED,\n \t\trte_memory_order_release);\n \n \trte_eal_trace_service_lcore_stop(lcore);\n@@ -845,7 +854,7 @@ rte_service_lcore_stop(uint32_t lcore)\n static uint64_t\n lcore_attr_get_loops(unsigned int lcore)\n {\n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \treturn rte_atomic_load_explicit(&cs->loops, rte_memory_order_relaxed);\n }\n@@ -853,7 +862,7 @@ lcore_attr_get_loops(unsigned int lcore)\n static uint64_t\n lcore_attr_get_cycles(unsigned int lcore)\n {\n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \treturn rte_atomic_load_explicit(&cs->cycles, rte_memory_order_relaxed);\n }\n@@ -861,7 +870,7 @@ lcore_attr_get_cycles(unsigned int lcore)\n static uint64_t\n lcore_attr_get_service_calls(uint32_t service_id, unsigned int lcore)\n {\n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \treturn rte_atomic_load_explicit(&cs->service_stats[service_id].calls,\n \t\trte_memory_order_relaxed);\n@@ -870,7 +879,7 @@ lcore_attr_get_service_calls(uint32_t service_id, unsigned int lcore)\n static uint64_t\n lcore_attr_get_service_cycles(uint32_t service_id, unsigned int lcore)\n {\n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \treturn rte_atomic_load_explicit(&cs->service_stats[service_id].cycles,\n \t\trte_memory_order_relaxed);\n@@ -886,7 +895,10 @@ attr_get(uint32_t id, lcore_attr_get_fun lcore_attr_get)\n \tuint64_t sum = 0;\n \n \tfor (lcore = 0; lcore < RTE_MAX_LCORE; lcore++) {\n-\t\tif (lcore_states[lcore].is_service_core)\n+\t\tstruct core_state *cs =\n+\t\t\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n+\n+\t\tif (cs->is_service_core)\n \t\t\tsum += lcore_attr_get(id, lcore);\n \t}\n \n@@ -930,12 +942,11 @@ int32_t\n rte_service_lcore_attr_get(uint32_t lcore, uint32_t attr_id,\n \t\t\t uint64_t *attr_value)\n {\n-\tstruct core_state *cs;\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \tif (lcore >= RTE_MAX_LCORE || !attr_value)\n \t\treturn -EINVAL;\n \n-\tcs = &lcore_states[lcore];\n \tif (!cs->is_service_core)\n \t\treturn -ENOTSUP;\n \n@@ -960,7 +971,8 @@ rte_service_attr_reset_all(uint32_t id)\n \t\treturn -EINVAL;\n \n \tfor (lcore = 0; lcore < RTE_MAX_LCORE; lcore++) {\n-\t\tstruct core_state *cs = &lcore_states[lcore];\n+\t\tstruct core_state *cs =\n+\t\t\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \t\tcs->service_stats[id] = (struct service_stats) {};\n \t}\n@@ -971,12 +983,11 @@ rte_service_attr_reset_all(uint32_t id)\n int32_t\n rte_service_lcore_attr_reset_all(uint32_t lcore)\n {\n-\tstruct core_state *cs;\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \tif (lcore >= RTE_MAX_LCORE)\n \t\treturn -EINVAL;\n \n-\tcs = &lcore_states[lcore];\n \tif (!cs->is_service_core)\n \t\treturn -ENOTSUP;\n \n@@ -1011,7 +1022,7 @@ static void\n service_dump_calls_per_lcore(FILE *f, uint32_t lcore)\n {\n \tuint32_t i;\n-\tstruct core_state *cs = &lcore_states[lcore];\n+\tstruct core_state *cs =\tRTE_LCORE_VAR_LCORE_VALUE(lcore, lcore_states);\n \n \tfprintf(f, \"%02d\\t\", lcore);\n \tfor (i = 0; i < RTE_SERVICE_NUM_MAX; i++) {\n", "prefixes": [ "RFC", "v6", "5/6" ] }