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GET /api/patches/139872/?format=api
{ "id": 139872, "url": "https://patches.dpdk.org/api/patches/139872/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240505083737.118649-7-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240505083737.118649-7-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240505083737.118649-7-mattias.ronnblom@ericsson.com", "date": "2024-05-05T08:37:37", "name": "[RFC,v7,6/6] eal: add unit tests for atomic bit access functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bbaf67d51868c7186fb1a0fc33bf7f4196744b6a", "submitter": { "id": 1077, "url": "https://patches.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240505083737.118649-7-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31882, "url": "https://patches.dpdk.org/api/series/31882/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31882", "date": "2024-05-05T08:37:31", "name": "Improve EAL bit operations API", "version": 7, "mbox": "https://patches.dpdk.org/series/31882/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139872/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/139872/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9A0A143FAE;\n\tSun, 5 May 2024 10:48:42 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 030E940685;\n\tSun, 5 May 2024 10:48:09 +0200 (CEST)", "from EUR01-HE1-obe.outbound.protection.outlook.com\n (mail-he1eur01on2085.outbound.protection.outlook.com [40.107.13.85])\n by mails.dpdk.org (Postfix) with ESMTP id EB7A2402E7\n for <dev@dpdk.org>; Sun, 5 May 2024 10:48:01 +0200 (CEST)", "from DB3PR08CA0028.eurprd08.prod.outlook.com (2603:10a6:8::41) by\n AM7PR07MB7009.eurprd07.prod.outlook.com (2603:10a6:20b:1b0::10) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.39; Sun, 5 May\n 2024 08:48:00 +0000", "from DU2PEPF0001E9C4.eurprd03.prod.outlook.com\n (2603:10a6:8:0:cafe::2b) by DB3PR08CA0028.outlook.office365.com\n (2603:10a6:8::41) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.40 via Frontend\n Transport; Sun, 5 May 2024 08:48:00 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n DU2PEPF0001E9C4.mail.protection.outlook.com (10.167.8.73) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7544.18 via Frontend Transport; Sun, 5 May 2024 08:47:59 +0000", "from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.64) with Microsoft SMTP Server\n id 15.2.1544.9; Sun, 5 May 2024 10:47:59 +0200", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>, Heng Wang <heng.wang@ericsson.com>,\n \"Stephen Hemminger\" <stephen@networkplumber.org>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>, =?utf-8?q?Mattia?=\n\t=?utf-8?q?s_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC v7 6/6] eal: add unit tests for atomic bit access functions", "Date": "Sun, 5 May 2024 10:37:37 +0200", "Message-ID": "<20240505083737.118649-7-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240505083737.118649-1-mattias.ronnblom@ericsson.com>", "References": "<20240502055706.112443-2-mattias.ronnblom@ericsson.com>\n <20240505083737.118649-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DU2PEPF0001E9C4:EE_|AM7PR07MB7009:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3d80fdf8-c30c-45c0-d2db-08dc6ce01143", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400017|36860700004|1800799015|376005;", "X-Microsoft-Antispam-Message-Info": "=?utf-8?q?vklzcXrI4UFVGuGMyEI2ODSddqmnSdU?=\n\t=?utf-8?q?CZEPUGhHZEzzhU0nsnL2Bahsk1fJtPCbOC6MGgMM9Fsb1cpbVKu9smHnChLE8DwZ5?=\n\t=?utf-8?q?EGMAc19nSJcHIUwro57vHo1DqIzx6qxTel802VuTZBEbofKAS+/0MiKTf7T+iZLjY?=\n\t=?utf-8?q?m81yoJ7wzoYGaEf4rRmbU2dcJiqFNvwU0VVMbM0mTgN+DDemCSaHloY/0GbmZH71Y?=\n\t=?utf-8?q?7+BLqBHHDdVhMHURnnU7UOtBjRanGUF6EmvEFECikk/WC6ZuGIq2YZVCTDQSBFEzn?=\n\t=?utf-8?q?j25KZheD3dXqY5l2KGeBJXANA5R6LKinegn+9MEMYoNeHP4rzbH/0k16jwM9RMRjd?=\n\t=?utf-8?q?goz+6PY1ibn1qe36s/Ak2Y46R7/bTz4Ctwp7hR9adNE7bi/BZZ437bBpO5LI5DZMB?=\n\t=?utf-8?q?UJPuDF9zfJ6K81oSAnEXEK57gK/2QOkT0wX2B58YLHEUy88Bk4Uooeh6aM8XUsnuC?=\n\t=?utf-8?q?LYHcLP4t0bHlMMCllTxaepBWR6YvWr96vwCsx98aZgnd0wUU1RbBaRs4/pPxi5QlS?=\n\t=?utf-8?q?sUhVKXr5NmD/hyeu1jT4InJkkCQYHbi90T8tBJmgN8Jo5QjBsldMuzv63OF/QPq9v?=\n\t=?utf-8?q?SRh/yB846um8gVxXjdSGXtHvMH2ufHagU4rGnS1uxCgaEqH5ypijsbLXXZleXJrLS?=\n\t=?utf-8?q?LaNalRivW41AGviWMgS4OLGXbTwCAP2VnfCz4rymxYo28a6zhMK/WL7LdaYjOxQWw?=\n\t=?utf-8?q?dLoaY5FkgWgLWN5KJuSh0BKw3X6V0CjPJTpaO8t+UqgQhgme5NgvFNwxTvjcm4L6z?=\n\t=?utf-8?q?Hk1f9IHg+i2NUERC5RPZ4RQ1Cn2yGdn2gLIl/9u0QobJJ+txLgjYQkaVieIjUpr01?=\n\t=?utf-8?q?J63/mrcN23qr2gOeMokEKnU9DLeQkJ4/5B3S9S2AEz0cJkLbGaxlXqWrAwulD16ST?=\n\t=?utf-8?q?9Zw2js/F60/kTH6uOUkITts3+Ms5eT18T1oESu70xqrtHHomKH4+rsvVMLcD3wGI7?=\n\t=?utf-8?q?+kfHJQohBMokSXoGUhrlgZ7TeYGcqsizTjEd23g9roVyOoZBwKvTiBECjWCjdbSK5?=\n\t=?utf-8?q?foghtfCU50btpyCB3lLVWMJAEyeSUf7LKvocuqARz//yUwaJcx9TI+3eBpH3YFN6y?=\n\t=?utf-8?q?qOn1rGNE7r1AxJY5QBHacK5xXS1jZbIB8wRPVxvfCvtFcv5vPnWT+RXOFOctaVPfY?=\n\t=?utf-8?q?nd3Ej9Qx6Yrb7NljlUFFhHghlcezABbQqXw20AdY9IW/FlH9odGJ85SIrDlhvDT5/?=\n\t=?utf-8?q?hOUSAC1SkuFNt23fOP/Y/bE7411CIh7wQjTbaigggMtz77cDCDq82MEk3FxL2/ycS?=\n\t=?utf-8?q?qEOsBN+sGoetBW9w9IbwAttlt3s2aLnoTo9WWwcr51T5v3ZCU8dcLN5e+ZzlvQpoG?=\n\t=?utf-8?q?PKk2jg6K1ind?=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(82310400017)(36860700004)(1800799015)(376005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2024 08:47:59.6961 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3d80fdf8-c30c-45c0-d2db-08dc6ce01143", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DU2PEPF0001E9C4.eurprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM7PR07MB7009", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Extend bitops tests to cover the rte_bit_atomic_*() family of\nfunctions.\n\nRFC v4:\n * Add atomicity test for atomic bit flip.\n\nRFC v3:\n * Rename variable 'main' to make ICC happy.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\nAcked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\n---\n app/test/test_bitops.c | 315 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 314 insertions(+), 1 deletion(-)", "diff": "diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c\nindex 9bffc4da14..c86d7e1f77 100644\n--- a/app/test/test_bitops.c\n+++ b/app/test/test_bitops.c\n@@ -3,10 +3,13 @@\n * Copyright(c) 2024 Ericsson AB\n */\n \n+#include <inttypes.h>\n #include <stdbool.h>\n \n-#include <rte_launch.h>\n #include <rte_bitops.h>\n+#include <rte_cycles.h>\n+#include <rte_launch.h>\n+#include <rte_lcore.h>\n #include <rte_random.h>\n #include \"test.h\"\n \n@@ -69,6 +72,304 @@ GEN_TEST_BIT_ACCESS(test_bit_once_access64, rte_bit_once_set,\n \t\t rte_bit_once_clear, rte_bit_once_assign,\n \t\t rte_bit_once_flip, rte_bit_once_test, 64)\n \n+#define bit_atomic_set(addr, nr)\t\t\t\t\\\n+\trte_bit_atomic_set(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_clear(addr, nr)\t\t\t\t\t\\\n+\trte_bit_atomic_clear(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_assign(addr, nr, value)\t\t\t\t\\\n+\trte_bit_atomic_assign(addr, nr, value, rte_memory_order_relaxed)\n+\n+#define bit_atomic_flip(addr, nr)\t\t\t\t\t\\\n+ rte_bit_atomic_flip(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_test(addr, nr)\t\t\t\t\\\n+\trte_bit_atomic_test(addr, nr, rte_memory_order_relaxed)\n+\n+GEN_TEST_BIT_ACCESS(test_bit_atomic_access32, bit_atomic_set,\n+\t\t bit_atomic_clear, bit_atomic_assign,\n+\t\t bit_atomic_flip, bit_atomic_test, 32)\n+\n+GEN_TEST_BIT_ACCESS(test_bit_atomic_access64, bit_atomic_set,\n+\t\t bit_atomic_clear, bit_atomic_assign,\n+\t\t bit_atomic_flip, bit_atomic_test, 64)\n+\n+#define PARALLEL_TEST_RUNTIME 0.25\n+\n+#define GEN_TEST_BIT_PARALLEL_ASSIGN(size)\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_access_lcore ## size\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tbool failed;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_assign ## size(void *arg)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_access_lcore ## size *lcore = arg;\t\\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tbool value = false;\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tbool new_value = rte_rand() & 1;\t\t\\\n+\t\t\tbool use_test_and_modify = rte_rand() & 1;\t\\\n+\t\t\tbool use_assign = rte_rand() & 1;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (rte_bit_atomic_test(lcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed) != value) { \\\n+\t\t\t\tlcore->failed = true;\t\t\t\\\n+\t\t\t\tbreak;\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (use_test_and_modify) {\t\t\t\\\n+\t\t\t\tbool old_value;\t\t\t\t\\\n+\t\t\t\tif (use_assign) \t\t\t\\\n+\t\t\t\t\told_value = rte_bit_atomic_test_and_assign( \\\n+\t\t\t\t\t\tlcore->word, lcore->bit, new_value, \\\n+\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\telse {\t\t\t\t\t\\\n+\t\t\t\t\told_value = new_value ?\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_test_and_set( \\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed) : \\\n+\t\t\t\t\t\trte_bit_atomic_test_and_clear( \\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t\tif (old_value != value) {\t\t\\\n+\t\t\t\t\tlcore->failed = true;\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t} else {\t\t\t\t\t\\\n+\t\t\t\tif (use_assign)\t\t\t\t\\\n+\t\t\t\t\trte_bit_atomic_assign(lcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\t new_value, \\\n+\t\t\t\t\t\t\t rte_memory_order_relaxed); \\\n+\t\t\t\telse {\t\t\t\t\t\\\n+\t\t\t\t\tif (new_value)\t\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_set(\t\\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t\telse\t\t\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_clear(\t\\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tvalue = new_value;\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_assign ## size(void)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tstruct parallel_access_lcore ## size lmain = {\t\t\\\n+\t\t\t.word = &word\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_access_lcore ## size lworker = {\t\\\n+\t\t\t.word = &word\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tlmain.bit = rte_rand_max(size);\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tlworker.bit = rte_rand_max(size);\t\t\\\n+\t\t} while (lworker.bit == lmain.bit);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_assign ## size, \\\n+\t\t\t\t\t &lworker, worker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_assign ## size(&lmain);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(!lmain.failed, \"Main lcore atomic access failed\"); \\\n+\t\tTEST_ASSERT(!lworker.failed, \"Worker lcore atomic access \" \\\n+\t\t\t \"failed\");\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_ASSIGN(32)\n+GEN_TEST_BIT_PARALLEL_ASSIGN(64)\n+\n+#define GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(size)\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_test_and_set_lcore ## size\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint64_t flips;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_test_and_modify ## size(void *arg)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore ## size *lcore = arg; \\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tbool old_value;\t\t\t\t\t\\\n+\t\t\tbool new_value = rte_rand() & 1;\t\t\\\n+\t\t\tbool use_assign = rte_rand() & 1;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (use_assign)\t\t\t\t\t\\\n+\t\t\t\told_value = rte_bit_atomic_test_and_assign( \\\n+\t\t\t\t\tlcore->word, lcore->bit, new_value, \\\n+\t\t\t\t\trte_memory_order_relaxed);\t\\\n+\t\t\telse\t\t\t\t\t\t\\\n+\t\t\t\told_value = new_value ?\t\t\t\\\n+\t\t\t\t\trte_bit_atomic_test_and_set(\t\\\n+\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed) : \\\n+\t\t\t\t\trte_bit_atomic_test_and_clear(\t\\\n+\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\tif (old_value != new_value)\t\t\t\\\n+\t\t\t\tlcore->flips++;\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_test_and_modify ## size(void)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tunsigned int bit = rte_rand_max(size);\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore ## size lmain = {\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore ## size lworker = {\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_test_and_modify ## size, \\\n+\t\t\t\t\t &lworker, worker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_test_and_modify ## size(&lmain);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t total_flips = lmain.flips + lworker.flips;\t\\\n+\t\tbool expected_value = total_flips % 2;\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_value == rte_bit_test(&word, bit), \\\n+\t\t\t \"After %\"PRId64\" flips, the bit value \"\t\\\n+\t\t\t \"should be %d\", total_flips, expected_value); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t expected_word = 0;\t\t\t\t\\\n+\t\trte_bit_assign(&expected_word, bit, expected_value);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_word == word, \"Untouched bits have \" \\\n+\t\t\t \"changed value\");\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(32)\n+GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(64)\n+\n+#define GEN_TEST_BIT_PARALLEL_FLIP(size)\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_flip_lcore ## size\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint64_t flips;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_flip ## size(void *arg)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_flip_lcore ## size *lcore = arg; \\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\trte_bit_atomic_flip(lcore->word, lcore->bit,\t\\\n+\t\t\t\t\t rte_memory_order_relaxed);\t\\\n+\t\t\tlcore->flips++;\t\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_flip ## size(void)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tunsigned int bit = rte_rand_max(size);\t\t\t\\\n+\t\tstruct parallel_flip_lcore ## size lmain = {\t\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_flip_lcore ## size lworker = {\t\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_flip ## size, \\\n+\t\t\t\t\t &lworker, worker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_flip ## size(&lmain);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t total_flips = lmain.flips + lworker.flips;\t\\\n+\t\tbool expected_value = total_flips % 2;\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_value == rte_bit_test(&word, bit), \\\n+\t\t\t \"After %\"PRId64\" flips, the bit value \"\t\\\n+\t\t\t \"should be %d\", total_flips, expected_value); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t expected_word = 0;\t\t\t\t\\\n+\t\trte_bit_assign(&expected_word, bit, expected_value);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_word == word, \"Untouched bits have \" \\\n+\t\t\t \"changed value\");\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_FLIP(32)\n+GEN_TEST_BIT_PARALLEL_FLIP(64)\n+\n static uint32_t val32;\n static uint64_t val64;\n \n@@ -187,6 +488,18 @@ static struct unit_test_suite test_suite = {\n \t\tTEST_CASE(test_bit_access64),\n \t\tTEST_CASE(test_bit_once_access32),\n \t\tTEST_CASE(test_bit_once_access64),\n+\t\tTEST_CASE(test_bit_access32),\n+\t\tTEST_CASE(test_bit_access64),\n+\t\tTEST_CASE(test_bit_once_access32),\n+\t\tTEST_CASE(test_bit_once_access64),\n+\t\tTEST_CASE(test_bit_atomic_access32),\n+\t\tTEST_CASE(test_bit_atomic_access64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_assign32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_assign64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_test_and_modify32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_test_and_modify64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_flip32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_flip64),\n \t\tTEST_CASE(test_bit_relaxed_set),\n \t\tTEST_CASE(test_bit_relaxed_clear),\n \t\tTEST_CASE(test_bit_relaxed_test_set_clear),\n", "prefixes": [ "RFC", "v7", "6/6" ] }