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GET /api/patches/139853/?format=api
{ "id": 139853, "url": "https://patches.dpdk.org/api/patches/139853/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/90f5cb719f2e67442506a7a9a8aa62d599970128.1714744629.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<90f5cb719f2e67442506a7a9a8aa62d599970128.1714744629.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/90f5cb719f2e67442506a7a9a8aa62d599970128.1714744629.git.anatoly.burakov@intel.com", "date": "2024-05-03T13:57:56", "name": "[v2,25/27] net/ixgbe/base: add support for NVM handling in E610 device", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5025a3f3ae08750c21907cb04618daadc990b74f", "submitter": { "id": 4, "url": "https://patches.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/90f5cb719f2e67442506a7a9a8aa62d599970128.1714744629.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 31875, "url": "https://patches.dpdk.org/api/series/31875/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31875", "date": "2024-05-03T13:57:31", "name": "Update IXGBE base driver", "version": 2, "mbox": "https://patches.dpdk.org/series/31875/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139853/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/139853/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 529D343F76;\n\tFri, 3 May 2024 16:01:26 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8E50A410ED;\n\tFri, 3 May 2024 15:59:14 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.15])\n by mails.dpdk.org (Postfix) with ESMTP id 9EE214067E\n for <dev@dpdk.org>; Fri, 3 May 2024 15:59:12 +0200 (CEST)", "from fmviesa002.fm.intel.com ([10.60.135.142])\n by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 May 2024 06:59:12 -0700", "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa002.fm.intel.com with ESMTP; 03 May 2024 06:59:10 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714744752; x=1746280752;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=0e5vpZcxT8q4skNLPwtlCGKMEqRtMIMrWIxpWyRnCak=;\n b=R3I3TkMfTk20y3ZK1GvIiHuEk6f5BGB2gSLW+GiwbhKJC8pq1QrRkDQK\n cLJO1I7J1oMMqGm9M0p4wxjlS+J5AjbEANiRbLgTv5Kxe0N7bMRD5wiTJ\n EfBV4F0CvIHoKcsxZfCw72kDLbLvVVgApjEz+uvpiWTcjcMZPrMrmeOW4\n P3zKPnuYWh+/oGEZCNgwij5kgUf0AqAS/bxAR9EupysSiwXgUQY80cCz4\n TjBFlzQRc52zD5lqDiGgwzXF7Ov00GV3F8cWpwfyuarjOHpUvB5OtIyvh\n GGIpqdVWrgJpMWMDvaamf4SnSFbxIbOWdibKVoIc8x7THPtNbscGMxszy w==;", "X-CSE-ConnectionGUID": [ "SXd+xKEzRxa9ROo1xUNA4g==", "plmSphfgQvGLTVzdoCCQeA==" ], "X-CSE-MsgGUID": [ "x7Urc3sEQ0mS0p9NclbHpg==", "X/DrHb4BT46qUml/ouQ5hw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11063\"; a=\"10714984\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"10714984\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"50642061\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Piotr Kwapulinski <piotr.kwapulinski@intel.com>,\n bruce.richardson@intel.com, vladimir.medvedkin@intel.com,\n Stefan Wegrzyn <stefan.wegrzyn@intel.com>,\n Jedrzej Jagielski <jedrzej.jagielski@intel.com>", "Subject": "[PATCH v2 25/27] net/ixgbe/base: add support for NVM handling in E610\n device", "Date": "Fri, 3 May 2024 14:57:56 +0100", "Message-ID": "\n <90f5cb719f2e67442506a7a9a8aa62d599970128.1714744629.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1714744628.git.anatoly.burakov@intel.com>", "References": "<cover.1713964707.git.anatoly.burakov@intel.com>\n <cover.1714744628.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\n\nAdd low level support for accessing NVM in E610 device. NVM operations are\nhandled via the Admin Command Interface.\n\nSigned-off-by: Stefan Wegrzyn <stefan.wegrzyn@intel.com>\nSigned-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>\nSigned-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_e610.c | 294 ++++++++++++++++++++++++++++\n drivers/net/ixgbe/base/ixgbe_e610.h | 15 ++\n 2 files changed, 309 insertions(+)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c b/drivers/net/ixgbe/base/ixgbe_e610.c\nindex e7e37e794b..a197c6274e 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.c\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.c\n@@ -1699,6 +1699,222 @@ s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_acquire_nvm - Generic request for acquiring the NVM ownership\n+ * @hw: pointer to the HW structure\n+ * @access: NVM access type (read or write)\n+ *\n+ * Request NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_acquire_nvm(struct ixgbe_hw *hw,\n+\t\t enum ixgbe_aci_res_access_type access)\n+{\n+\tu32 fla;\n+\n+\t/* Skip if we are in blank NVM programming mode */\n+\tfla = IXGBE_READ_REG(hw, GLNVM_FLA);\n+\tif ((fla & GLNVM_FLA_LOCKED_M) == 0)\n+\t\treturn IXGBE_SUCCESS;\n+\n+\treturn ixgbe_acquire_res(hw, IXGBE_NVM_RES_ID, access,\n+\t\t\t\t IXGBE_NVM_TIMEOUT);\n+}\n+\n+/**\n+ * ixgbe_release_nvm - Generic request for releasing the NVM ownership\n+ * @hw: pointer to the HW structure\n+ *\n+ * Release NVM ownership.\n+ */\n+void ixgbe_release_nvm(struct ixgbe_hw *hw)\n+{\n+\tu32 fla;\n+\n+\t/* Skip if we are in blank NVM programming mode */\n+\tfla = IXGBE_READ_REG(hw, GLNVM_FLA);\n+\tif ((fla & GLNVM_FLA_LOCKED_M) == 0)\n+\t\treturn;\n+\n+\tixgbe_release_res(hw, IXGBE_NVM_RES_ID);\n+}\n+\n+\n+/**\n+ * ixgbe_aci_read_nvm - read NVM\n+ * @hw: pointer to the HW struct\n+ * @module_typeid: module pointer location in words from the NVM beginning\n+ * @offset: byte offset from the module beginning\n+ * @length: length of the section to be read (in bytes from the offset)\n+ * @data: command buffer (size [bytes] = length)\n+ * @last_command: tells if this is the last command in a series\n+ * @read_shadow_ram: tell if this is a shadow RAM read\n+ *\n+ * Read the NVM using ACI command (0x0701).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,\n+\t\t u16 length, void *data, bool last_command,\n+\t\t bool read_shadow_ram)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\tstruct ixgbe_aci_cmd_nvm *cmd;\n+\n+\tcmd = &desc.params.nvm;\n+\n+\tif (offset > IXGBE_ACI_NVM_MAX_OFFSET)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read);\n+\n+\tif (!read_shadow_ram && module_typeid == IXGBE_ACI_NVM_START_POINT)\n+\t\tcmd->cmd_flags |= IXGBE_ACI_NVM_FLASH_ONLY;\n+\n+\t/* If this is the last command in a series, set the proper flag. */\n+\tif (last_command)\n+\t\tcmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD;\n+\tcmd->module_typeid = IXGBE_CPU_TO_LE16(module_typeid);\n+\tcmd->offset_low = IXGBE_CPU_TO_LE16(offset & 0xFFFF);\n+\tcmd->offset_high = (offset >> 16) & 0xFF;\n+\tcmd->length = IXGBE_CPU_TO_LE16(length);\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, data, length);\n+}\n+\n+/**\n+ * ixgbe_nvm_validate_checksum - validate checksum\n+ * @hw: pointer to the HW struct\n+ *\n+ * Verify NVM PFA checksum validity using ACI command (0x0706).\n+ * If the checksum verification failed, IXGBE_ERR_NVM_CHECKSUM is returned.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_nvm_checksum *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd = &desc.params.nvm_checksum;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum);\n+\tcmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\tif (!status)\n+\t\tif (IXGBE_LE16_TO_CPU(cmd->checksum) !=\n+\t\t IXGBE_ACI_NVM_CHECKSUM_CORRECT) {\n+\t\t\tERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,\n+\t\t\t\t \"Invalid Shadow Ram checksum\");\n+\t\t\tstatus = IXGBE_ERR_NVM_CHECKSUM;\n+\t\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using ixgbe_read_flat_nvm.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data)\n+{\n+\tu32 bytes = sizeof(u16);\n+\t__le16 data_local;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_flat_nvm(hw, offset * sizeof(u16), &bytes,\n+\t\t\t\t (u8 *)&data_local, true);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*data = IXGBE_LE16_TO_CPU(data_local);\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_flat_nvm - Read portion of NVM by flat offset\n+ * @hw: pointer to the HW struct\n+ * @offset: offset from beginning of NVM\n+ * @length: (in) number of bytes to read; (out) number of bytes actually read\n+ * @data: buffer to return data in (sized to fit the specified length)\n+ * @read_shadow_ram: if true, read from shadow RAM instead of NVM\n+ *\n+ * Reads a portion of the NVM, as a flat memory space. This function correctly\n+ * breaks read requests across Shadow RAM sectors, prevents Shadow RAM size\n+ * from being exceeded in case of Shadow RAM read requests and ensures that no\n+ * single read request exceeds the maximum 4KB read for a single admin command.\n+ *\n+ * Returns a status code on failure. Note that the data pointer may be\n+ * partially updated if some reads succeed before a failure.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,\n+\t\t\tu8 *data, bool read_shadow_ram)\n+{\n+\tu32 inlen = *length;\n+\tu32 bytes_read = 0;\n+\tbool last_cmd;\n+\ts32 status;\n+\n+\t*length = 0;\n+\n+\t/* Verify the length of the read if this is for the Shadow RAM */\n+\tif (read_shadow_ram && ((offset + inlen) >\n+\t\t\t\t(hw->eeprom.word_size * 2u))) {\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+\n+\tdo {\n+\t\tu32 read_size, sector_offset;\n+\n+\t\t/* ixgbe_aci_read_nvm cannot read more than 4KB at a time.\n+\t\t * Additionally, a read from the Shadow RAM may not cross over\n+\t\t * a sector boundary. Conveniently, the sector size is also 4KB.\n+\t\t */\n+\t\tsector_offset = offset % IXGBE_ACI_MAX_BUFFER_SIZE;\n+\t\tread_size = MIN_T(u32,\n+\t\t\t\t IXGBE_ACI_MAX_BUFFER_SIZE - sector_offset,\n+\t\t\t\t inlen - bytes_read);\n+\n+\t\tlast_cmd = !(bytes_read + read_size < inlen);\n+\n+\t\t/* ixgbe_aci_read_nvm takes the length as a u16. Our read_size\n+\t\t * is calculated using a u32, but the IXGBE_ACI_MAX_BUFFER_SIZE\n+\t\t * maximum size guarantees that it will fit within the 2 bytes.\n+\t\t */\n+\t\tstatus = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_START_POINT,\n+\t\t\t\t\t offset, (u16)read_size,\n+\t\t\t\t\t data + bytes_read, last_cmd,\n+\t\t\t\t\t read_shadow_ram);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\tbytes_read += read_size;\n+\t\toffset += read_size;\n+\t} while (!last_cmd);\n+\n+\t*length = bytes_read;\n+\treturn status;\n+}\n+\n /**\n * ixgbe_get_media_type_E610 - Gets media type\n * @hw: pointer to the HW struct\n@@ -2540,3 +2756,81 @@ s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw)\n \n \treturn status;\n }\n+\n+/**\n+ * ixgbe_read_ee_aci_E610 - Read EEPROM word using the admin command.\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n+ *\n+ * Reads a 16 bit word from the EEPROM using the ACI.\n+ * If the EEPROM params are not initialized, the function\n+ * initialize them before proceeding with reading.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data)\n+{\n+\ts32 status;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_sr_word_aci(hw, offset, data);\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_validate_eeprom_checksum_E610 - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n+ *\n+ * Performs checksum calculation and validates the EEPROM checksum. If the\n+ * caller does not need checksum_val, the value can be NULL.\n+ * If the EEPROM params are not initialized, the function\n+ * initialize them before proceeding.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val)\n+{\n+\tu32 status;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_nvm_validate_checksum(hw);\n+\n+\tif (status)\n+\t\treturn status;\n+\n+\tif (checksum_val) {\n+\t\tu16 tmp_checksum;\n+\t\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tstatus = ixgbe_read_sr_word_aci(hw, E610_SR_SW_CHECKSUM_WORD,\n+\t\t\t\t\t\t&tmp_checksum);\n+\t\tixgbe_release_nvm(hw);\n+\n+\t\tif (!status)\n+\t\t\t*checksum_val = tmp_checksum;\n+\t}\n+\n+\treturn status;\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.h b/drivers/net/ixgbe/base/ixgbe_e610.h\nindex 7327d92239..2c6e6b1bde 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.h\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.h\n@@ -45,7 +45,20 @@ s32 ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask);\n s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,\n \t\t\t u16 mem_addr, u8 page, u8 page_bank_ctrl, u8 *data,\n \t\t\t u8 length, bool write);\n+s32 ixgbe_acquire_nvm(struct ixgbe_hw *hw,\n+\t\t enum ixgbe_aci_res_access_type access);\n+void ixgbe_release_nvm(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,\n+\t\t u16 length, void *data, bool last_command,\n+\t\t bool read_shadow_ram);\n+\n+s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw);\n+s32 ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data);\n+s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,\n+\t\t\tu8 *data, bool read_shadow_ram);\n enum ixgbe_media_type ixgbe_get_media_type_E610(struct ixgbe_hw *hw);\n+u64 ixgbe_get_supported_physical_layer_E610(struct ixgbe_hw *hw);\n s32 ixgbe_setup_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n \t\t\t bool autoneg_wait);\n s32 ixgbe_check_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n@@ -77,5 +90,7 @@ s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw);\n s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,\n \t\t\t struct ixgbe_aci_cmd_get_link_topo *cmd,\n \t\t\t u8 *node_part_number, u16 *node_handle);\n+s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data);\n+s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val);\n \n #endif /* _IXGBE_E610_H_ */\n", "prefixes": [ "v2", "25/27" ] }