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GET /api/patches/139553/?format=api
{ "id": 139553, "url": "https://patches.dpdk.org/api/patches/139553/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240419195310.21432-2-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240419195310.21432-2-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240419195310.21432-2-andrew.boyer@amd.com", "date": "2024-04-19T19:53:05", "name": "[1/6] crypto/ionic: introduce AMD Pensando ionic crypto driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "b4d919f3d30038c2aa7b9d4e583fc8ad1827bd69", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240419195310.21432-2-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31795, "url": "https://patches.dpdk.org/api/series/31795/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31795", "date": "2024-04-19T19:53:04", "name": "crypto/ionic: introduce AMD Pensando ionic crypto driver", "version": 1, "mbox": "https://patches.dpdk.org/series/31795/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139553/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/139553/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EBF4843EB5;\n\tFri, 19 Apr 2024 21:53:47 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D2586406BC;\n\tFri, 19 Apr 2024 21:53:47 +0200 (CEST)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1nam02on2064.outbound.protection.outlook.com [40.107.96.64])\n by mails.dpdk.org (Postfix) with ESMTP id C942E406B8\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Akhil Goyal <gakhil@marvell.com>, Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH 1/6] crypto/ionic: introduce AMD Pensando ionic crypto driver", "Date": "Fri, 19 Apr 2024 12:53:05 -0700", "Message-ID": "<20240419195310.21432-2-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240419195310.21432-1-andrew.boyer@amd.com>", "References": "<20240419195310.21432-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF0000150B:EE_|PH0PR12MB8774:EE_", "X-MS-Office365-Filtering-Correlation-Id": "32906bc2-3fd4-41c1-d854-08dc60aa69da", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n NSrOJ4sdJwiZeyc2YAUZSsZDDQNl2YtzGjZn6MsLrkgnE/yep95+gPaq6B8ng1K99PbgMIpdHuUJrfwqLXPKb5sjgKHlzVEUu36Pv1jDT8m423hketGGZPgj4sda2YAMRkwODko9nUJsURgAugJZie0Z2xwKFpEPoztNLv3A1LoNsDPi5ZxVcyHEKILlXHMjYKEzn/uTKZCRkzNI2iWphpdSY9etfvzIVplurvVryoeWl3GZivdhStk1I/KB9q00QT26MkHinCUQqLwKAaYNHMh2dma+DnGSxPgk9mD0oiu629ziVVA3srET0ooC42lCrERrob3x8BuD/F/C6MFD2y4smzYtSiHwW6J/ILI02fXY1//ETKYmy/isxtKxJIMFbG7TyHwstbNkmrRtis8+EELusqZMgmv2hHql/ELl7c5Vbhsf7LDh2qrUua/fxMtKXwcgZDzLfNnuDhoqbOo1DgZoElhd0Qg+1z1h6Hvb2+Z1y/4PjesAVKuPZvFXu0NNpfkc47D29nvuuXMQmfoyoaOEsR9ltd3jHU99StA7wGVuWzZkwJ86yCUkaT46BN81pdv4c1828ItOvFeeccKOBFiLlIkmjFvzHiyG49vClw/EPoMDji1Hogkg69B4Y2wGenEHOBPt2GaVYNOoSlYH+Wy+2Z7uZmOFFyoMrTOP1JLQWce2jHk4wf2MoOOZsK5MoTx/ziOxzapjtSbVfHbAFH5hnAnfzOjMe+3+3ZTP+R89ei7sHw/7b1QgcVsyrt4y", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Apr 2024 19:53:41.5955 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 32906bc2-3fd4-41c1-d854-08dc60aa69da", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF0000150B.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB8774", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Introduce a new crypto PMD for AMD Pensando hardware accelerators. It\nallows applications running directly on the AMD Pensando DSC to offload\ncryptographic operations to hardware cryptographic blocks.\n\nThis commit adds the firmware interface definition file.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/crypto/ionic/ionic_crypto_if.h | 1021 ++++++++++++++++++++++++\n 1 file changed, 1021 insertions(+)\n create mode 100644 drivers/crypto/ionic/ionic_crypto_if.h", "diff": "diff --git a/drivers/crypto/ionic/ionic_crypto_if.h b/drivers/crypto/ionic/ionic_crypto_if.h\nnew file mode 100644\nindex 0000000000..ea418f3d4b\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_if.h\n@@ -0,0 +1,1021 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef _IONIC_CRYPTO_IF_H_\n+#define _IONIC_CRYPTO_IF_H_\n+\n+#define IOCPT_DEV_INFO_SIGNATURE\t\t0x43585660 /* 'CRPT' */\n+#define IOCPT_DEV_INFO_VERSION\t\t\t1\n+#define IOCPT_IFNAMSIZ\t\t\t\t16\n+\n+/**\n+ * enum iocpt_cmd_opcode - Device commands\n+ */\n+enum iocpt_cmd_opcode {\n+\tIOCPT_CMD_NOP\t\t\t\t= 0,\t/* D, A */\n+\n+\t/* Device commands */\n+\tIOCPT_CMD_IDENTIFY\t\t\t= 1,\t/* D */\n+\tIOCPT_CMD_RESET\t\t\t\t= 3,\t/* D */\n+\n+\t/* LIF commands */\n+\tIOCPT_CMD_LIF_IDENTIFY\t\t\t= 20,\t/* D */\n+\tIOCPT_CMD_LIF_INIT\t\t\t= 21,\t/* D */\n+\tIOCPT_CMD_LIF_RESET\t\t\t= 22,\t/* D */\n+\tIOCPT_CMD_LIF_GETATTR\t\t\t= 23,\t/* D, A */\n+\tIOCPT_CMD_LIF_SETATTR\t\t\t= 24,\t/* D, A */\n+\n+\t/* Queue commands */\n+\tIOCPT_CMD_Q_IDENTIFY\t\t\t= 39,\t/* D, A */\n+\tIOCPT_CMD_Q_INIT\t\t\t= 40,\t/* D, A */\n+\tIOCPT_CMD_Q_CONTROL\t\t\t= 41,\t/* D, A */\n+\n+\t/* Session commands */\n+\tIOCPT_CMD_SESS_CONTROL\t\t\t= 45,\t/* D, A */\n+};\n+\n+/**\n+ * enum iocpt_status_code - Device command return codes\n+ */\n+enum iocpt_status_code {\n+\tIOCPT_RC_SUCCESS\t= 0,\t/* Success */\n+\tIOCPT_RC_EVERSION\t= 1,\t/* Incorrect version for request */\n+\tIOCPT_RC_EOPCODE\t= 2,\t/* Invalid cmd opcode */\n+\tIOCPT_RC_EIO\t\t= 3,\t/* I/O error */\n+\tIOCPT_RC_EPERM\t\t= 4,\t/* Permission denied */\n+\tIOCPT_RC_EQID\t\t= 5,\t/* Bad qid */\n+\tIOCPT_RC_EQTYPE\t\t= 6,\t/* Bad qtype */\n+\tIOCPT_RC_ENOENT\t\t= 7,\t/* No such element */\n+\tIOCPT_RC_EINTR\t\t= 8,\t/* Operation interrupted */\n+\tIOCPT_RC_EAGAIN\t\t= 9,\t/* Try again */\n+\tIOCPT_RC_ENOMEM\t\t= 10,\t/* Out of memory */\n+\tIOCPT_RC_EFAULT\t\t= 11,\t/* Bad address */\n+\tIOCPT_RC_EBUSY\t\t= 12,\t/* Device or resource busy */\n+\tIOCPT_RC_EEXIST\t\t= 13,\t/* Object already exists */\n+\tIOCPT_RC_EINVAL\t\t= 14,\t/* Invalid argument */\n+\tIOCPT_RC_ENOSPC\t\t= 15,\t/* No space left or alloc failure */\n+\tIOCPT_RC_ERANGE\t\t= 16,\t/* Parameter out of range */\n+\tIOCPT_RC_BAD_ADDR\t= 17,\t/* Descriptor contains a bad ptr */\n+\tIOCPT_RC_DEV_CMD\t= 18,\t/* Device cmd attempted on AdminQ */\n+\tIOCPT_RC_ENOSUPP\t= 19,\t/* Operation not supported */\n+\tIOCPT_RC_ERROR\t\t= 29,\t/* Generic error */\n+};\n+\n+enum iocpt_notifyq_opcode {\n+\tIOCPT_EVENT_RESET\t\t= 1,\n+\tIOCPT_EVENT_HEARTBEAT\t\t= 2,\n+\tIOCPT_EVENT_LOG\t\t\t= 3,\n+};\n+\n+enum iocpt_lif_type {\n+\tIOCPT_LIF_TYPE_DEFAULT = 0,\n+};\n+\n+/**\n+ * struct iocpt_admin_cmd - General admin command format\n+ * @opcode:\tOpcode for the command\n+ * @lif_index:\tLIF index\n+ * @cmd_data:\tOpcode-specific command bytes\n+ */\n+struct iocpt_admin_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\tu8 cmd_data[60];\n+};\n+\n+/**\n+ * struct iocpt_admin_comp - General admin command completion format\n+ * @status: Status of the command (enum iocpt_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @cmd_data: Command-specific bytes\n+ * @color: Color bit (Always 0 for commands issued to the\n+ * Device Cmd Registers)\n+ */\n+struct iocpt_admin_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 cmd_data[11];\n+\tu8 color;\n+#define IOCPT_COMP_COLOR_MASK 0x80\n+};\n+\n+static inline u8 iocpt_color_match(u8 color, u8 done_color)\n+{\n+\treturn (!!(color & IOCPT_COMP_COLOR_MASK)) == done_color;\n+}\n+\n+/**\n+ * struct iocpt_nop_cmd - NOP command\n+ * @opcode:\tOpcode\n+ */\n+struct iocpt_nop_cmd {\n+\tu8 opcode;\n+\tu8 rsvd[63];\n+};\n+\n+/**\n+ * struct iocpt_nop_comp - NOP command completion\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ */\n+struct iocpt_nop_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+#define IOCPT_IDENTITY_VERSION_1\t1\n+\n+/**\n+ * struct iocpt_dev_identify_cmd - Driver/device identify command\n+ * @opcode:\tOpcode\n+ * @ver:\tHighest version of identify supported by driver\n+ */\n+struct iocpt_dev_identify_cmd {\n+\tu8 opcode;\n+\tu8 ver;\n+\tu8 rsvd[62];\n+};\n+\n+/**\n+ * struct iocpt_dev_identify_comp - Device identify command completion\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ * @ver:\tVersion of identify returned by device\n+ */\n+struct iocpt_dev_identify_comp {\n+\tu8 status;\n+\tu8 ver;\n+\tu8 rsvd[14];\n+};\n+\n+/**\n+ * struct iocpt_dev_reset_cmd - Device reset command\n+ * Will reset all LIFs on the device.\n+ * @opcode:\tOpcode\n+ */\n+struct iocpt_dev_reset_cmd {\n+\tu8 opcode;\n+\tu8 rsvd[63];\n+};\n+\n+/**\n+ * struct iocpt_dev_reset_comp - Reset command completion\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ */\n+struct iocpt_dev_reset_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+/**\n+ * struct iocpt_lif_identify_cmd - LIF identify command\n+ * @opcode:\tOpcode\n+ * @type:\tLIF type (enum iocpt_lif_type)\n+ * @lif_index:\tLIF index\n+ * @ver:\tVersion of identify returned by device\n+ */\n+struct iocpt_lif_identify_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\tu8 ver;\n+\tu8 rsvd[59];\n+};\n+\n+/**\n+ * struct iocpt_lif_identify_comp - LIF identify command completion\n+ * @status: Status of the command (enum iocpt_status_code)\n+ * @ver: Version of identify returned by device\n+ */\n+struct iocpt_lif_identify_comp {\n+\tu8 status;\n+\tu8 ver;\n+\tu8 rsvd2[14];\n+};\n+\n+/**\n+ * struct iocpt_lif_init_cmd - LIF init command\n+ * @opcode:\tOpcode\n+ * @type:\tLIF type (enum iocpt_lif_type)\n+ * @lif_index:\tLIF index\n+ * @info_pa:\tDestination address for LIF info (struct iocpt_lif_info)\n+ */\n+struct iocpt_lif_init_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\t__le32 rsvd;\n+\t__le64 info_pa;\n+\tu8 rsvd2[48];\n+};\n+\n+/**\n+ * struct iocpt_lif_init_comp - LIF init command completion\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ * @hw_index:\tHardware index of the initialized LIF\n+ */\n+struct iocpt_lif_init_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 hw_index;\n+\tu8 rsvd2[12];\n+};\n+\n+/**\n+ * struct iocpt_lif_reset_cmd - LIF reset command\n+ * Will reset only the specified LIF.\n+ * @opcode:\tOpcode\n+ * @lif_index:\tLIF index\n+ */\n+struct iocpt_lif_reset_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\t__le32 rsvd2[15];\n+};\n+\n+/**\n+ * enum iocpt_lif_attr - List of LIF attributes\n+ * @IOCPT_LIF_ATTR_STATE:\tLIF state attribute\n+ * @IOCPT_LIF_ATTR_NAME:\tLIF name attribute\n+ * @IOCPT_LIF_ATTR_FEATURES:\tLIF features attribute\n+ * @IOCPT_LIF_ATTR_STATS_CTRL:\tLIF statistics control attribute\n+ */\n+enum iocpt_lif_attr {\n+\tIOCPT_LIF_ATTR_STATE\t = 0,\n+\tIOCPT_LIF_ATTR_NAME\t = 1,\n+\tIOCPT_LIF_ATTR_FEATURES\t = 4,\n+\tIOCPT_LIF_ATTR_STATS_CTRL = 6,\n+};\n+\n+/**\n+ * struct iocpt_lif_setattr_cmd - Set LIF attributes on the NIC\n+ * @opcode:\tOpcode\n+ * @attr:\tAttribute type (enum iocpt_lif_attr)\n+ * @lif_index:\tLIF index\n+ * @state:\tLIF state (enum iocpt_lif_state)\n+ * @name:\tThe name string, 0 terminated\n+ * @features:\tFeatures (enum iocpt_hw_features)\n+ * @stats_ctl:\tStats control commands (enum iocpt_stats_ctl_cmd)\n+ */\n+struct iocpt_lif_setattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 lif_index;\n+\tunion {\n+\t\tu8\tstate;\n+\t\tchar\tname[IOCPT_IFNAMSIZ];\n+\t\t__le64\tfeatures;\n+\t\tu8\tstats_ctl;\n+\t\tu8\trsvd[60];\n+\t} __rte_packed;\n+};\n+\n+/**\n+ * struct iocpt_lif_setattr_comp - LIF set attr command completion\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @features:\tFeatures (enum iocpt_hw_features)\n+ * @color:\tColor bit\n+ */\n+struct iocpt_lif_setattr_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tunion {\n+\t\t__le64\tfeatures;\n+\t\tu8\trsvd2[11];\n+\t} __rte_packed;\n+\tu8 color;\n+};\n+\n+/**\n+ * struct iocpt_lif_getattr_cmd - Get LIF attributes from the NIC\n+ * @opcode:\tOpcode\n+ * @attr:\tAttribute type (enum iocpt_lif_attr)\n+ * @lif_index:\tLIF index\n+ */\n+struct iocpt_lif_getattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 lif_index;\n+\tu8 rsvd[60];\n+};\n+\n+/**\n+ * struct iocpt_lif_getattr_comp - LIF get attr command completion\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @state:\tLIF state (enum iocpt_lif_state)\n+ * @name:\tLIF name string, 0 terminated\n+ * @features:\tFeatures (enum iocpt_hw_features)\n+ * @color:\tColor bit\n+ */\n+struct iocpt_lif_getattr_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tunion {\n+\t\tu8\tstate;\n+\t\t__le64\tfeatures;\n+\t\tu8\trsvd2[11];\n+\t} __rte_packed;\n+\tu8 color;\n+};\n+\n+/**\n+ * enum iocpt_logical_qtype - Logical Queue Types\n+ * @IOCPT_QTYPE_ADMINQ: Administrative Queue\n+ * @IOCPT_QTYPE_NOTIFYQ: Notify Queue\n+ * @IOCPT_QTYPE_CRYPTOQ: Cryptographic Queue\n+ * @IOCPT_QTYPE_MAX: Max queue type supported\n+ */\n+enum iocpt_logical_qtype {\n+\tIOCPT_QTYPE_ADMINQ = 0,\n+\tIOCPT_QTYPE_NOTIFYQ = 1,\n+\tIOCPT_QTYPE_CRYPTOQ = 2,\n+\tIOCPT_QTYPE_MAX = 8,\n+};\n+\n+/**\n+ * struct iocpt_q_identify_cmd - queue identify command\n+ * @opcode: Opcode\n+ * @type: Logical queue type (enum iocpt_logical_qtype)\n+ * @lif_index: LIF index\n+ * @ver: Highest queue type version that the driver supports\n+ */\n+struct iocpt_q_identify_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\tu8 ver;\n+\tu8 rsvd2[59];\n+};\n+\n+/**\n+ * struct iocpt_q_identify_comp - queue identify command completion\n+ * @status: Status of the command (enum iocpt_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @ver: Queue type version that can be used with FW\n+ */\n+struct iocpt_q_identify_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 ver;\n+\tu8 rsvd2[11];\n+};\n+\n+/**\n+ * struct iocpt_q_init_cmd - Queue init command\n+ * @opcode: Opcode\n+ * @type: Logical queue type\n+ * @lif_index: LIF index\n+ * @ver: Queue type version\n+ * @index: (LIF, qtype) relative admin queue index\n+ * @intr_index: Interrupt control register index, or Event queue index\n+ * @pid: Process ID\n+ * @flags:\n+ * IRQ: Interrupt requested on completion\n+ * ENA: Enable the queue. If ENA=0 the queue is initialized\n+ * but remains disabled, to be later enabled with the\n+ * Queue Enable command. If ENA=1, then queue is\n+ * initialized and then enabled.\n+ * SG: Enable Scatter-Gather on the queue.\n+ * @cos: Class of service for this queue\n+ * @ring_size: Queue ring size, encoded as a log2(size), in\n+ * number of descriptors. The actual ring size is\n+ * (1 << ring_size). For example, to select a ring size\n+ * of 64 descriptors write ring_size = 6. The minimum\n+ * ring_size value is 2 for a ring of 4 descriptors.\n+ * The maximum ring_size value is 12 for a ring of 4k\n+ * descriptors. Values of ring_size <2 and >12 are\n+ * reserved.\n+ * @ring_base: Queue ring base address\n+ * @cq_ring_base: Completion queue ring base address\n+ * @sg_ring_base: Scatter/Gather ring base address\n+ */\n+struct iocpt_q_init_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\tu8 ver;\n+\tu8 rsvd[3];\n+\t__le32 index;\n+\t__le16 pid;\n+\t__le16 intr_index;\n+\t__le16 flags;\n+#define IOCPT_QINIT_F_IRQ\t0x01\t/* Request interrupt on completion */\n+#define IOCPT_QINIT_F_ENA\t0x02\t/* Enable the queue */\n+#define IOCPT_QINIT_F_SG\t0x04\t/* Enable scatter/gather on queue */\n+\tu8 cos;\n+#define IOCPT_QSIZE_MIN_LG2\t2\n+#define IOCPT_QSIZE_MAX_LG2\t12\n+\tu8 ring_size;\n+\t__le64 ring_base;\n+\t__le64 cq_ring_base;\n+\t__le64 sg_ring_base;\n+\tu8 rsvd2[20];\n+} __rte_packed;\n+\n+/**\n+ * struct iocpt_q_init_comp - Queue init command completion\n+ * @status: Status of the command (enum iocpt_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @hw_index: Hardware Queue ID\n+ * @hw_type: Hardware Queue type\n+ * @color: Color\n+ */\n+struct iocpt_q_init_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\t__le32 hw_index;\n+\tu8 hw_type;\n+\tu8 rsvd2[6];\n+\tu8 color;\n+};\n+\n+enum iocpt_desc_opcode {\n+\tIOCPT_DESC_OPCODE_GCM_AEAD_ENCRYPT = 0,\n+\tIOCPT_DESC_OPCODE_GCM_AEAD_DECRYPT = 1,\n+\tIOCPT_DESC_OPCODE_XTS_ENCRYPT = 2,\n+\tIOCPT_DESC_OPCODE_XTS_DECRYPT = 3,\n+};\n+\n+#define IOCPT_DESC_F_AAD_VALID\t\t0x1\n+\n+/**\n+ * struct iocpt_desc - Crypto queue descriptor format\n+ * @opcode:\n+ * IOCPT_DESC_OPCODE_GCM_AEAD_ENCRYPT:\n+ * Perform a GCM-AES encrypt operation\n+ *\n+ * IOCPT_DESC_OPCODE_GCM_AEAD_DECRYPT:\n+ * Perform a GCM-AES decrypt operation\n+ *\n+ * IOCPT_DESC_OPCODE_XTS_ENCRYPT:\n+ * Perform an XTS encrypt operation\n+ *\n+ * IOCPT_DESC_OPCODE_XTS_DECRYPT:\n+ * Perform an XTS decrypt operation\n+ * @flags:\n+ * IOCPT_DESC_F_AAD_VALID:\n+ * Source SGL contains an AAD addr and length\n+ * @num_src_dst_sgs: Number of scatter-gather elements in SG\n+ * descriptor (4 bits for source, 4 bits for destination)\n+ * @session_tag: Session tag (key index)\n+ * @intr_ctx_addr: Completion interrupt context address\n+ * @intr_ctx_data: Completion interrupt context data\n+ */\n+struct iocpt_crypto_desc {\n+\tuint8_t opcode;\n+\tuint8_t flags;\n+\tuint8_t num_src_dst_sgs;\n+#define IOCPT_DESC_NSGE_SRC_MASK\t0xf\n+#define IOCPT_DESC_NSGE_SRC_SHIFT\t0\n+#define IOCPT_DESC_NSGE_DST_MASK\t0xf\n+#define IOCPT_DESC_NSGE_DST_SHIFT\t4\n+\tuint8_t rsvd[9];\n+\t__le32 session_tag;\n+\t__le64 intr_ctx_addr;\n+\t__le64 intr_ctx_data;\n+} __rte_packed;\n+\n+static inline uint8_t iocpt_encode_nsge_src_dst(uint8_t src, uint8_t dst)\n+{\n+\tuint8_t nsge_src_dst;\n+\n+\tnsge_src_dst = (src & IOCPT_DESC_NSGE_SRC_MASK) <<\n+\t\tIOCPT_DESC_NSGE_SRC_SHIFT;\n+\tnsge_src_dst |= (dst & IOCPT_DESC_NSGE_DST_MASK) <<\n+\t\tIOCPT_DESC_NSGE_DST_SHIFT;\n+\n+\treturn nsge_src_dst;\n+};\n+\n+static inline void iocpt_decode_nsge_src_dst(uint8_t nsge_src_dst,\n+\t\t\t\t\t uint8_t *src, uint8_t *dst)\n+{\n+\t*src = (nsge_src_dst >> IOCPT_DESC_NSGE_SRC_SHIFT) &\n+\t\tIOCPT_DESC_NSGE_SRC_MASK;\n+\t*dst = (nsge_src_dst >> IOCPT_DESC_NSGE_DST_SHIFT) &\n+\t\tIOCPT_DESC_NSGE_DST_MASK;\n+};\n+\n+/**\n+ * struct iocpt_crypto_sg_elem - Crypto scatter-gather (SG) descriptor element\n+ * @addr:\tDMA address of SG element data buffer\n+ * @len:\tLength of SG element data buffer, in bytes\n+ */\n+struct iocpt_crypto_sg_elem {\n+\t__le64 addr;\n+\t__le16 len;\n+\tuint8_t rsvd[6];\n+};\n+\n+/**\n+ * struct iocpt_crypto_sg_desc - Crypto scatter-gather (SG) list\n+ * @src_elems: Source SG elements; also destination in IP case\n+ * AES_GCM:\n+ * SGE0: Nonce\n+ * SGE1: AAD (see IOCPT_DESC_F_AAD_VALID)\n+ * SGE2 to SGE(N): Payload\n+ * SGE(N+1): Auth tag\n+ * @dst_elems: Destination SG elements for OOP case; unused in IP case\n+ */\n+struct iocpt_crypto_sg_desc {\n+#define IOCPT_CRYPTO_MAX_SG_ELEMS\t8\n+#define IOCPT_CRYPTO_NONCE_ELEM\t\t0\n+#define IOCPT_CRYPTO_AAD_ELEM\t\t1\n+\tstruct iocpt_crypto_sg_elem src_elems[IOCPT_CRYPTO_MAX_SG_ELEMS];\n+\tstruct iocpt_crypto_sg_elem dst_elems[IOCPT_CRYPTO_MAX_SG_ELEMS];\n+};\n+\n+/**\n+ * struct iocpt_crypto_comp - Crypto queue completion descriptor\n+ * @status:\tStatus of the command (enum iocpt_status_code)\n+ * @comp_index:\tIndex in the descriptor ring for which this is the completion\n+ * @color:\tColor bit\n+ */\n+struct iocpt_crypto_comp {\n+#define IOCPT_COMP_SUCCESS\t\t\t0\n+#define IOCPT_COMP_INVAL_OPCODE_ERROR\t\t1\n+#define IOCPT_COMP_UNSUPP_OPCODE_ERROR\t\t2\n+#define IOCPT_COMP_SYMM_SRC_SG_ERROR\t\t3\n+#define IOCPT_COMP_SYMM_DST_SG_ERROR\t\t4\n+#define IOCPT_COMP_SYMM_SRC_DST_LEN_MISMATCH\t5\n+#define IOCPT_COMP_SYMM_HW_QAVAIL_ERROR\t\t6\n+#define IOCPT_COMP_SYMM_AUTH_VERIFY_ERROR\t7\n+#define IOCPT_COMP_SYMM_OTHER_VERIFY_ERROR\t8\n+#define IOCPT_COMP_SYMM_PI_MODE_CHKSUM_ERROR\t9\n+#define IOCPT_COMP_SYMM_HARDWARE_ERROR\t\t10\n+#define IOCPT_COMP_SYMM_KEY_IDX_ERROR\t\t11\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 rsvd2[11];\n+\tu8 color;\n+};\n+\n+/**\n+ * enum iocpt_hw_features - Feature flags supported by hardware\n+ * @IOCPT_HW_SYM: Symmetric crypto operations\n+ * @IOCPT_HW_ASYM: Asymmetric crypto operations\n+ * @IOCPT_HW_CHAIN: Chained crypto operations\n+ * @IOCPT_HW_IP: In-Place (destination same as source)\n+ * @IOCPT_HW_OOP: Out-Of-Place (destination differs from source)\n+ */\n+enum iocpt_hw_features {\n+\tIOCPT_HW_SYM = BIT(0),\n+\tIOCPT_HW_ASYM = BIT(1),\n+\tIOCPT_HW_CHAIN = BIT(2),\n+\tIOCPT_HW_IP = BIT(3),\n+\tIOCPT_HW_OOP = BIT(4),\n+};\n+\n+/**\n+ * struct iocpt_q_control_cmd - Queue control command\n+ * @opcode:\tOpcode\n+ * @type:\tQueue type\n+ * @lif_index:\tLIF index\n+ * @index:\tQueue index\n+ * @oper:\tOperation (enum iocpt_q_control_oper)\n+ */\n+struct iocpt_q_control_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\t__le32 index;\n+\tu8 oper;\n+\tu8 rsvd2[55];\n+};\n+\n+enum iocpt_q_control_oper {\n+\tIOCPT_Q_DISABLE\t\t= 0,\n+\tIOCPT_Q_ENABLE\t\t= 1,\n+};\n+\n+/* NB: It will take 64 transfers to update a 2048B key */\n+#define IOCPT_SESS_KEY_LEN_MIN\t\t16\n+#define IOCPT_SESS_KEY_LEN_MAX_SYMM\t32\n+#define IOCPT_SESS_KEY_LEN_MAX_ASYM\t2048\n+#define IOCPT_SESS_KEY_SEG_LEN\t\t32\n+#define IOCPT_SESS_KEY_SEG_SHFT\t\t5\n+#define IOCPT_SESS_KEY_SEG_CNT\t\t\\\n+\t(IOCPT_SESS_KEY_LEN_MAX_SYMM >> IOCPT_SESS_KEY_SEG_SHFT)\n+\n+enum iocpt_sess_type {\n+\tIOCPT_SESS_NONE\t\t\t= 0,\n+\tIOCPT_SESS_AEAD_AES_GCM\t\t= 1,\n+};\n+\n+enum iocpt_sess_control_oper {\n+\tIOCPT_SESS_INIT\t\t\t= 0,\n+\tIOCPT_SESS_UPDATE_KEY\t\t= 2,\n+\tIOCPT_SESS_DISABLE\t\t= 3,\n+};\n+\n+/**\n+ * struct iocpt_sess_control_cmd - Session control command\n+ * @opcode: Opcode\n+ * @type: Session type (enum iocpt_sess_type)\n+ * @lif_index: LIF index\n+ * @oper: Operation (enum iocpt_sess_control_oper)\n+ * @flags:\n+ * END: Indicates that this is the final segment of the key.\n+ * When this flag is set, a write will be triggered from the\n+ * controller's memory into the dedicated key-storage area.\n+ * @key_len: Crypto key length in bytes\n+ * @index: Session index, as allocated by PMD\n+ * @key_seg_len: Crypto key segment length in bytes\n+ * @key_seg_idx: Crypto key segment index\n+ * @key: Crypto key\n+ */\n+struct iocpt_sess_control_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\tu8 oper;\n+\tu8 flags;\n+#define IOCPT_SCTL_F_END\t0x01\t/* Final segment of key */\n+\t__le16 key_len;\n+\t__le32 index;\n+\tu8 key_seg_len;\n+\tu8 key_seg_idx;\n+\tu8 rsvd[18];\n+\tu8 key[IOCPT_SESS_KEY_SEG_LEN];\n+};\n+\n+/**\n+ * struct iocpt_sess_control_comp - Session control command completion\n+ * @status: Status of the command (enum iocpt_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @index: Session index\n+ * @hw_type: Hardware Session type\n+ * @color: Color\n+ */\n+struct iocpt_sess_control_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\t__le32 index;\n+\tu8 hw_type;\n+\tu8 rsvd2[6];\n+\tu8 color;\n+};\n+\n+/**\n+ * enum iocpt_stats_ctl_cmd - List of commands for stats control\n+ * @IOCPT_STATS_CTL_RESET: Reset statistics\n+ */\n+enum iocpt_stats_ctl_cmd {\n+\tIOCPT_STATS_CTL_RESET\t\t= 0,\n+};\n+\n+/**\n+ * struct iocpt_dev_status - Device status register\n+ * @eid: most recent NotifyQ event id\n+ */\n+struct iocpt_dev_status {\n+\t__le64 eid;\n+\tu8 rsvd2[56];\n+};\n+\n+enum iocpt_dev_state {\n+\tIOCPT_DEV_DISABLE\t= 0,\n+\tIOCPT_DEV_ENABLE\t= 1,\n+\tIOCPT_DEV_HANG_RESET\t= 2,\n+};\n+\n+/**\n+ * enum iocpt_dev_attr - List of device attributes\n+ * @IOCPT_DEV_ATTR_STATE: Device state attribute\n+ * @IOCPT_DEV_ATTR_NAME: Device name attribute\n+ * @IOCPT_DEV_ATTR_FEATURES: Device feature attributes\n+ */\n+enum iocpt_dev_attr {\n+\tIOCPT_DEV_ATTR_STATE = 0,\n+\tIOCPT_DEV_ATTR_NAME = 1,\n+\tIOCPT_DEV_ATTR_FEATURES = 2,\n+};\n+\n+/**\n+ * struct iocpt_notify_event - Generic event reporting structure\n+ * @eid: event number\n+ * @ecode: event code\n+ * @data: unspecified data about the event\n+ *\n+ * This is the generic event report struct from which the other\n+ * actual events will be formed.\n+ */\n+struct iocpt_notify_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 data[54];\n+};\n+\n+/**\n+ * struct iocpt_reset_event - Reset event notification\n+ * @eid:\t\tevent number\n+ * @ecode:\t\tevent code = IOCPT_EVENT_RESET\n+ * @reset_code:\t\treset type\n+ * @state:\t\t0=pending, 1=complete, 2=error\n+ *\n+ * Sent when the NIC or some subsystem is going to be or\n+ * has been reset.\n+ */\n+struct iocpt_reset_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 reset_code;\n+\tu8 state;\n+\tu8 rsvd[52];\n+};\n+\n+/**\n+ * struct iocpt_heartbeat_event - Sent periodically by NIC to indicate health\n+ * @eid:\tevent number\n+ * @ecode:\tevent code = IOCPT_EVENT_HEARTBEAT\n+ */\n+struct iocpt_heartbeat_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 rsvd[54];\n+};\n+\n+/**\n+ * struct iocpt_log_event - Sent to notify the driver of an internal error\n+ * @eid:\tevent number\n+ * @ecode:\tevent code = IOCPT_EVENT_LOG\n+ * @data:\tlog data\n+ */\n+struct iocpt_log_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 data[54];\n+};\n+\n+/**\n+ * union iocpt_lif_config - LIF configuration\n+ * @state:\t LIF state (enum iocpt_lif_state)\n+ * @name:\t LIF name\n+ * @features:\t LIF features active (enum iocpt_hw_features)\n+ * @queue_count: Queue counts per queue-type\n+ */\n+union iocpt_lif_config {\n+\tstruct {\n+\t\tu8 state;\n+\t\tu8 rsvd[3];\n+\t\tchar name[IOCPT_IFNAMSIZ];\n+\t\tu8 rsvd2[12];\n+\t\t__le64 features;\n+\t\t__le32 queue_count[IOCPT_QTYPE_MAX];\n+\t} __rte_packed;\n+\t__le32 words[56];\n+};\n+\n+/**\n+ * struct iocpt_lif_status - LIF status register\n+ * @eid:\t most recent NotifyQ event id\n+ */\n+struct iocpt_lif_status {\n+\t__le64 eid;\n+\tu8 rsvd[56];\n+};\n+\n+/**\n+ * struct iocpt_lif_info - LIF info structure\n+ * @config:\tLIF configuration structure\n+ * @status:\tLIF status structure\n+ * @stats:\tLIF statistics structure\n+ */\n+struct iocpt_lif_info {\n+\tunion iocpt_lif_config config;\n+\tstruct iocpt_lif_status status;\n+};\n+\n+union iocpt_dev_cmd {\n+\tu32 words[16];\n+\tstruct iocpt_admin_cmd cmd;\n+\tstruct iocpt_nop_cmd nop;\n+\n+\tstruct iocpt_dev_identify_cmd identify;\n+\tstruct iocpt_dev_reset_cmd reset;\n+\n+\tstruct iocpt_lif_identify_cmd lif_identify;\n+\tstruct iocpt_lif_init_cmd lif_init;\n+\tstruct iocpt_lif_reset_cmd lif_reset;\n+\tstruct iocpt_lif_getattr_cmd lif_getattr;\n+\tstruct iocpt_lif_setattr_cmd lif_setattr;\n+\n+\tstruct iocpt_q_identify_cmd q_identify;\n+\tstruct iocpt_q_init_cmd q_init;\n+\tstruct iocpt_q_control_cmd q_control;\n+\n+\tstruct iocpt_sess_control_cmd sess_control;\n+};\n+\n+union iocpt_dev_cmd_comp {\n+\tu32 words[4];\n+\tu8 status;\n+\tstruct iocpt_admin_comp comp;\n+\tstruct iocpt_nop_comp nop;\n+\n+\tstruct iocpt_dev_identify_comp identify;\n+\tstruct iocpt_dev_reset_comp reset;\n+\n+\tstruct iocpt_lif_identify_comp lif_identify;\n+\tstruct iocpt_lif_init_comp lif_init;\n+\tstruct iocpt_lif_getattr_comp lif_getattr;\n+\tstruct iocpt_lif_setattr_comp lif_setattr;\n+\n+\tstruct iocpt_q_identify_comp q_identify;\n+\tstruct iocpt_q_init_comp q_init;\n+\n+\tstruct iocpt_sess_control_comp sess_control;\n+};\n+\n+/**\n+ * union iocpt_dev_info_regs - Device info register format (read-only)\n+ * @signature: Signature value of 0x43585660 ('CRPT')\n+ * @version: Current version of info\n+ * @asic_type: Asic type\n+ * @asic_rev: Asic revision\n+ * @fw_status: Firmware status\n+ * @fw_heartbeat: Firmware heartbeat counter\n+ * @serial_num: Serial number\n+ * @fw_version: Firmware version\n+ */\n+union iocpt_dev_info_regs {\n+#define IOCPT_FWVERS_BUFLEN 32\n+#define IOCPT_SERIAL_BUFLEN 32\n+\tstruct {\n+\t\tu32 signature;\n+\t\tu8 version;\n+\t\tu8 asic_type;\n+\t\tu8 asic_rev;\n+#define IOCPT_FW_STS_F_RUNNING\t0x1\n+\t\tu8 fw_status;\n+\t\tu32 fw_heartbeat;\n+\t\tchar fw_version[IOCPT_FWVERS_BUFLEN];\n+\t\tchar serial_num[IOCPT_SERIAL_BUFLEN];\n+\t};\n+\tu32 words[512];\n+};\n+\n+/**\n+ * union iocpt_dev_cmd_regs - Device command register format (read-write)\n+ * @doorbell: Device Cmd Doorbell, write-only\n+ * Write a 1 to signal device to process cmd,\n+ * poll done for completion.\n+ * @done: Done indicator, bit 0 == 1 when command is complete\n+ * @cmd: Opcode-specific command bytes\n+ * @comp: Opcode-specific response bytes\n+ * @data: Opcode-specific side-data\n+ */\n+union iocpt_dev_cmd_regs {\n+\tstruct {\n+\t\tu32 doorbell;\n+\t\tu32 done;\n+\t\tunion iocpt_dev_cmd cmd;\n+\t\tunion iocpt_dev_cmd_comp comp;\n+\t\tu8 rsvd[48];\n+\t\tu32 data[478];\n+\t} __rte_packed;\n+\tu32 words[512];\n+};\n+\n+/**\n+ * union iocpt_dev_regs - Device register format for bar 0 page 0\n+ * @info: Device info registers\n+ * @devcmd: Device command registers\n+ */\n+union iocpt_dev_regs {\n+\tstruct {\n+\t\tunion iocpt_dev_info_regs info;\n+\t\tunion iocpt_dev_cmd_regs devcmd;\n+\t} __rte_packed;\n+\t__le32 words[1024];\n+};\n+\n+union iocpt_adminq_cmd {\n+\tstruct iocpt_admin_cmd cmd;\n+\tstruct iocpt_nop_cmd nop;\n+\tstruct iocpt_q_identify_cmd q_identify;\n+\tstruct iocpt_q_init_cmd q_init;\n+\tstruct iocpt_q_control_cmd q_control;\n+\tstruct iocpt_lif_setattr_cmd lif_setattr;\n+\tstruct iocpt_lif_getattr_cmd lif_getattr;\n+\tstruct iocpt_sess_control_cmd sess_control;\n+};\n+\n+union iocpt_adminq_comp {\n+\tstruct iocpt_admin_comp comp;\n+\tstruct iocpt_nop_comp nop;\n+\tstruct iocpt_q_identify_comp q_identify;\n+\tstruct iocpt_q_init_comp q_init;\n+\tstruct iocpt_lif_setattr_comp lif_setattr;\n+\tstruct iocpt_lif_getattr_comp lif_getattr;\n+\tstruct iocpt_sess_control_comp sess_control;\n+};\n+\n+union iocpt_notify_comp {\n+\tstruct iocpt_notify_event event;\n+\tstruct iocpt_reset_event reset;\n+\tstruct iocpt_heartbeat_event heartbeat;\n+\tstruct iocpt_log_event log;\n+};\n+\n+/**\n+ * union iocpt_dev_identity - device identity information\n+ * @version: Version of device identify\n+ * @type: Identify type (0 for now)\n+ * @state: Device state\n+ * @nlifs: Number of LIFs provisioned\n+ * @nintrs: Number of interrupts provisioned\n+ * @ndbpgs_per_lif: Number of doorbell pages per LIF\n+ * @intr_coal_mult: Interrupt coalescing multiplication factor\n+ * Scale user-supplied interrupt coalescing\n+ * value in usecs to device units using:\n+ * device units = usecs * mult / div\n+ * @intr_coal_div: Interrupt coalescing division factor\n+ * Scale user-supplied interrupt coalescing\n+ * value in usecs to device units using:\n+ * device units = usecs * mult / div\n+ */\n+union iocpt_dev_identity {\n+\tstruct {\n+\t\tu8 version;\n+\t\tu8 type;\n+\t\tu8 state;\n+\t\tu8 rsvd;\n+\t\t__le32 nlifs;\n+\t\t__le32 nintrs;\n+\t\t__le32 ndbpgs_per_lif;\n+\t\t__le32 intr_coal_mult;\n+\t\t__le32 intr_coal_div;\n+\t\tu8 rsvd2[8];\n+\t};\n+\t__le32 words[8];\n+};\n+\n+/**\n+ * union iocpt_lif_identity - LIF identity information (type-specific)\n+ *\n+ * @features: LIF features (see enum iocpt_hw_features)\n+ * @version: Identify structure version\n+ * @hw_index: LIF hardware index\n+ * @max_nb_sessions: Maximum number of sessions supported\n+ * @config: LIF config struct with features, q counts\n+ */\n+union iocpt_lif_identity {\n+\tstruct {\n+\t\t__le64 features;\n+\n+\t\tu8 version;\n+\t\tu8 hw_index;\n+\t\tu8 rsvd[2];\n+\t\t__le32 max_nb_sessions;\n+\t\tu8 rsvd2[120];\n+\t\tunion iocpt_lif_config config;\n+\t} __rte_packed;\n+\t__le32 words[90];\n+};\n+\n+/**\n+ * union iocpt_q_identity - queue identity information\n+ * @version: Queue type version that can be used with FW\n+ * @supported: Bitfield of queue versions, first bit = ver 0\n+ * @features: Queue features\n+ * @desc_sz: Descriptor size\n+ * @comp_sz: Completion descriptor size\n+ * @sg_desc_sz: Scatter/Gather descriptor size\n+ * @max_sg_elems: Maximum number of Scatter/Gather elements\n+ * @sg_desc_stride: Number of Scatter/Gather elements per descriptor\n+ */\n+union iocpt_q_identity {\n+\tstruct {\n+\t\tu8 version;\n+\t\tu8 supported;\n+\t\tu8 rsvd[6];\n+#define IOCPT_QIDENT_F_CQ\t0x01\t/* queue has completion ring */\n+#define IOCPT_QIDENT_F_SG\t0x02\t/* queue has scatter/gather ring */\n+\t\t__le64 features;\n+\t\t__le16 desc_sz;\n+\t\t__le16 comp_sz;\n+\t\t__le16 sg_desc_sz;\n+\t\t__le16 max_sg_elems;\n+\t\t__le16 sg_desc_stride;\n+\t};\n+\t__le32 words[20];\n+};\n+\n+struct iocpt_identity {\n+\tunion iocpt_dev_identity dev;\n+\tunion iocpt_lif_identity lif;\n+\tunion iocpt_q_identity q;\n+};\n+\n+#endif /* _IONIC_CRYPTO_IF_H_ */\n", "prefixes": [ "1/6" ] }