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GET /api/patches/139266/?format=api
{ "id": 139266, "url": "https://patches.dpdk.org/api/patches/139266/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240412125249.10625-17-VenkatKumar.Ande@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240412125249.10625-17-VenkatKumar.Ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240412125249.10625-17-VenkatKumar.Ande@amd.com", "date": "2024-04-12T12:52:42", "name": "[17/24] net/axgbe: flow Tx Ctrl Registers are h/w ver dependent", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "baea71f55831d675029b3c2baa0fa6a0c7e07c58", "submitter": { "id": 3256, "url": "https://patches.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240412125249.10625-17-VenkatKumar.Ande@amd.com/mbox/", "series": [ { "id": 31734, "url": "https://patches.dpdk.org/api/series/31734/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31734", "date": "2024-04-12T12:52:26", "name": "[01/24] net/axgbe: remove use of comm_owned field", "version": 1, "mbox": "https://patches.dpdk.org/series/31734/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139266/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/139266/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E40FB43E52;\n\tFri, 12 Apr 2024 14:55:24 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3A29742D6B;\n\tFri, 12 Apr 2024 14:54:33 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2065.outbound.protection.outlook.com [40.107.236.65])\n by mails.dpdk.org (Postfix) with ESMTP id 2F5DD41104\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Venkat Kumar Ande <VenkatKumar.Ande@amd.com>", "To": "<dev@dpdk.org>", "CC": "<Selwin.Sebastian@amd.com>, Venkat Kumar Ande <VenkatKumar.Ande@amd.com>", "Subject": "[PATCH 17/24] net/axgbe: flow Tx Ctrl Registers are h/w ver dependent", "Date": "Fri, 12 Apr 2024 08:52:42 -0400", "Message-ID": "<20240412125249.10625-17-VenkatKumar.Ande@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240412125249.10625-1-VenkatKumar.Ande@amd.com>", "References": "<20240412125249.10625-1-VenkatKumar.Ande@amd.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF00020E5F:EE_|MN2PR12MB4454:EE_", "X-MS-Office365-Filtering-Correlation-Id": "89353880-0614-4d60-733c-08dc5aefab9c", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n L/bjnPn5x+8O0Vu4+xIUcs0FZsrfFl0lEVX1qH+MAKbNN+rTSJsPazOuT4xH3Jtw1+dqARsGqbrqQZq/eRFtl468osIB+n3Rr2z/yfiPNeKMSrEkHKoRDIg7ZJv5VyO6l/9W3TvCdIpuJwO8PCOZmoUrsodhsP6sqqJ6tlxcxDj+HpqU/CvWijMrbObe/V44xNbtCnXrp/yuo1t/vxUN3Ohc3SK3RARVHkSO+xgKCqHHD+ItpgOipwqq+HRBmxy3fsJ1dMmfPG7ijevmf+D87fgaddYbMs0rpea6SJT8zzt6Jwv3hnAnKAqfr/qeupoaecnCGv4JZ8iuCEQrXdOrFrgZeynNkVJcBXD4HAPylOdPxhw1Xnur0j363PJ5b7Q0hWcF3/uwpzEIHZcPIlHQeoosUKvTbb/DmC3SrdHH8WrVHxQyT+ZhSbM4RBzkIXGN98tzwxCN8OOVCiXZGxLWhvTRm+y505fx7JdUOYzVhjuAazOFAVDPk//BX/qA/gtkzrnaLCkNi6AFPDokFjAYba7/Ek8s5EyziozkRAsjrdGH0vuF46j/6HUmPTVa5fs1yKd52abVC70Sc2KAC8a3w63VfmrRdAak/EJlp5AHDLJBFy0FtjPJF7gq+cxKKMUdDoXYu+gKmT6Qvhcg69gbMyLEYky1NWZuD3Cw9qoWfXkFXdXfrwU7wZOvtqiz3S3CT7bSyJgebve3lcfD5+DxuKO+nyIUGtwijwD1TYpc8z9AoGG9PpKJRMMSpn0KUBKJ", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(376005)(1800799015)(82310400014)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Apr 2024 12:54:20.2139 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 89353880-0614-4d60-733c-08dc5aefab9c", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL6PEPF00020E5F.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4454", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is difference in the TX Flow Control registers (TFCR) between the\nrevisions of the hardware. The older revisions of hardware used to have\nsingle register per queue. Whereas, the newer revision of hardware (from\nver 30H onwards) have one register per priority.\n\nSigned-off-by: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>\n---\n drivers/net/axgbe/axgbe_dev.c | 25 +++++++++++++++----------\n 1 file changed, 15 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c\nindex b4afcf20ab..6b413160c2 100644\n--- a/drivers/net/axgbe/axgbe_dev.c\n+++ b/drivers/net/axgbe/axgbe_dev.c\n@@ -272,20 +272,28 @@ static int axgbe_set_speed(struct axgbe_port *pdata, int speed)\n \treturn 0;\n }\n \n+static unsigned int axgbe_get_fc_queue_count(struct axgbe_port *pdata)\n+{\n+\tunsigned int max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;\n+\n+\t/* From MAC ver 30H the TFCR is per priority, instead of per queue */\n+\tif (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30)\n+\t\treturn max_q_count;\n+\telse\n+\t\treturn (RTE_MIN(pdata->tx_q_count, max_q_count));\n+}\n+\n static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata)\n {\n-\tunsigned int max_q_count, q_count;\n \tunsigned int reg, reg_val;\n-\tunsigned int i;\n+\tunsigned int i, q_count;\n \n \t/* Clear MTL flow control */\n \tfor (i = 0; i < pdata->rx_q_count; i++)\n \t\tAXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);\n \n \t/* Clear MAC flow control */\n-\tmax_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;\n-\tq_count = RTE_MIN(pdata->tx_q_count,\n-\t\t\tmax_q_count);\n+\tq_count = axgbe_get_fc_queue_count(pdata);\n \treg = MAC_Q0TFCR;\n \tfor (i = 0; i < q_count; i++) {\n \t\treg_val = AXGMAC_IOREAD(pdata, reg);\n@@ -300,9 +308,8 @@ static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata)\n \n static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)\n {\n-\tunsigned int max_q_count, q_count;\n \tunsigned int reg, reg_val;\n-\tunsigned int i;\n+\tunsigned int i, q_count;\n \n \t/* Set MTL flow control */\n \tfor (i = 0; i < pdata->rx_q_count; i++) {\n@@ -319,9 +326,7 @@ static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)\n \t}\n \n \t/* Set MAC flow control */\n-\tmax_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;\n-\tq_count = RTE_MIN(pdata->tx_q_count,\n-\t\t\tmax_q_count);\n+\tq_count = axgbe_get_fc_queue_count(pdata);\n \treg = MAC_Q0TFCR;\n \tfor (i = 0; i < q_count; i++) {\n \t\treg_val = AXGMAC_IOREAD(pdata, reg);\n", "prefixes": [ "17/24" ] }