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GET /api/patches/136594/?format=api
{ "id": 136594, "url": "https://patches.dpdk.org/api/patches/136594/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240212134743.15153-4-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240212134743.15153-4-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240212134743.15153-4-rnagadheeraj@marvell.com", "date": "2024-02-12T13:47:39", "name": "[v2,3/7] common/nitrox: add compress hardware queue management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d1469a4d1b6c828e8fa9094c776143e241897259", "submitter": { "id": 1365, "url": "https://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240212134743.15153-4-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 31075, "url": "https://patches.dpdk.org/api/series/31075/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31075", "date": "2024-02-12T13:47:36", "name": "add Nitrox compress device support", "version": 1, "mbox": "https://patches.dpdk.org/series/31075/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/136594/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/136594/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C67943B01;\n\tMon, 12 Feb 2024 14:48:17 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 398B340DC9;\n\tMon, 12 Feb 2024 14:48:03 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 8E53140A79\n for <dev@dpdk.org>; Mon, 12 Feb 2024 14:48:01 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 41C2U7cn023155; Mon, 12 Feb 2024 05:48:01 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3w69hkc8bm-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 12 Feb 2024 05:48:00 -0800 (PST)", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 12 Feb 2024 05:47:58 -0800", "from hyd1399.caveonetworks.com.com (10.69.176.80) by\n DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id\n 15.0.1497.48 via Frontend Transport; Mon, 12 Feb 2024 05:47:56 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=F9f8P0Hd1RrWedPllQBKMuFrx8fjA93arBbjU3NwDxE=; b=UJx\n ofgQOw1Smfj56YtXq4NPClkk1aTpU/GJ9cXn+TiYHEG+S4kuADhkZ7E5VPnqxaPu\n 3ctulW0sc2up/6rBvoOgt7opY2Z39nC/aBpEvsTvxNbKZHai+Kxy00lU05qDaGYT\n oY7J4BnQfiFHJBEHEz+sC3IkztSYnx0CAiktgI4j/himgnya2jh9JvNCnWgWpU8Y\n T2EuwEzJPXLeRGNaUfjz/ouMffv4vpCJ01cUJelnHGmaw2n5irRLLVe7v1XnNsWU\n 7mZhT8fQtBwr79ZPeZNCRdtPwizLA5tVCDoClxKmJMKaQJh+1Cs/u8Fh97kYwbs7\n vTV11DA3Jo13/Y8+RDg==", "From": "Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "To": "<gakhil@marvell.com>, <fanzhang.oss@gmail.com>, <ashishg@marvell.com>", "CC": "<dev@dpdk.org>, Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "Subject": "[PATCH v2 3/7] common/nitrox: add compress hardware queue management", "Date": "Mon, 12 Feb 2024 19:17:39 +0530", "Message-ID": "<20240212134743.15153-4-rnagadheeraj@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20240212134743.15153-1-rnagadheeraj@marvell.com>", "References": "<20240212134743.15153-1-rnagadheeraj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "LGR-7mMDlvy80Cf2RHS-flgODGnYE2lo", "X-Proofpoint-GUID": "LGR-7mMDlvy80Cf2RHS-flgODGnYE2lo", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-02-12_10,2024-02-12_03,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add compress device ring initialization and cleanup code.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/common/nitrox/nitrox_csr.h | 12 +++\n drivers/common/nitrox/nitrox_hal.c | 116 +++++++++++++++++++++++++++++\n drivers/common/nitrox/nitrox_hal.h | 115 ++++++++++++++++++++++++++++\n drivers/common/nitrox/nitrox_qp.c | 53 +++++++++++--\n drivers/common/nitrox/nitrox_qp.h | 35 ++++++++-\n 5 files changed, 322 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/common/nitrox/nitrox_csr.h b/drivers/common/nitrox/nitrox_csr.h\nindex de7a3c6713..97c797c2e2 100644\n--- a/drivers/common/nitrox/nitrox_csr.h\n+++ b/drivers/common/nitrox/nitrox_csr.h\n@@ -25,6 +25,18 @@\n /* AQM Virtual Function Registers */\n #define AQMQ_QSZX(_i)\t\t\t(0x20008UL + ((_i) * 0x40000UL))\n \n+/* ZQM virtual function registers */\n+#define ZQMQ_DRBLX(_i)\t\t\t(0x30000UL + ((_i) * 0x40000UL))\n+#define ZQMQ_QSZX(_i)\t\t\t(0x30008UL + ((_i) * 0x40000UL))\n+#define ZQMQ_BADRX(_i)\t\t\t(0x30010UL + ((_i) * 0x40000UL))\n+#define ZQMQ_NXT_CMDX(_i)\t\t(0x30018UL + ((_i) * 0x40000UL))\n+#define ZQMQ_CMD_CNTX(_i)\t\t(0x30020UL + ((_i) * 0x40000UL))\n+#define ZQMQ_CMP_THRX(_i)\t\t(0x30028UL + ((_i) * 0x40000UL))\n+#define ZQMQ_CMP_CNTX(_i)\t\t(0x30030UL + ((_i) * 0x40000UL))\n+#define ZQMQ_TIMER_LDX(_i)\t\t(0x30038UL + ((_i) * 0x40000UL))\n+#define ZQMQ_ENX(_i)\t\t\t(0x30048UL + ((_i) * 0x40000UL))\n+#define ZQMQ_ACTIVITY_STATX(_i)\t\t(0x30050UL + ((_i) * 0x40000UL))\n+\n static inline uint64_t\n nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)\n {\ndiff --git a/drivers/common/nitrox/nitrox_hal.c b/drivers/common/nitrox/nitrox_hal.c\nindex 433f3adb20..451549a664 100644\n--- a/drivers/common/nitrox/nitrox_hal.c\n+++ b/drivers/common/nitrox/nitrox_hal.c\n@@ -9,6 +9,7 @@\n \n #include \"nitrox_hal.h\"\n #include \"nitrox_csr.h\"\n+#include \"nitrox_logs.h\"\n \n #define MAX_VF_QUEUES\t8\n #define MAX_PF_QUEUES\t64\n@@ -164,6 +165,121 @@ setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port)\n \t}\n }\n \n+int\n+zqmq_input_ring_disable(uint8_t *bar_addr, uint16_t ring)\n+{\n+\tunion zqmq_activity_stat zqmq_activity_stat;\n+\tunion zqmq_en zqmq_en;\n+\tunion zqmq_cmp_cnt zqmq_cmp_cnt;\n+\tuint64_t reg_addr;\n+\tint max_retries = 5;\n+\n+\t/* clear queue enable */\n+\treg_addr = ZQMQ_ENX(ring);\n+\tzqmq_en.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tzqmq_en.s.queue_enable = 0;\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_en.u64);\n+\trte_delay_us_block(100);\n+\n+\t/* wait for queue active to clear */\n+\treg_addr = ZQMQ_ACTIVITY_STATX(ring);\n+\tzqmq_activity_stat.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\twhile (zqmq_activity_stat.s.queue_active && max_retries--) {\n+\t\trte_delay_ms(10);\n+\t\tzqmq_activity_stat.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t}\n+\n+\tif (zqmq_activity_stat.s.queue_active) {\n+\t\tNITROX_LOG(ERR, \"Failed to disable zqmq ring %d\\n\", ring);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\t/* clear commands completed count */\n+\treg_addr = ZQMQ_CMP_CNTX(ring);\n+\tzqmq_cmp_cnt.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_cmp_cnt.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\treturn 0;\n+}\n+\n+int\n+setup_zqmq_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,\n+\t\t phys_addr_t raddr)\n+{\n+\tunion zqmq_drbl zqmq_drbl;\n+\tunion zqmq_qsz zqmq_qsz;\n+\tunion zqmq_en zqmq_en;\n+\tunion zqmq_cmp_thr zqmq_cmp_thr;\n+\tunion zqmq_timer_ld zqmq_timer_ld;\n+\tuint64_t reg_addr = 0;\n+\tint max_retries = 5;\n+\tint err = 0;\n+\n+\terr = zqmq_input_ring_disable(bar_addr, ring);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* clear doorbell count */\n+\treg_addr = ZQMQ_DRBLX(ring);\n+\tzqmq_drbl.u64 = 0;\n+\tzqmq_drbl.s.dbell_count = 0xFFFFFFFF;\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_drbl.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\treg_addr = ZQMQ_NXT_CMDX(ring);\n+\tnitrox_write_csr(bar_addr, reg_addr, 0);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* write queue length */\n+\treg_addr = ZQMQ_QSZX(ring);\n+\tzqmq_qsz.u64 = 0;\n+\tzqmq_qsz.s.host_queue_size = rsize;\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_qsz.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* write queue base address */\n+\treg_addr = ZQMQ_BADRX(ring);\n+\tnitrox_write_csr(bar_addr, reg_addr, raddr);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* write commands completed threshold */\n+\treg_addr = ZQMQ_CMP_THRX(ring);\n+\tzqmq_cmp_thr.u64 = 0;\n+\tzqmq_cmp_thr.s.commands_completed_threshold = 0;\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_cmp_thr.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* write timer load value */\n+\treg_addr = ZQMQ_TIMER_LDX(ring);\n+\tzqmq_timer_ld.u64 = 0;\n+\tzqmq_timer_ld.s.timer_load_value = 0;\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_timer_ld.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\treg_addr = ZQMQ_ENX(ring);\n+\tzqmq_en.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tzqmq_en.s.queue_enable = 1;\n+\tnitrox_write_csr(bar_addr, reg_addr, zqmq_en.u64);\n+\trte_delay_us_block(100);\n+\n+\t/* enable queue */\n+\tzqmq_en.u64 = 0;\n+\tzqmq_en.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\twhile (!zqmq_en.s.queue_enable && max_retries--) {\n+\t\trte_delay_ms(10);\n+\t\tzqmq_en.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t}\n+\n+\tif (!zqmq_en.s.queue_enable) {\n+\t\tNITROX_LOG(ERR, \"Failed to enable zqmq ring %d\\n\", ring);\n+\t\terr = -EFAULT;\n+\t} else {\n+\t\terr = 0;\n+\t}\n+\n+\treturn err;\n+}\n+\n int\n vf_get_vf_config_mode(uint8_t *bar_addr)\n {\ndiff --git a/drivers/common/nitrox/nitrox_hal.h b/drivers/common/nitrox/nitrox_hal.h\nindex dcfbd11d85..2367b967e5 100644\n--- a/drivers/common/nitrox/nitrox_hal.h\n+++ b/drivers/common/nitrox/nitrox_hal.h\n@@ -146,6 +146,101 @@ union aqmq_qsz {\n \t} s;\n };\n \n+union zqmq_activity_stat {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t: 63;\n+\t\tuint64_t queue_active\t: 1;\n+#else\n+\t\tuint64_t queue_active\t: 1;\n+\t\tuint64_t raz\t\t: 63;\n+#endif\n+\t} s;\n+};\n+\n+union zqmq_en {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t: 63;\n+\t\tuint64_t queue_enable\t: 1;\n+#else\n+\t\tuint64_t queue_enable\t: 1;\n+\t\tuint64_t raz\t\t: 63;\n+#endif\n+\t} s;\n+};\n+\n+union zqmq_cmp_cnt {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t\t: 30;\n+\t\tuint64_t resend\t\t\t: 1;\n+\t\tuint64_t completion_status\t: 1;\n+\t\tuint64_t commands_completed_count: 32;\n+#else\n+\t\tuint64_t commands_completed_count: 32;\n+\t\tuint64_t completion_status\t: 1;\n+\t\tuint64_t resend\t\t\t: 1;\n+\t\tuint64_t raz\t\t\t: 30;\n+#endif\n+\t} s;\n+};\n+\n+union zqmq_drbl {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t: 32;\n+\t\tuint64_t dbell_count\t: 32;\n+#else\n+\t\tuint64_t dbell_count\t: 32;\n+\t\tuint64_t raz\t\t: 32;\n+#endif\n+\t} s;\n+};\n+\n+union zqmq_qsz {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t: 32;\n+\t\tuint64_t host_queue_size: 32;\n+#else\n+\t\tuint64_t host_queue_size: 32;\n+\t\tuint64_t raz\t\t: 32;\n+#endif\n+\t} s;\n+};\n+\n+union zqmq_cmp_thr {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t\t\t: 32;\n+\t\tuint64_t commands_completed_threshold\t: 32;\n+#else\n+\t\tuint64_t commands_completed_threshold\t: 32;\n+\t\tuint64_t raz\t\t\t\t: 32;\n+#endif\n+\t} s;\n+};\n+\n+union zqmq_timer_ld {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz\t\t: 32;\n+\t\tuint64_t timer_load_value: 32;\n+#else\n+\t\tuint64_t timer_load_value: 32;\n+\t\tuint64_t raz\t\t: 32;\n+#endif\n+\t} s;\n+};\n+\n enum nitrox_vf_mode {\n \tNITROX_MODE_PF = 0x0,\n \tNITROX_MODE_VF16 = 0x1,\n@@ -154,6 +249,23 @@ enum nitrox_vf_mode {\n \tNITROX_MODE_VF128 = 0x4,\n };\n \n+static inline int\n+inc_zqmq_next_cmd(uint8_t *bar_addr, uint16_t ring)\n+{\n+\tuint64_t reg_addr = 0;\n+\tuint64_t val;\n+\n+\treg_addr = ZQMQ_NXT_CMDX(ring);\n+\tval = nitrox_read_csr(bar_addr, reg_addr);\n+\tval++;\n+\tnitrox_write_csr(bar_addr, reg_addr, val);\n+\trte_delay_us_block(CSR_DELAY);\n+\tif (nitrox_read_csr(bar_addr, reg_addr) != val)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n int vf_get_vf_config_mode(uint8_t *bar_addr);\n int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);\n void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,\n@@ -161,5 +273,8 @@ void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,\n void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port);\n void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring);\n void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port);\n+int setup_zqmq_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,\n+\t\t\t phys_addr_t raddr);\n+int zqmq_input_ring_disable(uint8_t *bar_addr, uint16_t ring);\n \n #endif /* _NITROX_HAL_H_ */\ndiff --git a/drivers/common/nitrox/nitrox_qp.c b/drivers/common/nitrox/nitrox_qp.c\nindex 5e85ccbd51..6ec0781f1a 100644\n--- a/drivers/common/nitrox/nitrox_qp.c\n+++ b/drivers/common/nitrox/nitrox_qp.c\n@@ -2,7 +2,7 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n-#include <rte_cryptodev.h>\n+#include <rte_memzone.h>\n #include <rte_malloc.h>\n \n #include \"nitrox_qp.h\"\n@@ -20,6 +20,7 @@ nitrox_setup_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr,\n \tconst struct rte_memzone *mz;\n \tsize_t cmdq_size = qp->count * instr_size;\n \tuint64_t offset;\n+\tint err = 0;\n \n \tsnprintf(mz_name, sizeof(mz_name), \"%s_cmdq_%d\", dev_name, qp->qno);\n \tmz = rte_memzone_reserve_aligned(mz_name, cmdq_size, socket_id,\n@@ -32,14 +33,34 @@ nitrox_setup_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr,\n \t\treturn -ENOMEM;\n \t}\n \n+\tswitch (qp->type) {\n+\tcase NITROX_QUEUE_SE:\n+\t\toffset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(qp->qno);\n+\t\tqp->cmdq.dbell_csr_addr = NITROX_CSR_ADDR(bar_addr, offset);\n+\t\tsetup_nps_pkt_input_ring(bar_addr, qp->qno, qp->count,\n+\t\t\t\t\t mz->iova);\n+\t\tsetup_nps_pkt_solicit_output_port(bar_addr, qp->qno);\n+\t\tbreak;\n+\tcase NITROX_QUEUE_ZIP:\n+\t\toffset = ZQMQ_DRBLX(qp->qno);\n+\t\tqp->cmdq.dbell_csr_addr = NITROX_CSR_ADDR(bar_addr, offset);\n+\t\terr = setup_zqmq_input_ring(bar_addr, qp->qno, qp->count,\n+\t\t\t\t\t mz->iova);\n+\t\tbreak;\n+\tdefault:\n+\t\tNITROX_LOG(ERR, \"Invalid queue type %d\\n\", qp->type);\n+\t\terr = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (err) {\n+\t\trte_memzone_free(mz);\n+\t\treturn err;\n+\t}\n+\n \tqp->cmdq.mz = mz;\n-\toffset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(qp->qno);\n-\tqp->cmdq.dbell_csr_addr = NITROX_CSR_ADDR(bar_addr, offset);\n \tqp->cmdq.ring = mz->addr;\n \tqp->cmdq.instr_size = instr_size;\n-\tsetup_nps_pkt_input_ring(bar_addr, qp->qno, qp->count, mz->iova);\n-\tsetup_nps_pkt_solicit_output_port(bar_addr, qp->qno);\n-\n \treturn 0;\n }\n \n@@ -62,8 +83,23 @@ nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)\n static int\n nitrox_release_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr)\n {\n-\tnps_pkt_solicited_port_disable(bar_addr, qp->qno);\n-\tnps_pkt_input_ring_disable(bar_addr, qp->qno);\n+\tint err = 0;\n+\n+\tswitch (qp->type) {\n+\tcase NITROX_QUEUE_SE:\n+\t\tnps_pkt_solicited_port_disable(bar_addr, qp->qno);\n+\t\tnps_pkt_input_ring_disable(bar_addr, qp->qno);\n+\t\tbreak;\n+\tcase NITROX_QUEUE_ZIP:\n+\t\terr = zqmq_input_ring_disable(bar_addr, qp->qno);\n+\t\tbreak;\n+\tdefault:\n+\t\terr = -EINVAL;\n+\t}\n+\n+\tif (err)\n+\t\treturn err;\n+\n \treturn rte_memzone_free(qp->cmdq.mz);\n }\n \n@@ -83,6 +119,7 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n \t\treturn -EINVAL;\n \t}\n \n+\tqp->bar_addr = bar_addr;\n \tqp->count = count;\n \tqp->head = qp->tail = 0;\n \trte_atomic16_init(&qp->pending_count);\ndiff --git a/drivers/common/nitrox/nitrox_qp.h b/drivers/common/nitrox/nitrox_qp.h\nindex d42d53f92b..177bcd7705 100644\n--- a/drivers/common/nitrox/nitrox_qp.h\n+++ b/drivers/common/nitrox/nitrox_qp.h\n@@ -8,9 +8,16 @@\n #include <stdbool.h>\n \n #include <rte_io.h>\n+#include \"nitrox_hal.h\"\n \n struct nitrox_softreq;\n \n+enum nitrox_queue_type {\n+\tNITROX_QUEUE_SE,\n+\tNITROX_QUEUE_AE,\n+\tNITROX_QUEUE_ZIP,\n+};\n+\n struct command_queue {\n \tconst struct rte_memzone *mz;\n \tuint8_t *dbell_csr_addr;\n@@ -22,14 +29,23 @@ struct rid {\n \tstruct nitrox_softreq *sr;\n };\n \n+struct nitrox_qp_stats {\n+\tuint64_t enqueued_count;\n+\tuint64_t dequeued_count;\n+\tuint64_t enqueue_err_count;\n+\tuint64_t dequeue_err_count;\n+};\n+\n struct nitrox_qp {\n+\tenum nitrox_queue_type type;\n+\tuint8_t *bar_addr;\n \tstruct command_queue cmdq;\n \tstruct rid *ridq;\n \tuint32_t count;\n \tuint32_t head;\n \tuint32_t tail;\n \tstruct rte_mempool *sr_mp;\n-\tstruct rte_cryptodev_stats stats;\n+\tstruct nitrox_qp_stats stats;\n \tuint16_t qno;\n \trte_atomic16_t pending_count;\n };\n@@ -89,6 +105,23 @@ nitrox_qp_enqueue(struct nitrox_qp *qp, void *instr, struct nitrox_softreq *sr)\n \trte_atomic16_inc(&qp->pending_count);\n }\n \n+static inline int\n+nitrox_qp_enqueue_sr(struct nitrox_qp *qp, struct nitrox_softreq *sr)\n+{\n+\tuint32_t head = qp->head % qp->count;\n+\tint err;\n+\n+\terr = inc_zqmq_next_cmd(qp->bar_addr, qp->qno);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\tqp->head++;\n+\tqp->ridq[head].sr = sr;\n+\trte_smp_wmb();\n+\trte_atomic16_inc(&qp->pending_count);\n+\treturn 0;\n+}\n+\n static inline void\n nitrox_qp_dequeue(struct nitrox_qp *qp)\n {\n", "prefixes": [ "v2", "3/7" ] }