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GET /api/patches/136430/?format=api
{ "id": 136430, "url": "https://patches.dpdk.org/api/patches/136430/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240206143950.1499532-6-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240206143950.1499532-6-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240206143950.1499532-6-michaelba@nvidia.com", "date": "2024-02-06T14:39:48", "name": "[v1,5/7] net/mlx5: add support for modify inner fields", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d2bd4858ad20ac541d264ce7f2e50156909e0a43", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240206143950.1499532-6-michaelba@nvidia.com/mbox/", "series": [ { "id": 31011, "url": "https://patches.dpdk.org/api/series/31011/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31011", "date": "2024-02-06T14:39:45", "name": "net/mlx5: support copy from inner fields", "version": 1, "mbox": "https://patches.dpdk.org/series/31011/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/136430/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/136430/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7395443A3A;\n\tTue, 6 Feb 2024 15:40:51 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D8C8D427E8;\n\tTue, 6 Feb 2024 15:40:27 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2074.outbound.protection.outlook.com [40.107.220.74])\n by mails.dpdk.org (Postfix) with ESMTP id EAA58427E4\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,\n Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v1 5/7] net/mlx5: add support for modify inner fields", "Date": "Tue, 6 Feb 2024 16:39:48 +0200", "Message-ID": "<20240206143950.1499532-6-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240206143950.1499532-1-michaelba@nvidia.com>", "References": "<20240206143950.1499532-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF00003440:EE_|CY5PR12MB6454:EE_", "X-MS-Office365-Filtering-Correlation-Id": "efe2184f-7f3c-481c-0202-08dc27218d25", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n YxWZKQJ1PojTbPvgcBQqXsEkrTJZldwF5slH5OFnNMqrTRvlEAERgNTrcFdDBNLYkr0iCIlu90skgCkvW7I2uGVs55VwtWJsaqv5v/tpwODQkk5dXVNR347oULu9WPTxf82rBX/PQnMwKajc8erJO6weA2t4jxFRz2honuAZZa59xgsAsPFZQEly0BF+OXqOU/Ow4BJ1BuFxLZd3mdKfd2Glog6z8plEP5ILz8GC+9TddWVqGz8Y3MKMyQE0xcIgnGXgOj5Nqxooovpd5sexAZijQqvEWiHqxEVsDKtUnLh31ZxvXVqqiFOKMxoGPK7rj5lb/T+ZF2dcIKpW94wv9wWF58QQKebzZ/pPZWxhwWf6YhQZx+qZAcxa7/TmuKpWR918od6etBlgVTvaLbvygLuvuV2UyFMxZysqq0WYoVLehw4QinxBg2vmxMwxCReAwljHTfImpCSRhwYn3XPuQmzMrLLRFNIP7xggb93iq+wF/PkybSeVvoq3/76/F4UMnWyl8/l6YBrZR7qoEoM84fthYTTOQNp18fF+q/Ko5Cc7JZlc8qLMa1PDl/mtLvpwvwt9I5nJSCzwqnHP4KDfSSDU7SMBIea828RRy2p0u93My8/eAT0cvdKeovC6e7H6jGI0JQAxql1lbWpJKG7nFyWj/y42HkORBQkaOjgwcjd5dy1RFWqrIMVcbSeI8jOZ0N711P07VLKdcGOs4MHi5ygNtJglj2lVoly+SvL+W3fu9Z2qoTHRXof3tACNrE25", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF00003440.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY5PR12MB6454", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support for copying from inner fields using \"level\" 2.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 28 ++++++-\n drivers/net/mlx5/mlx5_flow.c | 12 ++-\n drivers/net/mlx5/mlx5_flow_dv.c | 113 ++++++++++++++-------------\n drivers/net/mlx5/mlx5_flow_hw.c | 130 +++++++++++++++++++++++++++++++-\n 4 files changed, 222 insertions(+), 61 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 6e1e2df79a..030bbe664f 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -595,7 +595,6 @@ Limitations\n Only DWs configured in :ref:`parser creation <geneve_parser_api>` can be modified,\n 'type' and 'class' fields can be modified when ``match_on_class_mode=2``.\n - Modification of GENEVE TLV option data supports one DW per action.\n- - Encapsulation levels are not supported, can modify outermost header fields only.\n - Offsets cannot skip past the boundary of a field.\n - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``\n and packet contains one or more VLAN headers,\n@@ -609,6 +608,33 @@ Limitations\n - For flow metadata fields (e.g. META or TAG)\n offset specifies the number of bits to skip from field's start,\n starting from LSB in the least significant byte, in the host order.\n+ - Modification of the MPLS header is supported with some limitations:\n+\n+ - Only in HW steering.\n+ - Only in ``src`` field.\n+ - Only for outermost tunnel header (``level=2``).\n+ For ``RTE_FLOW_FIELD_MPLS``,\n+ the default encapsulation level ``0`` describes the outermost tunnel header.\n+\n+ .. note::\n+\n+ the default encapsulation level ``0`` describes the \"outermost that match is supported\",\n+ currently it is first tunnel, but it can be changed to outer when it is supported.\n+\n+ - Default encapsulation level ``0`` describes outermost.\n+ - Encapsulation level ``1`` is supported.\n+ - Encapsulation level ``2`` is supported with some limitations:\n+\n+ - Only in HW steering.\n+ - Only in ``src`` field.\n+ - ``RTE_FLOW_FIELD_VLAN_ID`` is not supported.\n+ - ``RTE_FLOW_FIELD_IPV4_PROTO`` is not supported.\n+ - ``RTE_FLOW_FIELD_IPV6_PROTO/DSCP/ECN`` are not supported.\n+ - ``RTE_FLOW_FIELD_ESP_PROTO/SPI/SEQ_NUM`` are not supported.\n+ - ``RTE_FLOW_FIELD_TCP_SEQ/ACK_NUM`` are not supported.\n+ - Second tunnel fields are not supported.\n+\n+ - Encapsulation levels greater than ``2`` are not supported.\n \n - Age action:\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 5159e8e773..fa85089364 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -2507,10 +2507,14 @@ flow_validate_modify_field_level(const struct rte_flow_action_modify_data *data,\n \tif (data->level == 0)\n \t\treturn 0;\n \tif (data->field != RTE_FLOW_FIELD_TAG &&\n-\t data->field != (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG)\n-\t\treturn rte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n-\t\t\t\t\t \"inner header fields modification is not supported\");\n+\t data->field != (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {\n+\t\tif (data->level > 1)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t NULL,\n+\t\t\t\t\t\t \"inner header fields modification is not supported\");\n+\t\treturn 0;\n+\t}\n \tif (data->tag_index != 0)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 90413f4a38..8454d00d4f 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -82,6 +82,9 @@\n \t\t} \\\n \t} while (0)\n \n+#define CALC_MODI_ID(field, level) \\\n+\t(((level) > 1) ? MLX5_MODI_IN_##field : MLX5_MODI_OUT_##field)\n+\n union flow_dv_attr {\n \tstruct {\n \t\tuint32_t valid:1;\n@@ -1638,8 +1641,8 @@ mlx5_flow_field_id_to_modify_info\n \t\tMLX5_ASSERT(data->offset + width <= 48);\n \t\toff_be = 48 - (data->offset + width);\n \t\tif (off_be < 16) {\n-\t\t\tinfo[idx] = (struct field_modify_info){2, 4,\n-\t\t\t\t\tMLX5_MODI_OUT_DMAC_15_0};\n+\t\t\tmodi_id = CALC_MODI_ID(DMAC_15_0, data->level);\n+\t\t\tinfo[idx] = (struct field_modify_info){2, 4, modi_id};\n \t\t\tlength = off_be + width <= 16 ? width : 16 - off_be;\n \t\t\tif (mask)\n \t\t\t\tmask[1] = flow_modify_info_mask_16(length,\n@@ -1654,8 +1657,8 @@ mlx5_flow_field_id_to_modify_info\n \t\t} else {\n \t\t\toff_be -= 16;\n \t\t}\n-\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\tMLX5_MODI_OUT_DMAC_47_16};\n+\t\tmodi_id = CALC_MODI_ID(DMAC_47_16, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[0] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -1665,8 +1668,8 @@ mlx5_flow_field_id_to_modify_info\n \t\tMLX5_ASSERT(data->offset + width <= 48);\n \t\toff_be = 48 - (data->offset + width);\n \t\tif (off_be < 16) {\n-\t\t\tinfo[idx] = (struct field_modify_info){2, 4,\n-\t\t\t\t\tMLX5_MODI_OUT_SMAC_15_0};\n+\t\t\tmodi_id = CALC_MODI_ID(SMAC_15_0, data->level);\n+\t\t\tinfo[idx] = (struct field_modify_info){2, 4, modi_id};\n \t\t\tlength = off_be + width <= 16 ? width : 16 - off_be;\n \t\t\tif (mask)\n \t\t\t\tmask[1] = flow_modify_info_mask_16(length,\n@@ -1681,8 +1684,8 @@ mlx5_flow_field_id_to_modify_info\n \t\t} else {\n \t\t\toff_be -= 16;\n \t\t}\n-\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\tMLX5_MODI_OUT_SMAC_47_16};\n+\t\tmodi_id = CALC_MODI_ID(SMAC_47_16, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[0] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -1704,8 +1707,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_MAC_TYPE:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_ETHERTYPE};\n+\t\tmodi_id = CALC_MODI_ID(ETHERTYPE, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1714,8 +1717,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_IHL:\n \t\tMLX5_ASSERT(data->offset + width <= 4);\n \t\toff_be = 4 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IPV4_IHL};\n+\t\tmodi_id = CALC_MODI_ID(IPV4_IHL, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -1724,8 +1727,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_DSCP:\n \t\tMLX5_ASSERT(data->offset + width <= 6);\n \t\toff_be = 6 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IP_DSCP};\n+\t\tmodi_id = CALC_MODI_ID(IP_DSCP, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -1734,8 +1737,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_TOTAL_LEN:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IPV4_TOTAL_LEN};\n+\t\tmodi_id = CALC_MODI_ID(IPV4_TOTAL_LEN, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1744,8 +1747,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_TTL:\n \t\tMLX5_ASSERT(data->offset + width <= 8);\n \t\toff_be = 8 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IPV4_TTL};\n+\t\tmodi_id = CALC_MODI_ID(IPV4_TTL, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -1754,8 +1757,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_SRC:\n \t\tMLX5_ASSERT(data->offset + width <= 32);\n \t\toff_be = 32 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_SIPV4};\n+\t\tmodi_id = CALC_MODI_ID(SIPV4, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -1764,8 +1767,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_DST:\n \t\tMLX5_ASSERT(data->offset + width <= 32);\n \t\toff_be = 32 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_DIPV4};\n+\t\tmodi_id = CALC_MODI_ID(DIPV4, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -1795,8 +1798,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IPV6_PAYLOAD_LEN};\n+\t\tmodi_id = CALC_MODI_ID(IPV6_PAYLOAD_LEN, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1805,8 +1808,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV6_HOPLIMIT:\n \t\tMLX5_ASSERT(data->offset + width <= 8);\n \t\toff_be = 8 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IPV6_HOPLIMIT};\n+\t\tmodi_id = CALC_MODI_ID(IPV6_HOPLIMIT, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -1818,10 +1821,10 @@ mlx5_flow_field_id_to_modify_info\n \t\t * arranged according to network byte ordering.\n \t\t */\n \t\tstruct field_modify_info fields[] = {\n-\t\t\t{ 4, 0, MLX5_MODI_OUT_SIPV6_127_96 },\n-\t\t\t{ 4, 4, MLX5_MODI_OUT_SIPV6_95_64 },\n-\t\t\t{ 4, 8, MLX5_MODI_OUT_SIPV6_63_32 },\n-\t\t\t{ 4, 12, MLX5_MODI_OUT_SIPV6_31_0 },\n+\t\t\t{ 4, 0, CALC_MODI_ID(SIPV6_127_96, data->level)},\n+\t\t\t{ 4, 4, CALC_MODI_ID(SIPV6_95_64, data->level)},\n+\t\t\t{ 4, 8, CALC_MODI_ID(SIPV6_63_32, data->level)},\n+\t\t\t{ 4, 12, CALC_MODI_ID(SIPV6_31_0, data->level)},\n \t\t};\n \t\t/* First mask to be modified is the mask of 4th address byte. */\n \t\tuint32_t midx = 3;\n@@ -1861,10 +1864,10 @@ mlx5_flow_field_id_to_modify_info\n \t\t * arranged according to network byte ordering.\n \t\t */\n \t\tstruct field_modify_info fields[] = {\n-\t\t\t{ 4, 0, MLX5_MODI_OUT_DIPV6_127_96 },\n-\t\t\t{ 4, 4, MLX5_MODI_OUT_DIPV6_95_64 },\n-\t\t\t{ 4, 8, MLX5_MODI_OUT_DIPV6_63_32 },\n-\t\t\t{ 4, 12, MLX5_MODI_OUT_DIPV6_31_0 },\n+\t\t\t{ 4, 0, CALC_MODI_ID(DIPV6_127_96, data->level)},\n+\t\t\t{ 4, 4, CALC_MODI_ID(DIPV6_95_64, data->level)},\n+\t\t\t{ 4, 8, CALC_MODI_ID(DIPV6_63_32, data->level)},\n+\t\t\t{ 4, 12, CALC_MODI_ID(DIPV6_31_0, data->level)},\n \t\t};\n \t\t/* First mask to be modified is the mask of 4th address byte. */\n \t\tuint32_t midx = 3;\n@@ -1901,8 +1904,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_TCP_PORT_SRC:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_TCP_SPORT};\n+\t\tmodi_id = CALC_MODI_ID(TCP_SPORT, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1911,8 +1914,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_TCP_PORT_DST:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_TCP_DPORT};\n+\t\tmodi_id = CALC_MODI_ID(TCP_DPORT, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1921,8 +1924,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_TCP_SEQ_NUM:\n \t\tMLX5_ASSERT(data->offset + width <= 32);\n \t\toff_be = 32 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_TCP_SEQ_NUM};\n+\t\tmodi_id = CALC_MODI_ID(TCP_SEQ_NUM, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -1931,8 +1934,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_TCP_ACK_NUM:\n \t\tMLX5_ASSERT(data->offset + width <= 32);\n \t\toff_be = 32 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_TCP_ACK_NUM};\n+\t\tmodi_id = CALC_MODI_ID(TCP_ACK_NUM, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -1941,8 +1944,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_TCP_FLAGS:\n \t\tMLX5_ASSERT(data->offset + width <= 9);\n \t\toff_be = 9 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_TCP_FLAGS};\n+\t\tmodi_id = CALC_MODI_ID(TCP_FLAGS, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1951,8 +1954,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_TCP_DATA_OFFSET:\n \t\tMLX5_ASSERT(data->offset + width <= 4);\n \t\toff_be = 4 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_TCP_DATA_OFFSET};\n+\t\tmodi_id = CALC_MODI_ID(TCP_DATA_OFFSET, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -1961,8 +1964,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_UDP_PORT_SRC:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_UDP_SPORT};\n+\t\tmodi_id = CALC_MODI_ID(UDP_SPORT, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -1971,8 +1974,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_UDP_PORT_DST:\n \t\tMLX5_ASSERT(data->offset + width <= 16);\n \t\toff_be = 16 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){2, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_UDP_DPORT};\n+\t\tmodi_id = CALC_MODI_ID(UDP_DPORT, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){2, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_16(width, off_be);\n \t\telse\n@@ -2124,8 +2127,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_IPV4_ECN:\n \t\tMLX5_ASSERT(data->offset + width <= 2);\n \t\toff_be = 2 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IP_ECN};\n+\t\tmodi_id = CALC_MODI_ID(IP_ECN, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){1, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -2221,7 +2224,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_ESP_SPI:\n \t\tMLX5_ASSERT(data->offset + width <= 32);\n \t\toff_be = 32 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_ESP_SPI};\n+\t\tmodi_id = CALC_MODI_ID(ESP_SPI, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n \t\telse\n@@ -2230,7 +2234,8 @@ mlx5_flow_field_id_to_modify_info\n \tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\tMLX5_ASSERT(data->offset + width <= 32);\n \t\toff_be = 32 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_ESP_SEQ_NUM};\n+\t\tmodi_id = CALC_MODI_ID(ESP_SEQ_NUM, data->level);\n+\t\tinfo[idx] = (struct field_modify_info){4, 0, modi_id};\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_32(width, off_be);\n \t\telse\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7510715189..fc0f9dabb3 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4994,6 +4994,131 @@ flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field\n \treturn false;\n }\n \n+/**\n+ * Validate the level value for modify field action.\n+ *\n+ * @param[in] data\n+ * Pointer to the rte_flow_field_data structure either src or dst.\n+ * @param[in] inner_supported\n+ * Indicator whether inner should be supported.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_hw_validate_modify_field_level(const struct rte_flow_action_modify_data *data,\n+\t\t\t\t bool inner_supported,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tswitch ((int)data->field) {\n+\tcase RTE_FLOW_FIELD_START:\n+\tcase RTE_FLOW_FIELD_VLAN_TYPE:\n+\tcase RTE_FLOW_FIELD_RANDOM:\n+\tcase RTE_FLOW_FIELD_FLEX_ITEM:\n+\t\t/*\n+\t\t * Level shouldn't be valid since field isn't supported or\n+\t\t * doesn't use 'level'.\n+\t\t */\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_MARK:\n+\tcase RTE_FLOW_FIELD_META:\n+\tcase RTE_FLOW_FIELD_METER_COLOR:\n+\tcase RTE_FLOW_FIELD_HASH_RESULT:\n+\t\t/* For meta data fields encapsulation level is don't-care. */\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_TAG:\n+\tcase MLX5_RTE_FLOW_FIELD_META_REG:\n+\t\t/*\n+\t\t * The tag array for RTE_FLOW_FIELD_TAG type is provided using\n+\t\t * 'tag_index' field. In old API, it was provided using 'level'\n+\t\t * field and it is still supported for backwards compatibility.\n+\t\t * Therefore, for meta tag field only, level is matter. It is\n+\t\t * taken as tag index when 'tag_index' field isn't set, and\n+\t\t * return error otherwise.\n+\t\t */\n+\t\tif (data->level > 0) {\n+\t\t\tif (data->tag_index > 0)\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t\t data,\n+\t\t\t\t\t\t\t \"tag array can be provided using 'level' or 'tag_index' fields, not both\");\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"tag array provided in 'level' field instead of 'tag_index' field.\");\n+\t\t}\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_MAC_DST:\n+\tcase RTE_FLOW_FIELD_MAC_SRC:\n+\tcase RTE_FLOW_FIELD_MAC_TYPE:\n+\tcase RTE_FLOW_FIELD_IPV4_IHL:\n+\tcase RTE_FLOW_FIELD_IPV4_TOTAL_LEN:\n+\tcase RTE_FLOW_FIELD_IPV4_DSCP:\n+\tcase RTE_FLOW_FIELD_IPV4_ECN:\n+\tcase RTE_FLOW_FIELD_IPV4_TTL:\n+\tcase RTE_FLOW_FIELD_IPV4_SRC:\n+\tcase RTE_FLOW_FIELD_IPV4_DST:\n+\tcase RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:\n+\tcase RTE_FLOW_FIELD_IPV6_HOPLIMIT:\n+\tcase RTE_FLOW_FIELD_IPV6_SRC:\n+\tcase RTE_FLOW_FIELD_IPV6_DST:\n+\tcase RTE_FLOW_FIELD_TCP_PORT_SRC:\n+\tcase RTE_FLOW_FIELD_TCP_PORT_DST:\n+\tcase RTE_FLOW_FIELD_TCP_FLAGS:\n+\tcase RTE_FLOW_FIELD_TCP_DATA_OFFSET:\n+\tcase RTE_FLOW_FIELD_UDP_PORT_SRC:\n+\tcase RTE_FLOW_FIELD_UDP_PORT_DST:\n+\t\tif (data->level > 2)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t data,\n+\t\t\t\t\t\t \"second inner header fields modification is not supported\");\n+\t\tif (inner_supported)\n+\t\t\tbreak;\n+\t\t/* Fallthrough */\n+\tcase RTE_FLOW_FIELD_VLAN_ID:\n+\tcase RTE_FLOW_FIELD_IPV4_PROTO:\n+\tcase RTE_FLOW_FIELD_IPV6_PROTO:\n+\tcase RTE_FLOW_FIELD_IPV6_DSCP:\n+\tcase RTE_FLOW_FIELD_IPV6_ECN:\n+\tcase RTE_FLOW_FIELD_TCP_SEQ_NUM:\n+\tcase RTE_FLOW_FIELD_TCP_ACK_NUM:\n+\tcase RTE_FLOW_FIELD_ESP_PROTO:\n+\tcase RTE_FLOW_FIELD_ESP_SPI:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n+\tcase RTE_FLOW_FIELD_VXLAN_VNI:\n+\tcase RTE_FLOW_FIELD_GENEVE_VNI:\n+\tcase RTE_FLOW_FIELD_GENEVE_OPT_TYPE:\n+\tcase RTE_FLOW_FIELD_GENEVE_OPT_CLASS:\n+\tcase RTE_FLOW_FIELD_GENEVE_OPT_DATA:\n+\tcase RTE_FLOW_FIELD_GTP_TEID:\n+\tcase RTE_FLOW_FIELD_GTP_PSC_QFI:\n+\t\tif (data->level > 1)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t data,\n+\t\t\t\t\t\t \"inner header fields modification is not supported\");\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_MPLS:\n+\t\tif (data->level == 1)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t data,\n+\t\t\t\t\t\t \"outer MPLS header modification is not supported\");\n+\t\tif (data->level > 2)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t data,\n+\t\t\t\t\t\t \"inner MPLS header modification is not supported\");\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_POINTER:\n+\tcase RTE_FLOW_FIELD_VALUE:\n+\tdefault:\n+\t\tMLX5_ASSERT(false);\n+\t}\n+\treturn 0;\n+}\n+\n static int\n flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\t\t const struct rte_flow_action *action,\n@@ -5024,7 +5149,7 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"immediate value, pointer and hash result cannot be used as destination\");\n-\tret = flow_validate_modify_field_level(&action_conf->dst, error);\n+\tret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);\n \tif (ret)\n \t\treturn ret;\n \tif (!flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {\n@@ -5071,7 +5196,7 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"source offset level must be fully masked\");\n-\t\tret = flow_validate_modify_field_level(&action_conf->src, error);\n+\t\tret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n@@ -5136,6 +5261,7 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\t\t\"invalid add_field destination\");\n \treturn 0;\n }\n+\n static int\n flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,\n \t\t\t\t\t const struct rte_flow_actions_template_attr *attr,\n", "prefixes": [ "v1", "5/7" ] }