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GET /api/patches/136352/?format=api
{ "id": 136352, "url": "https://patches.dpdk.org/api/patches/136352/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240202193238.62669-14-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240202193238.62669-14-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240202193238.62669-14-andrew.boyer@amd.com", "date": "2024-02-02T19:32:38", "name": "[13/13] net/ionic: optimize device start operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d21b99a394104791b8ecfa75e92f7f02bb26ea2d", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240202193238.62669-14-andrew.boyer@amd.com/mbox/", "series": [ { "id": 30994, "url": "https://patches.dpdk.org/api/series/30994/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30994", "date": "2024-02-02T19:32:25", "name": "net/ionic: miscellaneous fixes and improvements", "version": 1, "mbox": "https://patches.dpdk.org/series/30994/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/136352/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/136352/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=gF6hOJwQquSpy1dbolM7l5D6ghB6D83urH4MWCRvuKEt9fW31tviA2ZD13FcL7zFyjNy5QSYGuYYkltO2gtxGikiBrgauXM5U8vH0T/oxs+Zeh7H+FVQW+ZK7Q1OtXiwBOQr0mblBqQ964Ixu9CmgL7PeGnEIro8F2Xpw+1w5Hk=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH 13/13] net/ionic: optimize device start operation", "Date": "Fri, 2 Feb 2024 11:32:38 -0800", "Message-ID": "<20240202193238.62669-14-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240202193238.62669-1-andrew.boyer@amd.com>", "References": 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SKPZI3iza04BGkouEhT4GQL3k0o3ipvfjky0ZRDo478BhM1miCaQCVeV2912uxjcpG2gvixmr+bAi9YkGUwikr32xDwx5XeUdUpUrrlvgu1U6m4nvI91/P3t6RyoiEpM3iOQC59BodlBSz6LBEoVIB+4/Nv+i+rfBSatAac2j2NRqtEHuL+EZKN3cHo39WTpoIick/9W9XFpUTxk7h+TU+DaBEPkXY59U1QOMUStx+IdfH3fnvHlBA76zpC3phiw28nFCd399t76q8SgERhHmEOQAfLTsuN73XrdWCSOcaYEMp18n3+DyVhyVpTypNWRYEVkbbAlBgJSsLdC8s300XG1iaiSHPvMcdGKks+UM74Q1sMSh+p9GUq79ZxvusMufYuFUau8lGbPwndGYNGA4wI50Qc6GOgoaFfkbHcfHQjSc+qdVLSM/AOWu+BP2wj4D7F/i3OdlgY4wvW1CHjY/Ox1rOAmbjyO3FtqzJ/BHYzpDrFd+x2R9y5uwe67AyTw4JZLrdPnMCUrHrXIbmS3mH2ebJVA3gSrQ00PIoV84MZlhiWutzKSPfZYmN8TVBODvg18b/MHMcmkjA6682LOkcQ3CYcA59Bmw4OIOcPlEZzv1R+8YbBm5LCa96Qch2VDLS3+la1uGCYzRGvQSqA3cTW4Y6+pHIgTqAry7+qsmU0IQGqj7wNCqsqLVaMue3fF+Md6yfdB7UJB9SdRo2iFhz+py3OmmIo7ABt7mM6MVZ42h1K1tJ4VKHQIXMA1AjdjMMUItN8NXF6jskdyb/NJzA==", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(136003)(346002)(376002)(396003)(230922051799003)(451199024)(186009)(64100799003)(82310400011)(1800799012)(36840700001)(40470700004)(46966006)(41300700001)(16526019)(1076003)(26005)(2616005)(81166007)(478600001)(356005)(6916009)(70206006)(82740400003)(4326008)(70586007)(8936002)(36860700001)(426003)(30864003)(336012)(8676002)(83380400001)(316002)(44832011)(2906002)(5660300002)(86362001)(47076005)(36756003)(40480700001)(40460700003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Feb 2024 19:33:33.9599 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f95a4abf-2cb2-4a7e-ae0d-08dc2425d844", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF00017095.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5118", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Split the queue_start operation into first-half and second-half helpers.\n\nThis allows us to batch up the queue commands during dev_start(), reducing\nthe outage window when restarting the process by about 1ms per queue.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/net/ionic/ionic_lif.c | 178 +++++++++++++++++++++------------\n drivers/net/ionic/ionic_lif.h | 6 +-\n drivers/net/ionic/ionic_rxtx.c | 81 ++++++++++++---\n drivers/net/ionic/ionic_rxtx.h | 10 ++\n 4 files changed, 194 insertions(+), 81 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex 8ffdbc4df7..1937e48d9b 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -1598,52 +1598,61 @@ ionic_lif_set_features(struct ionic_lif *lif)\n }\n \n int\n-ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n+ionic_lif_txq_init_nowait(struct ionic_tx_qcq *txq)\n {\n \tstruct ionic_qcq *qcq = &txq->qcq;\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_lif *lif = qcq->lif;\n \tstruct ionic_cq *cq = &qcq->cq;\n-\tstruct ionic_admin_ctx ctx = {\n-\t\t.pending_work = true,\n-\t\t.cmd.q_init = {\n-\t\t\t.opcode = IONIC_CMD_Q_INIT,\n-\t\t\t.type = q->type,\n-\t\t\t.ver = lif->qtype_info[q->type].version,\n-\t\t\t.index = rte_cpu_to_le_32(q->index),\n-\t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),\n-\t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n-\t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n-\t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n-\t\t},\n-\t};\n+\tstruct ionic_admin_ctx *ctx = &txq->admin_ctx;\n \tint err;\n \n+\tmemset(ctx, 0, sizeof(*ctx));\n+\tctx->pending_work = true;\n+\tctx->cmd.q_init.opcode = IONIC_CMD_Q_INIT;\n+\tctx->cmd.q_init.type = q->type;\n+\tctx->cmd.q_init.ver = lif->qtype_info[q->type].version;\n+\tctx->cmd.q_init.index = rte_cpu_to_le_32(q->index);\n+\tctx->cmd.q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA);\n+\tctx->cmd.q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE);\n+\tctx->cmd.q_init.ring_size = rte_log2_u32(q->num_descs);\n+\tctx->cmd.q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa);\n+\tctx->cmd.q_init.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa);\n+\n \tif (txq->flags & IONIC_QCQ_F_SG)\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n \tif (txq->flags & IONIC_QCQ_F_CMB) {\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n \t} else {\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n \t}\n \n \tIONIC_PRINT(DEBUG, \"txq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_size %d\",\n-\t\tctx.cmd.q_init.ring_size);\n-\tIONIC_PRINT(DEBUG, \"txq_init.ver %u\", ctx.cmd.q_init.ver);\n+\t\tctx->cmd.q_init.ring_size);\n+\tIONIC_PRINT(DEBUG, \"txq_init.ver %u\", ctx->cmd.q_init.ver);\n \n \tionic_q_reset(q);\n \tionic_cq_reset(cq);\n \n-\terr = ionic_adminq_post_wait(lif, &ctx);\n+\t/* Caller responsible for calling ionic_lif_txq_init_done() */\n+\terr = ionic_adminq_post(lif, ctx);\n \tif (err)\n-\t\treturn err;\n+\t\tctx->pending_work = false;\n+\treturn err;\n+}\n \n-\tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n+void\n+ionic_lif_txq_init_done(struct ionic_tx_qcq *txq)\n+{\n+\tstruct ionic_lif *lif = txq->qcq.lif;\n+\tstruct ionic_queue *q = &txq->qcq.q;\n+\tstruct ionic_admin_ctx *ctx = &txq->admin_ctx;\n+\n+\tq->hw_type = ctx->comp.q_init.hw_type;\n+\tq->hw_index = rte_le_to_cpu_32(ctx->comp.q_init.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \tIONIC_PRINT(DEBUG, \"txq->hw_type %d\", q->hw_type);\n@@ -1651,57 +1660,64 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \tIONIC_PRINT(DEBUG, \"txq->db %p\", q->db);\n \n \ttxq->flags |= IONIC_QCQ_F_INITED;\n-\n-\treturn 0;\n }\n \n int\n-ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n+ionic_lif_rxq_init_nowait(struct ionic_rx_qcq *rxq)\n {\n \tstruct ionic_qcq *qcq = &rxq->qcq;\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_lif *lif = qcq->lif;\n \tstruct ionic_cq *cq = &qcq->cq;\n-\tstruct ionic_admin_ctx ctx = {\n-\t\t.pending_work = true,\n-\t\t.cmd.q_init = {\n-\t\t\t.opcode = IONIC_CMD_Q_INIT,\n-\t\t\t.type = q->type,\n-\t\t\t.ver = lif->qtype_info[q->type].version,\n-\t\t\t.index = rte_cpu_to_le_32(q->index),\n-\t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),\n-\t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n-\t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n-\t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n-\t\t},\n-\t};\n+\tstruct ionic_admin_ctx *ctx = &rxq->admin_ctx;\n \tint err;\n \n+\tmemset(ctx, 0, sizeof(*ctx));\n+\tctx->pending_work = true;\n+\tctx->cmd.q_init.opcode = IONIC_CMD_Q_INIT;\n+\tctx->cmd.q_init.type = q->type;\n+\tctx->cmd.q_init.ver = lif->qtype_info[q->type].version;\n+\tctx->cmd.q_init.index = rte_cpu_to_le_32(q->index);\n+\tctx->cmd.q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA);\n+\tctx->cmd.q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE);\n+\tctx->cmd.q_init.ring_size = rte_log2_u32(q->num_descs);\n+\tctx->cmd.q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa);\n+\tctx->cmd.q_init.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa);\n+\n \tif (rxq->flags & IONIC_QCQ_F_SG)\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n \tif (rxq->flags & IONIC_QCQ_F_CMB) {\n-\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n+\t\tctx->cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n \t} else {\n-\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n+\t\tctx->cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n \t}\n \n \tIONIC_PRINT(DEBUG, \"rxq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_size %d\",\n-\t\tctx.cmd.q_init.ring_size);\n-\tIONIC_PRINT(DEBUG, \"rxq_init.ver %u\", ctx.cmd.q_init.ver);\n+\t\tctx->cmd.q_init.ring_size);\n+\tIONIC_PRINT(DEBUG, \"rxq_init.ver %u\", ctx->cmd.q_init.ver);\n \n \tionic_q_reset(q);\n \tionic_cq_reset(cq);\n \n-\terr = ionic_adminq_post_wait(lif, &ctx);\n+\t/* Caller responsible for calling ionic_lif_rxq_init_done() */\n+\terr = ionic_adminq_post(lif, ctx);\n \tif (err)\n-\t\treturn err;\n+\t\tctx->pending_work = false;\n+\treturn err;\n+}\n \n-\tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n+void\n+ionic_lif_rxq_init_done(struct ionic_rx_qcq *rxq)\n+{\n+\tstruct ionic_lif *lif = rxq->qcq.lif;\n+\tstruct ionic_queue *q = &rxq->qcq.q;\n+\tstruct ionic_admin_ctx *ctx = &rxq->admin_ctx;\n+\n+\tq->hw_type = ctx->comp.q_init.hw_type;\n+\tq->hw_index = rte_le_to_cpu_32(ctx->comp.q_init.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \trxq->flags |= IONIC_QCQ_F_INITED;\n@@ -1709,8 +1725,6 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \tIONIC_PRINT(DEBUG, \"rxq->hw_type %d\", q->hw_type);\n \tIONIC_PRINT(DEBUG, \"rxq->hw_index %d\", q->hw_index);\n \tIONIC_PRINT(DEBUG, \"rxq->db %p\", q->db);\n-\n-\treturn 0;\n }\n \n static int\n@@ -1959,9 +1973,11 @@ ionic_lif_configure(struct ionic_lif *lif)\n int\n ionic_lif_start(struct ionic_lif *lif)\n {\n+\tstruct rte_eth_dev *dev = lif->eth_dev;\n \tuint32_t rx_mode;\n-\tuint32_t i;\n+\tuint32_t i, j, chunk;\n \tint err;\n+\tbool fatal = false;\n \n \terr = ionic_lif_rss_setup(lif);\n \tif (err)\n@@ -1982,25 +1998,57 @@ ionic_lif_start(struct ionic_lif *lif)\n \t\t\"on port %u\",\n \t\tlif->nrxqcqs, lif->ntxqcqs, lif->port_id);\n \n-\tfor (i = 0; i < lif->nrxqcqs; i++) {\n-\t\tstruct ionic_rx_qcq *rxq = lif->rxqcqs[i];\n-\t\tif (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {\n-\t\t\terr = ionic_dev_rx_queue_start(lif->eth_dev, i);\n+\tchunk = ionic_adminq_space_avail(lif);\n+\n+\tfor (i = 0; i < lif->nrxqcqs; i += chunk) {\n+\t\tif (lif->rxqcqs[0]->flags & IONIC_QCQ_F_DEFERRED) {\n+\t\t\tIONIC_PRINT(DEBUG, \"Rx queue start deferred\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tfor (j = 0; j < chunk && i + j < lif->nrxqcqs; j++) {\n+\t\t\terr = ionic_dev_rx_queue_start_firsthalf(dev, i + j);\n+\t\t\tif (err) {\n+\t\t\t\tfatal = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \n+\t\tfor (j = 0; j < chunk && i + j < lif->nrxqcqs; j++) {\n+\t\t\t/* Commands that failed to post return immediately */\n+\t\t\terr = ionic_dev_rx_queue_start_secondhalf(dev, i + j);\n \t\t\tif (err)\n-\t\t\t\treturn err;\n+\t\t\t\t/* Don't break */\n+\t\t\t\tfatal = true;\n \t\t}\n \t}\n+\tif (fatal)\n+\t\treturn -EIO;\n \n-\tfor (i = 0; i < lif->ntxqcqs; i++) {\n-\t\tstruct ionic_tx_qcq *txq = lif->txqcqs[i];\n-\t\tif (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {\n-\t\t\terr = ionic_dev_tx_queue_start(lif->eth_dev, i);\n+\tfor (i = 0; i < lif->ntxqcqs; i += chunk) {\n+\t\tif (lif->txqcqs[0]->flags & IONIC_QCQ_F_DEFERRED) {\n+\t\t\tIONIC_PRINT(DEBUG, \"Tx queue start deferred\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tfor (j = 0; j < chunk && i + j < lif->ntxqcqs; j++) {\n+\t\t\terr = ionic_dev_tx_queue_start_firsthalf(dev, i + j);\n+\t\t\tif (err) {\n+\t\t\t\tfatal = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \n+\t\tfor (j = 0; j < chunk && i + j < lif->ntxqcqs; j++) {\n+\t\t\t/* Commands that failed to post return immediately */\n+\t\t\terr = ionic_dev_tx_queue_start_secondhalf(dev, i + j);\n \t\t\tif (err)\n-\t\t\t\treturn err;\n+\t\t\t\t/* Don't break */\n+\t\t\t\tfatal = true;\n \t\t}\n \t}\n+\tif (fatal)\n+\t\treturn -EIO;\n \n \t/* Carrier ON here */\n \tlif->state |= IONIC_LIF_F_UP;\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex ee13f5b7c8..591cf1a2ff 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -228,11 +228,13 @@ int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id,\n \tstruct ionic_tx_qcq **qcq_out);\n void ionic_qcq_free(struct ionic_qcq *qcq);\n \n-int ionic_lif_rxq_init(struct ionic_rx_qcq *rxq);\n+int ionic_lif_rxq_init_nowait(struct ionic_rx_qcq *rxq);\n+void ionic_lif_rxq_init_done(struct ionic_rx_qcq *rxq);\n void ionic_lif_rxq_deinit_nowait(struct ionic_rx_qcq *rxq);\n void ionic_lif_rxq_stats(struct ionic_rx_qcq *rxq);\n \n-int ionic_lif_txq_init(struct ionic_tx_qcq *txq);\n+int ionic_lif_txq_init_nowait(struct ionic_tx_qcq *txq);\n+void ionic_lif_txq_init_done(struct ionic_tx_qcq *txq);\n void ionic_lif_txq_deinit_nowait(struct ionic_tx_qcq *txq);\n void ionic_lif_txq_stats(struct ionic_tx_qcq *txq);\n \ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex 774dc596c0..ad04e987eb 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -203,27 +203,54 @@ ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,\n * Start Transmit Units for specified queue.\n */\n int __rte_cold\n-ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)\n+ionic_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n {\n-\tuint8_t *tx_queue_state = eth_dev->data->tx_queue_state;\n-\tstruct ionic_tx_qcq *txq;\n \tint err;\n \n+\terr = ionic_dev_tx_queue_start_firsthalf(dev, tx_queue_id);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn ionic_dev_tx_queue_start_secondhalf(dev, tx_queue_id);\n+}\n+\n+int __rte_cold\n+ionic_dev_tx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t tx_queue_id)\n+{\n+\tuint8_t *tx_queue_state = dev->data->tx_queue_state;\n+\tstruct ionic_tx_qcq *txq = dev->data->tx_queues[tx_queue_id];\n+\n \tif (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {\n \t\tIONIC_PRINT(DEBUG, \"TX queue %u already started\",\n \t\t\ttx_queue_id);\n \t\treturn 0;\n \t}\n \n-\ttxq = eth_dev->data->tx_queues[tx_queue_id];\n-\n \tIONIC_PRINT(DEBUG, \"Starting TX queue %u, %u descs\",\n \t\ttx_queue_id, txq->qcq.q.num_descs);\n \n-\terr = ionic_lif_txq_init(txq);\n+\treturn ionic_lif_txq_init_nowait(txq);\n+}\n+\n+int __rte_cold\n+ionic_dev_tx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t tx_queue_id)\n+{\n+\tuint8_t *tx_queue_state = dev->data->tx_queue_state;\n+\tstruct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(dev);\n+\tstruct ionic_tx_qcq *txq = dev->data->tx_queues[tx_queue_id];\n+\tint err;\n+\n+\tif (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED)\n+\t\treturn 0;\n+\n+\terr = ionic_adminq_wait(lif, &txq->admin_ctx);\n \tif (err)\n \t\treturn err;\n \n+\tionic_lif_txq_init_done(txq);\n+\n \ttx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n \treturn 0;\n@@ -680,22 +707,31 @@ ionic_rx_init_descriptors(struct ionic_rx_qcq *rxq)\n * Start Receive Units for specified queue.\n */\n int __rte_cold\n-ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n+ionic_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n-\tuint8_t *rx_queue_state = eth_dev->data->rx_queue_state;\n-\tstruct ionic_rx_qcq *rxq;\n-\tstruct ionic_queue *q;\n \tint err;\n \n+\terr = ionic_dev_rx_queue_start_firsthalf(dev, rx_queue_id);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn ionic_dev_rx_queue_start_secondhalf(dev, rx_queue_id);\n+}\n+\n+int __rte_cold\n+ionic_dev_rx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t rx_queue_id)\n+{\n+\tuint8_t *rx_queue_state = dev->data->rx_queue_state;\n+\tstruct ionic_rx_qcq *rxq = dev->data->rx_queues[rx_queue_id];\n+\tstruct ionic_queue *q = &rxq->qcq.q;\n+\n \tif (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {\n \t\tIONIC_PRINT(DEBUG, \"RX queue %u already started\",\n \t\t\trx_queue_id);\n \t\treturn 0;\n \t}\n \n-\trxq = eth_dev->data->rx_queues[rx_queue_id];\n-\tq = &rxq->qcq.q;\n-\n \trxq->frame_size = rxq->qcq.lif->frame_size - RTE_ETHER_CRC_LEN;\n \n \t/* Recalculate segment count based on MTU */\n@@ -707,10 +743,27 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \n \tionic_rx_init_descriptors(rxq);\n \n-\terr = ionic_lif_rxq_init(rxq);\n+\treturn ionic_lif_rxq_init_nowait(rxq);\n+}\n+\n+int __rte_cold\n+ionic_dev_rx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\t\t\t\tuint16_t rx_queue_id)\n+{\n+\tuint8_t *rx_queue_state = dev->data->rx_queue_state;\n+\tstruct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(dev);\n+\tstruct ionic_rx_qcq *rxq = dev->data->rx_queues[rx_queue_id];\n+\tint err;\n+\n+\tif (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED)\n+\t\treturn 0;\n+\n+\terr = ionic_adminq_wait(lif, &rxq->admin_ctx);\n \tif (err)\n \t\treturn err;\n \n+\tionic_lif_rxq_init_done(rxq);\n+\n \t/* Allocate buffers for descriptor ring */\n \tif (rxq->flags & IONIC_QCQ_F_SG)\n \t\terr = ionic_rx_fill_sg(rxq);\ndiff --git a/drivers/net/ionic/ionic_rxtx.h b/drivers/net/ionic/ionic_rxtx.h\nindex 7ca23178cc..a342afec54 100644\n--- a/drivers/net/ionic/ionic_rxtx.h\n+++ b/drivers/net/ionic/ionic_rxtx.h\n@@ -46,6 +46,16 @@ void ionic_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n int ionic_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n int ionic_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n \n+/* Helpers for optimized dev_start() */\n+int ionic_dev_rx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\tuint16_t rx_queue_id);\n+int ionic_dev_rx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\tuint16_t rx_queue_id);\n+int ionic_dev_tx_queue_start_firsthalf(struct rte_eth_dev *dev,\n+\tuint16_t tx_queue_id);\n+int ionic_dev_tx_queue_start_secondhalf(struct rte_eth_dev *dev,\n+\tuint16_t tx_queue_id);\n+\n /* Helpers for optimized dev_stop() */\n void ionic_dev_rx_queue_stop_firsthalf(struct rte_eth_dev *dev,\n \tuint16_t rx_queue_id);\n", "prefixes": [ "13/13" ] }