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{
    "id": 1363,
    "url": "https://patches.dpdk.org/api/patches/1363/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416473922-8314-1-git-send-email-zhida.zang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1416473922-8314-1-git-send-email-zhida.zang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1416473922-8314-1-git-send-email-zhida.zang@intel.com",
    "date": "2014-11-20T08:58:42",
    "name": "[dpdk-dev,v2] i40e: link flow control support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "bf0011f4e8008131a40100fc971033d8c3a6ab66",
    "submitter": {
        "id": 81,
        "url": "https://patches.dpdk.org/api/people/81/?format=api",
        "name": "zzang",
        "email": "zhida.zang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416473922-8314-1-git-send-email-zhida.zang@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/1363/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/1363/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1B2EC7F11;\n\tThu, 20 Nov 2014 09:48:45 +0100 (CET)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 758087F0C\n\tfor <dev@dpdk.org>; Thu, 20 Nov 2014 09:48:42 +0100 (CET)",
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            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid sAK8whgn008349; Thu, 20 Nov 2014 16:58:45 +0800",
            "(from zzang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id sAK8wge6008345; \n\tThu, 20 Nov 2014 16:58:42 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.07,422,1413270000\"; d=\"scan'208\";a=\"610984396\"",
        "From": "zhida zang <zhida.zang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Thu, 20 Nov 2014 16:58:42 +0800",
        "Message-Id": "<1416473922-8314-1-git-send-email-zhida.zang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "Subject": "[dpdk-dev] [PATCH v2] i40e: link flow control support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: zzang <zhida.zang@intel.com>\n\nAdd link flow control support for i40e\n\nSigned-off-by: zhida zang <zhida.zang@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 155 +++++++++++++++++++++++++++++++++++++-\n lib/librte_pmd_i40e/i40e_ethdev.h |  10 +++\n 2 files changed, 162 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex a860af7..183b0be 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -69,6 +69,18 @@\n #define I40E_DEFAULT_TX_WTHRESH      0\n #define I40E_DEFAULT_TX_RSBIT_THRESH 32\n \n+/* Flow control default timer */\n+#define I40E_DEFAULT_PAUSE_TIME 0xFFFFU\n+\n+/* Flow control default high water */\n+#define I40E_DEFAULT_HIGH_WATER 0x1C40\n+\n+/* Flow control default low water */\n+#define I40E_DEFAULT_LOW_WATER  0x1A40\n+\n+/* Flow control enable fwd bit */\n+#define I40E_PRTMAC_FWD_CTRL   0x00000001\n+\n /* Maximun number of MAC addresses */\n #define I40E_NUM_MACADDR_MAX       64\n #define I40E_CLEAR_PXE_WAIT_MS     200\n@@ -98,6 +110,12 @@\n \n #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */\n \n+/* Receive Packet Buffer size */\n+#define I40E_RXPBSIZE (968 * 1024)\n+\n+/* Receive Average Packet Size in Byte*/\n+#define I40E_PACKET_AVERAGE_SIZE 128\n+\n static int eth_i40e_dev_init(\\\n \t\t\t__attribute__((unused)) struct eth_driver *eth_drv,\n \t\t\tstruct rte_eth_dev *eth_dev);\n@@ -131,6 +149,8 @@ static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,\n static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);\n static int i40e_dev_led_on(struct rte_eth_dev *dev);\n static int i40e_dev_led_off(struct rte_eth_dev *dev);\n+static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,\n+\t\t\t      struct rte_eth_fc_conf *fc_conf);\n static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,\n \t\t\t      struct rte_eth_fc_conf *fc_conf);\n static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,\n@@ -237,6 +257,7 @@ static struct eth_dev_ops i40e_eth_dev_ops = {\n \t.tx_queue_release             = i40e_dev_tx_queue_release,\n \t.dev_led_on                   = i40e_dev_led_on,\n \t.dev_led_off                  = i40e_dev_led_off,\n+\t.flow_ctrl_get                = i40e_flow_ctrl_get,\n \t.flow_ctrl_set                = i40e_flow_ctrl_set,\n \t.priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,\n \t.mac_addr_add                 = i40e_macaddr_add,\n@@ -358,6 +379,9 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n \tpf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tpf->adapter->eth_dev = dev;\n \tpf->dev_data = dev->data;\n+\tpf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;\n+\tpf->fc_conf.high_water[0] = I40E_DEFAULT_HIGH_WATER;\n+\tpf->fc_conf.low_water[0] = I40E_DEFAULT_LOW_WATER;\n \n \thw->back = I40E_PF_TO_ADAPTER(pf);\n \thw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);\n@@ -1516,12 +1540,137 @@ i40e_dev_led_off(struct rte_eth_dev *dev)\n }\n \n static int\n-i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,\n-\t\t   __rte_unused struct rte_eth_fc_conf *fc_conf)\n+i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n {\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\n+\tfc_conf->pause_time = pf->fc_conf.pause_time;\n+\tfc_conf->high_water = (pf->fc_conf.high_water[0] *\n+\t\t\t\tI40E_PACKET_AVERAGE_SIZE) >> 10;\n+\tfc_conf->low_water = (pf->fc_conf.low_water[0] *\n+\t\t\t\tI40E_PACKET_AVERAGE_SIZE) >> 10;\n+\n+\t/*\n+\t * Return current mode according to actual setting\n+\t */\n+\tswitch (hw->fc.current_mode) {\n+\tcase I40E_FC_FULL:\n+\t\tfc_conf->mode = RTE_FC_FULL;\n+\t\tbreak;\n+\tcase I40E_FC_TX_PAUSE:\n+\t\tfc_conf->mode = I40E_FC_TX_PAUSE;\n+\t\tbreak;\n+\tcase I40E_FC_RX_PAUSE:\n+\t\tfc_conf->mode = I40E_FC_RX_PAUSE;\n+\t\tbreak;\n+\tcase I40E_FC_NONE:\n+\t\tfc_conf->mode = RTE_FC_NONE;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t};\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n+{\n+\tuint32_t mflcn_reg, fctrl_reg, reg;\n+\tuint32_t max_high_water;\n+\tuint8_t i, aq_failure;\n+\tint err;\n+\tenum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {\n+\t\tI40E_FC_NONE,\n+\t\tI40E_FC_RX_PAUSE,\n+\t\tI40E_FC_TX_PAUSE,\n+\t\tI40E_FC_FULL\n+\t};\n+\n+\tmax_high_water = I40E_RXPBSIZE >> 10;\n+\tif ((fc_conf->high_water > max_high_water) ||\n+\t\t(fc_conf->high_water < fc_conf->low_water)) {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid high/low water setup value in KB, \"\n+\t\t\t\"High_water must <= %d.\", max_high_water);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\thw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];\n+\n+\tpf->fc_conf.pause_time = fc_conf->pause_time;\n+\tpf->fc_conf.high_water[0] = (fc_conf->high_water << 10) /\n+\t\t\t\tI40E_PACKET_AVERAGE_SIZE;\n+\tpf->fc_conf.low_water[0] = (fc_conf->low_water << 10) /\n+\t\t\t\tI40E_PACKET_AVERAGE_SIZE;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n-\treturn -ENOSYS;\n+\terr = i40e_set_fc(hw, &aq_failure, true);\n+\tif (err < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"failed to set link flow control,\"\n+\t\t\t\"err = %d\", aq_failure);\n+\t\treturn err;\n+\t}\n+\n+\tif (i40e_is_40G_device(hw->device_id)) {\n+\n+\t\t/*\n+\t\t * Configure flow control refresh threshold,\n+\t\t * the value for stat_tx_pause_refresh_timer[8]\n+\t\t * is used for global pause operation.\n+\t\t */\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\tI40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),\n+\t\t\tpf->fc_conf.pause_time);\n+\n+\t\t/* configure the timer value included in transmitted pause\n+\t\t * frame,\n+\t\t * the value for stat_tx_pause_quanta[8] is used for global\n+\t\t * pause operation\n+\t\t */\n+\t\tI40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),\n+\t\t\tpf->fc_conf.pause_time);\n+\n+\t\tfctrl_reg = I40E_READ_REG(hw,\n+\t\t\t\tI40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);\n+\n+\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n+\t\t\tfctrl_reg |= I40E_PRTMAC_FWD_CTRL;\n+\t\telse\n+\t\t\tfctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,\n+\t\t\t\tfctrl_reg);\n+\t} else {\n+\t\t/* Configure pause time (2 TCs per register) */\n+\t\treg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;\n+\t\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)\n+\t\t\tI40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);\n+\n+\t\t/* Configure flow control refresh threshold value */\n+\t\tI40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,\n+\t\t\t\tpf->fc_conf.pause_time / 2);\n+\n+\t\tmflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);\n+\n+\t\t/* set or clear MFLCN.PMCF bit depending on configuration */\n+\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n+\t\t\tmflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;\n+\t\telse\n+\t\t\tmflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);\n+\t}\n+\n+\tI40E_WRITE_REG(hw, I40E_GLRPB_PHW, pf->fc_conf.high_water[0]);\n+\tI40E_WRITE_REG(hw, I40E_GLRPB_PLW, pf->fc_conf.low_water[0]);\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n }\n \n static int\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex e61d258..c793c2d 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -231,6 +231,14 @@ struct i40e_pf_vf {\n \tuint16_t lan_nb_qps; /* Actual queues allocated */\n \tuint16_t reset_cnt; /* Total vf reset times */\n };\n+/*\n+ * Structure to store private data for flow control.\n+ */\n+struct i40e_fc_conf {\n+\tuint16_t pause_time; /* Flow control pause timer */\n+\tuint32_t high_water[I40E_MAX_TRAFFIC_CLASS]; /* FC high water */\n+\tuint32_t low_water[I40E_MAX_TRAFFIC_CLASS]; /* FC low water */\n+};\n \n /*\n  * Structure to store private data specific for PF instance.\n@@ -264,6 +272,8 @@ struct i40e_pf {\n \t/* store VXLAN UDP ports */\n \tuint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];\n \tuint16_t vxlan_bitmap; /* Vxlan bit mask */\n+\n+\tstruct i40e_fc_conf fc_conf; /* Flow control conf */\n };\n \n enum pending_msg {\n",
    "prefixes": [
        "dpdk-dev",
        "v2"
    ]
}